arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28 /*************************cru define********************************************/
  29 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,id%16,0x1),RK3288_CRU_GATEID_CONS(id))
  30 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,id%16,0x1),RK3288_CRU_GATEID_CONS(id))
  31
  32 /*******************************gpio define **********************************************/
  33
  34 /* GPIO control registers */
  35 #define GPIO_SWPORT_DR          0x00
  36 #define GPIO_SWPORT_DDR         0x04
  37 #define GPIO_INTEN                      0x30
  38 #define GPIO_INTMASK            0x34
  39 #define GPIO_INTTYPE_LEVEL      0x38
  40 #define GPIO_INT_POLARITY       0x3c
  41 #define GPIO_INT_STATUS         0x40
  42 #define GPIO_INT_RAWSTATUS      0x44
  43 #define GPIO_DEBOUNCE           0x48
  44 #define GPIO_PORTS_EOI          0x4c
  45 #define GPIO_EXT_PORT           0x50
  46 #define GPIO_LS_SYNC            0x60
  47
  48 /***********************************sleep func*********************************************/
  49
  50 // sys resume data in boot ram
  51 #define SLP_DATA_SAVE_PHY  (RK3288_BOOTRAM_PHYS+PM_BOOT_CODE_OFFSET+PM_BOOT_CODE_SIZE)
  52 #define SLP_DATA_SAVE_BASE  (RK_BOOTRAM_VIRT+PM_BOOT_CODE_OFFSET+PM_BOOT_CODE_SIZE)
  53
  54 // ddr resume data in boot ram
  55 #define SLP_DDR_DATA_SAVE_PHY  (RK3288_BOOTRAM_PHYS + PM_BOOT_DDR_CODE_OFFSET)
  56 #define SLP_DDR_DATA_SAVE_BASE  (RK_BOOTRAM_VIRT+PM_BOOT_DDR_CODE_OFFSET)
  57
  58 #define PM_BOOT_DDR_CODE_OFFSET (((PM_BOOT_CODE_OFFSET+PM_BOOT_CODE_SIZE+PM_BOOT_DATA_SIZE)/4+2)*4)
  59 #define PM_BOOT_CODE_SP (RK3288_BOOTRAM_PHYS+((RK3288_BOOTRAM_SIZE-1)&~0x7))
  60
  61
  62 #define BOOT_RAM_SIZE   (4*1024)
  63 #define INT_RAM_SIZE            (64*1024)
  64
  65 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
  66 static char int_ram_data[INT_RAM_SIZE];
  67
  68
  69 // the value is used to control cpu resume flow
  70 static u32 sleep_resume_data[SLPDATA_SLEEP_RES_CON_CNT];
  71 static char *resume_data_base=(char *)(SLP_DATA_SAVE_BASE);
  72 static char *resume_data_phy=  (char *)(SLP_DATA_SAVE_PHY);
  73
  74 static void sram_code_reset(char *data, char *save, char* sram_base,char* sram_phy,u32 _size)
  75 {
  76   char *addr_d=(char *)sram_base;
  77
  78   if(save)
  79           memcpy(save,addr_d, _size);
  80
  81   memcpy((char *)addr_d,(char *)data, _size);
  82   flush_icache_range((unsigned long)addr_d, (unsigned long)addr_d + _size);
  83   outer_clean_range((phys_addr_t) sram_phy, _size);
  84 }
  85
  86 /**
  87 ddr code and data
  88
  89 *** code start
  90 ---data offset--
  91 ---code----
  92 ---data----
  93 */
  94 static void sram_data_for_sleep(char *boot_save, char *int_save)
  95 {
  96
  97         char *addr_base,*addr_phy,*data_src,*data_dst;
  98         u32 sr_size,data_size;
  99
 100         addr_base=(char *)RK_BOOTRAM_VIRT;
 101         addr_phy=(char *)RK3288_BOOTRAM_PHYS;
 102         sr_size=RK3288_BOOTRAM_SIZE;
 103
 104         // save boot sram
 105          if(boot_save)
 106                  memcpy(boot_save,addr_base, sr_size);
 107
 108         // move resume code and date to boot sram
 109         // move sys code
 110         data_dst=(char *)RK_BOOTRAM_VIRT+PM_BOOT_CODE_OFFSET;
 111         data_src=(char *)rkpm_slp_cpu_resume;
 112         data_size=PM_BOOT_CODE_SIZE;
 113         memcpy((char *)data_dst,(char *)data_src, data_size);
 114
 115         // move sys data
 116         data_dst=(char *)resume_data_base;
 117         data_src=(char *)sleep_resume_data;
 118         data_size=sizeof(sleep_resume_data);
 119         memcpy((char *)data_dst,(char *)data_src, data_size);
 120 #if 0
 121         /*************************ddr code cpy*************************************/
 122         // ddr code
 123         data_dst=(char *)(char *)SLP_DDR_DATA_SAVE_BASE;
 124         data_src=(char *)ddr_get_resume_code_info(&data_size);
 125
 126         data_size=(data_size/4+1)*4;
 127
 128         memcpy((char *)data_dst,(char *)data_src, data_size);
 129
 130         // ddr data
 131         data_dst=(char *)(data_dst+data_size);
 132
 133         data_src=(char *)ddr_get_resume_data_info(&data_size);
 134         data_size=(data_size/4+1)*4;
 135         memcpy((char *)data_dst,(char *)data_src, data_size);
 136
 137         /*************************ddr code cpy  end*************************************/
 138 #endif
 139         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 140          outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 141 #if 0
 142          /*************************int mem bak*************************************/
 143         // int mem
 144         addr_base=(char *)rockchip_sram_virt;
 145         //addr_phy=(char *)RK319X_IMEM_PHYS;
 146         sr_size=rockchip_sram_size;
 147         //mmap
 148         if(int_save)
 149           memcpy(int_save,addr_base, sr_size);
 150
 151          flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 152         // outer_clean_range((phys_addr_t) addr_phy, sr_size);
 153 #endif
 154  }
 155
 156 static void sram_data_resume(char *boot_save, char *int_save)
 157 {
 158
 159     char *addr_base,*addr_phy;
 160     u32 sr_size;
 161
 162     addr_base=(char *)RK_BOOTRAM_VIRT;
 163     addr_phy=(char *)RK3288_BOOTRAM_PHYS;
 164     sr_size=RK3288_BOOTRAM_SIZE;
 165     // save boot sram
 166     if(boot_save)
 167         memcpy(addr_base,boot_save, sr_size);
 168
 169     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 170     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 171
 172     #if 0
 173     // int mem
 174     addr_base=(char *)RK319X_IMEM_BASE;
 175     addr_phy=(char *)RK319X_IMEM_PHYS;
 176     sr_size=RK319X_IMEM_SIZE;
 177
 178      if(int_save)
 179        memcpy(addr_base, int_save,sr_size);
 180
 181       flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 182       outer_clean_range((phys_addr_t) addr_phy, sr_size);
 183       #endif
 184 }
 185
 186 /**************************************gic save and resume**************************/
 187 #define  RK_GICD_BASE (RK_GIC_VIRT)
 188 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 189
 190 #define PM_IRQN_START 32
 191 #define PM_IRQN_END     107//107
 192 static void pm_gic_enable(u32 irqs)
 193 {
 194
 195         int irqstart=0;
 196         u32 bit_off;
 197         void __iomem *reg_off;
 198         unsigned int gic_irqs;
 199
 200         gic_irqs = PM_IRQN_END;
 201         irqstart=PM_IRQN_START;//PM_IRQN_START;
 202
 203         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 204         bit_off=irqs%32;
 205         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 206
 207         dsb();
 208 }
 209
 210 static void rkpm_gic_disable(u32 irqs)
 211 {
 212         int irqstart=0;
 213         u32 bit_off;
 214         void __iomem *reg_off;
 215         unsigned int gic_irqs;
 216
 217         gic_irqs = PM_IRQN_END;
 218         irqstart=PM_IRQN_START;//PM_IRQN_START;
 219
 220         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 221         bit_off=irqs%32;
 222         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 223         dsb();
 224 }
 225
 226 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 227
 228 static u32 slp_gic_save[260+50];
 229
 230 static void rkpm_gic_dist_save(u32 *context)
 231 {
 232      int i = 0,j,irqstart=0;
 233      unsigned int gic_irqs;
 234
 235      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 236      gic_irqs = (gic_irqs + 1) * 32;
 237      if (gic_irqs > 1020)
 238      gic_irqs = 1020;
 239      //printk("gic_irqs=%d\n",gic_irqs);
 240      //gic_irqs = PM_IRQN_END;
 241      irqstart=PM_IRQN_START;//PM_IRQN_START;
 242
 243      i = 0;
 244      //level
 245      for (j = irqstart; j < gic_irqs; j += 16)
 246       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 247      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 248
 249      /*
 250      * Set all global interrupts to this CPU only.
 251      */
 252      for(j = 0; j < gic_irqs; j += 4)
 253          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 254
 255      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 256
 257      //pri
 258      for (j = 0; j < gic_irqs; j += 4)
 259          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 260      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 261
 262
 263
 264
 265      //secure
 266      for (j = 0; j < gic_irqs; j += 32)
 267          context[i++]=readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4) / 32);
 268      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 269
 270      for (j = irqstart; j < gic_irqs; j += 32)
 271          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 272
 273      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 274
 275
 276
 277     #if 0
 278      //disable
 279      for (j = 0; j < gic_irqs; j += 32)
 280          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 281
 282      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 283     #endif
 284      //enable
 285      for (j = 0; j < gic_irqs; j += 32)
 286          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 287
 288         //sram_printhex(j);
 289      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 290
 291
 292
 293      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 294      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 295
 296      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 297      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 298      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 299
 300
 301     #if 0
 302      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 303      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 304      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 305      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 306      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 307     #endif
 308     #if 0  //rk319x is not need
 309      for (j = irqstart; j < gic_irqs; j += 32)
 310      {
 311          writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 312          dsb();
 313
 314      }
 315     #endif
 316
 317 }
 318
 319 static void rkpm_gic_dist_resume(u32 *context)
 320 {
 321
 322          int i = 0,j,irqstart=0;
 323          unsigned int gic_irqs;
 324
 325          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 326          gic_irqs = (gic_irqs + 1) * 32;
 327          if (gic_irqs > 1020)
 328                  gic_irqs = 1020;
 329
 330
 331          //gic_irqs = PM_IRQN_END;
 332          irqstart=PM_IRQN_START;//PM_IRQN_START;
 333
 334          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 335          dsb();
 336          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 337          dsb();
 338          for (j = irqstart; j < gic_irqs; j += 32)
 339          {
 340                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 341                  dsb();
 342          }
 343
 344
 345          i = 0;
 346
 347          //trig
 348          for (j = irqstart; j < gic_irqs; j += 16)
 349          {
 350                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 351                  dsb();
 352          }
 353          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 354
 355          /*
 356          * Set all global interrupts to this CPU only.
 357          */
 358          for (j = 0; j < gic_irqs; j += 4)
 359          {
 360                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 361                  dsb();
 362          }
 363          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 364
 365          //pri
 366          for (j = 0; j < gic_irqs; j += 4)
 367          {
 368                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 369
 370                  dsb();
 371          }
 372          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 373
 374
 375          //secu
 376          for (j = 0; j < gic_irqs; j += 32)
 377          {
 378                  writel_relaxed(context[i++],RK_GICD_BASE + 0x80 + (j * 4 )/ 32);
 379                  #if 0
 380                  sram_printhex((j * 4 )/ 32);
 381
 382                  sram_printch('_');
 383                  sram_printhex(temp);
 384
 385                  sram_printch('_');
 386                  sram_printhex(readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4 )/ 32));
 387                  sram_printch('\n');
 388 #endif
 389
 390                  dsb();
 391          }
 392
 393          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 394
 395
 396          //pending
 397          for (j = irqstart; j < gic_irqs; j += 32)
 398          {
 399                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 400                  i++;
 401                  dsb();
 402          }
 403          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 404
 405
 406          //disable
 407 #if 0
 408          for (j = 0; j < gic_irqs; j += 32)
 409          {
 410                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 411
 412                  dsb();
 413          }
 414          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 415
 416 #else
 417         //for (j = 0; j < gic_irqs; j += 32)
 418                 // writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 419 #endif
 420
 421
 422          //enable
 423          for (j = 0; j < gic_irqs; j += 32)
 424          {
 425                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 426
 427                  dsb();
 428          }
 429         // sram_printhex(j);
 430          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 431
 432          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 433
 434          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 435
 436          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 437
 438          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 439          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 440
 441 }
 442
 443
 444
 445 /**************************************regs save and resume**************************/
 446 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 447 {
 448      u32 i;
 449          u32 cnt=(end_offset-st_offset)/4+1;
 450      for(i=0;i<cnt;i++)
 451      {
 452          data[i]=readl_relaxed(base+st_offset+i*4);
 453      }
 454 }
 455
 456 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 457 {
 458      u32 i;
 459      u32 cnt=(end_offset-st_offset)/4+1;
 460      for(i=0;i<cnt;i++)
 461      {
 462          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 463      }
 464 }
 465
 466 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 467 {
 468         u32 i;
 469         u32 cnt=(end_offset-st_offset)/4+1;
 470          for(i=0;i<cnt;i++)
 471          {
 472                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 473          }
 474 }
 475
 476 /**************************************uarts save and resume**************************/
 477
 478 #define RK3288_UART_NUM (4)
 479
 480 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 481 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 482
 483 static u32 slp_uart_data[RK3288_UART_NUM][10];
 484
 485 #define UART_DLL        0       /* Out: Divisor Latch Low */
 486 #define UART_DLM        1       /* Out: Divisor Latch High */
 487
 488 #define UART_IER        1
 489 #define UART_FCR        2
 490
 491 #define UART_LCR        3       /* Out: Line Control Register */
 492 #define UART_MCR        4
 493
 494  void slp_uart_save(int ch)
 495  {
 496          int i=0;
 497         void __iomem *b_addr=slp_uart_base[ch];
 498          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 499          u32 gate_reg;
 500          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 501                 return;
 502         if(ch==2)
 503         {
 504             idx=RK3288_CLKGATE_PCLK_UART2;
 505             b_addr=RK_DEBUG_UART_VIRT;
 506         }
 507
 508
 509         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 510         RK3288_CRU_UNGATING_OPS(idx);
 511          i=0;
 512          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 513          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 514
 515          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 516          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 517
 518          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 519          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 520          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 521          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 522
 523         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 524
 525  }
 526
 527  void slp_uart_resume(int ch)
 528  {
 529         int i=0;
 530
 531         u32 temp;
 532         void __iomem *b_addr=slp_uart_base[ch];
 533         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 534         u32 gate_reg;
 535
 536         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 537             return;
 538
 539         if(ch==2)
 540             idx=RK3288_CLKGATE_PCLK_UART2;
 541
 542
 543         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 544         RK3288_CRU_UNGATING_OPS(idx);
 545
 546          i=0;
 547          temp=slp_uart_data[ch][i++];
 548          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 549
 550          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 551          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 552
 553          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 554
 555          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 556          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 557          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 558
 559          writel_relaxed(temp,b_addr+UART_LCR*4);
 560
 561          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 562  }
 563
 564 /**************************************i2c save and resume**************************/
 565
 566 //#define RK3288_I2C_REG_DUMP
 567 #define RK3288_I2C_NUM (6)
 568 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 569 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 570
 571 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 572
 573 void slp_i2c_save(int ch)
 574 {
 575
 576         void __iomem *b_addr=slp_i2c_base[ch];
 577         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 578         u32 gate_reg;
 579
 580         if(!b_addr)
 581                 return;
 582
 583         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 584         RK3288_CRU_UNGATING_OPS(idx);
 585
 586         #ifdef RK3288_I2C_REG_DUMP
 587         rkpm_ddr_printascii("i2c save");
 588         rkpm_ddr_printhex(ch);
 589         rkpm_ddr_printch('\n');
 590         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 591         #endif
 592
 593         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 594
 595
 596         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 597
 598 }
 599 void slp_i2c_resume(int ch)
 600 {
 601         void __iomem *b_addr=slp_i2c_base[ch];
 602         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 603         u32 gate_reg;
 604
 605         if(!b_addr)
 606                 return;
 607         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 608         RK3288_CRU_UNGATING_OPS(idx);
 609
 610         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 611
 612         #ifdef RK3288_I2C_REG_DUMP
 613         rkpm_ddr_printascii("i2c resume");
 614         rkpm_ddr_printhex(ch);
 615         rkpm_ddr_printch('\n');
 616         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 617         #endif
 618
 619         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 620 }
 621
 622 /**************************************gpios save and resume**************************/
 623 #define RK3288_GPIO_CH (9)
 624 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 625 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 626 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 627
 628 static void gpio_ddr_dump_reg(int ports)
 629 {
 630     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 631
 632     rkpm_ddr_printascii("gpio-");
 633     rkpm_ddr_printhex(ports);
 634     rkpm_ddr_printhex('\n');
 635
 636     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 637     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 638     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 639     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 640     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 641     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 642     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 643     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 644     rkpm_ddr_printhex('\n');
 645
 646     rkpm_ddr_printascii("iomux\n");
 647     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 648
 649     rkpm_ddr_printascii("iomux\n");
 650     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 651
 652 }
 653
 654  static void slp_pin_gpio_save(int ports)
 655  {
 656         int i;
 657         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 658         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 659         u32 gate_reg;
 660
 661         if(ports==0||ports>=RK3288_GPIO_CH)
 662                 return;
 663
 664          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 665          RK3288_CRU_UNGATING_OPS(idx);
 666
 667          //gpio_ddr_dump_reg(ports);
 668          i=0;
 669          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 670          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 671          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 672          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 673          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 674          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 675          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 676          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 677
 678         if(ports>0)
 679         {
 680             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 681             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 682          }
 683
 684
 685         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 686
 687  }
 688
 689  static void slp_pin_gpio_resume (int ports)
 690  {
 691          int i;
 692         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 693         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 694          u32 gate_reg;
 695
 696          if(ports==0||ports>=RK3288_GPIO_CH)
 697                 return;
 698           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 699          RK3288_CRU_UNGATING_OPS(idx);
 700
 701
 702         if(ports>0)
 703         {
 704             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 705             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 706         }
 707
 708         i=0;
 709         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 710         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 711         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 712         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 713         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 714         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 715         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 716         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 717
 718         //gpio_ddr_dump_reg(ports);
 719         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 720
 721  }
 722
 723 /**************************************sleep func**************************/
 724
 725 void ddr_reg_save(uint32_t *pArg);
 726 void fiq_glue_resume(void);
 727 void rk30_cpu_resume(void);
 728 void rk30_l2_cache_init_pm(void);
 729 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 730 void ddr_cfg_to_lp_mode(void);
 731 void l2x0_inv_all_pm(void);
 732 void rk30_cpu_while_tst(void);
 733
 734 #if 0
 735 static u32 slp_grf_soc_con_data[5];
 736 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 737
 738 static u32 slp_grf_cpu_con_data[5];
 739 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 740
 741 static u32 slp_grf_uoc0_con_data[4];
 742 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 743
 744 static u32 slp_grf_uoc1_con_data[2];
 745 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 746
 747 static u32 slp_grf_uoc2_con_data[2];
 748 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 749
 750 static u32 slp_grf_uoc3_con_data[2];
 751 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 752
 753 #endif
 754 static u32 slp_pmu_pwrmode_con_data[1];
 755
 756
 757 static u32 slp_nandc_data[8];
 758 static void __iomem *rk30_nandc_base=NULL;
 759
 760 #define MS_37K (37)
 761 #define US_24M (24)
 762
 763 void inline pm_io_base_map(void)
 764 {
 765         int i;
 766         for(i=0;i<RK3288_I2C_NUM;i++)
 767             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 768
 769         for(i=0;i<RK3288_UART_NUM;i++)
 770             {
 771                 if(i!=CONFIG_RK_DEBUG_UART)
 772                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 773                 else
 774                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 775             }
 776
 777 }
 778 #if 0
 779 void pm_gpio_setting(void)
 780 {
 781
 782         //gpio wake up setting
 783         gpio0_lp_wakeup_en(1,3);
 784         gpio0s_lp_wakeup_type(1);
 785         gpio0_lp_wakeup_en(6,3);
 786
 787 }
 788 #endif
 789  enum rk3288_pwr_mode_con {
 790
 791         pmu_pwr_mode_en=0,
 792         pmu_clk_core_src_gate_en,
 793         pmu_global_int_disable,
 794         pmu_l2flush_en,
 795
 796         pmu_bus_pd_en,
 797         pmu_a12_0_pd_en,
 798         pmu_scu_en,
 799         pmu_pll_pd_en,
 800
 801         pmu_chip_pd_en, // power off pin enable
 802         pmu_pwroff_comb,
 803         pmu_alive_use_lf,
 804         pmu_pmu_use_lf,
 805
 806         pmu_osc_24m_dis,
 807         pmu_input_clamp_en,
 808         pmu_wakeup_reset_en,
 809         pmu_sref0_enter_en,
 810
 811         pmu_sref1_enter_en,
 812         pmu_ddr0io_ret_en,
 813         pmu_ddr1io_ret_en,
 814         pmu_ddr0_gating_en,
 815
 816         pmu_ddr1_gating_en,
 817         pmu_ddr0io_ret_de_req,
 818         pmu_ddr1io_ret_de_req
 819
 820 };
 821  enum rk3288_pwr_mode_con1 {
 822
 823         pmu_clr_bus=0,
 824         pmu_clr_core,
 825         pmu_clr_cpup,
 826         pmu_clr_alive,
 827
 828         pmu_clr_dma,
 829         pmu_clr_peri,
 830         pmu_clr_gpu,
 831         pmu_clr_video,
 832         pmu_clr_hevc,
 833         pmu_clr_vio
 834
 835 };
 836
 837 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 838
 839 static u32 sgrf_soc_con0,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 840
 841 static void  rkpm_slp_mode_set(u32 val)
 842 {
 843     u32 mode_set,mode_set1;
 844
 845     // setting gpio0_a0 arm off pin
 846     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 847
 848     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 849     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 850     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 851
 852     mode_set1=pmu_pwr_mode_con1;
 853     mode_set=pmu_pwr_mode_con0;
 854
 855
 856     pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 857
 858     // enable boot ram
 859     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 860     reg_writel(RK3288_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 861
 862     mode_set|=  BIT(pmu_pwr_mode_en)|BIT(pmu_global_int_disable)
 863                         | BIT(pmu_l2flush_en)
 864                         |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en) |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en);
 865
 866
 867     if(rkpm_chk_val_ctrbit(val,RKPM_CTR_IDLEAUTO_MD))
 868     {
 869         rkpm_ddr_printascii("-autoidle-");
 870         mode_set|=BIT(pmu_clk_core_src_gate_en);
 871     }
 872     else if(rkpm_chk_val_ctrbit(val,RKPM_CTR_ARMDP_LPMD))
 873     {
 874         rkpm_ddr_printascii("-armdp-");
 875         //rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
 876
 877        // pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 878         mode_set|=BIT(pmu_a12_0_pd_en);
 879     }
 880     else if(rkpm_chk_val_ctrbit(val,RKPM_CTR_ARMOFF_LPMD))
 881     {
 882
 883         rkpm_ddr_printascii("-armoff-");
 884         //rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
 885
 886         mode_set|=BIT(pmu_scu_en)|BIT(pmu_chip_pd_en);
 887         mode_set1|=BIT(pmu_clr_core)|BIT(pmu_clr_cpup);
 888     }
 889     else
 890     {
 891         mode_set=pmu_pwr_mode_con0;
 892         mode_set1=pmu_pwr_mode_con1;
 893     }
 894
 895
 896     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
 897     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
 898
 899 }
 900
 901 static inline void  rkpm_slp_mode_set_resume(void)
 902 {
 903
 904     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
 905     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
 906     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 907
 908 }
 909
 910 static inline u32 rkpm_l2_config(void)
 911 {
 912         u32 l2ctlr;
 913         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 914         return l2ctlr;
 915 }
 916
 917
 918 static int sleep_resume_all=0;
 919 void pm_sleep_func_save(void)
 920 {
 921         //char *data_src;
 922         //u32 data_size;
 923         //u32 *p;
 924
 925         sleep_resume_data[SLPDATA_L2_CON]=rkpm_l2_config();// in sys resume ,ddr is need resume
 926         sleep_resume_data[SLPDATA_SP_ADDR]=PM_BOOT_CODE_SP;// in sys resume ,ddr is need resume
 927         sleep_resume_data[SLPDATA_SP_CPU_RESUME]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
 928         sleep_resume_data[SLPDATA_DDR_NEED_RES]=0;// in sys resume ,ddr is need resume
 929         sleep_resume_data[SLPDATA_DPLL_NEED_RES]=0;// in ddr resume ,dpll is need resume
 930         //data_src=(char *)ddr_get_resume_code_info(&data_size);
 931         //sleep_resume_data[SLPDATA_DDR_CODE_PHY]=SLP_DDR_DATA_SAVE_PHY;
 932         //sleep_resume_data[SLPDATA_DDR_DATA_PHY]=SLP_DDR_DATA_SAVE_PHY+(data_size/4+1)*4;
 933
 934         //ddr_reg_save(resume_data_phy+SLP_DPLL_NEED_RES*4);
 935         sram_data_for_sleep(boot_ram_data,int_ram_data);
 936        rkpm_gic_dist_save(&slp_gic_save[0]);
 937         flush_cache_all();
 938         outer_flush_all();
 939         local_flush_tlb_all();
 940
 941         //slp_regs_save(slp_grf_iomux_data,(u32)RK_GRF_VIRT+0x10,16);
 942         //slp_regs_save(slp_nandc_data,(u32)rk30_nandc_base,8);
 943
 944         //slp_pin_gpio_save(1);
 945         //slp_pin_gpio_save(2);
 946         //slp_pin_gpio_save(3);
 947         //slp_pin_gpio_save(4);
 948         //slp_uart_save(2);
 949         #if 0
 950         rkpm_ddr_printascii("l2-");
 951         rkpm_ddr_printhex(sleep_resume_data[SLPDATA_L2_CON]);
 952         rkpm_ddr_printascii("\n");
 953         #endif
 954
 955         sleep_resume_all=0;
 956 }
 957 void pm_sleep_func_rusume_first(void)
 958 {
 959
 960        // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
 961         #if 0
 962         //rk319x_pm_set_power_domain(PD_PERI,true);
 963         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
 964         slp_pin_gpio_resume(1);
 965         slp_pin_gpio_resume(2);
 966         slp_pin_gpio_resume(3);
 967         slp_pin_gpio_resume(4);
 968
 969         #if 0
 970         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
 971         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
 972
 973         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
 974         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
 975         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
 976         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
 977         #endif
 978         //sram_printch_uart_enable();
 979         slp_uart_resume(2);
 980     #endif
 981
 982     sleep_resume_all=1;
 983
 984
 985 }
 986
 987 void pm_sleep_func_rusume_last(void)
 988 {
 989     if(sleep_resume_all)
 990     {
 991
 992         // slp_uart_resume(0);
 993         // slp_uart_resume(1);
 994         // slp_uart_resume(3);
 995         // slp_regs_resume(slp_nandc_data,(u32)rk30_nandc_base,8,0);
 996
 997         //rkpm_ddr_printch('g');
 998         rkpm_gic_dist_resume(&slp_gic_save[0]);
 999
1000         fiq_glue_resume();
1001         #if 0
1002         rkpm_ddr_printascii("l2-");
1003         rkpm_ddr_printhex(rkpm_l2_config());
1004         rkpm_ddr_printascii("\n");
1005         #endif
1006
1007     }
1008     rkpm_slp_mode_set_resume();
1009     sram_data_resume(boot_ram_data,int_ram_data);
1010 }
1011
1012 /*******************************common code  for rkxxx*********************************/
1013 static void  inline uart_printch(char byte)
1014 {
1015         u32 reg_save[2];
1016         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1017         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1018
1019         if(CONFIG_RK_DEBUG_UART==4)
1020             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1021         if(CONFIG_RK_DEBUG_UART==2)
1022             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1023
1024         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1025         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1026         RK3288_CRU_UNGATING_OPS(u_clk_id);
1027         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1028
1029         rkpm_udelay(1);
1030
1031         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1032         dsb();
1033
1034         /* loop check LSR[6], Transmitter Empty bit */
1035         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1036                 barrier();
1037
1038          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1039          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1040
1041         if (byte == '\n')
1042                 uart_printch('\r');
1043 }
1044
1045 void PIE_FUNC(sram_printch)(char byte)
1046 {
1047         uart_printch(byte);
1048 }
1049
1050 static void pll_udelay(u32 udelay);
1051
1052 static void  ddr_printch(char byte)
1053 {
1054         uart_printch(byte);
1055         pll_udelay(2);
1056 }
1057 /*******************************gpio func*******************************************/
1058 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1059 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1060 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1061 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1062
1063
1064 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1065 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1066 {
1067     u8 off_set;
1068     bank-=0xa;
1069
1070     if(port==0)
1071     {
1072         if(bank>2)
1073             return;
1074
1075         off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1076         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1077     }
1078     else
1079     {
1080
1081         off_set=port*(4*4)+bank*4;
1082         //form RK3288_GRF_GPIO1D_IOMUX
1083          reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1084     }
1085 }
1086
1087 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1088 {
1089     u8 off_set;
1090     bank-=0xa;
1091
1092     if(port==0)
1093     {
1094       if(bank>2)
1095             return 0;
1096         off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1097         return (pmu_readl(off_set)>>(b_gpio*2))&0x3;
1098     }
1099     else
1100     {
1101
1102         off_set=port*(4*4)+bank*4;
1103         //form RK3288_GRF_GPIO1D_IOMUX
1104          return (reg_readl(RK_GRF_VIRT+0+off_set)>>(b_gpio*2))&0x3;
1105     }
1106 }
1107
1108 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1109 {
1110     u8 off_set;
1111
1112     bank-=0xa;
1113
1114     if(port > 0)
1115     {
1116         //gpio1_d st
1117         if(port==1&&bank<3)
1118          return;
1119         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1120         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1121         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1122
1123     }
1124     else
1125     {
1126         if(bank>2)// gpio0_d is not support
1127             return;
1128         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1129     }
1130
1131 }
1132
1133 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1134 {
1135     u8 off_set;
1136
1137     bank-=0xa;
1138
1139     if(port > 0)
1140     {
1141         //gpio1_d st
1142         if(port==1&&bank<3)
1143             return 0;
1144         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1145         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1146         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1147
1148     }
1149     else
1150     {
1151         if(bank>2)// gpio0_d is not support
1152             return 0;
1153         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1154     }
1155
1156 }
1157
1158
1159 //RKPM_GPIOS_INPUT
1160 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1161 {
1162     u8 val;
1163
1164     bank-=0xa;
1165     b_gpio=bank*8+b_gpio;//
1166
1167     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1168
1169     if(type==RKPM_GPIO_OUTPUT)
1170         val|=(0x1<<b_gpio);
1171     else
1172         val&=~(0x1<<b_gpio);
1173
1174     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1175 }
1176
1177 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1178 {
1179     bank-=0xa;
1180     b_gpio=bank*8+b_gpio;
1181     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1182 }
1183
1184 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1185 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1186 {
1187     u8 val;
1188
1189     bank-=0xa;
1190     b_gpio=bank*8+b_gpio;
1191
1192     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1193
1194     if(level==RKPM_GPIO_OUT_H)
1195         val|=(0x1<<b_gpio);
1196     else //
1197         val&=~(0x1<<b_gpio);
1198
1199      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1200 }
1201
1202 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1203 {
1204     bank-=0xa;
1205     b_gpio=bank*8+b_gpio;
1206     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1207 }
1208
1209 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1210 {
1211
1212     bank-=0xa;
1213     b_gpio=bank*8+b_gpio;
1214
1215     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1216 }
1217
1218 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1219 {
1220         pin_set_fun(port,bank,b_gpio,fun);
1221 }
1222 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1223 {
1224     return pin_get_funset(port,bank,b_gpio);
1225 }
1226
1227 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1228 {
1229         pin_set_pull(port,bank,b_gpio,fun);
1230 }
1231 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1232 {
1233     return pin_get_pullset(port,bank,b_gpio);
1234 }
1235
1236 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1237 {
1238     gpio_set_in_output(port,bank,b_gpio,type);
1239 }
1240
1241 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1242 {
1243     return gpio_get_in_outputset(port,bank,b_gpio);
1244 }
1245
1246 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1247 {
1248
1249     gpio_set_output_level(port,bank,b_gpio,level);
1250
1251 }
1252
1253 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1254 {
1255     return gpio_get_output_levelset(port,bank,b_gpio);
1256 }
1257
1258 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1259 {
1260     return gpio_get_input_level(port,bank,b_gpio);
1261 }
1262 //ddr
1263 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1264 {
1265         pin_set_fun(port,bank,b_gpio,fun);
1266 }
1267 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1268 {
1269     return pin_get_funset(port,bank,b_gpio);
1270 }
1271
1272 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1273 {
1274         pin_set_pull(port,bank,b_gpio,fun);
1275 }
1276 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1277 {
1278     return pin_get_pullset(port,bank,b_gpio);
1279 }
1280
1281 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1282 {
1283     gpio_set_in_output(port,bank,b_gpio,type);
1284 }
1285
1286 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1287 {
1288     return gpio_get_in_outputset(port,bank,b_gpio);
1289 }
1290
1291 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1292 {
1293     gpio_set_output_level(port,bank,b_gpio,level);
1294 }
1295
1296 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1297 {
1298     return gpio_get_output_levelset(port,bank,b_gpio);
1299 }
1300
1301 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1302 {
1303     return gpio_get_input_level(port,bank,b_gpio);
1304 }
1305
1306
1307
1308 static  void __sramfunc rkpm_pin_gpio_config_sram(u32 pin_gpio_bits,u32 *save_bits)
1309 {
1310
1311     u32 pins;
1312     u8 port,bank,b_gpio,fun,in_out, level, pull;
1313
1314     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1315     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1316     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1317     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1318
1319     port=RKPM_PINBITS_PORT(pins);
1320     bank=RKPM_PINBITS_BANK(pins);
1321     b_gpio=RKPM_PINBITS_BGPIO(pins);
1322     fun=RKPM_PINBITS_FUN(pins);
1323
1324     //save pins info
1325     if(save_bits)
1326     {
1327         pins=RKPM_PINBITS_SET_FUN(pins,sram_pin_get_funset(port,bank,b_gpio));
1328        *save_bits=RKPM_PINGPIO_BITS(pins,sram_pin_get_pullset(port,bank,b_gpio),sram_gpio_get_in_outputset(port,bank,b_gpio),
1329                                                                                         sram_gpio_get_output_levelset(port,bank,b_gpio));
1330     }
1331     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1332    {
1333         if(level==RKPM_GPIO_OUT_L)
1334             pull=RKPM_GPIO_PULL_DN;
1335         else
1336             pull=RKPM_GPIO_PULL_UP;
1337
1338         sram_gpio_set_output_level(port,bank,b_gpio,level);
1339     }
1340
1341     sram_pin_set_pull(port,bank,b_gpio,pull);
1342     sram_pin_set_fun(port,bank,b_gpio,fun);
1343
1344     if(!fun)
1345     {
1346         sram_gpio_set_in_output(port,bank,b_gpio,in_out);
1347     }
1348
1349 }
1350
1351 static inline void rkpm_pin_gpio_config_ddr(u32 pin_gpio_bits,u32 *save_bits)
1352 {
1353
1354     u32 pins;
1355     u8 port,bank,b_gpio,fun,in_out, level, pull;
1356
1357     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1358     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1359     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1360     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1361
1362     port=RKPM_PINBITS_PORT(pins);
1363     bank=RKPM_PINBITS_BANK(pins);
1364     b_gpio=RKPM_PINBITS_BGPIO(pins);
1365     fun=RKPM_PINBITS_FUN(pins);
1366
1367     //save pins info
1368     if(save_bits)
1369     {
1370         pins=RKPM_PINBITS_SET_FUN(pins,ddr_pin_get_funset(port,bank,b_gpio));
1371        *save_bits=RKPM_PINGPIO_BITS(pins,ddr_pin_get_pullset(port,bank,b_gpio),ddr_gpio_get_in_outputset(port,bank,b_gpio),
1372                                                                                         ddr_gpio_get_output_levelset(port,bank,b_gpio));
1373     }
1374     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1375    {
1376         if(level==RKPM_GPIO_OUT_L)
1377             pull=RKPM_GPIO_PULL_DN;
1378         else
1379             pull=RKPM_GPIO_PULL_UP;
1380
1381         ddr_gpio_set_output_level(port,bank,b_gpio,level);
1382     }
1383
1384     ddr_pin_set_pull(port,bank,b_gpio,pull);
1385     ddr_pin_set_fun(port,bank,b_gpio,fun);
1386
1387     if(!fun)
1388     {
1389         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1390     }
1391
1392 }
1393
1394
1395 #define GPIO_DTS_NUM 10
1396
1397 static  u32 gpio_dts_save[GPIO_DTS_NUM];
1398 static  u32 gpio_dts[GPIO_DTS_NUM];
1399
1400 #define PMICGPIO_DTS_NUM 3
1401
1402
1403 u32 DEFINE_PIE_DATA(pmicgpio_dts[PMICGPIO_DTS_NUM]);
1404 static u32 *p_pmicgpio_dts;
1405 static __sramdata u32 pmicgpio_dts_save[PMICGPIO_DTS_NUM];
1406
1407 static void __sramfunc pmic_gpio_suspend(void)
1408 {
1409        int i;
1410        for(i=0;;i++)
1411        {
1412             if(DATA(pmicgpio_dts[i]))
1413                 rkpm_pin_gpio_config_sram(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1414             else
1415             {
1416                     pmicgpio_dts_save[i]=0;
1417                     break;
1418              }
1419        }
1420     #if 0
1421          for(i=0;i<6;i++)
1422         {
1423             rkpm_sram_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1424         }
1425         //
1426         rkpm_sram_reg_dump(RK_GRF_VIRT,0xc,0x84);
1427         rkpm_sram_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1428         rkpm_sram_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1429         rkpm_sram_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1430     #endif
1431
1432 }
1433
1434 static void  __sramfunc pmic_gpio_resume(void)
1435 {
1436        int i;
1437        for(i=0;;i++)
1438        {
1439             if(pmicgpio_dts_save[i])
1440                 rkpm_pin_gpio_config_sram(pmicgpio_dts_save[i],NULL);
1441        }
1442
1443 }
1444
1445 void PIE_FUNC(pmic_suspend)(void)
1446 {
1447     pmic_gpio_suspend();
1448
1449 }
1450
1451 void PIE_FUNC(pmic_resume)(void)
1452 {
1453     pmic_gpio_resume();
1454 }
1455
1456
1457 static void  rkpm_gpio_suspend(void)
1458 {
1459        int i;
1460        for(i=0;;i++)
1461        {
1462             if(DATA(pmicgpio_dts[i]))
1463                 rkpm_pin_gpio_config_ddr(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1464             else
1465             {
1466                     pmicgpio_dts_save[i]=0;
1467                     break;
1468              }
1469        }
1470     #if 0
1471          for(i=0;i<6;i++)
1472         {
1473             rkpm_ddr_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1474         }
1475         //
1476         rkpm_ddr_reg_dump(RK_GRF_VIRT,0xc,0x84);
1477         rkpm_ddr_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1478         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1479         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1480     #endif
1481
1482 }
1483
1484 static void  rkpm_gpio_resume(void)
1485 {
1486        int i;
1487        for(i=0;;i++)
1488        {
1489             if(pmicgpio_dts_save[i])
1490                 rkpm_pin_gpio_config_ddr(pmicgpio_dts_save[i],NULL);
1491        }
1492
1493 }
1494 static void gpio_get_dts_info(struct device_node *parent)
1495 {
1496         int i;
1497
1498         for(i=0;i<PMICGPIO_DTS_NUM;i++)
1499             p_pmicgpio_dts[i]=0;
1500
1501         for(i=0;i<GPIO_DTS_NUM;i++)
1502             gpio_dts[i]=0;
1503
1504
1505         p_pmicgpio_dts= kern_to_pie(rockchip_pie_chunk, &DATA(pmicgpio_dts[0]));
1506
1507        if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",p_pmicgpio_dts,PMICGPIO_DTS_NUM))
1508        {
1509                 p_pmicgpio_dts[0]=0;
1510                PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1511        }
1512
1513        for(i=0;i<PMICGPIO_DTS_NUM;i++)
1514             printk("%s:pmic gpio(%x)\n",__FUNCTION__,p_pmicgpio_dts[i]);
1515
1516         if(of_property_read_u32_array(parent,"rockchip,pm-gpios",gpio_dts,GPIO_DTS_NUM))
1517         {
1518                  gpio_dts[0]=0;
1519                 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1520         }
1521         for(i=0;i<GPIO_DTS_NUM;i++)
1522          printk("%s:pmic gpio(%x)\n",__FUNCTION__,gpio_dts[i]);
1523
1524     rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1525     rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_suspend)),
1526                   fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_resume)));
1527
1528 }
1529
1530
1531 /*******************************clk gating config*******************************************/
1532 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1533 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1534
1535
1536 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1537 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1538 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1539
1540
1541 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1542 static u32 *p_rkpm_clkgt_last_set;
1543
1544 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1545
1546 void PIE_FUNC(gtclks_sram_suspend)(void)
1547 {
1548     int i;
1549    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1550    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1551
1552     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1553     {
1554         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1555         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1556         #if 0
1557         rkpm_sram_printch('\n');
1558         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1559         rkpm_sram_printch('-');
1560         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1561         rkpm_sram_printch('-');
1562         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1563         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1564         rkpm_sram_printch('\n');
1565         #endif
1566     }
1567
1568         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1569         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1570
1571 }
1572
1573 void PIE_FUNC(gtclks_sram_resume)(void)
1574 {
1575     int i;
1576     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1577     {
1578         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1579     }
1580 }
1581
1582 static void gtclks_suspend(void)
1583 {
1584     int i;
1585
1586   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1587                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1588     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1589     {
1590             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1591            //if(RK3288_CRU_CLKGATES_CON(i)<0x170||RK3288_CRU_CLKGATES_CON(i)>0x194)
1592             {
1593                 CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
1594
1595             }
1596            #if 0
1597             rkpm_ddr_printch('\n');
1598             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
1599             rkpm_ddr_printch('-');
1600             rkpm_ddr_printhex(clk_ungt_msk[i]);
1601             rkpm_ddr_printch('-');
1602             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
1603             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1604             rkpm_ddr_printch('\n');
1605             #endif
1606     }
1607
1608 }
1609
1610 static void gtclks_resume(void)
1611 {
1612     int i;
1613      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1614     {
1615        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
1616      }
1617      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1618                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1619
1620 }
1621 /********************************pll power down***************************************/
1622
1623 enum rk_plls_id {
1624         APLL_ID = 0,
1625         DPLL_ID,
1626         CPLL_ID,
1627         GPLL_ID,
1628         NPLL_ID,
1629         END_PLL_ID,
1630 };
1631
1632 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
1633 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
1634 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
1635
1636
1637 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
1638 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
1639
1640 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
1641 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
1642 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
1643
1644 static void pm_pll_wait_lock(u32 pll_idx)
1645 {
1646         u32 delay = 600000U;
1647        // u32 mode;
1648      //  mode=cru_readl(RK3288_CRU_MODE_CON);
1649         dsb();
1650         dsb();
1651         dsb();
1652         dsb();
1653         dsb();
1654         dsb();
1655         while (delay > 0) {
1656                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
1657                         break;
1658                 delay--;
1659         }
1660         if (delay == 0) {
1661                 rkpm_ddr_printascii("unlock-pll:");
1662                 rkpm_ddr_printhex(pll_idx);
1663                 rkpm_ddr_printch('\n');
1664         }
1665     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
1666 }
1667
1668 static void pll_udelay(u32 udelay)
1669 {
1670     u32 mode;
1671     mode=cru_readl(RK3288_CRU_MODE_CON);
1672     // delay in 24m
1673     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
1674
1675     rkpm_udelay(udelay*5);
1676
1677     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
1678 }
1679
1680 static u32 plls_con0_save[END_PLL_ID];
1681 static u32 plls_con1_save[END_PLL_ID];
1682 static u32 plls_con2_save[END_PLL_ID];
1683 static u32 plls_con3_save[END_PLL_ID];
1684
1685 static u32 cru_mode_con;
1686
1687 static inline void plls_suspend(u32 pll_id)
1688 {
1689     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
1690     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
1691     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
1692     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
1693
1694     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
1695
1696 }
1697 static inline void plls_resume(u32 pll_id)
1698 {
1699         u32 pllcon0, pllcon1, pllcon2;
1700
1701         if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
1702             return ;
1703
1704         //enter slowmode
1705         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
1706
1707         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
1708         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
1709
1710         pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
1711         pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
1712         pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
1713
1714         //enter rest
1715         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
1716         cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
1717         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
1718         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
1719
1720         pll_udelay(5);
1721         //udelay(5); //timer7 delay
1722
1723         //return form rest
1724         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
1725
1726         //wating lock state
1727         pll_udelay(168);
1728         pm_pll_wait_lock(pll_id);
1729
1730         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
1731
1732 }
1733
1734 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
1735
1736 static void pm_plls_suspend(void)
1737 {
1738
1739    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
1740    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
1741    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
1742
1743     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
1744     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
1745     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
1746     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
1747     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
1748     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
1749     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
1750
1751     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
1752
1753
1754     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
1755     plls_suspend(NPLL_ID);
1756
1757 // cpll
1758     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
1759
1760 // gpll
1761     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
1762
1763     // set 1,pdbus pll is gpll
1764     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
1765
1766     // pd_bus clk
1767     cru_writel(0
1768                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
1769                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
1770                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
1771                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
1772                      , RK3288_CRU_CLKSELS_CON(1));
1773
1774     //crypto for pd_bus
1775     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
1776
1777     // peri aclk hclk pclk
1778     cru_writel(0
1779                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
1780                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
1781                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
1782                         , RK3288_CRU_CLKSELS_CON(10));
1783
1784     plls_suspend(CPLL_ID);
1785     plls_suspend(GPLL_ID);
1786
1787 //apll
1788    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
1789      // core_m0 core_mp a12_core
1790     cru_writel(0
1791                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
1792                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
1793                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
1794                       , RK3288_CRU_CLKSELS_CON(0));
1795     // core0 core1 core2 core3
1796     cru_writel(0
1797                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
1798                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
1799                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
1800                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
1801                       , RK3288_CRU_CLKSELS_CON(36));
1802     // l2ram atclk pclk
1803     cru_writel(0
1804                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
1805                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
1806                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
1807                      , RK3288_CRU_CLKSELS_CON(37));
1808     plls_suspend(APLL_ID);
1809
1810 }
1811
1812 static void pm_plls_resume(void)
1813 {
1814
1815         plls_resume(APLL_ID);
1816
1817         // core_m0 core_mp a12_core
1818         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
1819         // core0 core1 core2 core3
1820         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
1821                         , RK3288_CRU_CLKSELS_CON(36));
1822         // l2ram atclk pclk
1823         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
1824
1825         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
1826
1827
1828         plls_resume(GPLL_ID);
1829         plls_resume(CPLL_ID);
1830
1831         // peri aclk hclk pclk
1832         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
1833                                                                             , RK3288_CRU_CLKSELS_CON(10));
1834         //pd bus gpll sel
1835         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
1836         // pd_bus clk
1837         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
1838                     , RK3288_CRU_CLKSELS_CON(1));
1839
1840         // crypto
1841         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
1842
1843
1844           // pmu alive
1845         cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
1846
1847         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
1848         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
1849
1850         plls_resume(NPLL_ID);
1851         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
1852
1853        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
1854        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
1855        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
1856
1857 }
1858
1859 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
1860
1861 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
1862 {
1863
1864     int div;
1865     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
1866     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
1867     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
1868
1869
1870     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
1871     {
1872         div=3;
1873         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
1874         cru_writel(0
1875                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
1876                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
1877                             , RK3288_CRU_MODE_CON);
1878     }
1879     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
1880     {
1881         div=31;
1882     }
1883
1884     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
1885     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
1886     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
1887
1888 }
1889
1890 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
1891 {
1892
1893     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
1894     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
1895     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
1896     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
1897                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
1898                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
1899                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
1900
1901 }
1902
1903
1904 static void clks_gating_suspend_init(void)
1905 {
1906     // get clk gating info
1907     if(rockchip_pie_chunk)
1908         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
1909     else
1910         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
1911     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
1912         ==RK3288_CRU_CLKGATES_CON(0))
1913     {
1914         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
1915         if(rockchip_pie_chunk)
1916             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
1917                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
1918
1919         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
1920
1921     }
1922     if(rockchip_pie_chunk)
1923         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
1924                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
1925 }
1926
1927 /***************************prepare and finish reg_pread***********************************/
1928
1929
1930
1931 #define GIC_DIST_PENDING_SET            0x200
1932 #define DUMP_GPIO_INT_STATUS(ID) \
1933 do { \
1934         if (irq_gpio & (1 << ID)) \
1935                 printk("wakeup gpio" #ID ": %08x\n", readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INT_STATUS)); \
1936 } while (0)
1937 static noinline void rk30_pm_dump_irq(void)
1938 {
1939         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
1940         printk("wakeup irq: %08x %08x %08x %08x\n",
1941                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 4),
1942                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 8),
1943                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12),
1944                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 16));
1945         DUMP_GPIO_INT_STATUS(0);
1946         DUMP_GPIO_INT_STATUS(1);
1947         DUMP_GPIO_INT_STATUS(2);
1948         DUMP_GPIO_INT_STATUS(3);
1949         DUMP_GPIO_INT_STATUS(4);
1950         DUMP_GPIO_INT_STATUS(5);
1951         DUMP_GPIO_INT_STATUS(6);
1952         DUMP_GPIO_INT_STATUS(7);
1953         DUMP_GPIO_INT_STATUS(8);
1954
1955 }
1956
1957 #define DUMP_GPIO_INTEN(ID) \
1958 do { \
1959         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
1960         if (en) { \
1961                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
1962                 rkpm_ddr_printhex(en); \
1963                 rkpm_ddr_printch('\n'); \
1964                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
1965         } \
1966 } while (0)
1967
1968 //dump while irq is enable
1969 static noinline void rk30_pm_dump_inten(void)
1970 {
1971         DUMP_GPIO_INTEN(0);
1972         DUMP_GPIO_INTEN(1);
1973         DUMP_GPIO_INTEN(2);
1974         DUMP_GPIO_INTEN(3);
1975         DUMP_GPIO_INTEN(4);
1976         DUMP_GPIO_INTEN(5);
1977         DUMP_GPIO_INTEN(6);
1978         DUMP_GPIO_INTEN(7);
1979         DUMP_GPIO_INTEN(8);
1980 }
1981
1982 static  void rkpm_prepare(void)
1983 {
1984         #if 0
1985         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
1986
1987        // rkpm_ddr_printhex(temp);
1988         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
1989         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
1990        // rkpm_ddr_printhex(temp);
1991         #endif
1992         // dump GPIO INTEN for debug
1993         rk30_pm_dump_inten();
1994 }
1995
1996 static void rkpm_finish(void)
1997 {
1998         rk30_pm_dump_irq();
1999 }
2000
2001
2002 static  void interface_ctr_reg_pread(void)
2003 {
2004         //u32 addr;
2005         flush_cache_all();
2006         outer_flush_all();
2007         local_flush_tlb_all();
2008         #if 0  // do it in ddr suspend
2009         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2010                 readl_relaxed(addr);
2011         #endif
2012         readl_relaxed(RK_PMU_VIRT);
2013         readl_relaxed(RK_GRF_VIRT);
2014         readl_relaxed(RK_DDR_VIRT);
2015         readl_relaxed(RK_GPIO_VIRT(0));
2016         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2017         //readl_relaxed(RK_GPIO_VIRT(3));
2018 }
2019 void PIE_FUNC(ddr_leakage_tst)(void)
2020 {
2021     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2022     rkpm_sram_printch('\n');
2023     rkpm_sram_printch('t');
2024     rkpm_sram_printch('e');
2025     rkpm_sram_printch('s');
2026     rkpm_sram_printch('t');
2027     while(1);
2028 }
2029
2030 static void __init  rk3288_suspend_init(void)
2031 {
2032     struct device_node *parent;
2033     u32 pm_ctrbits;
2034
2035     PM_LOG("%s enter\n",__FUNCTION__);
2036
2037     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2038
2039     if (IS_ERR_OR_NULL(parent)) {
2040                 PM_ERR("%s dev node err\n", __func__);
2041                 return;
2042         }
2043
2044
2045     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2046     {
2047             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2048             return ;
2049     }
2050     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2051
2052     rkpm_set_ctrbits(pm_ctrbits);
2053
2054     clks_gating_suspend_init();
2055
2056     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2057
2058     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2059     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2060     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2061
2062     rkpm_set_ops_regs_sleep(pm_sleep_func_save,rkpm_slp_mode_set,pm_sleep_func_rusume_first,pm_sleep_func_rusume_last);
2063     if(rockchip_pie_chunk)
2064         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2065
2066     rkpm_set_ops_printch(ddr_printch);
2067 }