arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28
  29 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
  30 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
  31 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
  32
  33
  34 /*************************cru define********************************************/
  35
  36
  37 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  38 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  39
  40 enum rk_plls_id {
  41         APLL_ID = 0,
  42         DPLL_ID,
  43         CPLL_ID,
  44         GPLL_ID,
  45         NPLL_ID,
  46         END_PLL_ID,
  47 };
  48
  49 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
  50 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
  51 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
  52
  53
  54 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
  55 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
  56
  57 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
  58 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
  59 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
  60
  61
  62 /*******************************gpio define **********************************************/
  63
  64 /* GPIO control registers */
  65 #define GPIO_SWPORT_DR          0x00
  66 #define GPIO_SWPORT_DDR         0x04
  67 #define GPIO_INTEN                      0x30
  68 #define GPIO_INTMASK            0x34
  69 #define GPIO_INTTYPE_LEVEL      0x38
  70 #define GPIO_INT_POLARITY       0x3c
  71 #define GPIO_INT_STATUS         0x40
  72 #define GPIO_INT_RAWSTATUS      0x44
  73 #define GPIO_DEBOUNCE           0x48
  74 #define GPIO_PORTS_EOI          0x4c
  75 #define GPIO_EXT_PORT           0x50
  76 #define GPIO_LS_SYNC            0x60
  77
  78 /***********************************sleep func*********************************************/
  79
  80 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
  81 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
  82 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
  83
  84 // sys resume code in boot ram
  85 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
  86 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
  87
  88
  89 // sys resume data in boot ram
  90 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
  91 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
  92
  93 // ddr resume data in boot ram
  94 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
  95 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
  96
  97 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
  98
  99 // the value is used to control cpu resume flow
 100 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 101 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
 102 static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);
 103
 104
 105
 106 #define BOOT_RAM_SIZE   (4*1024)
 107 #define INT_RAM_SIZE            (64*1024)
 108
 109 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
 110 static char int_ram_data[INT_RAM_SIZE];
 111
 112 char * ddr_get_resume_code_info(u32 *size);
 113 char * ddr_get_resume_data_info(u32 *size);
 114
 115 /**
 116 ddr code and data
 117
 118 *** code start
 119 ---data offset--
 120 ---code----
 121 ---data----
 122 */
 123 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
 124 {
 125
 126         char *addr_base,*addr_phy,*data_src,*data_dst;
 127         u32 sr_size,data_size;
 128
 129         addr_base=(char *)RKPM_BOOTRAM_BASE;
 130         addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 131         sr_size=RKPM_BOOTRAM_SIZE;
 132
 133         // save boot sram
 134          if(boot_save)
 135                  memcpy(boot_save,addr_base, sr_size);
 136
 137         // move resume code and date to boot sram
 138         // move sys code
 139         data_dst=(char *)RKPM_BOOT_CODE_BASE;
 140         data_src=(char *)rkpm_slp_cpu_resume;
 141         data_size=RKPM_BOOT_CODE_SIZE;
 142         memcpy((char *)data_dst,(char *)data_src, data_size);
 143
 144         // move sys data
 145         data_dst=(char *)resume_data_base;
 146         data_src=(char *)sleep_resume_data;
 147         data_size=sizeof(sleep_resume_data);
 148         memcpy((char *)data_dst,(char *)data_src, data_size);
 149
 150         if(flag)
 151         {
 152                 /*************************ddr code cpy*************************************/
 153                 // ddr code
 154                 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
 155                 data_src=(char *)ddr_get_resume_code_info(&data_size);
 156
 157                 data_size=RKPM_ALIGN(data_size,4);
 158
 159                 memcpy((char *)data_dst,(char *)data_src, data_size);
 160
 161                 // ddr data
 162                 data_dst=(char *)(data_dst+data_size);
 163
 164                 data_src=(char *)ddr_get_resume_data_info(&data_size);
 165                 data_size=RKPM_ALIGN(data_size,4);
 166                 memcpy((char *)data_dst,(char *)data_src, data_size);
 167
 168                 /*************************ddr code cpy  end*************************************/
 169                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 170                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 171                 /*************************int mem bak*************************************/
 172                 // int mem
 173                 addr_base=(char *)rockchip_sram_virt;
 174                 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 175                 sr_size=rockchip_sram_size;
 176                 //  rkpm_ddr_printascii("piephy\n");
 177                 //rkpm_ddr_printhex(addr_phy);
 178                 //mmap
 179                 if(int_save)
 180                     memcpy(int_save,addr_base, sr_size);
 181
 182                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 183                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 184         }
 185
 186  }
 187
 188 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
 189 {
 190
 191     char *addr_base,*addr_phy;
 192     u32 sr_size;
 193
 194     addr_base=(char *)RKPM_BOOTRAM_BASE;
 195     addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 196     sr_size=RKPM_BOOTRAM_SIZE;
 197     // save boot sram
 198     if(boot_save)
 199         memcpy(addr_base,boot_save, sr_size);
 200
 201     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 202     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 203
 204     if(flag)
 205     {
 206         // int mem
 207         addr_base=(char *)rockchip_sram_virt;
 208         addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 209         sr_size=rockchip_sram_size;
 210
 211         if(int_save)
 212         memcpy(addr_base, int_save,sr_size);
 213
 214         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 215         outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
 216      }
 217 }
 218
 219 /**************************************gic save and resume**************************/
 220 #define  RK_GICD_BASE (RK_GIC_VIRT)
 221 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 222
 223 #define PM_IRQN_START 32
 224 #define PM_IRQN_END     107//107
 225 static void pm_gic_enable(u32 irqs)
 226 {
 227
 228         int irqstart=0;
 229         u32 bit_off;
 230         void __iomem *reg_off;
 231         unsigned int gic_irqs;
 232
 233         gic_irqs = PM_IRQN_END;
 234         irqstart=PM_IRQN_START;//PM_IRQN_START;
 235
 236         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 237         bit_off=irqs%32;
 238         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 239
 240         dsb();
 241 }
 242
 243 static void rkpm_gic_disable(u32 irqs)
 244 {
 245         int irqstart=0;
 246         u32 bit_off;
 247         void __iomem *reg_off;
 248         unsigned int gic_irqs;
 249
 250         gic_irqs = PM_IRQN_END;
 251         irqstart=PM_IRQN_START;//PM_IRQN_START;
 252
 253         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 254         bit_off=irqs%32;
 255         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 256         dsb();
 257 }
 258
 259 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 260
 261 static u32 slp_gic_save[260+50];
 262
 263
 264 static void rkpm_gic_dist_save(u32 *context)
 265 {
 266      int i = 0,j,irqstart=0;
 267      unsigned int gic_irqs;
 268
 269      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 270      gic_irqs = (gic_irqs + 1) * 32;
 271      if (gic_irqs > 1020)
 272      gic_irqs = 1020;
 273      //printk("gic_irqs=%d\n",gic_irqs);
 274      //gic_irqs = PM_IRQN_END;
 275      irqstart=PM_IRQN_START;//PM_IRQN_START;
 276
 277      i = 0;
 278      //level
 279      for (j = irqstart; j < gic_irqs; j += 16)
 280       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 281      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 282
 283      /*
 284      * Set all global interrupts to this CPU only.
 285      */
 286      for(j = 0; j < gic_irqs; j += 4)
 287          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 288
 289      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 290
 291      //pri
 292      for (j = 0; j < gic_irqs; j += 4)
 293          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 294      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 295
 296
 297
 298
 299      //secure
 300      for (j = 0; j < gic_irqs; j += 32)
 301          context[i++]=readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4) / 32);
 302      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 303
 304      for (j = irqstart; j < gic_irqs; j += 32)
 305          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 306
 307      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 308
 309
 310
 311     #if 0
 312      //disable
 313      for (j = 0; j < gic_irqs; j += 32)
 314          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 315
 316      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 317     #endif
 318      //enable
 319      for (j = 0; j < gic_irqs; j += 32)
 320          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 321
 322         //sram_printhex(j);
 323      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 324
 325
 326
 327      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 328      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 329
 330      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 331      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 332      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 333
 334
 335     #if 0
 336      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 337      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 338      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 339      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 340      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 341     #endif
 342     #if 0  //rk319x is not need
 343
 344      for (j = irqstart; j < gic_irqs; j += 32)
 345      {
 346          writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 347          dsb();
 348
 349      }
 350     #endif
 351
 352 }
 353
 354 static void rkpm_gic_dist_resume(u32 *context)
 355 {
 356
 357          int i = 0,j,irqstart=0;
 358          unsigned int gic_irqs;
 359
 360
 361          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 362          gic_irqs = (gic_irqs + 1) * 32;
 363          if (gic_irqs > 1020)
 364                  gic_irqs = 1020;
 365
 366
 367          //gic_irqs = PM_IRQN_END;
 368          irqstart=PM_IRQN_START;//PM_IRQN_START;
 369
 370          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 371          dsb();
 372          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 373          dsb();
 374          for (j = irqstart; j < gic_irqs; j += 32)
 375          {
 376                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 377                  dsb();
 378          }
 379
 380
 381          i = 0;
 382
 383          //trig
 384          for (j = irqstart; j < gic_irqs; j += 16)
 385          {
 386                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 387                  dsb();
 388          }
 389          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 390
 391          /*
 392          * Set all global interrupts to this CPU only.
 393          */
 394          for (j = 0; j < gic_irqs; j += 4)
 395          {
 396                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 397                  dsb();
 398          }
 399          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 400
 401          //pri
 402          for (j = 0; j < gic_irqs; j += 4)
 403          {
 404                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 405
 406                  dsb();
 407          }
 408          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 409
 410
 411          //secu
 412          for (j = 0; j < gic_irqs; j += 32)
 413          {
 414                  writel_relaxed(context[i++],RK_GICD_BASE + 0x80 + (j * 4 )/ 32);
 415                  #if 0
 416                  sram_printhex((j * 4 )/ 32);
 417
 418                  sram_printch('_');
 419                  sram_printhex(temp);
 420
 421                  sram_printch('_');
 422                  sram_printhex(readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4 )/ 32));
 423                  sram_printch('\n');
 424 #endif
 425
 426                  dsb();
 427          }
 428
 429          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 430
 431
 432          //pending
 433          for (j = irqstart; j < gic_irqs; j += 32)
 434          {
 435                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 436                  i++;
 437                  dsb();
 438          }
 439          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 440
 441
 442          //disable
 443 #if 0
 444          for (j = 0; j < gic_irqs; j += 32)
 445          {
 446                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 447
 448                  dsb();
 449          }
 450          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 451
 452 #else
 453         //for (j = 0; j < gic_irqs; j += 32)
 454                 // writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 455 #endif
 456
 457
 458          //enable
 459          for (j = 0; j < gic_irqs; j += 32)
 460          {
 461                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 462
 463                  dsb();
 464          }
 465         // sram_printhex(j);
 466          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 467
 468          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 469
 470          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 471
 472          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 473
 474          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 475          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 476
 477 }
 478
 479 /**************************************regs save and resume**************************/
 480
 481 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 482 {
 483      u32 i;
 484          u32 cnt=(end_offset-st_offset)/4+1;
 485      for(i=0;i<cnt;i++)
 486      {
 487          data[i]=readl_relaxed(base+st_offset+i*4);
 488      }
 489 }
 490
 491 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 492 {
 493      u32 i;
 494      u32 cnt=(end_offset-st_offset)/4+1;
 495      for(i=0;i<cnt;i++)
 496      {
 497          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 498      }
 499 }
 500
 501 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 502 {
 503         u32 i;
 504         u32 cnt=(end_offset-st_offset)/4+1;
 505          for(i=0;i<cnt;i++)
 506          {
 507                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 508          }
 509 }
 510
 511 /**************************************uarts save and resume**************************/
 512
 513 #define RK3288_UART_NUM (4)
 514
 515 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 516 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 517
 518 static u32 slp_uart_data[RK3288_UART_NUM][10];
 519 static u32 slp_uart_data_flag[RK3288_UART_NUM];
 520
 521
 522 #define UART_DLL        0       /* Out: Divisor Latch Low */
 523 #define UART_DLM        1       /* Out: Divisor Latch High */
 524
 525 #define UART_IER        1
 526 #define UART_FCR        2
 527
 528 #define UART_LCR        3       /* Out: Line Control Register */
 529 #define UART_MCR        4
 530
 531  void slp_uart_save(int ch)
 532  {
 533          int i=0;
 534         void __iomem *b_addr=slp_uart_base[ch];
 535          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 536          u32 gate_reg;
 537          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 538                 return;
 539
 540         if(ch==2)
 541         {
 542             idx=RK3288_CLKGATE_PCLK_UART2;
 543             b_addr=RK_DEBUG_UART_VIRT;
 544         }
 545
 546
 547         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 548         RK3288_CRU_UNGATING_OPS(idx);
 549          i=0;
 550          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 551          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 552
 553          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 554          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 555
 556          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 557          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 558          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 559          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 560
 561         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 562
 563  }
 564
 565  void slp_uart_resume(int ch)
 566  {
 567         int i=0;
 568
 569         u32 temp;
 570         void __iomem *b_addr=slp_uart_base[ch];
 571         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 572         u32 gate_reg;
 573
 574         //rkpm_ddr_printascii("\nch");
 575      //   rkpm_ddr_printhex(b_addr);
 576
 577         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 578             return;
 579
 580         if(ch==2)
 581             idx=RK3288_CLKGATE_PCLK_UART2;
 582
 583         //rkpm_ddr_printhex(ch);
 584
 585         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 586         RK3288_CRU_UNGATING_OPS(idx);
 587
 588          i=0;
 589          temp=slp_uart_data[ch][i++];
 590          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 591
 592          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 593          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 594
 595          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 596
 597          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 598          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 599          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 600
 601          writel_relaxed(temp,b_addr+UART_LCR*4);
 602
 603          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 604  }
 605
 606 /**************************************i2c save and resume**************************/
 607
 608 //#define RK3288_I2C_REG_DUMP
 609 #define RK3288_I2C_NUM (6)
 610 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 611 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 612
 613 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 614
 615 void slp_i2c_save(int ch)
 616 {
 617
 618         void __iomem *b_addr=slp_i2c_base[ch];
 619         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 620         u32 gate_reg;
 621
 622         if(!b_addr)
 623                 return;
 624
 625         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 626         RK3288_CRU_UNGATING_OPS(idx);
 627
 628         #ifdef RK3288_I2C_REG_DUMP
 629         rkpm_ddr_printascii("i2c save");
 630         rkpm_ddr_printhex(ch);
 631         rkpm_ddr_printch('\n');
 632         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 633         #endif
 634
 635         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 636
 637
 638         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 639
 640 }
 641 void slp_i2c_resume(int ch)
 642 {
 643         void __iomem *b_addr=slp_i2c_base[ch];
 644         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 645         u32 gate_reg;
 646
 647         if(!b_addr)
 648                 return;
 649         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 650         RK3288_CRU_UNGATING_OPS(idx);
 651
 652         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 653
 654         #ifdef RK3288_I2C_REG_DUMP
 655         rkpm_ddr_printascii("i2c resume");
 656         rkpm_ddr_printhex(ch);
 657         rkpm_ddr_printch('\n');
 658         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 659         #endif
 660
 661         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 662 }
 663
 664 /**************************************gpios save and resume**************************/
 665 #define RK3288_GPIO_CH (9)
 666 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 667 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 668 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 669
 670 static void gpio_ddr_dump_reg(int ports)
 671 {
 672     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 673
 674     rkpm_ddr_printascii("gpio-");
 675     rkpm_ddr_printhex(ports);
 676     rkpm_ddr_printhex('\n');
 677
 678     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 679     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 680     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 681     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 682     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 683     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 684     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 685     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 686     rkpm_ddr_printhex('\n');
 687
 688     rkpm_ddr_printascii("iomux\n");
 689     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 690
 691     rkpm_ddr_printascii("iomux\n");
 692     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 693
 694 }
 695
 696  static void slp_pin_gpio_save(int ports)
 697  {
 698         int i;
 699         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 700         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 701         u32 gate_reg;
 702
 703         if(ports==0||ports>=RK3288_GPIO_CH)
 704                 return;
 705
 706          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 707          RK3288_CRU_UNGATING_OPS(idx);
 708
 709          //gpio_ddr_dump_reg(ports);
 710          i=0;
 711          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 712          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 713          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 714          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 715          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 716          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 717          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 718          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 719
 720         if(ports>0)
 721         {
 722             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 723             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 724          }
 725
 726
 727         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 728
 729  }
 730
 731  static void slp_pin_gpio_resume (int ports)
 732  {
 733          int i;
 734         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 735         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 736          u32 gate_reg;
 737
 738          if(ports==0||ports>=RK3288_GPIO_CH)
 739                 return;
 740           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 741          RK3288_CRU_UNGATING_OPS(idx);
 742
 743
 744         if(ports>0)
 745         {
 746             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 747             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 748         }
 749
 750         i=0;
 751         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 752         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 753         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 754         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 755         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 756         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 757         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 758         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 759
 760         //gpio_ddr_dump_reg(ports);
 761         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 762
 763  }
 764
 765  static inline u32 rkpm_l2_config(void)
 766  {
 767      u32 l2ctlr;
 768      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 769          return l2ctlr;
 770  }
 771 /**************************************sleep func**************************/
 772
 773 void ddr_reg_save(uint32_t *pArg);
 774 void fiq_glue_resume(void);
 775 void rk30_cpu_resume(void);
 776 void rk30_l2_cache_init_pm(void);
 777 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 778 void ddr_cfg_to_lp_mode(void);
 779 void l2x0_inv_all_pm(void);
 780 void rk30_cpu_while_tst(void);
 781
 782 #if 0
 783 static u32 slp_grf_soc_con_data[5];
 784 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 785
 786 static u32 slp_grf_cpu_con_data[5];
 787 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 788
 789 static u32 slp_grf_uoc0_con_data[4];
 790 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 791
 792 static u32 slp_grf_uoc1_con_data[2];
 793 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 794
 795 static u32 slp_grf_uoc2_con_data[2];
 796 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 797
 798 static u32 slp_grf_uoc3_con_data[2];
 799 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 800
 801 #endif
 802 static u32 slp_pmu_pwrmode_con_data[1];
 803
 804
 805 static u32 slp_nandc_data[8];
 806 static void __iomem *rk30_nandc_base=NULL;
 807
 808 #define MS_37K (37)
 809 #define US_24M (24)
 810
 811 void inline pm_io_base_map(void)
 812 {
 813         int i;
 814         for(i=0;i<RK3288_I2C_NUM;i++)
 815             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 816
 817         for(i=0;i<RK3288_UART_NUM;i++)
 818             {
 819                 if(i!=CONFIG_RK_DEBUG_UART)
 820                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 821                 else
 822                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 823             }
 824
 825 }
 826 enum rk3288_pwr_mode_con {
 827
 828         pmu_pwr_mode_en=0,
 829         pmu_clk_core_src_gate_en,
 830         pmu_global_int_disable,
 831         pmu_l2flush_en,
 832
 833         pmu_bus_pd_en,
 834         pmu_a12_0_pd_en,
 835         pmu_scu_en,
 836         pmu_pll_pd_en,
 837
 838         pmu_chip_pd_en, // power off pin enable
 839         pmu_pwroff_comb,
 840         pmu_alive_use_lf,
 841         pmu_pmu_use_lf,
 842
 843         pmu_osc_24m_dis,
 844         pmu_input_clamp_en,
 845         pmu_wakeup_reset_en,
 846         pmu_sref0_enter_en,
 847
 848         pmu_sref1_enter_en,
 849         pmu_ddr0io_ret_en,
 850         pmu_ddr1io_ret_en,
 851         pmu_ddr0_gating_en,
 852
 853         pmu_ddr1_gating_en,
 854         pmu_ddr0io_ret_de_req,
 855         pmu_ddr1io_ret_de_req
 856
 857 };
 858  enum rk3288_pwr_mode_con1 {
 859
 860         pmu_clr_bus=0,
 861         pmu_clr_core,
 862         pmu_clr_cpup,
 863         pmu_clr_alive,
 864
 865         pmu_clr_dma,
 866         pmu_clr_peri,
 867         pmu_clr_gpu,
 868         pmu_clr_video,
 869         pmu_clr_hevc,
 870         pmu_clr_vio
 871
 872 };
 873  static u32 rk3288_powermode=0;
 874
 875 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 876
 877 static u32 sgrf_soc_con0,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 878
 879 static u32  rkpm_slp_mode_set(u32 ctrbits)
 880 {
 881     u32 mode_set,mode_set1;
 882
 883     // setting gpio0_a0 arm off pin
 884
 885     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 886
 887     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 888     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 889     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 890
 891     //mode_set1=pmu_pwr_mode_con1;
 892     //mode_set=pmu_pwr_mode_con0;
 893
 894    //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 895    pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
 896
 897     // enable boot ram
 898     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 899     dsb();
 900
 901     reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 902     dsb();
 903
 904     mode_set=  BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
 905      mode_set1=0;
 906
 907     if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
 908     {
 909         rkpm_ddr_printascii("-autoidle-");
 910         mode_set|=BIT(pmu_clk_core_src_gate_en);
 911     }
 912     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
 913     {
 914         rkpm_ddr_printascii("-armdp-");
 915         mode_set|=BIT(pmu_a12_0_pd_en);
 916     }
 917     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
 918     {
 919         rkpm_ddr_printascii("-armoff-");
 920         mode_set|=BIT(pmu_scu_en)
 921                             //|BIT(pmu_a12_0_pd_en)
 922                             |BIT(pmu_clk_core_src_gate_en) // »½ÐÑºóÒì³£
 923                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 924                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 925                             //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 926                             |BIT(pmu_chip_pd_en);
 927         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 928                                 |BIT(pmu_clr_alive)
 929                                 |BIT(pmu_clr_peri)
 930                                 |BIT(pmu_clr_bus)
 931                                 |BIT(pmu_clr_dma)
 932                                 ;
 933     }
 934     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
 935     {
 936
 937         rkpm_ddr_printascii("-armoff-logdp-");
 938
 939         mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
 940                             |BIT(pmu_chip_pd_en)
 941                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 942                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 943                             |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 944                             |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)
 945                             ;
 946         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 947                            |BIT(pmu_clr_alive)
 948                            |BIT(pmu_clr_peri)
 949                            |BIT(pmu_clr_bus)
 950                            |BIT(pmu_clr_dma)
 951                           ;
 952
 953     }
 954     else
 955     {
 956         mode_set=0;
 957         mode_set1=0;
 958     }
 959
 960
 961     if(mode_set&BIT(pmu_osc_24m_dis))
 962     {
 963         rkpm_ddr_printascii("osc_off");
 964         pmu_writel(32*30,RK3288_PMU_OSC_CNT);
 965         pmu_writel(32*30,RK3288_PMU_STABL_CNT);
 966     }
 967     else
 968     {
 969         pmu_writel(24*1000*10,RK3288_PMU_STABL_CNT);
 970
 971        // pmu_writel(24*1000*20,RK3288_PMU_CORE_PWRDWN_CNT);
 972     }
 973
 974     if(mode_set&BIT(pmu_ddr0io_ret_en))
 975     {
 976         rkpm_ddr_printascii("ddrc_off");
 977         ddr_pin_set_fun(0x0,0xa,0x1,0x1);
 978         ddr_pin_set_fun(0x0,0xa,0x2,0x1);
 979         ddr_pin_set_fun(0x0,0xa,0x3,0x1);
 980     }
 981
 982     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
 983     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
 984
 985   //  rkpm_ddr_printhex(mode_set);
 986   //  rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
 987
 988     return (pmu_readl(RK3288_PMU_PWRMODE_CON));
 989 }
 990
 991 static inline void  rkpm_slp_mode_set_resume(void)
 992 {
 993
 994     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
 995     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
 996     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 997
 998 }
 999
1000 static void sram_code_data_save(u32 pwrmode)
1001 {
1002         char *code_src,*data_src;
1003         u32 code_size,data_size;
1004         u32 ddr_bits= RKPM_CTR_ARMLOGDP_LPMD|RKPM_CTR_ARMOFF_LOGDP_LPMD|RKPM_CTR_ARMLOGOFF_DLPMD;
1005
1006         //u32 *p;
1007         if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1008         {
1009             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1010             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1011             sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1012             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1013         }
1014         else
1015         {
1016             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1017             return ;
1018         }
1019
1020         if(pwrmode&BIT(pmu_bus_pd_en))
1021         {
1022                 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1023                 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1024                 code_src=(char *)ddr_get_resume_code_info(&code_size);
1025                 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1026                 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1027                 data_src=(char *)ddr_get_resume_data_info(&data_size);
1028                 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1029        }
1030         else
1031         {
1032             sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1033         }
1034
1035         sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1036
1037         flush_cache_all();
1038         outer_flush_all();
1039         local_flush_tlb_all();
1040
1041 }
1042
1043 static inline void sram_code_data_resume(u32 pwrmode)
1044 {
1045          if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1046         {
1047              sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1048         }
1049
1050 }
1051
1052 static void  rkpm_peri_save(u32 power_mode)
1053 {
1054     u32 gpio_gate[2];
1055
1056     if(power_mode&BIT(pmu_scu_en))
1057     {
1058         rkpm_gic_dist_save(&slp_gic_save[0]);
1059     }
1060 #if 0
1061     gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1062     gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1063     RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1064     cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1065                          RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1066 #endif
1067
1068     if(power_mode&BIT(pmu_bus_pd_en))
1069    {
1070        #if 0
1071         //gpio7_c6
1072         //gpio7_c7
1073         ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1074         ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1075         ddr_pin_set_fun(7,0xc,0x6,0);
1076
1077         ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1078         ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1079         ddr_pin_set_fun(7,0xc,0x7,0);
1080         #endif
1081         slp_uart_save(2);
1082     #if 0
1083         ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1084         ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1085         ddr_pin_set_fun(0,0xb,0x7,0);
1086
1087         ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1088         ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1089         ddr_pin_set_fun(0,0xc,0x0,0);
1090         #endif
1091         slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1092         //slp_i2c_save(2);//i2c audio
1093     }
1094
1095 #if 0
1096         cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1097                                       RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1098         cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1099 #endif
1100
1101 }
1102
1103 static inline void  rkpm_peri_resume(u32 power_mode)
1104 {
1105     if(power_mode&BIT(pmu_scu_en))
1106     {
1107         //fiq_glue_resume();
1108         rkpm_gic_dist_resume(&slp_gic_save[0]);
1109         fiq_glue_resume();
1110         //rkpm_ddr_printascii("gic res");
1111     }
1112     if(power_mode&BIT(pmu_bus_pd_en))
1113    {
1114         slp_i2c_resume(0);// i2c pmu
1115         slp_i2c_resume(2);//i2c audio
1116     }
1117
1118 }
1119
1120 static inline void  rkpm_peri_resume_first(u32 power_mode)
1121 {
1122       if(power_mode&BIT(pmu_bus_pd_en))
1123         slp_uart_resume(2);
1124 }
1125
1126 static void rkpm_slp_setting(void)
1127 {
1128    //rkpm_gic_disable(130);
1129   //  rkpm_gic_disable(132);
1130
1131     //rkpm_ddr_printhex(pmu_readl(RK3288_PMU_WAKEUP_CFG1));
1132     //rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1133 }
1134
1135
1136 static void rkpm_save_setting_resume_first(void)
1137 {
1138         rkpm_peri_resume_first(rk3288_powermode);
1139
1140         // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1141         #if 0
1142         //rk319x_pm_set_power_domain(PD_PERI,true);
1143         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1144         slp_pin_gpio_resume(1);
1145         slp_pin_gpio_resume(2);
1146         slp_pin_gpio_resume(3);
1147         slp_pin_gpio_resume(4);
1148
1149         #if 0
1150         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1151         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1152
1153         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1154         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1155         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1156         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1157         #endif
1158         //sram_printch_uart_enable();
1159         slp_uart_resume(2);
1160        #endif
1161 }
1162
1163
1164
1165 static u32 rk3288_ctrbits=0;
1166
1167 static void rkpm_save_setting(u32 ctrbits)
1168 {
1169         //rk3288_ctrbits=ctrbits;
1170         rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1171         if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1172        {
1173                 sram_code_data_save(rk3288_powermode);
1174                 rkpm_peri_save(rk3288_powermode);
1175         }
1176         else
1177              return ;
1178
1179 }
1180 static void rkpm_save_setting_resume(void)
1181 {
1182
1183          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1184         {
1185             sram_code_data_resume(rk3288_powermode);
1186             rkpm_peri_resume(rk3288_powermode);
1187         }
1188
1189          rkpm_slp_mode_set_resume();
1190
1191 }
1192
1193
1194 /*******************************common code  for rkxxx*********************************/
1195 static void  inline uart_printch(char byte)
1196 {
1197         u32 reg_save[2];
1198         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1199         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1200
1201         if(CONFIG_RK_DEBUG_UART==4)
1202             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1203         if(CONFIG_RK_DEBUG_UART==2)
1204             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1205
1206         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1207         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1208         RK3288_CRU_UNGATING_OPS(u_clk_id);
1209         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1210
1211         rkpm_udelay(1);
1212
1213         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1214         dsb();
1215
1216         /* loop check LSR[6], Transmitter Empty bit */
1217         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1218                 barrier();
1219
1220          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1221          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1222
1223         if (byte == '\n')
1224                 uart_printch('\r');
1225 }
1226
1227 void PIE_FUNC(sram_printch)(char byte)
1228 {
1229         uart_printch(byte);
1230 }
1231
1232 static void pll_udelay(u32 udelay);
1233
1234 static void  ddr_printch(char byte)
1235 {
1236         uart_printch(byte);
1237         pll_udelay(2);
1238 }
1239 /*******************************gpio func*******************************************/
1240 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1241 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1242 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1243 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1244 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1245 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1246 {
1247     u8 off_set;
1248     bank-=0xa;
1249
1250     if(port==0)
1251     {
1252         if(bank>2)
1253             return;
1254
1255         off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1256         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1257     }
1258     else
1259     {
1260
1261         off_set=port*(4*4)+bank*4;
1262         //form RK3288_GRF_GPIO1D_IOMUX
1263          reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1264     }
1265 }
1266
1267 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1268 {
1269     u8 off_set;
1270     bank-=0xa;
1271
1272     if(port==0)
1273     {
1274       if(bank>2)
1275             return 0;
1276         off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1277         return (pmu_readl(off_set)>>(b_gpio*2))&0x3;
1278     }
1279     else
1280     {
1281
1282         off_set=port*(4*4)+bank*4;
1283         //form RK3288_GRF_GPIO1D_IOMUX
1284          return (reg_readl(RK_GRF_VIRT+0+off_set)>>(b_gpio*2))&0x3;
1285     }
1286 }
1287
1288 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1289 {
1290     u8 off_set;
1291
1292     bank-=0xa;
1293
1294     if(port > 0)
1295     {
1296         //gpio1_d st
1297         if(port==1&&bank<3)
1298          return;
1299         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1300         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1301         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1302
1303     }
1304     else
1305     {
1306         if(bank>2)// gpio0_d is not support
1307             return;
1308         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1309     }
1310
1311 }
1312
1313 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1314 {
1315     u8 off_set;
1316
1317     bank-=0xa;
1318
1319     if(port > 0)
1320     {
1321         //gpio1_d st
1322         if(port==1&&bank<3)
1323             return 0;
1324         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1325         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1326         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1327
1328     }
1329     else
1330     {
1331         if(bank>2)// gpio0_d is not support
1332             return 0;
1333         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1334     }
1335
1336 }
1337
1338
1339 //RKPM_GPIOS_INPUT
1340 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1341 {
1342     u32 val;
1343
1344     bank-=0xa;
1345     b_gpio=bank*8+b_gpio;//
1346
1347     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1348
1349     if(type==RKPM_GPIO_OUTPUT)
1350         val|=(0x1<<b_gpio);
1351     else
1352         val&=~(0x1<<b_gpio);
1353
1354     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1355 }
1356
1357 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1358 {
1359     bank-=0xa;
1360     b_gpio=bank*8+b_gpio;
1361     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1362 }
1363
1364 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1365 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1366 {
1367     u32 val;
1368
1369     bank-=0xa;
1370     b_gpio=bank*8+b_gpio;
1371
1372     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1373
1374     if(level==RKPM_GPIO_OUT_H)
1375         val|=(0x1<<b_gpio);
1376     else //
1377         val&=~(0x1<<b_gpio);
1378
1379      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1380 }
1381
1382 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1383 {
1384     bank-=0xa;
1385     b_gpio=bank*8+b_gpio;
1386     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1387 }
1388
1389 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1390 {
1391
1392     bank-=0xa;
1393     b_gpio=bank*8+b_gpio;
1394
1395     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1396 }
1397 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1398 {
1399     u32 val;
1400
1401     bank-=0xa;
1402     b_gpio=bank*8+b_gpio;
1403
1404     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1405     rkpm_ddr_printascii("\n inten:");
1406     rkpm_ddr_printhex(val);
1407
1408     rkpm_ddr_printascii("-");
1409     if(en==1)
1410         val|=(0x1<<b_gpio);
1411     else //
1412         val&=~(0x1<<b_gpio);
1413
1414     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1415     dsb();
1416
1417      rkpm_ddr_printhex(val);
1418      rkpm_ddr_printascii("-");
1419
1420      rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1421
1422     rkpm_ddr_printascii("\n");
1423
1424
1425 }
1426
1427 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1428 {
1429         pin_set_fun(port,bank,b_gpio,fun);
1430 }
1431 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1432 {
1433     return pin_get_funset(port,bank,b_gpio);
1434 }
1435
1436 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1437 {
1438         pin_set_pull(port,bank,b_gpio,fun);
1439 }
1440 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1441 {
1442     return pin_get_pullset(port,bank,b_gpio);
1443 }
1444
1445 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1446 {
1447     gpio_set_in_output(port,bank,b_gpio,type);
1448 }
1449
1450 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1451 {
1452     return gpio_get_in_outputset(port,bank,b_gpio);
1453 }
1454
1455 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1456 {
1457
1458     gpio_set_output_level(port,bank,b_gpio,level);
1459
1460 }
1461
1462 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1463 {
1464     return gpio_get_output_levelset(port,bank,b_gpio);
1465 }
1466
1467 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1468 {
1469     return gpio_get_input_level(port,bank,b_gpio);
1470 }
1471 //ddr
1472 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1473 {
1474         pin_set_fun(port,bank,b_gpio,fun);
1475 }
1476 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1477 {
1478     return pin_get_funset(port,bank,b_gpio);
1479 }
1480
1481 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1482 {
1483         pin_set_pull(port,bank,b_gpio,fun);
1484 }
1485 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1486 {
1487     return pin_get_pullset(port,bank,b_gpio);
1488 }
1489
1490 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1491 {
1492     gpio_set_in_output(port,bank,b_gpio,type);
1493 }
1494
1495 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1496 {
1497     return gpio_get_in_outputset(port,bank,b_gpio);
1498 }
1499
1500 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1501 {
1502     gpio_set_output_level(port,bank,b_gpio,level);
1503 }
1504
1505 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1506 {
1507     return gpio_get_output_levelset(port,bank,b_gpio);
1508 }
1509
1510 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1511 {
1512     return gpio_get_input_level(port,bank,b_gpio);
1513 }
1514
1515
1516
1517 static  void __sramfunc rkpm_pin_gpio_config_sram(u32 pin_gpio_bits,u32 *save_bits)
1518 {
1519
1520     u32 pins;
1521     u8 port,bank,b_gpio,fun,in_out, level, pull;
1522
1523     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1524     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1525     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1526     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1527
1528     port=RKPM_PINBITS_PORT(pins);
1529     bank=RKPM_PINBITS_BANK(pins);
1530     b_gpio=RKPM_PINBITS_BGPIO(pins);
1531     fun=RKPM_PINBITS_FUN(pins);
1532
1533     //save pins info
1534     if(save_bits)
1535     {
1536         pins=RKPM_PINBITS_SET_FUN(pins,sram_pin_get_funset(port,bank,b_gpio));
1537        *save_bits=RKPM_PINGPIO_BITS(pins,sram_pin_get_pullset(port,bank,b_gpio),sram_gpio_get_in_outputset(port,bank,b_gpio),
1538                                                                                         sram_gpio_get_output_levelset(port,bank,b_gpio));
1539     }
1540     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1541    {
1542         if(level==RKPM_GPIO_OUT_L)
1543             pull=RKPM_GPIO_PULL_DN;
1544         else
1545             pull=RKPM_GPIO_PULL_UP;
1546
1547         sram_gpio_set_output_level(port,bank,b_gpio,level);
1548     }
1549
1550     sram_pin_set_pull(port,bank,b_gpio,pull);
1551     sram_pin_set_fun(port,bank,b_gpio,fun);
1552
1553     if(!fun)
1554     {
1555         sram_gpio_set_in_output(port,bank,b_gpio,in_out);
1556     }
1557
1558 }
1559
1560 static inline void rkpm_pin_gpio_config_ddr(u32 pin_gpio_bits,u32 *save_bits)
1561 {
1562
1563     u32 pins;
1564     u8 port,bank,b_gpio,fun,in_out, level, pull;
1565
1566     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1567     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1568     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1569     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1570
1571     port=RKPM_PINBITS_PORT(pins);
1572     bank=RKPM_PINBITS_BANK(pins);
1573     b_gpio=RKPM_PINBITS_BGPIO(pins);
1574     fun=RKPM_PINBITS_FUN(pins);
1575
1576     //save pins info
1577     if(save_bits)
1578     {
1579         pins=RKPM_PINBITS_SET_FUN(pins,ddr_pin_get_funset(port,bank,b_gpio));
1580        *save_bits=RKPM_PINGPIO_BITS(pins,ddr_pin_get_pullset(port,bank,b_gpio),ddr_gpio_get_in_outputset(port,bank,b_gpio),
1581                                                                                         ddr_gpio_get_output_levelset(port,bank,b_gpio));
1582     }
1583     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1584    {
1585         if(level==RKPM_GPIO_OUT_L)
1586             pull=RKPM_GPIO_PULL_DN;
1587         else
1588             pull=RKPM_GPIO_PULL_UP;
1589
1590         ddr_gpio_set_output_level(port,bank,b_gpio,level);
1591     }
1592
1593     ddr_pin_set_pull(port,bank,b_gpio,pull);
1594     ddr_pin_set_fun(port,bank,b_gpio,fun);
1595
1596     if(!fun)
1597     {
1598         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1599     }
1600
1601 }
1602
1603
1604 #define GPIO_DTS_NUM 10
1605
1606 static  u32 gpio_dts_save[GPIO_DTS_NUM];
1607 static  u32 gpio_dts[GPIO_DTS_NUM];
1608
1609 #define PMICGPIO_DTS_NUM 3
1610
1611
1612 u32 DEFINE_PIE_DATA(pmicgpio_dts[PMICGPIO_DTS_NUM]);
1613 static u32 *p_pmicgpio_dts;
1614 static __sramdata u32 pmicgpio_dts_save[PMICGPIO_DTS_NUM];
1615
1616 static void __sramfunc pmic_gpio_suspend(void)
1617 {
1618        int i;
1619        for(i=0;;i++)
1620        {
1621             if(DATA(pmicgpio_dts[i]))
1622                 rkpm_pin_gpio_config_sram(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1623             else
1624             {
1625                     pmicgpio_dts_save[i]=0;
1626                     break;
1627              }
1628        }
1629     #if 0
1630          for(i=0;i<6;i++)
1631         {
1632             rkpm_sram_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1633         }
1634         //
1635         rkpm_sram_reg_dump(RK_GRF_VIRT,0xc,0x84);
1636         rkpm_sram_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1637         rkpm_sram_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1638         rkpm_sram_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1639     #endif
1640
1641 }
1642
1643 static void  __sramfunc pmic_gpio_resume(void)
1644 {
1645        int i;
1646        for(i=0;;i++)
1647        {
1648             if(pmicgpio_dts_save[i])
1649                 rkpm_pin_gpio_config_sram(pmicgpio_dts_save[i],NULL);
1650        }
1651
1652 }
1653
1654 void PIE_FUNC(pmic_suspend)(void)
1655 {
1656     pmic_gpio_suspend();
1657
1658 }
1659
1660 void PIE_FUNC(pmic_resume)(void)
1661 {
1662     pmic_gpio_resume();
1663 }
1664
1665
1666 static void  rkpm_gpio_suspend(void)
1667 {
1668        int i;
1669        for(i=0;;i++)
1670        {
1671             if(DATA(pmicgpio_dts[i]))
1672                 rkpm_pin_gpio_config_ddr(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1673             else
1674             {
1675                     pmicgpio_dts_save[i]=0;
1676                     break;
1677              }
1678        }
1679     #if 0
1680          for(i=0;i<6;i++)
1681         {
1682             rkpm_ddr_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1683         }
1684         //
1685         rkpm_ddr_reg_dump(RK_GRF_VIRT,0xc,0x84);
1686         rkpm_ddr_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1687         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1688         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1689     #endif
1690
1691 }
1692
1693 static void  rkpm_gpio_resume(void)
1694 {
1695        int i;
1696        for(i=0;;i++)
1697        {
1698             if(pmicgpio_dts_save[i])
1699                 rkpm_pin_gpio_config_ddr(pmicgpio_dts_save[i],NULL);
1700        }
1701
1702 }
1703 static void gpio_get_dts_info(struct device_node *parent)
1704 {
1705         int i;
1706
1707         for(i=0;i<PMICGPIO_DTS_NUM;i++)
1708             p_pmicgpio_dts[i]=0;
1709
1710         for(i=0;i<GPIO_DTS_NUM;i++)
1711             gpio_dts[i]=0;
1712
1713
1714         p_pmicgpio_dts= kern_to_pie(rockchip_pie_chunk, &DATA(pmicgpio_dts[0]));
1715
1716        if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",p_pmicgpio_dts,PMICGPIO_DTS_NUM))
1717        {
1718                 p_pmicgpio_dts[0]=0;
1719                PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1720        }
1721
1722        for(i=0;i<PMICGPIO_DTS_NUM;i++)
1723             printk("%s:pmic gpio(%x)\n",__FUNCTION__,p_pmicgpio_dts[i]);
1724
1725         if(of_property_read_u32_array(parent,"rockchip,pm-gpios",gpio_dts,GPIO_DTS_NUM))
1726         {
1727                  gpio_dts[0]=0;
1728                 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1729         }
1730         for(i=0;i<GPIO_DTS_NUM;i++)
1731          printk("%s:pmic gpio(%x)\n",__FUNCTION__,gpio_dts[i]);
1732
1733     rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1734     rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_suspend)),
1735                   fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_resume)));
1736
1737 }
1738
1739
1740 /*******************************clk gating config*******************************************/
1741 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1742 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1743
1744
1745 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1746 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1747 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1748
1749
1750 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1751 static u32 *p_rkpm_clkgt_last_set;
1752
1753 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1754
1755 void PIE_FUNC(gtclks_sram_suspend)(void)
1756 {
1757     int i;
1758    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1759    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1760
1761     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1762     {
1763         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1764         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1765         #if 0
1766         rkpm_sram_printch('\n');
1767         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1768         rkpm_sram_printch('-');
1769         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1770         rkpm_sram_printch('-');
1771         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1772         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1773         rkpm_sram_printch('\n');
1774         #endif
1775     }
1776
1777         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1778         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1779
1780 }
1781
1782 void PIE_FUNC(gtclks_sram_resume)(void)
1783 {
1784     int i;
1785     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1786     {
1787         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1788     }
1789 }
1790
1791 static void gtclks_suspend(void)
1792 {
1793     int i;
1794
1795   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1796                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1797     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1798     {
1799             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1800            // 160 1a8
1801            #if 0
1802            if(
1803                // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1804                 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1805                 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1806               //  RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1807                 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1808                // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1809                // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1810
1811
1812                 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1813                // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1814                // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1815                // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1816                 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1817                 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
1818                 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
1819                 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
1820                 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
1821                 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
1822                 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
1823                // RK3288_CRU_CLKGATES_CON(i)==0x1a8
1824                RK3288_CRU_CLKGATES_CON(i)==0xfff
1825             )
1826             {
1827
1828                  cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1829                // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
1830
1831             }
1832            else
1833             #endif
1834             {
1835                // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
1836                CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
1837            }
1838            #if 0
1839             rkpm_ddr_printch('\n');
1840             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
1841             rkpm_ddr_printch('-');
1842             rkpm_ddr_printhex(clk_ungt_msk[i]);
1843             rkpm_ddr_printch('-');
1844             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
1845             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1846             rkpm_ddr_printch('\n');
1847             #endif
1848     }
1849
1850 }
1851
1852 static void gtclks_resume(void)
1853 {
1854     int i;
1855      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1856     {
1857        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
1858      }
1859      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1860                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1861
1862 }
1863 /********************************pll power down***************************************/
1864
1865 static void pm_pll_wait_lock(u32 pll_idx)
1866 {
1867         u32 delay = 600000U;
1868        // u32 mode;
1869      //  mode=cru_readl(RK3288_CRU_MODE_CON);
1870         dsb();
1871         dsb();
1872         dsb();
1873         dsb();
1874         dsb();
1875         dsb();
1876         while (delay > 0) {
1877                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
1878                         break;
1879                 delay--;
1880         }
1881         if (delay == 0) {
1882                 rkpm_ddr_printascii("unlock-pll:");
1883                 rkpm_ddr_printhex(pll_idx);
1884                 rkpm_ddr_printch('\n');
1885         }
1886     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
1887 }
1888
1889 static void pll_udelay(u32 udelay)
1890 {
1891     u32 mode;
1892     mode=cru_readl(RK3288_CRU_MODE_CON);
1893     // delay in 24m
1894     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
1895
1896     rkpm_udelay(udelay*5);
1897
1898     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
1899 }
1900
1901 static u32 plls_con0_save[END_PLL_ID];
1902 static u32 plls_con1_save[END_PLL_ID];
1903 static u32 plls_con2_save[END_PLL_ID];
1904 static u32 plls_con3_save[END_PLL_ID];
1905
1906 static u32 cru_mode_con;
1907
1908 static inline void plls_suspend(u32 pll_id)
1909 {
1910     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
1911     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
1912     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
1913     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
1914
1915     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
1916
1917 }
1918 static inline void plls_resume(u32 pll_id)
1919 {
1920         u32 pllcon0, pllcon1, pllcon2;
1921
1922         if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
1923             return ;
1924
1925         //enter slowmode
1926         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
1927
1928         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
1929         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
1930
1931         pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
1932         pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
1933         pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
1934
1935         //enter rest
1936         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
1937         cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
1938         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
1939         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
1940
1941         pll_udelay(5);
1942         //udelay(5); //timer7 delay
1943
1944         //return form rest
1945         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
1946
1947         //wating lock state
1948         pll_udelay(168);
1949         pm_pll_wait_lock(pll_id);
1950
1951         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
1952
1953 }
1954
1955 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
1956
1957 static void pm_plls_suspend(void)
1958 {
1959
1960    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
1961    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
1962    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
1963
1964     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
1965     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
1966     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
1967     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
1968     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
1969     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
1970     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
1971
1972     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
1973
1974
1975     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
1976     plls_suspend(NPLL_ID);
1977
1978 // cpll
1979     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
1980
1981 // gpll
1982     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
1983
1984     // set 1,pdbus pll is gpll
1985     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
1986
1987     // pd_bus clk
1988     cru_writel(0
1989                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
1990                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
1991                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
1992                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
1993                      , RK3288_CRU_CLKSELS_CON(1));
1994
1995     //crypto for pd_bus
1996     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
1997
1998     // peri aclk hclk pclk
1999     cru_writel(0
2000                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2001                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
2002                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
2003                         , RK3288_CRU_CLKSELS_CON(10));
2004     // pmu alive
2005     cru_writel(clk_sel33|CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2006
2007     plls_suspend(CPLL_ID);
2008     plls_suspend(GPLL_ID);
2009
2010 //apll
2011    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2012      // core_m0 core_mp a12_core
2013     cru_writel(0
2014                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
2015                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
2016                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2017                       , RK3288_CRU_CLKSELS_CON(0));
2018     // core0 core1 core2 core3
2019     cru_writel(0
2020                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2021                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2022                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2023                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2024                       , RK3288_CRU_CLKSELS_CON(36));
2025     // l2ram atclk pclk
2026     #if 1
2027     cru_writel(0
2028                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2029                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2030                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2031                      , RK3288_CRU_CLKSELS_CON(37));
2032     #else
2033     cru_writel(0
2034                       |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2035                       |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2036                        |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2037                        , RK3288_CRU_CLKSELS_CON(37));
2038     #endif
2039
2040
2041     plls_suspend(APLL_ID);
2042
2043 }
2044
2045 static void pm_plls_resume(void)
2046 {
2047
2048
2049         // core_m0 core_mp a12_core
2050         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
2051         // core0 core1 core2 core3
2052         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
2053                         , RK3288_CRU_CLKSELS_CON(36));
2054         // l2ram atclk pclk
2055         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
2056
2057         plls_resume(APLL_ID);
2058         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2059
2060         // peri aclk hclk pclk
2061         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
2062                                                                             , RK3288_CRU_CLKSELS_CON(10));
2063         //pd bus gpll sel
2064         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
2065         // pd_bus clk
2066         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
2067                     , RK3288_CRU_CLKSELS_CON(1));
2068
2069         // crypto
2070         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
2071
2072
2073           // pmu alive
2074         cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2075
2076         plls_resume(GPLL_ID);
2077         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
2078
2079         plls_resume(CPLL_ID);
2080         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
2081
2082         plls_resume(NPLL_ID);
2083         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2084
2085        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2086        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2087        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2088
2089 }
2090
2091 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2092
2093 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2094 {
2095
2096     int div;
2097     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2098     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2099     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2100
2101
2102     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2103     {
2104         div=3;
2105         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2106         cru_writel(0
2107                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2108                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2109                             , RK3288_CRU_MODE_CON);
2110     }
2111     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2112     {
2113         div=31;
2114     }
2115
2116     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2117     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2118     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2119
2120 }
2121
2122 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2123 {
2124
2125     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2126     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2127     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2128     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2129                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2130                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2131                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2132
2133 }
2134
2135
2136 static void clks_gating_suspend_init(void)
2137 {
2138     // get clk gating info
2139     if(rockchip_pie_chunk)
2140         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2141     else
2142         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2143     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2144         ==RK3288_CRU_CLKGATES_CON(0))
2145     {
2146         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2147         if(rockchip_pie_chunk)
2148             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2149                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2150
2151         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2152
2153     }
2154     if(rockchip_pie_chunk)
2155         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2156                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2157 }
2158
2159 /***************************prepare and finish reg_pread***********************************/
2160
2161
2162
2163 #define GIC_DIST_PENDING_SET            0x200
2164 #define DUMP_GPIO_INT_STATUS(ID) \
2165 do { \
2166         if (irq_gpio & (1 << ID)) \
2167                 printk("wakeup gpio" #ID ": %08x\n", readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INT_STATUS)); \
2168 } while (0)
2169 static noinline void rk30_pm_dump_irq(void)
2170 {
2171         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2172         printk("wakeup irq: %08x %08x %08x %08x\n",
2173                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 4),
2174                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 8),
2175                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12),
2176                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 16));
2177         DUMP_GPIO_INT_STATUS(0);
2178         DUMP_GPIO_INT_STATUS(1);
2179         DUMP_GPIO_INT_STATUS(2);
2180         DUMP_GPIO_INT_STATUS(3);
2181         DUMP_GPIO_INT_STATUS(4);
2182         DUMP_GPIO_INT_STATUS(5);
2183         DUMP_GPIO_INT_STATUS(6);
2184         DUMP_GPIO_INT_STATUS(7);
2185         DUMP_GPIO_INT_STATUS(8);
2186
2187 }
2188
2189 #define DUMP_GPIO_INTEN(ID) \
2190 do { \
2191         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2192         if (en) { \
2193                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2194                 rkpm_ddr_printhex(en); \
2195                 rkpm_ddr_printch('\n'); \
2196                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2197         } \
2198 } while (0)
2199
2200 //dump while irq is enable
2201 static noinline void rk30_pm_dump_inten(void)
2202 {
2203         DUMP_GPIO_INTEN(0);
2204         DUMP_GPIO_INTEN(1);
2205         DUMP_GPIO_INTEN(2);
2206         DUMP_GPIO_INTEN(3);
2207         DUMP_GPIO_INTEN(4);
2208         DUMP_GPIO_INTEN(5);
2209         DUMP_GPIO_INTEN(6);
2210         DUMP_GPIO_INTEN(7);
2211         DUMP_GPIO_INTEN(8);
2212 }
2213
2214 static  void rkpm_prepare(void)
2215 {
2216         #if 0
2217         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2218
2219        // rkpm_ddr_printhex(temp);
2220         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2221         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2222        // rkpm_ddr_printhex(temp);
2223         #endif
2224         // dump GPIO INTEN for debug
2225         rk30_pm_dump_inten();
2226 }
2227
2228 static void rkpm_finish(void)
2229 {
2230         rk30_pm_dump_irq();
2231 }
2232
2233
2234 static  void interface_ctr_reg_pread(void)
2235 {
2236         //u32 addr;
2237         flush_cache_all();
2238         outer_flush_all();
2239         local_flush_tlb_all();
2240         #if 0  // do it in ddr suspend
2241         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2242                 readl_relaxed(addr);
2243         #endif
2244         readl_relaxed(RK_PMU_VIRT);
2245         readl_relaxed(RK_GRF_VIRT);
2246         readl_relaxed(RK_DDR_VIRT);
2247         readl_relaxed(RK_GPIO_VIRT(0));
2248         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2249         //readl_relaxed(RK_GPIO_VIRT(3));
2250 }
2251 void PIE_FUNC(ddr_leakage_tst)(void)
2252 {
2253     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2254     rkpm_sram_printch('\n');
2255     rkpm_sram_printch('t');
2256     rkpm_sram_printch('e');
2257     rkpm_sram_printch('s');
2258     rkpm_sram_printch('t');
2259     while(1);
2260 }
2261
2262 static void __init  rk3288_suspend_init(void)
2263 {
2264     struct device_node *parent;
2265     u32 pm_ctrbits;
2266
2267     PM_LOG("%s enter\n",__FUNCTION__);
2268
2269     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2270
2271     if (IS_ERR_OR_NULL(parent)) {
2272                 PM_ERR("%s dev node err\n", __func__);
2273                 return;
2274         }
2275
2276
2277     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2278     {
2279             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2280             return ;
2281     }
2282     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2283     pm_io_base_map();
2284     memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2285     rkpm_set_ctrbits(pm_ctrbits);
2286
2287     clks_gating_suspend_init();
2288
2289     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2290
2291     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2292
2293     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2294
2295     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2296
2297      rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2298      rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2299
2300     if(rockchip_pie_chunk)
2301         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2302
2303     rkpm_set_ops_printch(ddr_printch);
2304 }