2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <asm/cacheflush.h>
5 #include <asm/tlbflush.h>
6 #include <asm/hardware/cache-l2x0.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/wakeup_reason.h>
11 #include <linux/suspend.h>
15 #include <linux/of_address.h>
17 #include <linux/rockchip/cpu.h>
18 //#include <linux/rockchip/cru.h>
19 #include <linux/rockchip/grf.h>
20 #include <linux/rockchip/iomap.h>
22 #include <linux/irqchip/arm-gic.h>
28 __weak void rk_usb_power_down(void);
29 __weak void rk_usb_power_up(void);
31 //static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
32 //static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
35 /*************************cru define********************************************/
38 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
39 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
50 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
51 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
52 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
55 #define RK3288_PLL_RESET CRU_W_MSK_SETBITS(1,5,0x1)
56 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
58 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
59 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
60 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
62 /*******************************gpio define **********************************************/
64 /* GPIO control registers */
65 #define GPIO_SWPORT_DR 0x00
66 #define GPIO_SWPORT_DDR 0x04
67 #define GPIO_INTEN 0x30
68 #define GPIO_INTMASK 0x34
69 #define GPIO_INTTYPE_LEVEL 0x38
70 #define GPIO_INT_POLARITY 0x3c
71 #define GPIO_INT_STATUS 0x40
72 #define GPIO_INT_RAWSTATUS 0x44
73 #define GPIO_DEBOUNCE 0x48
74 #define GPIO_PORTS_EOI 0x4c
75 #define GPIO_EXT_PORT 0x50
76 #define GPIO_LS_SYNC 0x60
78 /***********************************sleep func*********************************************/
80 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
81 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
82 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
84 // sys resume code in boot ram
85 #define RKPM_BOOT_CODE_PHY (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
86 #define RKPM_BOOT_CODE_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
89 // sys resume data in boot ram
90 #define RKPM_BOOT_DATA_PHY (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
91 #define RKPM_BOOT_DATA_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
93 // ddr resume data in boot ram
94 #define RKPM_BOOT_DDRCODE_PHY (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
95 #define RKPM_BOOT_DDRCODE_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
97 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
99 // the value is used to control cpu resume flow
100 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
101 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
102 static char *resume_data_phy= (char *)( RKPM_BOOT_DATA_PHY);
106 #define BOOT_RAM_SIZE (4*1024)
107 #define INT_RAM_SIZE (64*1024)
109 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
110 static char int_ram_data[INT_RAM_SIZE];
112 char * ddr_get_resume_code_info(u32 *size);
113 char * ddr_get_resume_data_info(u32 *size);
123 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
126 char *addr_base,*addr_phy,*data_src,*data_dst;
127 u32 sr_size,data_size;
129 addr_base=(char *)RKPM_BOOTRAM_BASE;
130 addr_phy=(char *)RKPM_BOOTRAM_PHYS;
131 sr_size=RKPM_BOOTRAM_SIZE;
135 memcpy(boot_save,addr_base, sr_size);
137 // move resume code and date to boot sram
139 data_dst=(char *)RKPM_BOOT_CODE_BASE;
140 data_src=(char *)rkpm_slp_cpu_resume;
141 data_size=RKPM_BOOT_CODE_SIZE;
142 memcpy((char *)data_dst,(char *)data_src, data_size);
145 data_dst=(char *)resume_data_base;
146 data_src=(char *)sleep_resume_data;
147 data_size=sizeof(sleep_resume_data);
148 memcpy((char *)data_dst,(char *)data_src, data_size);
152 /*************************ddr code cpy*************************************/
154 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
155 data_src=(char *)ddr_get_resume_code_info(&data_size);
157 data_size=RKPM_ALIGN(data_size,4);
159 memcpy((char *)data_dst,(char *)data_src, data_size);
162 data_dst=(char *)(data_dst+data_size);
164 data_src=(char *)ddr_get_resume_data_info(&data_size);
165 data_size=RKPM_ALIGN(data_size,4);
166 memcpy((char *)data_dst,(char *)data_src, data_size);
168 /*************************ddr code cpy end*************************************/
169 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
170 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
171 /*************************int mem bak*************************************/
173 addr_base=(char *)rockchip_sram_virt;
174 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
175 sr_size=rockchip_sram_size;
176 // rkpm_ddr_printascii("piephy\n");
177 //rkpm_ddr_printhex(addr_phy);
180 memcpy(int_save,addr_base, sr_size);
182 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
183 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
188 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
191 char *addr_base,*addr_phy;
194 addr_base=(char *)RKPM_BOOTRAM_BASE;
195 addr_phy=(char *)RKPM_BOOTRAM_PHYS;
196 sr_size=RKPM_BOOTRAM_SIZE;
199 memcpy(addr_base,boot_save, sr_size);
201 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
202 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
207 addr_base=(char *)rockchip_sram_virt;
208 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
209 sr_size=rockchip_sram_size;
212 memcpy(addr_base, int_save,sr_size);
214 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
215 outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
219 /**************************************gic save and resume**************************/
220 #define RK_GICD_BASE (RK_GIC_VIRT)
221 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
223 #define PM_IRQN_START 32
224 #define PM_IRQN_END 107//107
225 #if 0 //funciton is ok ,but not used
226 static void pm_gic_enable(u32 irqs)
231 void __iomem *reg_off;
232 unsigned int gic_irqs;
234 gic_irqs = PM_IRQN_END;
235 irqstart=PM_IRQN_START;//PM_IRQN_START;
237 reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
239 writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
244 static void rkpm_gic_disable(u32 irqs)
248 void __iomem *reg_off;
249 unsigned int gic_irqs;
251 gic_irqs = PM_IRQN_END;
252 irqstart=PM_IRQN_START;//PM_IRQN_START;
254 reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
256 writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
260 #define gic_reg_dump(a,b,c) {}//reg_dump((a),(b),(c))
262 static u32 slp_gic_save[260+50];
265 static void rkpm_gic_dist_save(u32 *context)
267 int i = 0,j,irqstart=0;
268 unsigned int gic_irqs;
270 gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
271 gic_irqs = (gic_irqs + 1) * 32;
274 //printk("gic_irqs=%d\n",gic_irqs);
275 //gic_irqs = PM_IRQN_END;
276 irqstart=PM_IRQN_START;//PM_IRQN_START;
280 for (j = irqstart; j < gic_irqs; j += 16)
281 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
282 gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
285 * Set all global interrupts to this CPU only.
287 for(j = 0; j < gic_irqs; j += 4)
288 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET + (j * 4) / 4);
289 gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
292 for (j = 0; j < gic_irqs; j += 4)
293 context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
294 gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
297 for (j = 0; j < gic_irqs; j += 32)
298 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4) / 32);
299 gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
301 for (j = irqstart; j < gic_irqs; j += 32)
302 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
303 gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
307 for (j = 0; j < gic_irqs; j += 32)
308 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
309 gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
313 for (j = 0; j < gic_irqs; j += 32)
314 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
315 gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
319 gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
320 gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
322 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
323 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
324 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
327 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
328 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
329 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
330 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
331 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
335 for (j = irqstart; j < gic_irqs; j += 32)
337 writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
340 writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
341 writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
343 writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
344 writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
349 static void rkpm_gic_dist_resume(u32 *context)
352 int i = 0,j,irqstart=0;
353 unsigned int gic_irqs;
356 gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
357 gic_irqs = (gic_irqs + 1) * 32;
361 //gic_irqs = PM_IRQN_END;
362 irqstart=PM_IRQN_START;//PM_IRQN_START;
364 writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
366 writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
368 for (j = irqstart; j < gic_irqs; j += 32)
370 writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
377 for (j = irqstart; j < gic_irqs; j += 16)
379 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
382 gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
385 * Set all global interrupts to this CPU only.
387 for (j = 0; j < gic_irqs; j += 4)
389 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET + (j * 4) / 4);
392 gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
395 for (j = 0; j < gic_irqs; j += 4)
397 writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
401 gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
405 for (j = 0; j < gic_irqs; j += 32)
407 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4 )/ 32);
410 gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
413 for (j = irqstart; j < gic_irqs; j += 32)
415 //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
419 gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
423 for (j = 0; j < gic_irqs; j += 32)
425 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
428 gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
431 for (j = irqstart; j < gic_irqs; j += 32)
432 writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
433 writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
434 writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
438 for (j = 0; j < gic_irqs; j += 32)
440 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
445 gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
447 writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
448 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
449 writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
451 gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
452 gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
456 /**************************************regs save and resume**************************/
458 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
461 u32 cnt=(end_offset-st_offset)/4+1;
464 data[i]=readl_relaxed(base+st_offset+i*4);
468 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
471 u32 cnt=(end_offset-st_offset)/4+1;
474 reg_writel(data[i]|w_msk,(base+st_offset+i*4));
478 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
481 u32 cnt=(end_offset-st_offset)/4+1;
484 reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
488 /**************************************uarts save and resume**************************/
490 #define RK3288_UART_NUM (4)
492 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
493 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
495 #define UART_DLL 0 /* Out: Divisor Latch Low */
496 #define UART_DLM 1 /* Out: Divisor Latch High */
501 #define UART_LCR 3 /* Out: Line Control Register */
505 static u32 slp_uart_data[RK3288_UART_NUM][10];
506 static u32 slp_uart_data_flag[RK3288_UART_NUM];
508 void slp_uart_save(int ch)
511 void __iomem *b_addr=slp_uart_base[ch];
512 int idx=RK3288_CLKGATE_PCLK_UART0+ch;
514 if(b_addr==NULL || ch>=RK3288_UART_NUM)
519 idx=RK3288_CLKGATE_PCLK_UART2;
520 b_addr=RK_DEBUG_UART_VIRT;
524 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
525 RK3288_CRU_UNGATING_OPS(idx);
527 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
528 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
530 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
531 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
533 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
534 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
535 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
536 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
538 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
542 void slp_uart_resume(int ch)
547 void __iomem *b_addr=slp_uart_base[ch];
548 int idx=RK3288_CLKGATE_PCLK_UART0+ch;
551 //rkpm_ddr_printascii("\nch");
552 // rkpm_ddr_printhex(b_addr);
554 if(b_addr==NULL || ch>=RK3288_UART_NUM)
558 idx=RK3288_CLKGATE_PCLK_UART2;
560 //rkpm_ddr_printhex(ch);
562 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
563 RK3288_CRU_UNGATING_OPS(idx);
566 temp=slp_uart_data[ch][i++];
567 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
569 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
570 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
572 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
574 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
575 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
576 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
578 writel_relaxed(temp,b_addr+UART_LCR*4);
580 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
583 void slp_uartdbg_resume(void)
585 void __iomem *b_addr=RK_DEBUG_UART_VIRT;
586 u32 pclk_id=RK3288_CLKGATE_PCLK_UART2,clk_id=(RK3288_CLKGATE_UART0_SRC+2*2);
590 gate_reg[0]=cru_readl(RK3288_CRU_GATEID_CONS(pclk_id));
591 gate_reg[1]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id));
593 RK3288_CRU_UNGATING_OPS(pclk_id);
594 // 24M is no gating setting
595 ddr_pin_set_fun(0x7,0xc,0x6,0x0);
596 ddr_pin_set_fun(0x7,0xc,0x7,0x0);
600 cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
603 cru_writel(0|CRU_W_MSK_SETBITS(1,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
607 cru_writel(0|CRU_W_MSK_SETBITS(0,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
610 //out clk (form pll) is gating
611 RK3288_CRU_GATING_OPS(clk_id);
612 //out clk form pll gating to disable uart clk out
614 cru_writel(CRU_W_MSK_SETBITS(11,0,0x7f), RK3288_CRU_CLKSELS_CON(15));
619 cru_writel(CRU_W_MSK_SETBITS(0,8,0x3) , RK3288_CRU_CLKSELS_CON(15));
623 reg_writel(0x83,b_addr+UART_LCR*4);
625 reg_writel(0xd,b_addr+UART_DLL*4);
626 reg_writel(0x0,b_addr+UART_DLM*4);
628 reg_writel(0x3,b_addr+UART_LCR*4);
630 reg_writel(0x5,b_addr+UART_IER*4);
631 reg_writel(0xc1,b_addr+UART_FCR*4);
633 rfl_reg=readl_relaxed(b_addr+0x84);
634 lsr_reg=readl_relaxed(b_addr+0x14);
636 }while((rfl_reg&0x1f)||(lsr_reg&0xf));
639 cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
641 ddr_pin_set_fun(0x7,0xc,0x6,0x1);
642 ddr_pin_set_fun(0x7,0xc,0x7,0x1);
643 cru_writel(gate_reg[0]|CRU_W_MSK(pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(pclk_id));
644 cru_writel(gate_reg[1]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
647 /**************************************i2c save and resume**************************/
649 //#define RK3288_I2C_REG_DUMP
650 #define RK3288_I2C_NUM (6)
651 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
652 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
654 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
656 void slp_i2c_save(int ch)
659 void __iomem *b_addr=slp_i2c_base[ch];
660 int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
666 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
667 RK3288_CRU_UNGATING_OPS(idx);
669 #ifdef RK3288_I2C_REG_DUMP
670 rkpm_ddr_printascii("i2c save");
671 rkpm_ddr_printhex(ch);
672 rkpm_ddr_printch('\n');
673 rkpm_ddr_regs_dump(b_addr,0x0,0xc);
676 slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
679 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
682 void slp_i2c_resume(int ch)
684 void __iomem *b_addr=slp_i2c_base[ch];
685 int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
690 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
691 RK3288_CRU_UNGATING_OPS(idx);
693 slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
695 #ifdef RK3288_I2C_REG_DUMP
696 rkpm_ddr_printascii("i2c resume");
697 rkpm_ddr_printhex(ch);
698 rkpm_ddr_printch('\n');
699 rkpm_ddr_regs_dump(b_addr,0x0,0xc);
702 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
705 /**************************************gpios save and resume**************************/
706 #define RK3288_GPIO_CH (9)
707 #if 0 //fun is ok ,not used
709 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
710 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
711 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
712 static void gpio_ddr_dump_reg(int ports)
714 void __iomem *b_addr=RK_GPIO_VIRT(ports);
716 rkpm_ddr_printascii("gpio-");
717 rkpm_ddr_printhex(ports);
718 rkpm_ddr_printhex('\n');
720 rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
721 rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
722 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
723 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
724 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
725 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
726 rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
727 rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
728 rkpm_ddr_printhex('\n');
730 rkpm_ddr_printascii("iomux\n");
731 rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
733 rkpm_ddr_printascii("iomux\n");
734 rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
737 static void slp_pin_gpio_save(int ports)
740 void __iomem *b_addr=RK_GPIO_VIRT(ports);
741 int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
744 if(ports==0||ports>=RK3288_GPIO_CH)
747 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
748 RK3288_CRU_UNGATING_OPS(idx);
750 //gpio_ddr_dump_reg(ports);
752 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
753 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
754 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
755 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
756 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
757 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
758 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
759 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
763 slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
764 slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
768 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
772 static void slp_pin_gpio_resume (int ports)
775 void __iomem *b_addr=RK_GPIO_VIRT(ports);
776 int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
779 if(ports==0||ports>=RK3288_GPIO_CH)
781 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
782 RK3288_CRU_UNGATING_OPS(idx);
787 slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
788 slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
792 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
793 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
794 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
795 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
796 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
797 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
798 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
799 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
801 //gpio_ddr_dump_reg(ports);
802 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
807 static inline u32 rkpm_l2_config(void)
810 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
814 static inline u32 rkpm_armerrata_818325(void)
817 asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (armerrata));
823 /**************************************sleep func**************************/
825 void ddr_reg_save(uint32_t *pArg);
826 void fiq_glue_resume(void);
827 void rk30_cpu_resume(void);
828 void rk30_l2_cache_init_pm(void);
829 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
830 void ddr_cfg_to_lp_mode(void);
831 void l2x0_inv_all_pm(void);
832 void rk30_cpu_while_tst(void);
835 static u32 slp_grf_soc_con_data[5];
836 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
838 static u32 slp_grf_cpu_con_data[5];
839 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
841 static u32 slp_grf_uoc0_con_data[4];
842 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
844 static u32 slp_grf_uoc1_con_data[2];
845 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
847 static u32 slp_grf_uoc2_con_data[2];
848 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
850 static u32 slp_grf_uoc3_con_data[2];
851 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
854 //static u32 slp_pmu_pwrmode_con_data[1];
857 //static u32 slp_nandc_data[8];
858 //static void __iomem *rk30_nandc_base=NULL;
863 void inline pm_io_base_map(void)
866 for(i=0;i<RK3288_I2C_NUM;i++)
867 slp_i2c_base[i] = ioremap(slp_i2c_phy[i], 0x1000);
869 for(i=0;i<RK3288_UART_NUM;i++)
871 if(i!=CONFIG_RK_DEBUG_UART)
872 slp_uart_base[i] = ioremap(slp_uart_phy[i], 0x1000);
874 slp_uart_base[i] = RK_DEBUG_UART_VIRT;
878 enum rk3288_pwr_mode_con {
881 pmu_clk_core_src_gate_en,
882 pmu_global_int_disable,
890 pmu_chip_pd_en, // power off pin enable
906 pmu_ddr0io_ret_de_req,
907 pmu_ddr1io_ret_de_req
910 enum rk3288_pwr_mode_con1 {
925 static u32 rk3288_powermode=0;
926 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
928 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
930 static u32 rkpm_slp_mode_set(u32 ctrbits)
932 u32 mode_set,mode_set1;
933 // setting gpio0_a0 arm off pin
935 sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
937 pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
938 pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
940 pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
941 pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
943 ddr_pin_set_fun(0x0,0xa,0x0,0x1);
947 //mode_set1=pmu_pwr_mode_con1;
948 //mode_set=pmu_pwr_mode_con0;
950 //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
951 pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
954 reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
957 reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
960 mode_set= BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
963 if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
965 rkpm_ddr_printascii("-autoidle-");
966 mode_set|=BIT(pmu_clk_core_src_gate_en);
968 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
970 rkpm_ddr_printascii("-armdp-");
971 mode_set |= BIT(pmu_a12_0_pd_en)
972 | BIT(pmu_sref0_enter_en) | BIT(pmu_sref1_enter_en)
973 | BIT(pmu_ddr0_gating_en) | BIT(pmu_ddr1_gating_en)
974 | BIT(pmu_chip_pd_en);
976 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
978 rkpm_ddr_printascii("-armoff-");
979 mode_set|=BIT(pmu_scu_en)
980 //|BIT(pmu_a12_0_pd_en)
981 |BIT(pmu_clk_core_src_gate_en) // »½ÐѺóÒì³£
982 |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
983 |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
984 //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
985 |BIT(pmu_chip_pd_en);
986 mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
993 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
996 rkpm_ddr_printascii("-armoff-logdp-");
998 mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
1000 |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
1001 |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
1002 |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
1003 |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
1005 mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
1020 if(mode_set&BIT(pmu_osc_24m_dis))
1022 rkpm_ddr_printascii("osc_off");
1023 pmu_writel(32*30,RK3288_PMU_OSC_CNT);
1024 pmu_writel(32*30,RK3288_PMU_STABL_CNT);
1025 } else if (mode_set & BIT(pmu_a12_0_pd_en)) {
1026 pmu_writel(0x0, RK3288_PMU_STABL_CNT);
1027 pmu_writel(0x0, RK3288_PMU_OSC_CNT);
1028 pmu_writel(0x0, RK3288_PMU_PLL_CNT);
1029 pmu_writel(0x0, RK3288_PMU_DDR0IO_PWRON_CNT);
1030 pmu_writel(0x0, RK3288_PMU_DDR1IO_PWRON_CNT);
1031 pmu_writel(0x0, RK3288_PMU_GPU_PWRUP_CNT);
1032 pmu_writel(0x0, RK3288_PMU_WAKEUP_RST_CLR_CNT);
1033 /*pmu_writel(100,RK3288_PMU_CORE_PWRUP_CNT);*/
1035 pmu_writel(24*1000*10, RK3288_PMU_STABL_CNT);
1037 if(mode_set&BIT(pmu_ddr0io_ret_en))
1039 rkpm_ddr_printascii("ddrc_off");
1040 ddr_pin_set_fun(0x0,0xa,0x1,0x1);
1041 ddr_pin_set_fun(0x0,0xa,0x2,0x1);
1042 ddr_pin_set_fun(0x0,0xa,0x3,0x1);
1045 pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
1046 pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
1048 // rkpm_ddr_printhex(mode_set);
1049 // rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1051 return (pmu_readl(RK3288_PMU_PWRMODE_CON));
1054 static inline void rkpm_slp_mode_set_resume(void)
1057 pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1058 pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1060 pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1061 pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1062 reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1066 static void sram_code_data_save(u32 pwrmode)
1068 char *code_src,*data_src;
1069 u32 code_size,data_size;
1073 if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1075 sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1076 sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1078 sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=1;
1079 sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325]=rkpm_armerrata_818325();//
1081 sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1082 sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1084 rkpm_ddr_printascii("l2&arm_errata--");
1085 rkpm_ddr_printhex(rkpm_l2_config());
1086 rkpm_ddr_printhex(rkpm_armerrata_818325());
1087 rkpm_ddr_printascii("\n");
1092 sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=0;
1093 sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=0;
1094 sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1098 if(pwrmode&BIT(pmu_bus_pd_en))
1100 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1101 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1102 code_src=(char *)ddr_get_resume_code_info(&code_size);
1103 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1104 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1105 data_src=(char *)ddr_get_resume_data_info(&data_size);
1106 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1110 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1113 sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1117 local_flush_tlb_all();
1121 static inline void sram_code_data_resume(u32 pwrmode)
1123 if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1125 sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1130 static void rkpm_peri_save(u32 power_mode)
1132 // u32 gpio_gate[2];
1134 if (power_mode & (BIT(pmu_scu_en) | BIT(pmu_a12_0_pd_en)))
1135 rkpm_gic_dist_save(&slp_gic_save[0]);
1137 gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1138 gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1139 RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1140 cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1141 RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1144 if(power_mode&BIT(pmu_bus_pd_en))
1149 ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1150 ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1151 ddr_pin_set_fun(7,0xc,0x6,0);
1153 ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1154 ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1155 ddr_pin_set_fun(7,0xc,0x7,0);
1159 ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1160 ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1161 ddr_pin_set_fun(0,0xb,0x7,0);
1163 ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1164 ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1165 ddr_pin_set_fun(0,0xc,0x0,0);
1167 slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1168 slp_i2c_save(1);//i2c audio
1172 cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1173 RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1174 cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1179 static inline void rkpm_peri_resume(u32 power_mode)
1181 if (power_mode & (BIT(pmu_scu_en) | BIT(pmu_a12_0_pd_en))) {
1182 /*fiq_glue_resume();*/
1183 rkpm_gic_dist_resume(&slp_gic_save[0]);
1185 /*rkpm_ddr_printascii("gic res");*/
1187 if(power_mode&BIT(pmu_bus_pd_en))
1189 slp_i2c_resume(0);// i2c pmu
1190 slp_i2c_resume(1);//i2c audio
1195 static u32 pdbus_gate_reg[5];
1196 static inline void rkpm_peri_resume_first(u32 power_mode)
1199 if(power_mode&BIT(pmu_bus_pd_en))
1201 cru_writel(0xffff0000|pdbus_gate_reg[0],RK3288_CRU_CLKGATES_CON(0));
1202 cru_writel(0xffff0000|pdbus_gate_reg[1],RK3288_CRU_CLKGATES_CON(4));
1203 cru_writel(0xffff0000|pdbus_gate_reg[2],RK3288_CRU_CLKGATES_CON(5));
1204 cru_writel(0xffff0000|pdbus_gate_reg[3],RK3288_CRU_CLKGATES_CON(10));
1205 cru_writel(0xffff0000|pdbus_gate_reg[4],RK3288_CRU_CLKGATES_CON(11));
1209 if(power_mode&BIT(pmu_bus_pd_en))
1210 slp_uartdbg_resume();
1213 static void rkpm_slp_setting(void)
1215 rk_usb_power_down();
1217 if(rk3288_powermode&BIT(pmu_bus_pd_en))
1219 // pd bus will be power down ,but if it reup,ungating clk for its reset
1220 // ungating pdbus clk
1221 pdbus_gate_reg[0]=cru_readl(RK3288_CRU_CLKGATES_CON(0));
1222 pdbus_gate_reg[1]=cru_readl(RK3288_CRU_CLKGATES_CON(4));
1223 pdbus_gate_reg[2]=cru_readl(RK3288_CRU_CLKGATES_CON(5));
1224 pdbus_gate_reg[3]=cru_readl(RK3288_CRU_CLKGATES_CON(10));
1225 pdbus_gate_reg[4]=cru_readl(RK3288_CRU_CLKGATES_CON(11));
1227 cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(0));
1228 cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(4));
1229 cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(5));
1230 cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(10));
1231 cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(11));
1233 RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_UART2);
1234 // RK3288_CRU_UNGATING_OPS((RK3288_CLKGATE_UART0_SRC+2*2));
1236 RK3288_CRU_UNGATING_OPS(RK3288_CRU_CONS_GATEID(13)+8);
1243 static void rkpm_save_setting_resume_first(void)
1246 rkpm_peri_resume_first(rk3288_powermode);
1248 // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1250 //rk319x_pm_set_power_domain(PD_PERI,true);
1251 //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1252 slp_pin_gpio_resume(1);
1253 slp_pin_gpio_resume(2);
1254 slp_pin_gpio_resume(3);
1255 slp_pin_gpio_resume(4);
1258 slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1259 slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1261 slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1262 slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1263 slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1264 slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1266 //sram_printch_uart_enable();
1271 static void rkpm_save_setting(u32 ctrbits)
1275 rkpm_ddr_regs_dump(RK_DDR_VIRT,0,0x3fc);
1276 rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE,0,0x294);
1278 rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE+RK3288_DDR_PUBL_SIZE,0,0x3fc);
1279 rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE*2+RK3288_DDR_PUBL_SIZE,0,0x294);
1281 rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1282 if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1284 sram_code_data_save(rk3288_powermode);
1285 rkpm_peri_save(rk3288_powermode);
1291 static void rkpm_save_setting_resume(void)
1293 #ifdef CONFIG_ARM_ERRATA_821420
1296 asm volatile("mrc p15, 0, %0, c15, c0, 2" : "=r" (v));
1298 asm volatile("mcr p15, 0, %0, c15, c0, 2" : : "r" (v));
1303 rkpm_ddr_printascii("l2&arm_errata--");
1304 rkpm_ddr_printhex(rkpm_l2_config());
1305 rkpm_ddr_printhex(rkpm_armerrata_818325());
1306 rkpm_ddr_printascii("\n");
1309 if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1311 sram_code_data_resume(rk3288_powermode);
1312 rkpm_peri_resume(rk3288_powermode);
1314 rkpm_slp_mode_set_resume();
1318 /*******************************common code for rkxxx*********************************/
1319 static void inline uart_printch(char byte)
1322 u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART*2);
1323 u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1325 if(CONFIG_RK_DEBUG_UART==4)
1326 u_clk_id=RK3288_CLKGATE_UART4_SRC;
1327 if(CONFIG_RK_DEBUG_UART==2)
1328 u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1330 reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1331 reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1332 RK3288_CRU_UNGATING_OPS(u_clk_id);
1333 RK3288_CRU_UNGATING_OPS(u_pclk_id);
1338 writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1341 /* loop check LSR[6], Transmitter Empty bit */
1342 while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1350 cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1351 cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1354 void PIE_FUNC(sram_printch)(char byte)
1359 static void pll_udelay(u32 udelay);
1361 #ifdef CONFIG_RK_LAST_LOG
1362 extern void rk_last_log_text(char *text, size_t size);
1365 static void ddr_printch(char byte)
1369 #ifdef CONFIG_RK_LAST_LOG
1370 rk_last_log_text(&byte, 1);
1374 rk_last_log_text(&byte, 1);
1379 /*******************************gpio func*******************************************/
1380 //#define RK3288_PMU_GPIO0_A_IOMUX 0x0084
1381 //#define RK3288_PMU_GPIO0_B_IOMUX 0x0088
1382 //#define RK3288_PMU_GPIO0_C_IOMUX 0x008c
1383 //#define RK3288_PMU_GPIO0_D_IOMUX 0x0090
1384 //pin=0x0a21 gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1385 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1394 off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1395 pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1397 else if(port==1||port==2)
1399 off_set=port*(4*4)+bank*4;
1400 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1406 off_set=0x20+bank*4;
1407 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1412 off_set=0x2c+(b_gpio/4)*4;
1413 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1421 off_set=0x34+bank*8+(b_gpio/4)*4;
1422 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1426 off_set=0x44+(bank-2)*4;
1427 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1431 else if(port==5||port==6)
1433 off_set=0x4c+(port-5)*4*4+bank*4;
1434 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1440 off_set=0x6c+bank*4;
1441 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1445 off_set=0x74+(bank-2)*8+(b_gpio/4)*4;
1446 //rkpm_ddr_printascii("gpio");
1447 //rkpm_ddr_printhex(off_set);
1448 //rkpm_ddr_printascii("-");
1449 //rkpm_ddr_printhex((b_gpio%4)*4);
1451 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1453 //rkpm_ddr_printhex(reg_readl(RK_GRF_VIRT+0+off_set));
1454 //rkpm_ddr_printascii("\n");
1462 off_set=0x80+bank*4;
1463 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1470 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1475 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1484 //if(port==1&&bank<3)
1486 //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1487 off_set=(0x14c-0x1c)+port*(4*4)+bank*4;
1490 rkpm_ddr_printascii("gpio pull\n");
1491 rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1492 rkpm_ddr_printhex(b_gpio);
1493 rkpm_ddr_printhex(pull);
1494 rkpm_ddr_printhex(off_set);
1495 rkpm_ddr_printhex(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3));
1498 reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1503 if(bank>2)// gpio0_d is not support
1505 pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1510 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1521 //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1522 off_set=0x14c-0x1c+port*(4*4)+bank*4;
1523 return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1528 if(bank>2)// gpio0_d is not support
1530 return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1537 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1542 b_gpio=bank*8+b_gpio;//
1544 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1546 if(type==RKPM_GPIO_OUTPUT)
1549 val&=~(0x1<<b_gpio);
1551 rkpm_ddr_printascii("gpio out\n");
1552 rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1553 rkpm_ddr_printhex(b_gpio);
1555 rkpm_ddr_printhex(type);
1556 rkpm_ddr_printhex(val);
1558 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1560 //rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR));
1565 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1568 b_gpio=bank*8+b_gpio;
1569 return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1572 //RKPM_GPIOS_OUT_L RKPM_GPIOS_OUT_H
1573 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1578 b_gpio=bank*8+b_gpio;
1580 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1582 if(level==RKPM_GPIO_OUT_H)
1585 val&=~(0x1<<b_gpio);
1587 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1590 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1593 b_gpio=bank*8+b_gpio;
1594 return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1597 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1601 b_gpio=bank*8+b_gpio;
1603 return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1605 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1610 b_gpio=bank*8+b_gpio;
1612 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1613 rkpm_ddr_printascii("\n inten:");
1614 rkpm_ddr_printhex(val);
1616 rkpm_ddr_printascii("-");
1620 val&=~(0x1<<b_gpio);
1622 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1625 rkpm_ddr_printhex(val);
1626 rkpm_ddr_printascii("-");
1628 rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1630 rkpm_ddr_printascii("\n");
1635 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1637 pin_set_fun(port,bank,b_gpio,fun);
1639 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1641 return pin_get_funset(port,bank,b_gpio);
1644 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1646 pin_set_pull(port,bank,b_gpio,fun);
1648 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1650 return pin_get_pullset(port,bank,b_gpio);
1653 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1655 gpio_set_in_output(port,bank,b_gpio,type);
1658 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1660 return gpio_get_in_outputset(port,bank,b_gpio);
1663 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1666 gpio_set_output_level(port,bank,b_gpio,level);
1670 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1672 return gpio_get_output_levelset(port,bank,b_gpio);
1676 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1678 return gpio_get_input_level(port,bank,b_gpio);
1682 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1684 pin_set_fun(port,bank,b_gpio,fun);
1687 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1689 return pin_get_funset(port,bank,b_gpio);
1691 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1693 return pin_get_pullset(port,bank,b_gpio);
1695 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1697 return gpio_get_in_outputset(port,bank,b_gpio);
1700 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1702 return gpio_get_output_levelset(port,bank,b_gpio);
1704 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1706 return gpio_get_input_level(port,bank,b_gpio);
1713 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1715 pin_set_pull(port,bank,b_gpio,fun);
1718 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1720 gpio_set_in_output(port,bank,b_gpio,type);
1722 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1724 gpio_set_output_level(port,bank,b_gpio,level);
1729 #define GPIO_DTS_NUM (20)
1730 static u32 suspend_gpios[GPIO_DTS_NUM];
1731 static u32 resume_gpios[GPIO_DTS_NUM];
1733 static int of_find_property_value_getsize(const struct device_node *np,const char *propname)
1735 struct property *prop = of_find_property(np, propname, NULL);
1741 return prop->length;
1744 static void rkpm_pin_gpio_config(u32 pin_gpio_bits)
1748 u8 port,bank,b_gpio,fun,in_out, level, pull;
1750 pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1751 in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1752 pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1753 level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1755 port=RKPM_PINBITS_PORT(pins);
1756 bank=RKPM_PINBITS_BANK(pins);
1757 b_gpio=RKPM_PINBITS_BGPIO(pins);
1758 fun=RKPM_PINBITS_FUN(pins);
1763 if(in_out==RKPM_GPIO_OUTPUT)
1765 if(level==RKPM_GPIO_OUT_L)
1766 pull=RKPM_GPIO_PULL_DN;
1768 pull=RKPM_GPIO_PULL_UP;
1770 ddr_gpio_set_output_level(port,bank,b_gpio,level);
1772 //rkpm_ddr_printhex(pins);
1774 ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1777 ddr_pin_set_pull(port,bank,b_gpio,pull);
1778 ddr_pin_set_fun(port,bank,b_gpio,fun);
1784 #define RKPM_PINGPIO_BITS_PINTOPORT(pin_gpio_bits) RKPM_PINBITS_PORT(RKPM_PINGPIO_BITS_PIN((pin_gpio_bits)))
1785 #define rkpm_gpio_pclk_idx(port) ((port)==0) ? RK3288_CLKGATE_PCLK_GPIO0 : (RK3288_CLKGATE_PCLK_GPIO1+(port)-1)
1788 static void rkpm_pins_setting(u32 *gpios,u32 cnt)
1791 u32 gpio_clk_reg[9];
1794 // rkpm_ddr_printascii("\ngpios");
1798 gpio_clk_reg[i]=0xffff0000;
1805 port=RKPM_PINGPIO_BITS_PINTOPORT(gpios[i]);
1806 if(gpio_clk_reg[port]==0xffff0000)
1808 clk_id=rkpm_gpio_pclk_idx(port);
1809 gpio_clk_reg[port]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id))&0xffff;
1810 RK3288_CRU_UNGATING_OPS(clk_id);
1812 // rkpm_ddr_printhex(gpios[i]);
1813 rkpm_pin_gpio_config(gpios[i]);
1816 // rkpm_ddr_printascii("\n");
1821 rkpm_ddr_regs_dump(RK_GPIO_VIRT(i),0,0x4);
1824 rkpm_ddr_regs_dump(RK_GRF_VIRT,0xc,0x84);
1825 rkpm_ddr_regs_dump(RK_GRF_VIRT,0x14c,0x1b4);
1826 // rkpm_ddr_regs_dump(RK_PMU_VIRT,0x64,0x6c);
1827 //rkpm_ddr_regs_dump(RK_PMU_VIRT,0x84,0x9c);
1832 if(gpio_clk_reg[i]!=0xffff0000)
1834 clk_id=rkpm_gpio_pclk_idx(i);
1835 cru_writel(gpio_clk_reg[i]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
1841 static void rkpm_gpio_suspend(void)
1843 rkpm_pins_setting(&suspend_gpios[0],GPIO_DTS_NUM);
1848 static void rkpm_gpio_resume(void)
1850 rkpm_pins_setting(&resume_gpios[0],GPIO_DTS_NUM);
1854 static void gpio_get_dts_info(struct device_node *parent)
1860 for(i=0;i<GPIO_DTS_NUM;i++)
1867 temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-suspend_gpios");
1870 printk("%s suspend:%d\n",__FUNCTION__,temp_len);
1873 if(of_property_read_u32_array(parent,"rockchip,pmic-suspend_gpios",&suspend_gpios[0],temp_len/4))
1876 printk("%s:get pm ctr error\n",__FUNCTION__);
1881 temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-resume_gpios");
1884 printk("%s resume:%d\n",__FUNCTION__,temp_len);
1885 if(of_property_read_u32_array(parent,"rockchip,pmic-resume_gpios",&resume_gpios[0],temp_len/4))
1888 printk("%s:get pm ctr error\n",__FUNCTION__);
1893 printk("rockchip,pmic-suspend_gpios:");
1894 for(i=0;i<GPIO_DTS_NUM;i++)
1896 printk("%x ",suspend_gpios[i]);
1897 if(i==(GPIO_DTS_NUM-1))
1901 printk("rockchip,pmic-resume_gpios:");
1902 for(i=0;i<GPIO_DTS_NUM;i++)
1904 printk("%x ",resume_gpios[i]);
1905 if(i==(GPIO_DTS_NUM-1))
1909 rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1914 /*******************************clk gating config*******************************************/
1915 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1916 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1919 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1920 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1921 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1924 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1925 static u32 *p_rkpm_clkgt_last_set;
1927 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1929 void PIE_FUNC(gtclks_sram_suspend)(void)
1932 // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1933 // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1935 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1937 rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1938 CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1940 rkpm_sram_printch('\n');
1941 rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1942 rkpm_sram_printch('-');
1943 rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1944 rkpm_sram_printch('-');
1945 rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1946 if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1947 rkpm_sram_printch('\n');
1951 //RK3288_CRU_UNGATING_OPS(u_clk_id);
1952 //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1956 void PIE_FUNC(gtclks_sram_resume)(void)
1959 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1961 cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1964 #define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
1965 #define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1967 #define gpio7_readl(offset) readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1968 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1970 int gpio7_pin_data1, gpio7_pin_dir1;
1971 int gpio7_pin_iomux1;
1973 static void gtclks_suspend(void)
1977 gpio7_pin_data1= gpio7_readl(0);
1978 gpio7_pin_dir1 = gpio7_readl(0x04);
1979 gpio7_pin_iomux1 = gpio7_readl(0x6c);
1980 grf_writel(0x00040000, 0x6c);
1981 gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1982 gpio7_writel((gpio7_pin_data1|2), 0x00);
1984 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1985 // ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1987 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1989 clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1993 // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1994 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1995 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1996 // RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1997 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1998 // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1999 // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
2002 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
2003 // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
2004 // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
2005 // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
2006 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
2007 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
2008 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
2009 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
2010 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
2011 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
2012 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
2013 // RK3288_CRU_CLKGATES_CON(i)==0x1a8
2014 RK3288_CRU_CLKGATES_CON(i)==0xfff
2018 cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
2019 // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2025 // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
2026 CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2029 rkpm_ddr_printch('\n');
2030 rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
2031 rkpm_ddr_printch('-');
2032 rkpm_ddr_printhex(clk_ungt_msk[i]);
2033 rkpm_ddr_printch('-');
2034 rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
2035 if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
2036 rkpm_ddr_printch('\n');
2042 static void gtclks_resume(void)
2045 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2047 cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2049 //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
2050 // ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
2051 grf_writel(0x00040004, 0x6c);
2053 /********************************pll power down***************************************/
2055 static void pm_pll_wait_lock(u32 pll_idx)
2057 u32 delay = 600000U;
2059 // mode=cru_readl(RK3288_CRU_MODE_CON);
2067 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
2072 rkpm_ddr_printascii("unlock-pll:");
2073 rkpm_ddr_printhex(pll_idx);
2074 rkpm_ddr_printch('\n');
2076 //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
2079 static void pll_udelay(u32 udelay)
2082 mode=cru_readl(RK3288_CRU_MODE_CON);
2084 cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2086 rkpm_udelay(udelay*5);
2088 cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2091 static u32 plls_con0_save[END_PLL_ID];
2092 static u32 plls_con1_save[END_PLL_ID];
2093 static u32 plls_con2_save[END_PLL_ID];
2094 static u32 plls_con3_save[END_PLL_ID];
2096 static u32 cru_mode_con;
2098 static inline void plls_suspend(u32 pll_id)
2100 plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
2101 plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
2102 plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
2103 plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
2105 cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
2108 static inline void plls_resume_pre(u32 pll_id)
2110 u32 pllcon0, pllcon1, pllcon2;
2112 cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
2114 cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id), 3));
2115 cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id), 3));
2117 pllcon0 = plls_con0_save[pll_id];
2118 pllcon1 = plls_con1_save[pll_id];
2119 pllcon2 = plls_con2_save[pll_id];
2122 cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id, 3));
2123 cru_writel(pllcon0 | CRU_W_MSK(0, 0xf) | CRU_W_MSK(8, 0x3f)
2124 , RK3288_PLL_CONS(pll_id, 0));
2125 cru_writel(pllcon1, RK3288_PLL_CONS(pll_id, 1));
2126 cru_writel(pllcon2, RK3288_PLL_CONS(pll_id, 2));
2129 static inline void plls_resume(void)
2131 plls_resume_pre(APLL_ID);
2132 plls_resume_pre(GPLL_ID);
2133 plls_resume_pre(CPLL_ID);
2134 plls_resume_pre(NPLL_ID);
2138 /*return form rest*/
2139 cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(APLL_ID, 3));
2140 cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(GPLL_ID, 3));
2141 cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(CPLL_ID, 3));
2142 cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(NPLL_ID, 3));
2144 /*wating lock state*/
2147 pm_pll_wait_lock(APLL_ID);
2148 pm_pll_wait_lock(GPLL_ID);
2149 pm_pll_wait_lock(CPLL_ID);
2150 pm_pll_wait_lock(NPLL_ID);
2153 cru_writel(plls_con3_save[APLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2154 , RK3288_PLL_CONS(APLL_ID, 3));
2155 cru_writel(plls_con3_save[GPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2156 , RK3288_PLL_CONS(GPLL_ID, 3));
2157 cru_writel(plls_con3_save[CPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2158 , RK3288_PLL_CONS(CPLL_ID, 3));
2159 cru_writel(plls_con3_save[NPLL_ID] | (RK3288_PLL_BYPASS_MSK << 16)
2160 , RK3288_PLL_CONS(NPLL_ID, 3));
2163 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
2165 static void pm_plls_suspend(void)
2168 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2169 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2170 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2172 clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
2173 clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
2174 clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
2175 clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
2176 clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
2177 clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
2178 clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2180 cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2183 cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2184 plls_suspend(NPLL_ID);
2187 cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2190 cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2192 // set 1,pdbus pll is gpll
2193 cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2197 |CRU_W_MSK_SETBITS(0,0,0x7) // 1 aclk
2198 |CRU_W_MSK_SETBITS(0,3,0x1f) // 1 aclk src
2199 |CRU_W_MSK_SETBITS(0,8,0x3) // 1 hclk 0~1 1 2 4
2200 |CRU_W_MSK_SETBITS(0,12,0x7) // 3 pclk
2201 , RK3288_CRU_CLKSELS_CON(1));
2204 cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2206 // peri aclk hclk pclk
2208 |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2209 |CRU_W_MSK_SETBITS(0,8,0x3) // 2 hclk 0 1:1,1 2:1 ,2 4:1
2210 |CRU_W_MSK_SETBITS(0,12,0x3)// 2 0~3 1 2 4 8 div
2211 , RK3288_CRU_CLKSELS_CON(10));
2213 cru_writel(CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2215 plls_suspend(CPLL_ID);
2216 plls_suspend(GPLL_ID);
2219 cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2220 // core_m0 core_mp a12_core
2222 |CRU_W_MSK_SETBITS(0,0,0xf) // 1 axi_mo
2223 |CRU_W_MSK_SETBITS(0,4,0xf) // 3 axi mp
2224 |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2225 , RK3288_CRU_CLKSELS_CON(0));
2226 // core0 core1 core2 core3
2228 |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2229 |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2230 |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2231 |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2232 , RK3288_CRU_CLKSELS_CON(36));
2236 |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2237 |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2238 |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2239 , RK3288_CRU_CLKSELS_CON(37));
2242 |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2243 |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2244 |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2245 , RK3288_CRU_CLKSELS_CON(37));
2249 plls_suspend(APLL_ID);
2253 static void pm_plls_resume(void)
2255 /* core_m0 core_mp a12_core*/
2256 cru_writel(clk_sel0 | (CRU_W_MSK(0, 0xf) | CRU_W_MSK(4, 0xf)
2257 | CRU_W_MSK(8, 0xf)), RK3288_CRU_CLKSELS_CON(0));
2258 /*core0 core1 core2 core3*/
2259 cru_writel(clk_sel36 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(4, 0x7)
2260 | CRU_W_MSK(8, 0x7) | CRU_W_MSK(12, 0x7)), RK3288_CRU_CLKSELS_CON(36));
2261 /* l2ram atclk pclk*/
2262 cru_writel(clk_sel37 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(4, 0x1f)
2263 | CRU_W_MSK(9, 0x1f)), RK3288_CRU_CLKSELS_CON(37));
2265 /*resume APLL_ID GPLL_ID CPLL_ID NPLL_ID*/
2268 cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(APLL_ID) << 16)
2269 , RK3288_CRU_MODE_CON);
2271 /*peri aclk hclk pclk*/
2272 cru_writel(clk_sel10 | (CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x3)
2273 | CRU_W_MSK(12, 0x3)), RK3288_CRU_CLKSELS_CON(10));
2275 cru_writel(clk_sel1 | CRU_W_MSK(15, 0x1), RK3288_CRU_CLKSELS_CON(1));
2277 cru_writel(clk_sel1 | (CRU_W_MSK(0, 0x7) | CRU_W_MSK(3, 0x1f)
2278 | CRU_W_MSK(8, 0x3) | CRU_W_MSK(12, 0x7)), RK3288_CRU_CLKSELS_CON(1));
2281 cru_writel(clk_sel26 | CRU_W_MSK(6, 0x3), RK3288_CRU_CLKSELS_CON(26));
2284 cru_writel(clk_sel33 | CRU_W_MSK(0, 0x1f) | CRU_W_MSK(8, 0x1f)
2285 , RK3288_CRU_CLKSELS_CON(33));
2286 cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(GPLL_ID) << 16)
2287 , RK3288_CRU_MODE_CON);
2288 cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(CPLL_ID) << 16)
2289 , RK3288_CRU_MODE_CON);
2290 cru_writel(cru_mode_con | (RK3288_PLL_MODE_MSK(NPLL_ID) << 16)
2291 , RK3288_CRU_MODE_CON);
2295 static __sramdata u32 sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2297 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2301 sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2302 sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2303 sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2306 if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2309 sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2311 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2312 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2313 , RK3288_CRU_MODE_CON);
2315 else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2320 cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2321 cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2322 cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2326 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2329 cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2330 cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2331 cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2332 cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2333 |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2334 |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2335 |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2340 static void clks_gating_suspend_init(void)
2342 // get clk gating info
2343 if(rockchip_pie_chunk)
2344 p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2346 p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2347 if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2348 ==RK3288_CRU_CLKGATES_CON(0))
2350 rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2351 if(rockchip_pie_chunk)
2352 rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2353 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2355 PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2358 if(rockchip_pie_chunk)
2359 rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2360 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2363 /***************************prepare and finish reg_pread***********************************/
2367 #define GIC_DIST_PENDING_SET 0x200
2368 static noinline void rk3288_pm_dump_irq(void)
2370 u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2374 for (i = 0; i < ARRAY_SIZE(irq); i++)
2375 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2376 for (i = 0; i < ARRAY_SIZE(irq); i++) {
2378 log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2380 printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2381 for (i = 0; i <= 8; i++) {
2382 if (irq_gpio & (1 << i))
2383 printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2388 #define DUMP_GPIO_INTEN(ID) \
2390 u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2392 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2393 rkpm_ddr_printhex(en); \
2394 rkpm_ddr_printch('\n'); \
2395 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2400 #define DUMP_GPIO_INTEN(ID) \
2402 u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2404 printk("GPIO%d_INTEN: %08x\n", ID, en); \
2411 //dump while irq is enable
2412 static noinline void rk3288_pm_dump_inten(void)
2425 static void rkpm_prepare(void)
2429 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2431 //cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2435 u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2437 // rkpm_ddr_printhex(temp);
2438 reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2439 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2440 // rkpm_ddr_printhex(temp);
2442 // dump GPIO INTEN for debug
2443 rk3288_pm_dump_inten();
2446 static void rkpm_finish(void)
2448 rk3288_pm_dump_irq();
2452 static void interface_ctr_reg_pread(void)
2457 local_flush_tlb_all();
2458 #if 0 // do it in ddr suspend
2459 for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2460 readl_relaxed(addr);
2462 readl_relaxed(RK_PMU_VIRT);
2463 readl_relaxed(RK_GRF_VIRT);
2464 readl_relaxed(RK_DDR_VIRT);
2465 readl_relaxed(RK_GPIO_VIRT(0));
2466 //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2467 //readl_relaxed(RK_GPIO_VIRT(3));
2470 void PIE_FUNC(ddr_leakage_tst)(void)
2472 cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2473 rkpm_sram_printch('\n');
2474 rkpm_sram_printch('t');
2475 rkpm_sram_printch('e');
2476 rkpm_sram_printch('s');
2477 rkpm_sram_printch('t');
2481 static void __init rk3288_suspend_init(void)
2483 struct device_node *parent;
2486 PM_LOG("%s enter\n",__FUNCTION__);
2488 parent = of_find_node_by_name(NULL, "rockchip_suspend");
2490 if (IS_ERR_OR_NULL(parent)) {
2491 PM_ERR("%s dev node err\n", __func__);
2496 if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2498 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2501 PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2503 memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2504 rkpm_set_ctrbits(pm_ctrbits);
2506 gpio_get_dts_info(parent);
2507 clks_gating_suspend_init();
2509 rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2511 //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2513 rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2515 //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2517 rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2518 rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2520 if(rockchip_pie_chunk)
2521 rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2523 rkpm_set_ops_printch(ddr_printch);