arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/wakeup_reason.h>
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28 __weak void rk_usb_power_down(void);
  29 __weak void rk_usb_power_up(void);
  30
  31 //static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
  32 //static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
  33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
  34
  35
  36 /*************************cru define********************************************/
  37
  38
  39 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  40 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  41
  42 enum rk_plls_id {
  43         APLL_ID = 0,
  44         DPLL_ID,
  45         CPLL_ID,
  46         GPLL_ID,
  47         NPLL_ID,
  48         END_PLL_ID,
  49 };
  50
  51 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
  52 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
  53 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
  54
  55
  56 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
  57 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
  58
  59 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
  60 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
  61 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
  62
  63
  64 /*******************************gpio define **********************************************/
  65
  66 /* GPIO control registers */
  67 #define GPIO_SWPORT_DR          0x00
  68 #define GPIO_SWPORT_DDR         0x04
  69 #define GPIO_INTEN                      0x30
  70 #define GPIO_INTMASK            0x34
  71 #define GPIO_INTTYPE_LEVEL      0x38
  72 #define GPIO_INT_POLARITY       0x3c
  73 #define GPIO_INT_STATUS         0x40
  74 #define GPIO_INT_RAWSTATUS      0x44
  75 #define GPIO_DEBOUNCE           0x48
  76 #define GPIO_PORTS_EOI          0x4c
  77 #define GPIO_EXT_PORT           0x50
  78 #define GPIO_LS_SYNC            0x60
  79
  80 /***********************************sleep func*********************************************/
  81
  82 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
  83 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
  84 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
  85
  86 // sys resume code in boot ram
  87 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
  88 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
  89
  90
  91 // sys resume data in boot ram
  92 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
  93 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
  94
  95 // ddr resume data in boot ram
  96 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
  97 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
  98
  99 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
 100
 101 // the value is used to control cpu resume flow
 102 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 103 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
 104 static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);
 105
 106
 107
 108 #define BOOT_RAM_SIZE   (4*1024)
 109 #define INT_RAM_SIZE            (64*1024)
 110
 111 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
 112 static char int_ram_data[INT_RAM_SIZE];
 113
 114 char * ddr_get_resume_code_info(u32 *size);
 115 char * ddr_get_resume_data_info(u32 *size);
 116
 117 /**
 118 ddr code and data
 119
 120 *** code start
 121 ---data offset--
 122 ---code----
 123 ---data----
 124 */
 125 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
 126 {
 127
 128         char *addr_base,*addr_phy,*data_src,*data_dst;
 129         u32 sr_size,data_size;
 130
 131         addr_base=(char *)RKPM_BOOTRAM_BASE;
 132         addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 133         sr_size=RKPM_BOOTRAM_SIZE;
 134
 135         // save boot sram
 136          if(boot_save)
 137                  memcpy(boot_save,addr_base, sr_size);
 138
 139         // move resume code and date to boot sram
 140         // move sys code
 141         data_dst=(char *)RKPM_BOOT_CODE_BASE;
 142         data_src=(char *)rkpm_slp_cpu_resume;
 143         data_size=RKPM_BOOT_CODE_SIZE;
 144         memcpy((char *)data_dst,(char *)data_src, data_size);
 145
 146         // move sys data
 147         data_dst=(char *)resume_data_base;
 148         data_src=(char *)sleep_resume_data;
 149         data_size=sizeof(sleep_resume_data);
 150         memcpy((char *)data_dst,(char *)data_src, data_size);
 151
 152         if(flag)
 153         {
 154                 /*************************ddr code cpy*************************************/
 155                 // ddr code
 156                 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
 157                 data_src=(char *)ddr_get_resume_code_info(&data_size);
 158
 159                 data_size=RKPM_ALIGN(data_size,4);
 160
 161                 memcpy((char *)data_dst,(char *)data_src, data_size);
 162
 163                 // ddr data
 164                 data_dst=(char *)(data_dst+data_size);
 165
 166                 data_src=(char *)ddr_get_resume_data_info(&data_size);
 167                 data_size=RKPM_ALIGN(data_size,4);
 168                 memcpy((char *)data_dst,(char *)data_src, data_size);
 169
 170                 /*************************ddr code cpy  end*************************************/
 171                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 172                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 173                 /*************************int mem bak*************************************/
 174                 // int mem
 175                 addr_base=(char *)rockchip_sram_virt;
 176                 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 177                 sr_size=rockchip_sram_size;
 178                 //  rkpm_ddr_printascii("piephy\n");
 179                 //rkpm_ddr_printhex(addr_phy);
 180                 //mmap
 181                 if(int_save)
 182                     memcpy(int_save,addr_base, sr_size);
 183
 184                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 185                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 186         }
 187
 188  }
 189
 190 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
 191 {
 192
 193     char *addr_base,*addr_phy;
 194     u32 sr_size;
 195
 196     addr_base=(char *)RKPM_BOOTRAM_BASE;
 197     addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 198     sr_size=RKPM_BOOTRAM_SIZE;
 199     // save boot sram
 200     if(boot_save)
 201         memcpy(addr_base,boot_save, sr_size);
 202
 203     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 204     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 205
 206     if(flag)
 207     {
 208         // int mem
 209         addr_base=(char *)rockchip_sram_virt;
 210         addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 211         sr_size=rockchip_sram_size;
 212
 213         if(int_save)
 214         memcpy(addr_base, int_save,sr_size);
 215
 216         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 217         outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
 218      }
 219 }
 220
 221 /**************************************gic save and resume**************************/
 222 #define  RK_GICD_BASE (RK_GIC_VIRT)
 223 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 224
 225 #define PM_IRQN_START 32
 226 #define PM_IRQN_END     107//107
 227 #if 0 //funciton is ok ,but not used
 228 static void pm_gic_enable(u32 irqs)
 229 {
 230
 231         int irqstart=0;
 232         u32 bit_off;
 233         void __iomem *reg_off;
 234         unsigned int gic_irqs;
 235
 236         gic_irqs = PM_IRQN_END;
 237         irqstart=PM_IRQN_START;//PM_IRQN_START;
 238
 239         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 240         bit_off=irqs%32;
 241         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 242
 243         dsb();
 244 }
 245
 246 static void rkpm_gic_disable(u32 irqs)
 247 {
 248         int irqstart=0;
 249         u32 bit_off;
 250         void __iomem *reg_off;
 251         unsigned int gic_irqs;
 252
 253         gic_irqs = PM_IRQN_END;
 254         irqstart=PM_IRQN_START;//PM_IRQN_START;
 255
 256         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 257         bit_off=irqs%32;
 258         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 259         dsb();
 260 }
 261 #endif
 262 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 263
 264 static u32 slp_gic_save[260+50];
 265
 266
 267 static void rkpm_gic_dist_save(u32 *context)
 268 {
 269      int i = 0,j,irqstart=0;
 270      unsigned int gic_irqs;
 271
 272      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 273      gic_irqs = (gic_irqs + 1) * 32;
 274      if (gic_irqs > 1020)
 275      gic_irqs = 1020;
 276      //printk("gic_irqs=%d\n",gic_irqs);
 277      //gic_irqs = PM_IRQN_END;
 278      irqstart=PM_IRQN_START;//PM_IRQN_START;
 279
 280      i = 0;
 281      //level
 282      for (j = irqstart; j < gic_irqs; j += 16)
 283       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 284      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 285
 286      /*
 287      * Set all global interrupts to this CPU only.
 288      */
 289      for(j = 0; j < gic_irqs; j += 4)
 290          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 291      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 292
 293      //pri
 294      for (j = 0; j < gic_irqs; j += 4)
 295          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 296      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 297
 298      //secure
 299      for (j = 0; j < gic_irqs; j += 32)
 300          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4) / 32);
 301      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 302
 303      for (j = irqstart; j < gic_irqs; j += 32)
 304          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 305      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 306
 307     #if 0
 308      //disable
 309      for (j = 0; j < gic_irqs; j += 32)
 310          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 311      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 312     #endif
 313
 314      //enable
 315      for (j = 0; j < gic_irqs; j += 32)
 316          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 317      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 318
 319
 320
 321      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 322      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 323
 324      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 325      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 326      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 327
 328     #if 0
 329      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 330      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 331      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 332      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 333      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 334     #endif
 335
 336     #if 1
 337     for (j = irqstart; j < gic_irqs; j += 32)
 338     {
 339         writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 340         dsb();
 341     }
 342     writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 343     writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 344
 345     writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 346     writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 347     #endif
 348
 349 }
 350
 351 static void rkpm_gic_dist_resume(u32 *context)
 352 {
 353
 354          int i = 0,j,irqstart=0;
 355          unsigned int gic_irqs;
 356
 357
 358          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 359          gic_irqs = (gic_irqs + 1) * 32;
 360          if (gic_irqs > 1020)
 361                  gic_irqs = 1020;
 362
 363          //gic_irqs = PM_IRQN_END;
 364          irqstart=PM_IRQN_START;//PM_IRQN_START;
 365
 366          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 367          dsb();
 368          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 369          dsb();
 370          for (j = irqstart; j < gic_irqs; j += 32)
 371          {
 372                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 373                  dsb();
 374          }
 375
 376          i = 0;
 377
 378          //trig
 379          for (j = irqstart; j < gic_irqs; j += 16)
 380          {
 381                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 382                  dsb();
 383          }
 384          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 385
 386          /*
 387          * Set all global interrupts to this CPU only.
 388          */
 389          for (j = 0; j < gic_irqs; j += 4)
 390          {
 391                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 392                  dsb();
 393          }
 394          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 395
 396          //pri
 397          for (j = 0; j < gic_irqs; j += 4)
 398          {
 399                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 400
 401                  dsb();
 402          }
 403          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 404
 405
 406          //secu
 407          for (j = 0; j < gic_irqs; j += 32)
 408          {
 409                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4 )/ 32);
 410                  dsb();
 411          }
 412          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 413
 414          //pending
 415          for (j = irqstart; j < gic_irqs; j += 32)
 416          {
 417                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 418                  i++;
 419                  dsb();
 420          }
 421          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 422
 423          //disable
 424 #if 0
 425          for (j = 0; j < gic_irqs; j += 32)
 426          {
 427                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 428                  dsb();
 429          }
 430          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 431
 432 #else
 433         for (j = irqstart; j < gic_irqs; j += 32)
 434             writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 435         writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 436         writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 437 #endif
 438
 439          //enable
 440          for (j = 0; j < gic_irqs; j += 32)
 441          {
 442                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 443
 444                  dsb();
 445          }
 446
 447          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 448
 449          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 450          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 451          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 452
 453          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 454          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 455
 456 }
 457
 458 /**************************************regs save and resume**************************/
 459
 460 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 461 {
 462      u32 i;
 463          u32 cnt=(end_offset-st_offset)/4+1;
 464      for(i=0;i<cnt;i++)
 465      {
 466          data[i]=readl_relaxed(base+st_offset+i*4);
 467      }
 468 }
 469
 470 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 471 {
 472      u32 i;
 473      u32 cnt=(end_offset-st_offset)/4+1;
 474      for(i=0;i<cnt;i++)
 475      {
 476          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 477      }
 478 }
 479
 480 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 481 {
 482         u32 i;
 483         u32 cnt=(end_offset-st_offset)/4+1;
 484          for(i=0;i<cnt;i++)
 485          {
 486                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 487          }
 488 }
 489
 490 /**************************************uarts save and resume**************************/
 491
 492 #define RK3288_UART_NUM (4)
 493
 494 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 495 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 496
 497 #define UART_DLL        0       /* Out: Divisor Latch Low */
 498 #define UART_DLM        1       /* Out: Divisor Latch High */
 499
 500 #define UART_IER        1
 501 #define UART_FCR        2
 502
 503 #define UART_LCR        3       /* Out: Line Control Register */
 504 #define UART_MCR        4
 505
 506 #if 0 //
 507 static u32 slp_uart_data[RK3288_UART_NUM][10];
 508 static u32 slp_uart_data_flag[RK3288_UART_NUM];
 509
 510  void slp_uart_save(int ch)
 511  {
 512          int i=0;
 513         void __iomem *b_addr=slp_uart_base[ch];
 514          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 515          u32 gate_reg;
 516          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 517                 return;
 518
 519         if(ch==2)
 520         {
 521             idx=RK3288_CLKGATE_PCLK_UART2;
 522             b_addr=RK_DEBUG_UART_VIRT;
 523         }
 524
 525
 526         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 527         RK3288_CRU_UNGATING_OPS(idx);
 528          i=0;
 529          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 530          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 531
 532          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 533          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 534
 535          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 536          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 537          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 538          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 539
 540         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 541
 542  }
 543
 544  void slp_uart_resume(int ch)
 545  {
 546         int i=0;
 547
 548         u32 temp;
 549         void __iomem *b_addr=slp_uart_base[ch];
 550         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 551         u32 gate_reg;
 552
 553         //rkpm_ddr_printascii("\nch");
 554      //   rkpm_ddr_printhex(b_addr);
 555
 556         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 557             return;
 558
 559         if(ch==2)
 560             idx=RK3288_CLKGATE_PCLK_UART2;
 561
 562         //rkpm_ddr_printhex(ch);
 563
 564         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 565         RK3288_CRU_UNGATING_OPS(idx);
 566
 567          i=0;
 568          temp=slp_uart_data[ch][i++];
 569          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 570
 571          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 572          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 573
 574          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 575
 576          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 577          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 578          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 579
 580          writel_relaxed(temp,b_addr+UART_LCR*4);
 581
 582          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 583  }
 584 #endif
 585  void slp_uartdbg_resume(void)
 586 {
 587     void __iomem *b_addr=RK_DEBUG_UART_VIRT;
 588     u32 pclk_id=RK3288_CLKGATE_PCLK_UART2,clk_id=(RK3288_CLKGATE_UART0_SRC+2*2);
 589     u32 gate_reg[2];
 590     u32 rfl_reg,lsr_reg;
 591
 592     gate_reg[0]=cru_readl(RK3288_CRU_GATEID_CONS(pclk_id));
 593     gate_reg[1]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id));
 594
 595     RK3288_CRU_UNGATING_OPS(pclk_id);
 596     // 24M is no gating setting
 597     ddr_pin_set_fun(0x7,0xc,0x6,0x0);
 598     ddr_pin_set_fun(0x7,0xc,0x7,0x0);
 599
 600     do{
 601             // out clk sel 24M
 602             cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 603
 604             //uart2 dbg reset
 605             cru_writel(0|CRU_W_MSK_SETBITS(1,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 606             dsb();
 607             dsb();
 608             rkpm_udelay(10);
 609             cru_writel(0|CRU_W_MSK_SETBITS(0,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 610
 611         #if 0
 612             //out clk (form pll)  is gating
 613             RK3288_CRU_GATING_OPS(clk_id);
 614             //out clk form pll gating to disable uart clk out
 615             // div 12
 616             cru_writel(CRU_W_MSK_SETBITS(11,0,0x7f), RK3288_CRU_CLKSELS_CON(15));
 617             dsb();
 618             dsb();
 619             dsb();
 620             dsb();
 621             cru_writel(CRU_W_MSK_SETBITS(0,8,0x3) , RK3288_CRU_CLKSELS_CON(15));
 622          #endif
 623
 624
 625             reg_writel(0x83,b_addr+UART_LCR*4);
 626
 627             reg_writel(0xd,b_addr+UART_DLL*4);
 628             reg_writel(0x0,b_addr+UART_DLM*4);
 629
 630             reg_writel(0x3,b_addr+UART_LCR*4);
 631
 632             reg_writel(0x5,b_addr+UART_IER*4);
 633             reg_writel(0xc1,b_addr+UART_FCR*4);
 634
 635             rfl_reg=readl_relaxed(b_addr+0x84);
 636             lsr_reg=readl_relaxed(b_addr+0x14);
 637
 638         }while((rfl_reg&0x1f)||(lsr_reg&0xf));
 639
 640         // out clk sel 24M
 641         cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 642
 643         ddr_pin_set_fun(0x7,0xc,0x6,0x1);
 644         ddr_pin_set_fun(0x7,0xc,0x7,0x1);
 645         cru_writel(gate_reg[0]|CRU_W_MSK(pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(pclk_id));
 646         cru_writel(gate_reg[1]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
 647 }
 648
 649 /**************************************i2c save and resume**************************/
 650
 651 //#define RK3288_I2C_REG_DUMP
 652 #define RK3288_I2C_NUM (6)
 653 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 654 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 655
 656 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 657
 658 void slp_i2c_save(int ch)
 659 {
 660
 661         void __iomem *b_addr=slp_i2c_base[ch];
 662         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 663         u32 gate_reg;
 664
 665         if(!b_addr)
 666                 return;
 667
 668         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 669         RK3288_CRU_UNGATING_OPS(idx);
 670
 671         #ifdef RK3288_I2C_REG_DUMP
 672         rkpm_ddr_printascii("i2c save");
 673         rkpm_ddr_printhex(ch);
 674         rkpm_ddr_printch('\n');
 675         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 676         #endif
 677
 678         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 679
 680
 681         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 682
 683 }
 684 void slp_i2c_resume(int ch)
 685 {
 686         void __iomem *b_addr=slp_i2c_base[ch];
 687         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 688         u32 gate_reg;
 689
 690         if(!b_addr)
 691                 return;
 692         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 693         RK3288_CRU_UNGATING_OPS(idx);
 694
 695         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 696
 697         #ifdef RK3288_I2C_REG_DUMP
 698         rkpm_ddr_printascii("i2c resume");
 699         rkpm_ddr_printhex(ch);
 700         rkpm_ddr_printch('\n');
 701         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 702         #endif
 703
 704         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 705 }
 706
 707 /**************************************gpios save and resume**************************/
 708 #define RK3288_GPIO_CH (9)
 709 #if 0 //fun is ok ,not used
 710
 711 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 712 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 713 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 714 static void gpio_ddr_dump_reg(int ports)
 715 {
 716     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 717
 718     rkpm_ddr_printascii("gpio-");
 719     rkpm_ddr_printhex(ports);
 720     rkpm_ddr_printhex('\n');
 721
 722     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 723     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 724     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 725     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 726     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 727     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 728     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 729     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 730     rkpm_ddr_printhex('\n');
 731
 732     rkpm_ddr_printascii("iomux\n");
 733     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 734
 735     rkpm_ddr_printascii("iomux\n");
 736     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 737
 738 }
 739  static void slp_pin_gpio_save(int ports)
 740  {
 741         int i;
 742         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 743         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 744         u32 gate_reg;
 745
 746         if(ports==0||ports>=RK3288_GPIO_CH)
 747                 return;
 748
 749          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 750          RK3288_CRU_UNGATING_OPS(idx);
 751
 752          //gpio_ddr_dump_reg(ports);
 753          i=0;
 754          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 755          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 756          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 757          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 758          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 759          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 760          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 761          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 762
 763         if(ports>0)
 764         {
 765             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 766             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 767          }
 768
 769
 770         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 771
 772  }
 773
 774  static void slp_pin_gpio_resume (int ports)
 775  {
 776          int i;
 777         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 778         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 779          u32 gate_reg;
 780
 781          if(ports==0||ports>=RK3288_GPIO_CH)
 782                 return;
 783           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 784          RK3288_CRU_UNGATING_OPS(idx);
 785
 786
 787         if(ports>0)
 788         {
 789             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 790             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 791         }
 792
 793         i=0;
 794         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 795         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 796         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 797         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 798         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 799         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 800         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 801         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 802
 803         //gpio_ddr_dump_reg(ports);
 804         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 805
 806  }
 807
 808 #endif
 809  static inline u32 rkpm_l2_config(void)
 810  {
 811      u32 l2ctlr;
 812      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 813       return l2ctlr;
 814  }
 815
 816 static inline u32 rkpm_armerrata_818325(void)
 817 {
 818     u32 armerrata;
 819     asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (armerrata));
 820     return armerrata;
 821 }
 822
 823
 824
 825 /**************************************sleep func**************************/
 826
 827 void ddr_reg_save(uint32_t *pArg);
 828 void fiq_glue_resume(void);
 829 void rk30_cpu_resume(void);
 830 void rk30_l2_cache_init_pm(void);
 831 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 832 void ddr_cfg_to_lp_mode(void);
 833 void l2x0_inv_all_pm(void);
 834 void rk30_cpu_while_tst(void);
 835
 836 #if 0
 837 static u32 slp_grf_soc_con_data[5];
 838 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 839
 840 static u32 slp_grf_cpu_con_data[5];
 841 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 842
 843 static u32 slp_grf_uoc0_con_data[4];
 844 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 845
 846 static u32 slp_grf_uoc1_con_data[2];
 847 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 848
 849 static u32 slp_grf_uoc2_con_data[2];
 850 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 851
 852 static u32 slp_grf_uoc3_con_data[2];
 853 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 854
 855 #endif
 856 //static u32 slp_pmu_pwrmode_con_data[1];
 857
 858
 859 //static u32 slp_nandc_data[8];
 860 //static void __iomem *rk30_nandc_base=NULL;
 861
 862 #define MS_37K (37)
 863 #define US_24M (24)
 864
 865 void inline pm_io_base_map(void)
 866 {
 867         int i;
 868         for(i=0;i<RK3288_I2C_NUM;i++)
 869             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 870
 871         for(i=0;i<RK3288_UART_NUM;i++)
 872             {
 873                 if(i!=CONFIG_RK_DEBUG_UART)
 874                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 875                 else
 876                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 877             }
 878
 879 }
 880 enum rk3288_pwr_mode_con {
 881
 882         pmu_pwr_mode_en=0,
 883         pmu_clk_core_src_gate_en,
 884         pmu_global_int_disable,
 885         pmu_l2flush_en,
 886
 887         pmu_bus_pd_en,
 888         pmu_a12_0_pd_en,
 889         pmu_scu_en,
 890         pmu_pll_pd_en,
 891
 892         pmu_chip_pd_en, // power off pin enable
 893         pmu_pwroff_comb,
 894         pmu_alive_use_lf,
 895         pmu_pmu_use_lf,
 896
 897         pmu_osc_24m_dis,
 898         pmu_input_clamp_en,
 899         pmu_wakeup_reset_en,
 900         pmu_sref0_enter_en,
 901
 902         pmu_sref1_enter_en,
 903         pmu_ddr0io_ret_en,
 904         pmu_ddr1io_ret_en,
 905         pmu_ddr0_gating_en,
 906
 907         pmu_ddr1_gating_en,
 908         pmu_ddr0io_ret_de_req,
 909         pmu_ddr1io_ret_de_req
 910
 911 };
 912  enum rk3288_pwr_mode_con1 {
 913
 914         pmu_clr_bus=0,
 915         pmu_clr_core,
 916         pmu_clr_cpup,
 917         pmu_clr_alive,
 918
 919         pmu_clr_dma,
 920         pmu_clr_peri,
 921         pmu_clr_gpu,
 922         pmu_clr_video,
 923         pmu_clr_hevc,
 924         pmu_clr_vio
 925
 926 };
 927  static u32 rk3288_powermode=0;
 928 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 929
 930 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 931
 932 static u32  rkpm_slp_mode_set(u32 ctrbits)
 933 {
 934     u32 mode_set,mode_set1;
 935
 936     // setting gpio0_a0 arm off pin
 937
 938     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 939
 940     pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
 941     pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
 942
 943     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 944     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 945
 946     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 947
 948
 949
 950     //mode_set1=pmu_pwr_mode_con1;
 951     //mode_set=pmu_pwr_mode_con0;
 952
 953    //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 954    pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
 955
 956     // enable boot ram
 957     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 958     dsb();
 959
 960     reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 961     dsb();
 962
 963     mode_set=  BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
 964      mode_set1=0;
 965
 966     if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
 967     {
 968         rkpm_ddr_printascii("-autoidle-");
 969         mode_set|=BIT(pmu_clk_core_src_gate_en);
 970     }
 971     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
 972     {
 973         rkpm_ddr_printascii("-armdp-");
 974         mode_set|=BIT(pmu_a12_0_pd_en);
 975     }
 976     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
 977     {
 978         rkpm_ddr_printascii("-armoff-");
 979         mode_set|=BIT(pmu_scu_en)
 980                             //|BIT(pmu_a12_0_pd_en)
 981                             |BIT(pmu_clk_core_src_gate_en) // »½ÐÑºóÒì³£
 982                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 983                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 984                             //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 985                             |BIT(pmu_chip_pd_en);
 986         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 987                                 |BIT(pmu_clr_alive)
 988                                 |BIT(pmu_clr_peri)
 989                                 |BIT(pmu_clr_bus)
 990                                 |BIT(pmu_clr_dma)
 991                                 ;
 992     }
 993     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
 994     {
 995
 996         rkpm_ddr_printascii("-armoff-logdp-");
 997
 998         mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
 999                             |BIT(pmu_chip_pd_en)
1000                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
1001                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
1002                             |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
1003                             |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
1004                             ;
1005         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
1006                            |BIT(pmu_clr_alive)
1007                            |BIT(pmu_clr_peri)
1008                            |BIT(pmu_clr_bus)
1009                            |BIT(pmu_clr_dma)
1010                           ;
1011
1012     }
1013     else
1014     {
1015         mode_set=0;
1016         mode_set1=0;
1017     }
1018
1019
1020     if(mode_set&BIT(pmu_osc_24m_dis))
1021     {
1022         rkpm_ddr_printascii("osc_off");
1023         pmu_writel(32*30,RK3288_PMU_OSC_CNT);
1024         pmu_writel(32*30,RK3288_PMU_STABL_CNT);
1025     }
1026     else
1027     {
1028         pmu_writel(24*1000*10,RK3288_PMU_STABL_CNT);
1029
1030        // pmu_writel(24*1000*20,RK3288_PMU_CORE_PWRDWN_CNT);
1031     }
1032
1033     if(mode_set&BIT(pmu_ddr0io_ret_en))
1034     {
1035         rkpm_ddr_printascii("ddrc_off");
1036         ddr_pin_set_fun(0x0,0xa,0x1,0x1);
1037         ddr_pin_set_fun(0x0,0xa,0x2,0x1);
1038         ddr_pin_set_fun(0x0,0xa,0x3,0x1);
1039     }
1040
1041     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
1042     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
1043
1044   //  rkpm_ddr_printhex(mode_set);
1045   //  rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1046
1047     return (pmu_readl(RK3288_PMU_PWRMODE_CON));
1048 }
1049
1050 static inline void  rkpm_slp_mode_set_resume(void)
1051 {
1052
1053     pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1054     pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1055
1056     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1057     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1058     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1059
1060 }
1061
1062 static void sram_code_data_save(u32 pwrmode)
1063 {
1064         char *code_src,*data_src;
1065         u32 code_size,data_size;
1066
1067
1068         //u32 *p;
1069         if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1070         {
1071             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1072             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1073
1074             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=1;
1075             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325]=rkpm_armerrata_818325();//
1076
1077             sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1078             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1079             #if 0
1080             rkpm_ddr_printascii("l2&arm_errata--");
1081             rkpm_ddr_printhex(rkpm_l2_config());
1082             rkpm_ddr_printhex(rkpm_armerrata_818325());
1083             rkpm_ddr_printascii("\n");
1084             #endif
1085         }
1086         else
1087         {
1088             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=0;
1089             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=0;
1090             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1091             return ;
1092         }
1093
1094         if(pwrmode&BIT(pmu_bus_pd_en))
1095         {
1096                 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1097                 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1098                 code_src=(char *)ddr_get_resume_code_info(&code_size);
1099                 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1100                 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1101                 data_src=(char *)ddr_get_resume_data_info(&data_size);
1102                 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1103        }
1104         else
1105         {
1106             sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1107         }
1108
1109         sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1110
1111         flush_cache_all();
1112         outer_flush_all();
1113         local_flush_tlb_all();
1114
1115 }
1116
1117 static inline void sram_code_data_resume(u32 pwrmode)
1118 {
1119          if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1120         {
1121              sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1122         }
1123
1124 }
1125
1126 static void  rkpm_peri_save(u32 power_mode)
1127 {
1128 //    u32 gpio_gate[2];
1129
1130     if(power_mode&BIT(pmu_scu_en))
1131     {
1132         rkpm_gic_dist_save(&slp_gic_save[0]);
1133     }
1134 #if 0
1135     gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1136     gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1137     RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1138     cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1139                          RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1140 #endif
1141
1142     if(power_mode&BIT(pmu_bus_pd_en))
1143    {
1144        #if 0
1145         //gpio7_c6
1146         //gpio7_c7
1147         ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1148         ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1149         ddr_pin_set_fun(7,0xc,0x6,0);
1150
1151         ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1152         ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1153         ddr_pin_set_fun(7,0xc,0x7,0);
1154         #endif
1155         //slp_uart_save(2);
1156         #if 0
1157         ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1158         ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1159         ddr_pin_set_fun(0,0xb,0x7,0);
1160
1161         ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1162         ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1163         ddr_pin_set_fun(0,0xc,0x0,0);
1164         #endif
1165         slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1166         slp_i2c_save(1);//i2c audio
1167     }
1168
1169 #if 0
1170         cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1171                                       RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1172         cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1173 #endif
1174
1175 }
1176
1177 static inline void  rkpm_peri_resume(u32 power_mode)
1178 {
1179     if(power_mode&BIT(pmu_scu_en))
1180     {
1181         //fiq_glue_resume();
1182         rkpm_gic_dist_resume(&slp_gic_save[0]);
1183         fiq_glue_resume();
1184         //rkpm_ddr_printascii("gic res");
1185     }
1186     if(power_mode&BIT(pmu_bus_pd_en))
1187    {
1188         slp_i2c_resume(0);// i2c pmu
1189         slp_i2c_resume(1);//i2c audio
1190     }
1191
1192 }
1193
1194 static u32 pdbus_gate_reg[5];
1195 static inline void  rkpm_peri_resume_first(u32 power_mode)
1196 {
1197
1198     if(power_mode&BIT(pmu_bus_pd_en))
1199     {
1200         cru_writel(0xffff0000|pdbus_gate_reg[0],RK3288_CRU_CLKGATES_CON(0));
1201         cru_writel(0xffff0000|pdbus_gate_reg[1],RK3288_CRU_CLKGATES_CON(4));
1202         cru_writel(0xffff0000|pdbus_gate_reg[2],RK3288_CRU_CLKGATES_CON(5));
1203         cru_writel(0xffff0000|pdbus_gate_reg[3],RK3288_CRU_CLKGATES_CON(10));
1204         cru_writel(0xffff0000|pdbus_gate_reg[4],RK3288_CRU_CLKGATES_CON(11));
1205     }
1206
1207
1208       if(power_mode&BIT(pmu_bus_pd_en))
1209         slp_uartdbg_resume();
1210 }
1211
1212 static void rkpm_slp_setting(void)
1213 {
1214     rk_usb_power_down();
1215
1216     if(rk3288_powermode&BIT(pmu_bus_pd_en))
1217     {
1218         // pd bus will be power down ,but if it reup,ungating clk for its reset
1219         // ungating pdbus clk
1220         pdbus_gate_reg[0]=cru_readl(RK3288_CRU_CLKGATES_CON(0));
1221         pdbus_gate_reg[1]=cru_readl(RK3288_CRU_CLKGATES_CON(4));
1222         pdbus_gate_reg[2]=cru_readl(RK3288_CRU_CLKGATES_CON(5));
1223         pdbus_gate_reg[3]=cru_readl(RK3288_CRU_CLKGATES_CON(10));
1224         pdbus_gate_reg[4]=cru_readl(RK3288_CRU_CLKGATES_CON(11));
1225
1226         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(0));
1227         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(4));
1228         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(5));
1229         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(10));
1230         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(11));
1231
1232         RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_UART2);
1233        // RK3288_CRU_UNGATING_OPS((RK3288_CLKGATE_UART0_SRC+2*2));
1234        //c2c host
1235        RK3288_CRU_UNGATING_OPS(RK3288_CRU_CONS_GATEID(13)+8);
1236
1237     }
1238
1239 }
1240
1241
1242 static void rkpm_save_setting_resume_first(void)
1243 {
1244         rk_usb_power_up();
1245         rkpm_peri_resume_first(rk3288_powermode);
1246
1247         // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1248         #if 0
1249         //rk319x_pm_set_power_domain(PD_PERI,true);
1250         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1251         slp_pin_gpio_resume(1);
1252         slp_pin_gpio_resume(2);
1253         slp_pin_gpio_resume(3);
1254         slp_pin_gpio_resume(4);
1255
1256         #if 0
1257         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1258         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1259
1260         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1261         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1262         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1263         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1264         #endif
1265         //sram_printch_uart_enable();
1266         slp_uart_resume(2);
1267        #endif
1268 }
1269
1270 static void rkpm_save_setting(u32 ctrbits)
1271 {
1272         rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1273         if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1274        {
1275                 sram_code_data_save(rk3288_powermode);
1276                 rkpm_peri_save(rk3288_powermode);
1277         }
1278         else
1279              return ;
1280
1281 }
1282 static void rkpm_save_setting_resume(void)
1283 {
1284
1285         #if 0
1286         rkpm_ddr_printascii("l2&arm_errata--");
1287         rkpm_ddr_printhex(rkpm_l2_config());
1288         rkpm_ddr_printhex(rkpm_armerrata_818325());
1289         rkpm_ddr_printascii("\n");
1290         #endif
1291
1292          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1293         {
1294             sram_code_data_resume(rk3288_powermode);
1295             rkpm_peri_resume(rk3288_powermode);
1296         }
1297          rkpm_slp_mode_set_resume();
1298
1299 }
1300
1301 /*******************************common code  for rkxxx*********************************/
1302 static void  inline uart_printch(char byte)
1303 {
1304         u32 reg_save[2];
1305         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART*2);
1306         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1307
1308         if(CONFIG_RK_DEBUG_UART==4)
1309             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1310         if(CONFIG_RK_DEBUG_UART==2)
1311             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1312
1313         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1314         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1315         RK3288_CRU_UNGATING_OPS(u_clk_id);
1316         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1317
1318         rkpm_udelay(1);
1319
1320 write_uart:
1321         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1322         dsb();
1323
1324         /* loop check LSR[6], Transmitter Empty bit */
1325         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1326                 barrier();
1327
1328         if (byte == '\n') {
1329                 byte = '\r';
1330                 goto write_uart;
1331         }
1332
1333          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1334          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1335 }
1336
1337 void PIE_FUNC(sram_printch)(char byte)
1338 {
1339         uart_printch(byte);
1340 }
1341
1342 static void pll_udelay(u32 udelay);
1343
1344 #ifdef CONFIG_RK_LAST_LOG
1345 extern void rk_last_log_text(char *text, size_t size);
1346 #endif
1347
1348 static void  ddr_printch(char byte)
1349 {
1350         char last_char;
1351
1352         uart_printch(byte);
1353
1354 #ifdef CONFIG_RK_LAST_LOG
1355         last_char=byte;
1356         rk_last_log_text(&last_char,1);
1357
1358         if (byte == '\n') {
1359             last_char='\r';
1360             rk_last_log_text(&last_char,1);
1361          }
1362
1363 #endif
1364         pll_udelay(2);
1365 }
1366 /*******************************gpio func*******************************************/
1367 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1368 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1369 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1370 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1371 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1372 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1373 {
1374         u32 off_set;
1375         bank-=0xa;
1376
1377         if(port==0)
1378         {
1379             if(bank>2)
1380                 return;
1381             off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1382             pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1383         }
1384         else if(port==1||port==2)
1385         {
1386             off_set=port*(4*4)+bank*4;
1387             reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1388         }
1389         else if(port==3)
1390         {
1391             if(bank<=2)
1392             {
1393                 off_set=0x20+bank*4;
1394                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1395
1396             }
1397             else
1398             {
1399                 off_set=0x2c+(b_gpio/4)*4;
1400                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1401             }
1402
1403         }
1404         else if(port==4)
1405         {
1406             if(bank<=1)
1407             {
1408                 off_set=0x34+bank*8+(b_gpio/4)*4;
1409                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1410             }
1411             else
1412             {
1413                 off_set=0x44+(bank-2)*4;
1414                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1415             }
1416
1417         }
1418         else if(port==5||port==6)
1419         {
1420                 off_set=0x4c+(port-5)*4*4+bank*4;
1421                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1422         }
1423         else if(port==7)
1424         {
1425             if(bank<=1)
1426             {
1427                 off_set=0x6c+bank*4;
1428                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1429             }
1430             else
1431             {
1432                 off_set=0x74+(bank-2)*8+(b_gpio/4)*4;
1433                 //rkpm_ddr_printascii("gpio");
1434                 //rkpm_ddr_printhex(off_set);
1435                 //rkpm_ddr_printascii("-");
1436                 //rkpm_ddr_printhex((b_gpio%4)*4);
1437
1438                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1439
1440                 //rkpm_ddr_printhex(reg_readl(RK_GRF_VIRT+0+off_set));
1441                 //rkpm_ddr_printascii("\n");
1442             }
1443
1444         }
1445         else if(port==8)
1446         {
1447             if(bank<=1)
1448             {
1449                 off_set=0x80+bank*4;
1450                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1451             }
1452         }
1453
1454 }
1455
1456 #if 0
1457 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1458 {
1459
1460 }
1461 #endif
1462 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1463 {
1464     u32 off_set;
1465
1466     bank-=0xa;
1467
1468     if(port > 0)
1469     {
1470         //gpio1_d st
1471         //if(port==1&&bank<3)
1472        //  return;
1473         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1474         off_set=(0x14c-0x1c)+port*(4*4)+bank*4;
1475
1476         #if 0
1477         rkpm_ddr_printascii("gpio pull\n");
1478         rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1479         rkpm_ddr_printhex(b_gpio);
1480         rkpm_ddr_printhex(pull);
1481         rkpm_ddr_printhex(off_set);
1482         rkpm_ddr_printhex(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3));
1483         #endif
1484
1485         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1486
1487     }
1488     else
1489     {
1490         if(bank>2)// gpio0_d is not support
1491             return;
1492         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1493     }
1494
1495 }
1496
1497 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1498 {
1499     u32 off_set;
1500
1501     bank-=0xa;
1502
1503     if(port > 0)
1504     {
1505         //gpio1_d st
1506         if(port==1&&bank<3)
1507             return 0;
1508         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1509         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1510         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1511
1512     }
1513     else
1514     {
1515         if(bank>2)// gpio0_d is not support
1516             return 0;
1517         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1518     }
1519
1520 }
1521
1522
1523 //RKPM_GPIOS_INPUT
1524 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1525 {
1526     u32 val;
1527
1528     bank-=0xa;
1529     b_gpio=bank*8+b_gpio;//
1530
1531     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1532
1533     if(type==RKPM_GPIO_OUTPUT)
1534         val|=(0x1<<b_gpio);
1535     else
1536         val&=~(0x1<<b_gpio);
1537     #if 0
1538     rkpm_ddr_printascii("gpio out\n");
1539     rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1540     rkpm_ddr_printhex(b_gpio);
1541
1542     rkpm_ddr_printhex(type);
1543     rkpm_ddr_printhex(val);
1544     #endif
1545     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1546
1547     //rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR));
1548
1549
1550 }
1551
1552 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1553 {
1554     bank-=0xa;
1555     b_gpio=bank*8+b_gpio;
1556     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1557 }
1558
1559 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1560 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1561 {
1562     u32 val;
1563
1564     bank-=0xa;
1565     b_gpio=bank*8+b_gpio;
1566
1567     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1568
1569     if(level==RKPM_GPIO_OUT_H)
1570         val|=(0x1<<b_gpio);
1571     else //
1572         val&=~(0x1<<b_gpio);
1573
1574      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1575 }
1576
1577 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1578 {
1579     bank-=0xa;
1580     b_gpio=bank*8+b_gpio;
1581     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1582 }
1583
1584 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1585 {
1586
1587     bank-=0xa;
1588     b_gpio=bank*8+b_gpio;
1589
1590     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1591 }
1592 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1593 {
1594     u32 val;
1595
1596     bank-=0xa;
1597     b_gpio=bank*8+b_gpio;
1598
1599     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1600     rkpm_ddr_printascii("\n inten:");
1601     rkpm_ddr_printhex(val);
1602
1603     rkpm_ddr_printascii("-");
1604     if(en==1)
1605         val|=(0x1<<b_gpio);
1606     else //
1607         val&=~(0x1<<b_gpio);
1608
1609     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1610     dsb();
1611
1612      rkpm_ddr_printhex(val);
1613      rkpm_ddr_printascii("-");
1614
1615      rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1616
1617     rkpm_ddr_printascii("\n");
1618
1619
1620 }
1621 #if 0
1622 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1623 {
1624         pin_set_fun(port,bank,b_gpio,fun);
1625 }
1626 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1627 {
1628     return pin_get_funset(port,bank,b_gpio);
1629 }
1630
1631 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1632 {
1633         pin_set_pull(port,bank,b_gpio,fun);
1634 }
1635 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1636 {
1637     return pin_get_pullset(port,bank,b_gpio);
1638 }
1639
1640 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1641 {
1642     gpio_set_in_output(port,bank,b_gpio,type);
1643 }
1644
1645 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1646 {
1647     return gpio_get_in_outputset(port,bank,b_gpio);
1648 }
1649
1650 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1651 {
1652
1653     gpio_set_output_level(port,bank,b_gpio,level);
1654
1655 }
1656
1657 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1658 {
1659     return gpio_get_output_levelset(port,bank,b_gpio);
1660 }
1661 #endif
1662 #if 0
1663 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1664 {
1665     return gpio_get_input_level(port,bank,b_gpio);
1666 }
1667 #endif
1668 //ddr
1669 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1670 {
1671         pin_set_fun(port,bank,b_gpio,fun);
1672 }
1673 #if 0
1674 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1675 {
1676     return pin_get_funset(port,bank,b_gpio);
1677 }
1678 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1679 {
1680     return pin_get_pullset(port,bank,b_gpio);
1681 }
1682 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1683 {
1684     return gpio_get_in_outputset(port,bank,b_gpio);
1685 }
1686
1687 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1688 {
1689     return gpio_get_output_levelset(port,bank,b_gpio);
1690 }
1691 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1692 {
1693     return gpio_get_input_level(port,bank,b_gpio);
1694 }
1695
1696
1697 #endif
1698
1699
1700 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1701 {
1702         pin_set_pull(port,bank,b_gpio,fun);
1703 }
1704
1705 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1706 {
1707     gpio_set_in_output(port,bank,b_gpio,type);
1708 }
1709 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1710 {
1711     gpio_set_output_level(port,bank,b_gpio,level);
1712 }
1713
1714
1715
1716 #define GPIO_DTS_NUM (20)
1717 static  u32 suspend_gpios[GPIO_DTS_NUM];
1718 static  u32 resume_gpios[GPIO_DTS_NUM];
1719
1720 static int of_find_property_value_getsize(const struct device_node *np,const char *propname)
1721 {
1722         struct property *prop = of_find_property(np, propname, NULL);
1723
1724         if (!prop)
1725                 return 0;
1726         if (!prop->value)
1727                 return 0;
1728         return prop->length;
1729 }
1730
1731 static  void rkpm_pin_gpio_config(u32 pin_gpio_bits)
1732 {
1733
1734     u32 pins;
1735     u8 port,bank,b_gpio,fun,in_out, level, pull;
1736
1737     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1738     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1739     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1740     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1741
1742     port=RKPM_PINBITS_PORT(pins);
1743     bank=RKPM_PINBITS_BANK(pins);
1744     b_gpio=RKPM_PINBITS_BGPIO(pins);
1745     fun=RKPM_PINBITS_FUN(pins);
1746
1747
1748     if(!fun)
1749    {
1750         if(in_out==RKPM_GPIO_OUTPUT)
1751         {
1752             if(level==RKPM_GPIO_OUT_L)
1753                 pull=RKPM_GPIO_PULL_DN;
1754             else
1755                 pull=RKPM_GPIO_PULL_UP;
1756
1757             ddr_gpio_set_output_level(port,bank,b_gpio,level);
1758         }
1759         //rkpm_ddr_printhex(pins);
1760
1761         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1762     }
1763
1764     ddr_pin_set_pull(port,bank,b_gpio,pull);
1765     ddr_pin_set_fun(port,bank,b_gpio,fun);
1766
1767
1768
1769 }
1770
1771 #define RKPM_PINGPIO_BITS_PINTOPORT(pin_gpio_bits) RKPM_PINBITS_PORT(RKPM_PINGPIO_BITS_PIN((pin_gpio_bits)))
1772 #define  rkpm_gpio_pclk_idx(port) ((port)==0) ? RK3288_CLKGATE_PCLK_GPIO0 : (RK3288_CLKGATE_PCLK_GPIO1+(port)-1)
1773
1774 //rk3288_powermode
1775 static void rkpm_pins_setting(u32 *gpios,u32 cnt)
1776 {
1777        u32 i,clk_id;
1778        u32 gpio_clk_reg[9];
1779        u8 port;
1780
1781       // rkpm_ddr_printascii("\ngpios");
1782
1783         for(i=0;i<9;i++)
1784         {
1785             gpio_clk_reg[i]=0xffff0000;
1786         }
1787
1788        for(i=0;i<cnt;i++)
1789        {
1790             if(gpios[i]!=0)
1791            {
1792                 port=RKPM_PINGPIO_BITS_PINTOPORT(gpios[i]);
1793                 if(gpio_clk_reg[port]==0xffff0000)
1794                 {
1795                     clk_id=rkpm_gpio_pclk_idx(port);
1796                     gpio_clk_reg[port]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id))&0xffff;
1797                     RK3288_CRU_UNGATING_OPS(clk_id);
1798                 }
1799                // rkpm_ddr_printhex(gpios[i]);
1800                 rkpm_pin_gpio_config(gpios[i]);
1801            }
1802        }
1803       // rkpm_ddr_printascii("\n");
1804
1805  #if 0
1806         for(i=0;i<9;i++)
1807        {
1808            rkpm_ddr_regs_dump(RK_GPIO_VIRT(i),0,0x4);
1809        }
1810        //
1811        rkpm_ddr_regs_dump(RK_GRF_VIRT,0xc,0x84);
1812        rkpm_ddr_regs_dump(RK_GRF_VIRT,0x14c,0x1b4);
1813      //  rkpm_ddr_regs_dump(RK_PMU_VIRT,0x64,0x6c);
1814        //rkpm_ddr_regs_dump(RK_PMU_VIRT,0x84,0x9c);
1815    #endif
1816
1817         for(i=0;i<9;i++)
1818        {
1819             if(gpio_clk_reg[i]!=0xffff0000)
1820             {
1821                 clk_id=rkpm_gpio_pclk_idx(i);
1822                 cru_writel(gpio_clk_reg[i]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
1823             }
1824        }
1825
1826 }
1827
1828 static void  rkpm_gpio_suspend(void)
1829 {
1830     rkpm_pins_setting(&suspend_gpios[0],GPIO_DTS_NUM);
1831 }
1832
1833
1834
1835 static void  rkpm_gpio_resume(void)
1836 {
1837      rkpm_pins_setting(&resume_gpios[0],GPIO_DTS_NUM);
1838 }
1839
1840 #if 1
1841 static void gpio_get_dts_info(struct device_node *parent)
1842 {
1843         int i;
1844         size_t temp_len;
1845     //return;
1846
1847         for(i=0;i<GPIO_DTS_NUM;i++)
1848         {
1849             suspend_gpios[i]=0;
1850             resume_gpios[i]=0;
1851         }
1852
1853      #if 1
1854         temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-suspend_gpios");
1855         if(temp_len)
1856         {
1857             printk("%s suspend:%d\n",__FUNCTION__,temp_len);
1858             if(temp_len)
1859             {
1860                 if(of_property_read_u32_array(parent,"rockchip,pmic-suspend_gpios",&suspend_gpios[0],temp_len/4))
1861                 {
1862                         suspend_gpios[0]=0;
1863                        printk("%s:get pm ctr error\n",__FUNCTION__);
1864                 }
1865             }
1866         }
1867
1868        temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-resume_gpios");
1869        if(temp_len)
1870        {
1871            printk("%s resume:%d\n",__FUNCTION__,temp_len);
1872            if(of_property_read_u32_array(parent,"rockchip,pmic-resume_gpios",&resume_gpios[0],temp_len/4))
1873            {
1874                     resume_gpios[0]=0;
1875                    printk("%s:get pm ctr error\n",__FUNCTION__);
1876            }
1877         }
1878      #endif
1879
1880      printk("rockchip,pmic-suspend_gpios:");
1881      for(i=0;i<GPIO_DTS_NUM;i++)
1882      {
1883          printk("%x ",suspend_gpios[i]);
1884          if(i==(GPIO_DTS_NUM-1))
1885              printk("\n");
1886      }
1887
1888      printk("rockchip,pmic-resume_gpios:");
1889      for(i=0;i<GPIO_DTS_NUM;i++)
1890      {
1891           printk("%x ",resume_gpios[i]);
1892           if(i==(GPIO_DTS_NUM-1))
1893               printk("\n");
1894      }
1895
1896    rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1897
1898 }
1899 #endif
1900
1901 /*******************************clk gating config*******************************************/
1902 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1903 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1904
1905
1906 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1907 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1908 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1909
1910
1911 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1912 static u32 *p_rkpm_clkgt_last_set;
1913
1914 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1915
1916 void PIE_FUNC(gtclks_sram_suspend)(void)
1917 {
1918     int i;
1919    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1920    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1921
1922     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1923     {
1924         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1925         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1926         #if 0
1927         rkpm_sram_printch('\n');
1928         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1929         rkpm_sram_printch('-');
1930         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1931         rkpm_sram_printch('-');
1932         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1933         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1934         rkpm_sram_printch('\n');
1935         #endif
1936     }
1937
1938         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1939         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1940
1941 }
1942
1943 void PIE_FUNC(gtclks_sram_resume)(void)
1944 {
1945     int i;
1946     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1947     {
1948         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1949     }
1950 }
1951 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
1952 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1953
1954 #define gpio7_readl(offset)     readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1955 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1956
1957 int gpio7_pin_data1, gpio7_pin_dir1;
1958 int gpio7_pin_iomux1;
1959
1960 static void gtclks_suspend(void)
1961 {
1962     int i;
1963         gpio7_pin_data1= gpio7_readl(0);
1964         gpio7_pin_dir1 = gpio7_readl(0x04);
1965         gpio7_pin_iomux1 =  gpio7_readl(0x6c);
1966         grf_writel(0x00040000, 0x6c);
1967         gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1968         gpio7_writel((gpio7_pin_data1|2), 0x00);
1969
1970   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1971                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1972     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1973     {
1974             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1975            // 160 1a8
1976            #if 0
1977            if(
1978                // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1979                 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1980                 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1981               //  RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1982                 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1983                // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1984                // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1985
1986
1987                 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1988                // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1989                // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1990                // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1991                 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1992                 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
1993                 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
1994                 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
1995                 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
1996                 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
1997                 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
1998                // RK3288_CRU_CLKGATES_CON(i)==0x1a8
1999                RK3288_CRU_CLKGATES_CON(i)==0xfff
2000             )
2001             {
2002
2003                  cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
2004                // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2005
2006             }
2007            else
2008             #endif
2009             {
2010                // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
2011                CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2012            }
2013            #if 0
2014             rkpm_ddr_printch('\n');
2015             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
2016             rkpm_ddr_printch('-');
2017             rkpm_ddr_printhex(clk_ungt_msk[i]);
2018             rkpm_ddr_printch('-');
2019             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
2020             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
2021             rkpm_ddr_printch('\n');
2022             #endif
2023     }
2024
2025 }
2026
2027 static void gtclks_resume(void)
2028 {
2029     int i;
2030      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2031     {
2032        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2033      }
2034      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
2035                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
2036         grf_writel(0x00040004, 0x6c);
2037
2038 }
2039 /********************************pll power down***************************************/
2040
2041 static void pm_pll_wait_lock(u32 pll_idx)
2042 {
2043         u32 delay = 600000U;
2044        // u32 mode;
2045      //  mode=cru_readl(RK3288_CRU_MODE_CON);
2046         dsb();
2047         dsb();
2048         dsb();
2049         dsb();
2050         dsb();
2051         dsb();
2052         while (delay > 0) {
2053                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
2054                         break;
2055                 delay--;
2056         }
2057         if (delay == 0) {
2058                 rkpm_ddr_printascii("unlock-pll:");
2059                 rkpm_ddr_printhex(pll_idx);
2060                 rkpm_ddr_printch('\n');
2061         }
2062     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
2063 }
2064
2065 static void pll_udelay(u32 udelay)
2066 {
2067     u32 mode;
2068     mode=cru_readl(RK3288_CRU_MODE_CON);
2069     // delay in 24m
2070     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2071
2072     rkpm_udelay(udelay*5);
2073
2074     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2075 }
2076
2077 static u32 plls_con0_save[END_PLL_ID];
2078 static u32 plls_con1_save[END_PLL_ID];
2079 static u32 plls_con2_save[END_PLL_ID];
2080 static u32 plls_con3_save[END_PLL_ID];
2081
2082 static u32 cru_mode_con;
2083
2084 static inline void plls_suspend(u32 pll_id)
2085 {
2086     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
2087     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
2088     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
2089     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
2090
2091     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
2092
2093 }
2094 static inline void plls_resume(u32 pll_id)
2095 {
2096         u32 pllcon0, pllcon1, pllcon2;
2097
2098         if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
2099             return ;
2100
2101         //enter slowmode
2102         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
2103
2104         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
2105         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
2106
2107         pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
2108         pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
2109         pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
2110
2111         //enter rest
2112         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
2113         cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
2114         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
2115         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
2116
2117         pll_udelay(5);
2118         //udelay(5); //timer7 delay
2119
2120         //return form rest
2121         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
2122
2123         //wating lock state
2124         pll_udelay(168);
2125         pm_pll_wait_lock(pll_id);
2126
2127         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
2128
2129 }
2130
2131 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
2132
2133 static void pm_plls_suspend(void)
2134 {
2135
2136    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2137    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2138    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2139
2140     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
2141     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
2142     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
2143     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
2144     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
2145     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
2146     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2147
2148     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2149
2150
2151     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2152     plls_suspend(NPLL_ID);
2153
2154 // cpll
2155     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2156
2157 // gpll
2158     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2159
2160     // set 1,pdbus pll is gpll
2161     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2162
2163     // pd_bus clk
2164     cru_writel(0
2165                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
2166                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
2167                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
2168                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
2169                      , RK3288_CRU_CLKSELS_CON(1));
2170
2171     //crypto for pd_bus
2172     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2173
2174     // peri aclk hclk pclk
2175     cru_writel(0
2176                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2177                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
2178                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
2179                         , RK3288_CRU_CLKSELS_CON(10));
2180     // pmu alive
2181     cru_writel(CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2182
2183     plls_suspend(CPLL_ID);
2184     plls_suspend(GPLL_ID);
2185
2186 //apll
2187    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2188      // core_m0 core_mp a12_core
2189     cru_writel(0
2190                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
2191                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
2192                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2193                       , RK3288_CRU_CLKSELS_CON(0));
2194     // core0 core1 core2 core3
2195     cru_writel(0
2196                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2197                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2198                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2199                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2200                       , RK3288_CRU_CLKSELS_CON(36));
2201     // l2ram atclk pclk
2202     #if 1
2203     cru_writel(0
2204                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2205                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2206                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2207                      , RK3288_CRU_CLKSELS_CON(37));
2208     #else
2209     cru_writel(0
2210                       |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2211                       |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2212                        |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2213                        , RK3288_CRU_CLKSELS_CON(37));
2214     #endif
2215
2216
2217     plls_suspend(APLL_ID);
2218
2219 }
2220
2221 static void pm_plls_resume(void)
2222 {
2223
2224
2225         // core_m0 core_mp a12_core
2226         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
2227         // core0 core1 core2 core3
2228         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
2229                         , RK3288_CRU_CLKSELS_CON(36));
2230         // l2ram atclk pclk
2231         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
2232
2233         plls_resume(APLL_ID);
2234         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2235
2236         // peri aclk hclk pclk
2237         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
2238                                                                             , RK3288_CRU_CLKSELS_CON(10));
2239         //pd bus gpll sel
2240         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
2241         // pd_bus clk
2242         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
2243                     , RK3288_CRU_CLKSELS_CON(1));
2244
2245         // crypto
2246         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
2247
2248
2249           // pmu alive
2250         cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2251
2252         plls_resume(GPLL_ID);
2253         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
2254
2255         plls_resume(CPLL_ID);
2256         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
2257
2258         plls_resume(NPLL_ID);
2259         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2260
2261        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2262        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2263        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2264
2265 }
2266
2267 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2268
2269 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2270 {
2271
2272     int div;
2273     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2274     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2275     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2276
2277
2278     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2279     {
2280         div=3;
2281         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2282         cru_writel(0
2283                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2284                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2285                             , RK3288_CRU_MODE_CON);
2286     }
2287     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2288     {
2289         div=31;
2290     }
2291
2292     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2293     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2294     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2295
2296 }
2297
2298 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2299 {
2300
2301     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2302     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2303     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2304     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2305                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2306                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2307                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2308
2309 }
2310
2311
2312 static void clks_gating_suspend_init(void)
2313 {
2314     // get clk gating info
2315     if(rockchip_pie_chunk)
2316         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2317     else
2318         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2319     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2320         ==RK3288_CRU_CLKGATES_CON(0))
2321     {
2322         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2323         if(rockchip_pie_chunk)
2324             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2325                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2326
2327         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2328
2329     }
2330     if(rockchip_pie_chunk)
2331         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2332                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2333 }
2334
2335 /***************************prepare and finish reg_pread***********************************/
2336
2337
2338
2339 #define GIC_DIST_PENDING_SET            0x200
2340 static noinline void rk3288_pm_dump_irq(void)
2341 {
2342         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2343         u32 irq[4];
2344         int i;
2345
2346         for (i = 0; i < ARRAY_SIZE(irq); i++)
2347                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2348         for (i = 0; i < ARRAY_SIZE(irq); i++) {
2349                 if (irq[i])
2350                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2351         }
2352         printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2353         for (i = 0; i <= 8; i++) {
2354                 if (irq_gpio & (1 << i))
2355                         printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2356         }
2357 }
2358
2359 #if 0
2360 #define DUMP_GPIO_INTEN(ID) \
2361 do { \
2362         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2363         if (en) { \
2364                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2365                 rkpm_ddr_printhex(en); \
2366                 rkpm_ddr_printch('\n'); \
2367                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2368         } \
2369 } while (0)
2370 #else
2371
2372 #define DUMP_GPIO_INTEN(ID) \
2373     do { \
2374         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2375         if (en) { \
2376                 printk("GPIO%d_INTEN: %08x\n", ID, en); \
2377         } \
2378     } while (0)
2379
2380 #endif
2381
2382
2383 //dump while irq is enable
2384 static noinline void rk3288_pm_dump_inten(void)
2385 {
2386         DUMP_GPIO_INTEN(0);
2387         DUMP_GPIO_INTEN(1);
2388         DUMP_GPIO_INTEN(2);
2389         DUMP_GPIO_INTEN(3);
2390         DUMP_GPIO_INTEN(4);
2391         DUMP_GPIO_INTEN(5);
2392         DUMP_GPIO_INTEN(6);
2393         DUMP_GPIO_INTEN(7);
2394         DUMP_GPIO_INTEN(8);
2395 }
2396
2397 static  void rkpm_prepare(void)
2398 {
2399
2400         int i;
2401          for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2402         {
2403            //cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2404          }
2405
2406         #if 0
2407         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2408
2409        // rkpm_ddr_printhex(temp);
2410         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2411         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2412        // rkpm_ddr_printhex(temp);
2413         #endif
2414         // dump GPIO INTEN for debug
2415         rk3288_pm_dump_inten();
2416 }
2417
2418 static void rkpm_finish(void)
2419 {
2420         rk3288_pm_dump_irq();
2421 }
2422
2423 #if 0
2424 static  void interface_ctr_reg_pread(void)
2425 {
2426         //u32 addr;
2427         flush_cache_all();
2428         outer_flush_all();
2429         local_flush_tlb_all();
2430         #if 0  // do it in ddr suspend
2431         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2432                 readl_relaxed(addr);
2433         #endif
2434         readl_relaxed(RK_PMU_VIRT);
2435         readl_relaxed(RK_GRF_VIRT);
2436         readl_relaxed(RK_DDR_VIRT);
2437         readl_relaxed(RK_GPIO_VIRT(0));
2438         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2439         //readl_relaxed(RK_GPIO_VIRT(3));
2440 }
2441 #endif
2442 void PIE_FUNC(ddr_leakage_tst)(void)
2443 {
2444     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2445     rkpm_sram_printch('\n');
2446     rkpm_sram_printch('t');
2447     rkpm_sram_printch('e');
2448     rkpm_sram_printch('s');
2449     rkpm_sram_printch('t');
2450     while(1);
2451 }
2452
2453 static void __init  rk3288_suspend_init(void)
2454 {
2455     struct device_node *parent;
2456     u32 pm_ctrbits;
2457
2458     PM_LOG("%s enter\n",__FUNCTION__);
2459
2460     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2461
2462     if (IS_ERR_OR_NULL(parent)) {
2463                 PM_ERR("%s dev node err\n", __func__);
2464                 return;
2465         }
2466
2467
2468     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2469     {
2470             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2471             return ;
2472     }
2473     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2474     pm_io_base_map();
2475     memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2476     rkpm_set_ctrbits(pm_ctrbits);
2477
2478     gpio_get_dts_info(parent);
2479     clks_gating_suspend_init();
2480
2481     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2482
2483     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2484
2485     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2486
2487     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2488
2489      rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2490      rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2491
2492     if(rockchip_pie_chunk)
2493         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2494
2495     rkpm_set_ops_printch(ddr_printch);
2496 }