arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/wakeup_reason.h>
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28 __weak void rk_usb_power_down(void);
  29 __weak void rk_usb_power_up(void);
  30
  31 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
  32 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
  33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
  34
  35
  36 /*************************cru define********************************************/
  37
  38
  39 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  40 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  41
  42 enum rk_plls_id {
  43         APLL_ID = 0,
  44         DPLL_ID,
  45         CPLL_ID,
  46         GPLL_ID,
  47         NPLL_ID,
  48         END_PLL_ID,
  49 };
  50
  51 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
  52 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
  53 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
  54
  55
  56 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
  57 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
  58
  59 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
  60 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
  61 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
  62
  63
  64 /*******************************gpio define **********************************************/
  65
  66 /* GPIO control registers */
  67 #define GPIO_SWPORT_DR          0x00
  68 #define GPIO_SWPORT_DDR         0x04
  69 #define GPIO_INTEN                      0x30
  70 #define GPIO_INTMASK            0x34
  71 #define GPIO_INTTYPE_LEVEL      0x38
  72 #define GPIO_INT_POLARITY       0x3c
  73 #define GPIO_INT_STATUS         0x40
  74 #define GPIO_INT_RAWSTATUS      0x44
  75 #define GPIO_DEBOUNCE           0x48
  76 #define GPIO_PORTS_EOI          0x4c
  77 #define GPIO_EXT_PORT           0x50
  78 #define GPIO_LS_SYNC            0x60
  79
  80 /***********************************sleep func*********************************************/
  81
  82 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
  83 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
  84 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
  85
  86 // sys resume code in boot ram
  87 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
  88 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
  89
  90
  91 // sys resume data in boot ram
  92 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
  93 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
  94
  95 // ddr resume data in boot ram
  96 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
  97 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
  98
  99 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
 100
 101 // the value is used to control cpu resume flow
 102 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 103 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
 104 static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);
 105
 106
 107
 108 #define BOOT_RAM_SIZE   (4*1024)
 109 #define INT_RAM_SIZE            (64*1024)
 110
 111 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
 112 static char int_ram_data[INT_RAM_SIZE];
 113
 114 char * ddr_get_resume_code_info(u32 *size);
 115 char * ddr_get_resume_data_info(u32 *size);
 116
 117 /**
 118 ddr code and data
 119
 120 *** code start
 121 ---data offset--
 122 ---code----
 123 ---data----
 124 */
 125 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
 126 {
 127
 128         char *addr_base,*addr_phy,*data_src,*data_dst;
 129         u32 sr_size,data_size;
 130
 131         addr_base=(char *)RKPM_BOOTRAM_BASE;
 132         addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 133         sr_size=RKPM_BOOTRAM_SIZE;
 134
 135         // save boot sram
 136          if(boot_save)
 137                  memcpy(boot_save,addr_base, sr_size);
 138
 139         // move resume code and date to boot sram
 140         // move sys code
 141         data_dst=(char *)RKPM_BOOT_CODE_BASE;
 142         data_src=(char *)rkpm_slp_cpu_resume;
 143         data_size=RKPM_BOOT_CODE_SIZE;
 144         memcpy((char *)data_dst,(char *)data_src, data_size);
 145
 146         // move sys data
 147         data_dst=(char *)resume_data_base;
 148         data_src=(char *)sleep_resume_data;
 149         data_size=sizeof(sleep_resume_data);
 150         memcpy((char *)data_dst,(char *)data_src, data_size);
 151
 152         if(flag)
 153         {
 154                 /*************************ddr code cpy*************************************/
 155                 // ddr code
 156                 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
 157                 data_src=(char *)ddr_get_resume_code_info(&data_size);
 158
 159                 data_size=RKPM_ALIGN(data_size,4);
 160
 161                 memcpy((char *)data_dst,(char *)data_src, data_size);
 162
 163                 // ddr data
 164                 data_dst=(char *)(data_dst+data_size);
 165
 166                 data_src=(char *)ddr_get_resume_data_info(&data_size);
 167                 data_size=RKPM_ALIGN(data_size,4);
 168                 memcpy((char *)data_dst,(char *)data_src, data_size);
 169
 170                 /*************************ddr code cpy  end*************************************/
 171                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 172                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 173                 /*************************int mem bak*************************************/
 174                 // int mem
 175                 addr_base=(char *)rockchip_sram_virt;
 176                 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 177                 sr_size=rockchip_sram_size;
 178                 //  rkpm_ddr_printascii("piephy\n");
 179                 //rkpm_ddr_printhex(addr_phy);
 180                 //mmap
 181                 if(int_save)
 182                     memcpy(int_save,addr_base, sr_size);
 183
 184                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 185                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 186         }
 187
 188  }
 189
 190 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
 191 {
 192
 193     char *addr_base,*addr_phy;
 194     u32 sr_size;
 195
 196     addr_base=(char *)RKPM_BOOTRAM_BASE;
 197     addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 198     sr_size=RKPM_BOOTRAM_SIZE;
 199     // save boot sram
 200     if(boot_save)
 201         memcpy(addr_base,boot_save, sr_size);
 202
 203     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 204     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 205
 206     if(flag)
 207     {
 208         // int mem
 209         addr_base=(char *)rockchip_sram_virt;
 210         addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 211         sr_size=rockchip_sram_size;
 212
 213         if(int_save)
 214         memcpy(addr_base, int_save,sr_size);
 215
 216         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 217         outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
 218      }
 219 }
 220
 221 /**************************************gic save and resume**************************/
 222 #define  RK_GICD_BASE (RK_GIC_VIRT)
 223 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 224
 225 #define PM_IRQN_START 32
 226 #define PM_IRQN_END     107//107
 227 static void pm_gic_enable(u32 irqs)
 228 {
 229
 230         int irqstart=0;
 231         u32 bit_off;
 232         void __iomem *reg_off;
 233         unsigned int gic_irqs;
 234
 235         gic_irqs = PM_IRQN_END;
 236         irqstart=PM_IRQN_START;//PM_IRQN_START;
 237
 238         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 239         bit_off=irqs%32;
 240         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 241
 242         dsb();
 243 }
 244
 245 static void rkpm_gic_disable(u32 irqs)
 246 {
 247         int irqstart=0;
 248         u32 bit_off;
 249         void __iomem *reg_off;
 250         unsigned int gic_irqs;
 251
 252         gic_irqs = PM_IRQN_END;
 253         irqstart=PM_IRQN_START;//PM_IRQN_START;
 254
 255         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 256         bit_off=irqs%32;
 257         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 258         dsb();
 259 }
 260
 261 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 262
 263 static u32 slp_gic_save[260+50];
 264
 265
 266 static void rkpm_gic_dist_save(u32 *context)
 267 {
 268      int i = 0,j,irqstart=0;
 269      unsigned int gic_irqs;
 270
 271      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 272      gic_irqs = (gic_irqs + 1) * 32;
 273      if (gic_irqs > 1020)
 274      gic_irqs = 1020;
 275      //printk("gic_irqs=%d\n",gic_irqs);
 276      //gic_irqs = PM_IRQN_END;
 277      irqstart=PM_IRQN_START;//PM_IRQN_START;
 278
 279      i = 0;
 280      //level
 281      for (j = irqstart; j < gic_irqs; j += 16)
 282       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 283      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 284
 285      /*
 286      * Set all global interrupts to this CPU only.
 287      */
 288      for(j = 0; j < gic_irqs; j += 4)
 289          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 290      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 291
 292      //pri
 293      for (j = 0; j < gic_irqs; j += 4)
 294          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 295      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 296
 297      //secure
 298      for (j = 0; j < gic_irqs; j += 32)
 299          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4) / 32);
 300      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 301
 302      for (j = irqstart; j < gic_irqs; j += 32)
 303          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 304      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 305
 306     #if 0
 307      //disable
 308      for (j = 0; j < gic_irqs; j += 32)
 309          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 310      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 311     #endif
 312
 313      //enable
 314      for (j = 0; j < gic_irqs; j += 32)
 315          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 316      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 317
 318
 319
 320      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 321      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 322
 323      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 324      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 325      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 326
 327     #if 0
 328      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 329      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 330      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 331      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 332      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 333     #endif
 334
 335     #if 1
 336     for (j = irqstart; j < gic_irqs; j += 32)
 337     {
 338         writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 339         dsb();
 340     }
 341     writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 342     writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 343
 344     writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 345     writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 346     #endif
 347
 348 }
 349
 350 static void rkpm_gic_dist_resume(u32 *context)
 351 {
 352
 353          int i = 0,j,irqstart=0;
 354          unsigned int gic_irqs;
 355
 356
 357          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 358          gic_irqs = (gic_irqs + 1) * 32;
 359          if (gic_irqs > 1020)
 360                  gic_irqs = 1020;
 361
 362          //gic_irqs = PM_IRQN_END;
 363          irqstart=PM_IRQN_START;//PM_IRQN_START;
 364
 365          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 366          dsb();
 367          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 368          dsb();
 369          for (j = irqstart; j < gic_irqs; j += 32)
 370          {
 371                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 372                  dsb();
 373          }
 374
 375          i = 0;
 376
 377          //trig
 378          for (j = irqstart; j < gic_irqs; j += 16)
 379          {
 380                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 381                  dsb();
 382          }
 383          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 384
 385          /*
 386          * Set all global interrupts to this CPU only.
 387          */
 388          for (j = 0; j < gic_irqs; j += 4)
 389          {
 390                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 391                  dsb();
 392          }
 393          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 394
 395          //pri
 396          for (j = 0; j < gic_irqs; j += 4)
 397          {
 398                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 399
 400                  dsb();
 401          }
 402          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 403
 404
 405          //secu
 406          for (j = 0; j < gic_irqs; j += 32)
 407          {
 408                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4 )/ 32);
 409                  dsb();
 410          }
 411          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 412
 413          //pending
 414          for (j = irqstart; j < gic_irqs; j += 32)
 415          {
 416                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 417                  i++;
 418                  dsb();
 419          }
 420          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 421
 422          //disable
 423 #if 0
 424          for (j = 0; j < gic_irqs; j += 32)
 425          {
 426                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 427                  dsb();
 428          }
 429          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 430
 431 #else
 432         for (j = irqstart; j < gic_irqs; j += 32)
 433             writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 434         writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 435         writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 436 #endif
 437
 438          //enable
 439          for (j = 0; j < gic_irqs; j += 32)
 440          {
 441                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 442
 443                  dsb();
 444          }
 445
 446          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 447
 448          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 449          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 450          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 451
 452          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 453          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 454
 455 }
 456
 457 /**************************************regs save and resume**************************/
 458
 459 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 460 {
 461      u32 i;
 462          u32 cnt=(end_offset-st_offset)/4+1;
 463      for(i=0;i<cnt;i++)
 464      {
 465          data[i]=readl_relaxed(base+st_offset+i*4);
 466      }
 467 }
 468
 469 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 470 {
 471      u32 i;
 472      u32 cnt=(end_offset-st_offset)/4+1;
 473      for(i=0;i<cnt;i++)
 474      {
 475          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 476      }
 477 }
 478
 479 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 480 {
 481         u32 i;
 482         u32 cnt=(end_offset-st_offset)/4+1;
 483          for(i=0;i<cnt;i++)
 484          {
 485                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 486          }
 487 }
 488
 489 /**************************************uarts save and resume**************************/
 490
 491 #define RK3288_UART_NUM (4)
 492
 493 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 494 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 495
 496 static u32 slp_uart_data[RK3288_UART_NUM][10];
 497 static u32 slp_uart_data_flag[RK3288_UART_NUM];
 498
 499
 500 #define UART_DLL        0       /* Out: Divisor Latch Low */
 501 #define UART_DLM        1       /* Out: Divisor Latch High */
 502
 503 #define UART_IER        1
 504 #define UART_FCR        2
 505
 506 #define UART_LCR        3       /* Out: Line Control Register */
 507 #define UART_MCR        4
 508
 509 #if 0
 510  void slp_uart_save(int ch)
 511  {
 512          int i=0;
 513         void __iomem *b_addr=slp_uart_base[ch];
 514          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 515          u32 gate_reg;
 516          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 517                 return;
 518
 519         if(ch==2)
 520         {
 521             idx=RK3288_CLKGATE_PCLK_UART2;
 522             b_addr=RK_DEBUG_UART_VIRT;
 523         }
 524
 525
 526         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 527         RK3288_CRU_UNGATING_OPS(idx);
 528          i=0;
 529          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 530          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 531
 532          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 533          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 534
 535          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 536          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 537          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 538          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 539
 540         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 541
 542  }
 543
 544  void slp_uart_resume(int ch)
 545  {
 546         int i=0;
 547
 548         u32 temp;
 549         void __iomem *b_addr=slp_uart_base[ch];
 550         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 551         u32 gate_reg;
 552
 553         //rkpm_ddr_printascii("\nch");
 554      //   rkpm_ddr_printhex(b_addr);
 555
 556         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 557             return;
 558
 559         if(ch==2)
 560             idx=RK3288_CLKGATE_PCLK_UART2;
 561
 562         //rkpm_ddr_printhex(ch);
 563
 564         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 565         RK3288_CRU_UNGATING_OPS(idx);
 566
 567          i=0;
 568          temp=slp_uart_data[ch][i++];
 569          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 570
 571          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 572          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 573
 574          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 575
 576          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 577          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 578          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 579
 580          writel_relaxed(temp,b_addr+UART_LCR*4);
 581
 582          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 583  }
 584 #endif
 585  void slp_uartdbg_resume(void)
 586 {
 587     int i=0;
 588     void __iomem *b_addr=RK_DEBUG_UART_VIRT;
 589     u32 pclk_id=RK3288_CLKGATE_PCLK_UART2,clk_id=(RK3288_CLKGATE_UART0_SRC+2*2);
 590     u32 gate_reg[2];
 591     u32 rfl_reg,lsr_reg;
 592
 593     gate_reg[0]=cru_readl(RK3288_CRU_GATEID_CONS(pclk_id));
 594     gate_reg[1]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id));
 595
 596     RK3288_CRU_UNGATING_OPS(pclk_id);
 597     // 24M is no gating setting
 598     ddr_pin_set_fun(0x7,0xc,0x6,0x0);
 599     ddr_pin_set_fun(0x7,0xc,0x7,0x0);
 600
 601     do{
 602             // out clk sel 24M
 603             cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 604
 605             //uart2 dbg reset
 606             cru_writel(0|CRU_W_MSK_SETBITS(1,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 607             dsb();
 608             dsb();
 609             rkpm_udelay(10);
 610             cru_writel(0|CRU_W_MSK_SETBITS(0,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 611
 612         #if 0
 613             //out clk (form pll)  is gating
 614             RK3288_CRU_GATING_OPS(clk_id);
 615             //out clk form pll gating to disable uart clk out
 616             // div 12
 617             cru_writel(CRU_W_MSK_SETBITS(11,0,0x7f), RK3288_CRU_CLKSELS_CON(15));
 618             dsb();
 619             dsb();
 620             dsb();
 621             dsb();
 622             cru_writel(CRU_W_MSK_SETBITS(0,8,0x3) , RK3288_CRU_CLKSELS_CON(15));
 623          #endif
 624
 625
 626             reg_writel(0x83,b_addr+UART_LCR*4);
 627
 628             reg_writel(0xd,b_addr+UART_DLL*4);
 629             reg_writel(0x0,b_addr+UART_DLM*4);
 630
 631             reg_writel(0x3,b_addr+UART_LCR*4);
 632
 633             reg_writel(0x5,b_addr+UART_IER*4);
 634             reg_writel(0xc1,b_addr+UART_FCR*4);
 635
 636             rfl_reg=readl_relaxed(b_addr+0x84);
 637             lsr_reg=readl_relaxed(b_addr+0x14);
 638
 639         }while((rfl_reg&0x1f)||(lsr_reg&0xf));
 640
 641         // out clk sel 24M
 642         cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 643
 644         ddr_pin_set_fun(0x7,0xc,0x6,0x1);
 645         ddr_pin_set_fun(0x7,0xc,0x7,0x1);
 646         cru_writel(gate_reg[0]|CRU_W_MSK(pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(pclk_id));
 647         cru_writel(gate_reg[1]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
 648 }
 649
 650 /**************************************i2c save and resume**************************/
 651
 652 //#define RK3288_I2C_REG_DUMP
 653 #define RK3288_I2C_NUM (6)
 654 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 655 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 656
 657 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 658
 659 void slp_i2c_save(int ch)
 660 {
 661
 662         void __iomem *b_addr=slp_i2c_base[ch];
 663         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 664         u32 gate_reg;
 665
 666         if(!b_addr)
 667                 return;
 668
 669         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 670         RK3288_CRU_UNGATING_OPS(idx);
 671
 672         #ifdef RK3288_I2C_REG_DUMP
 673         rkpm_ddr_printascii("i2c save");
 674         rkpm_ddr_printhex(ch);
 675         rkpm_ddr_printch('\n');
 676         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 677         #endif
 678
 679         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 680
 681
 682         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 683
 684 }
 685 void slp_i2c_resume(int ch)
 686 {
 687         void __iomem *b_addr=slp_i2c_base[ch];
 688         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 689         u32 gate_reg;
 690
 691         if(!b_addr)
 692                 return;
 693         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 694         RK3288_CRU_UNGATING_OPS(idx);
 695
 696         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 697
 698         #ifdef RK3288_I2C_REG_DUMP
 699         rkpm_ddr_printascii("i2c resume");
 700         rkpm_ddr_printhex(ch);
 701         rkpm_ddr_printch('\n');
 702         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 703         #endif
 704
 705         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 706 }
 707
 708 /**************************************gpios save and resume**************************/
 709 #define RK3288_GPIO_CH (9)
 710 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 711 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 712 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 713
 714 static void gpio_ddr_dump_reg(int ports)
 715 {
 716     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 717
 718     rkpm_ddr_printascii("gpio-");
 719     rkpm_ddr_printhex(ports);
 720     rkpm_ddr_printhex('\n');
 721
 722     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 723     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 724     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 725     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 726     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 727     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 728     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 729     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 730     rkpm_ddr_printhex('\n');
 731
 732     rkpm_ddr_printascii("iomux\n");
 733     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 734
 735     rkpm_ddr_printascii("iomux\n");
 736     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 737
 738 }
 739
 740  static void slp_pin_gpio_save(int ports)
 741  {
 742         int i;
 743         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 744         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 745         u32 gate_reg;
 746
 747         if(ports==0||ports>=RK3288_GPIO_CH)
 748                 return;
 749
 750          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 751          RK3288_CRU_UNGATING_OPS(idx);
 752
 753          //gpio_ddr_dump_reg(ports);
 754          i=0;
 755          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 756          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 757          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 758          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 759          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 760          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 761          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 762          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 763
 764         if(ports>0)
 765         {
 766             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 767             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 768          }
 769
 770
 771         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 772
 773  }
 774
 775  static void slp_pin_gpio_resume (int ports)
 776  {
 777          int i;
 778         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 779         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 780          u32 gate_reg;
 781
 782          if(ports==0||ports>=RK3288_GPIO_CH)
 783                 return;
 784           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 785          RK3288_CRU_UNGATING_OPS(idx);
 786
 787
 788         if(ports>0)
 789         {
 790             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 791             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 792         }
 793
 794         i=0;
 795         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 796         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 797         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 798         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 799         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 800         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 801         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 802         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 803
 804         //gpio_ddr_dump_reg(ports);
 805         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 806
 807  }
 808
 809  static inline u32 rkpm_l2_config(void)
 810  {
 811      u32 l2ctlr;
 812      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 813          return l2ctlr;
 814  }
 815 /**************************************sleep func**************************/
 816
 817 void ddr_reg_save(uint32_t *pArg);
 818 void fiq_glue_resume(void);
 819 void rk30_cpu_resume(void);
 820 void rk30_l2_cache_init_pm(void);
 821 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 822 void ddr_cfg_to_lp_mode(void);
 823 void l2x0_inv_all_pm(void);
 824 void rk30_cpu_while_tst(void);
 825
 826 #if 0
 827 static u32 slp_grf_soc_con_data[5];
 828 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 829
 830 static u32 slp_grf_cpu_con_data[5];
 831 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 832
 833 static u32 slp_grf_uoc0_con_data[4];
 834 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 835
 836 static u32 slp_grf_uoc1_con_data[2];
 837 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 838
 839 static u32 slp_grf_uoc2_con_data[2];
 840 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 841
 842 static u32 slp_grf_uoc3_con_data[2];
 843 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 844
 845 #endif
 846 static u32 slp_pmu_pwrmode_con_data[1];
 847
 848
 849 static u32 slp_nandc_data[8];
 850 static void __iomem *rk30_nandc_base=NULL;
 851
 852 #define MS_37K (37)
 853 #define US_24M (24)
 854
 855 void inline pm_io_base_map(void)
 856 {
 857         int i;
 858         for(i=0;i<RK3288_I2C_NUM;i++)
 859             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 860
 861         for(i=0;i<RK3288_UART_NUM;i++)
 862             {
 863                 if(i!=CONFIG_RK_DEBUG_UART)
 864                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 865                 else
 866                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 867             }
 868
 869 }
 870 enum rk3288_pwr_mode_con {
 871
 872         pmu_pwr_mode_en=0,
 873         pmu_clk_core_src_gate_en,
 874         pmu_global_int_disable,
 875         pmu_l2flush_en,
 876
 877         pmu_bus_pd_en,
 878         pmu_a12_0_pd_en,
 879         pmu_scu_en,
 880         pmu_pll_pd_en,
 881
 882         pmu_chip_pd_en, // power off pin enable
 883         pmu_pwroff_comb,
 884         pmu_alive_use_lf,
 885         pmu_pmu_use_lf,
 886
 887         pmu_osc_24m_dis,
 888         pmu_input_clamp_en,
 889         pmu_wakeup_reset_en,
 890         pmu_sref0_enter_en,
 891
 892         pmu_sref1_enter_en,
 893         pmu_ddr0io_ret_en,
 894         pmu_ddr1io_ret_en,
 895         pmu_ddr0_gating_en,
 896
 897         pmu_ddr1_gating_en,
 898         pmu_ddr0io_ret_de_req,
 899         pmu_ddr1io_ret_de_req
 900
 901 };
 902  enum rk3288_pwr_mode_con1 {
 903
 904         pmu_clr_bus=0,
 905         pmu_clr_core,
 906         pmu_clr_cpup,
 907         pmu_clr_alive,
 908
 909         pmu_clr_dma,
 910         pmu_clr_peri,
 911         pmu_clr_gpu,
 912         pmu_clr_video,
 913         pmu_clr_hevc,
 914         pmu_clr_vio
 915
 916 };
 917  static u32 rk3288_powermode=0;
 918 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 919
 920 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 921
 922 static u32  rkpm_slp_mode_set(u32 ctrbits)
 923 {
 924     u32 mode_set,mode_set1;
 925
 926     // setting gpio0_a0 arm off pin
 927
 928     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 929
 930     pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
 931     pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
 932
 933     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 934     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 935
 936     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 937
 938
 939
 940     //mode_set1=pmu_pwr_mode_con1;
 941     //mode_set=pmu_pwr_mode_con0;
 942
 943    //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 944    pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
 945
 946     // enable boot ram
 947     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 948     dsb();
 949
 950     reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 951     dsb();
 952
 953     mode_set=  BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
 954      mode_set1=0;
 955
 956     if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
 957     {
 958         rkpm_ddr_printascii("-autoidle-");
 959         mode_set|=BIT(pmu_clk_core_src_gate_en);
 960     }
 961     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
 962     {
 963         rkpm_ddr_printascii("-armdp-");
 964         mode_set|=BIT(pmu_a12_0_pd_en);
 965     }
 966     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
 967     {
 968         rkpm_ddr_printascii("-armoff-");
 969         mode_set|=BIT(pmu_scu_en)
 970                             //|BIT(pmu_a12_0_pd_en)
 971                             |BIT(pmu_clk_core_src_gate_en) // »½ÐÑºóÒì³£
 972                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 973                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 974                             //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 975                             |BIT(pmu_chip_pd_en);
 976         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 977                                 |BIT(pmu_clr_alive)
 978                                 |BIT(pmu_clr_peri)
 979                                 |BIT(pmu_clr_bus)
 980                                 |BIT(pmu_clr_dma)
 981                                 ;
 982     }
 983     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
 984     {
 985
 986         rkpm_ddr_printascii("-armoff-logdp1-");
 987
 988         mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
 989                             |BIT(pmu_chip_pd_en)
 990                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 991                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 992                             |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 993                             |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
 994                             ;
 995         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 996                            |BIT(pmu_clr_alive)
 997                            |BIT(pmu_clr_peri)
 998                            |BIT(pmu_clr_bus)
 999                            |BIT(pmu_clr_dma)
1000                           ;
1001
1002     }
1003     else
1004     {
1005         mode_set=0;
1006         mode_set1=0;
1007     }
1008
1009
1010     if(mode_set&BIT(pmu_osc_24m_dis))
1011     {
1012         rkpm_ddr_printascii("osc_off");
1013         pmu_writel(32*30,RK3288_PMU_OSC_CNT);
1014         pmu_writel(32*30,RK3288_PMU_STABL_CNT);
1015     }
1016     else
1017     {
1018         pmu_writel(24*1000*10,RK3288_PMU_STABL_CNT);
1019
1020        // pmu_writel(24*1000*20,RK3288_PMU_CORE_PWRDWN_CNT);
1021     }
1022
1023     if(mode_set&BIT(pmu_ddr0io_ret_en))
1024     {
1025         rkpm_ddr_printascii("ddrc_off");
1026         ddr_pin_set_fun(0x0,0xa,0x1,0x1);
1027         ddr_pin_set_fun(0x0,0xa,0x2,0x1);
1028         ddr_pin_set_fun(0x0,0xa,0x3,0x1);
1029     }
1030
1031     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
1032     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
1033
1034   //  rkpm_ddr_printhex(mode_set);
1035   //  rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1036
1037     return (pmu_readl(RK3288_PMU_PWRMODE_CON));
1038 }
1039
1040 static inline void  rkpm_slp_mode_set_resume(void)
1041 {
1042
1043     pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1044     pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1045
1046     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1047     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1048     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1049
1050 }
1051
1052 static void sram_code_data_save(u32 pwrmode)
1053 {
1054         char *code_src,*data_src;
1055         u32 code_size,data_size;
1056         u32 ddr_bits= RKPM_CTR_ARMLOGDP_LPMD|RKPM_CTR_ARMOFF_LOGDP_LPMD|RKPM_CTR_ARMLOGOFF_DLPMD;
1057
1058         //u32 *p;
1059         if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1060         {
1061             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1062             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1063             sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1064             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1065         }
1066         else
1067         {
1068             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1069             return ;
1070         }
1071
1072         if(pwrmode&BIT(pmu_bus_pd_en))
1073         {
1074                 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1075                 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1076                 code_src=(char *)ddr_get_resume_code_info(&code_size);
1077                 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1078                 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1079                 data_src=(char *)ddr_get_resume_data_info(&data_size);
1080                 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1081        }
1082         else
1083         {
1084             sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1085         }
1086
1087         sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1088
1089         flush_cache_all();
1090         outer_flush_all();
1091         local_flush_tlb_all();
1092
1093 }
1094
1095 static inline void sram_code_data_resume(u32 pwrmode)
1096 {
1097          if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1098         {
1099              sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1100         }
1101
1102 }
1103
1104 static void  rkpm_peri_save(u32 power_mode)
1105 {
1106     u32 gpio_gate[2];
1107
1108     if(power_mode&BIT(pmu_scu_en))
1109     {
1110         rkpm_gic_dist_save(&slp_gic_save[0]);
1111     }
1112 #if 0
1113     gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1114     gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1115     RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1116     cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1117                          RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1118 #endif
1119
1120     if(power_mode&BIT(pmu_bus_pd_en))
1121    {
1122        #if 0
1123         //gpio7_c6
1124         //gpio7_c7
1125         ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1126         ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1127         ddr_pin_set_fun(7,0xc,0x6,0);
1128
1129         ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1130         ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1131         ddr_pin_set_fun(7,0xc,0x7,0);
1132         #endif
1133         //slp_uart_save(2);
1134     #if 0
1135         ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1136         ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1137         ddr_pin_set_fun(0,0xb,0x7,0);
1138
1139         ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1140         ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1141         ddr_pin_set_fun(0,0xc,0x0,0);
1142         #endif
1143         slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1144         slp_i2c_save(1);//i2c audio
1145     }
1146
1147 #if 0
1148         cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1149                                       RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1150         cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1151 #endif
1152
1153 }
1154
1155 static inline void  rkpm_peri_resume(u32 power_mode)
1156 {
1157     if(power_mode&BIT(pmu_scu_en))
1158     {
1159         //fiq_glue_resume();
1160         rkpm_gic_dist_resume(&slp_gic_save[0]);
1161         fiq_glue_resume();
1162         //rkpm_ddr_printascii("gic res");
1163     }
1164     if(power_mode&BIT(pmu_bus_pd_en))
1165    {
1166         slp_i2c_resume(0);// i2c pmu
1167         slp_i2c_resume(1);//i2c audio
1168     }
1169
1170 }
1171
1172 static u32 pdbus_gate_reg[5];
1173 static inline void  rkpm_peri_resume_first(u32 power_mode)
1174 {
1175
1176     if(power_mode&BIT(pmu_bus_pd_en))
1177     {
1178         cru_writel(0xffff0000|pdbus_gate_reg[0],RK3288_CRU_CLKGATES_CON(0));
1179         cru_writel(0xffff0000|pdbus_gate_reg[1],RK3288_CRU_CLKGATES_CON(4));
1180         cru_writel(0xffff0000|pdbus_gate_reg[2],RK3288_CRU_CLKGATES_CON(5));
1181         cru_writel(0xffff0000|pdbus_gate_reg[3],RK3288_CRU_CLKGATES_CON(10));
1182         cru_writel(0xffff0000|pdbus_gate_reg[4],RK3288_CRU_CLKGATES_CON(11));
1183     }
1184
1185
1186       if(power_mode&BIT(pmu_bus_pd_en))
1187         slp_uartdbg_resume();
1188 }
1189
1190 static void rkpm_slp_setting(void)
1191 {
1192     rk_usb_power_down();
1193
1194     if(rk3288_powermode&BIT(pmu_bus_pd_en))
1195     {
1196         // pd bus will be power down ,but if it reup,ungating clk for its reset
1197         // ungating pdbus clk
1198         pdbus_gate_reg[0]=cru_readl(RK3288_CRU_CLKGATES_CON(0));
1199         pdbus_gate_reg[1]=cru_readl(RK3288_CRU_CLKGATES_CON(4));
1200         pdbus_gate_reg[2]=cru_readl(RK3288_CRU_CLKGATES_CON(5));
1201         pdbus_gate_reg[3]=cru_readl(RK3288_CRU_CLKGATES_CON(10));
1202         pdbus_gate_reg[4]=cru_readl(RK3288_CRU_CLKGATES_CON(11));
1203
1204         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(0));
1205         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(4));
1206         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(5));
1207         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(10));
1208         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(11));
1209
1210         RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_UART2);
1211        // RK3288_CRU_UNGATING_OPS((RK3288_CLKGATE_UART0_SRC+2*2));
1212        //c2c host
1213        RK3288_CRU_UNGATING_OPS(RK3288_CRU_CONS_GATEID(13)+8);
1214
1215     }
1216
1217 }
1218
1219
1220 static void rkpm_save_setting_resume_first(void)
1221 {
1222         rk_usb_power_up();
1223         rkpm_peri_resume_first(rk3288_powermode);
1224
1225         // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1226         #if 0
1227         //rk319x_pm_set_power_domain(PD_PERI,true);
1228         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1229         slp_pin_gpio_resume(1);
1230         slp_pin_gpio_resume(2);
1231         slp_pin_gpio_resume(3);
1232         slp_pin_gpio_resume(4);
1233
1234         #if 0
1235         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1236         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1237
1238         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1239         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1240         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1241         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1242         #endif
1243         //sram_printch_uart_enable();
1244         slp_uart_resume(2);
1245        #endif
1246 }
1247
1248
1249
1250 static u32 rk3288_ctrbits=0;
1251
1252 static void rkpm_save_setting(u32 ctrbits)
1253 {
1254         //rk3288_ctrbits=ctrbits;
1255         rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1256         if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1257        {
1258                 sram_code_data_save(rk3288_powermode);
1259                 rkpm_peri_save(rk3288_powermode);
1260         }
1261         else
1262              return ;
1263
1264 }
1265 static void rkpm_save_setting_resume(void)
1266 {
1267
1268          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1269         {
1270             sram_code_data_resume(rk3288_powermode);
1271             rkpm_peri_resume(rk3288_powermode);
1272         }
1273
1274          rkpm_slp_mode_set_resume();
1275
1276 }
1277
1278 /*******************************common code  for rkxxx*********************************/
1279 static void  inline uart_printch(char byte)
1280 {
1281         u32 reg_save[2];
1282         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART*2);
1283         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1284
1285         if(CONFIG_RK_DEBUG_UART==4)
1286             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1287         if(CONFIG_RK_DEBUG_UART==2)
1288             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1289
1290         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1291         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1292         RK3288_CRU_UNGATING_OPS(u_clk_id);
1293         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1294
1295         rkpm_udelay(1);
1296
1297 write_uart:
1298         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1299         dsb();
1300
1301         /* loop check LSR[6], Transmitter Empty bit */
1302         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1303                 barrier();
1304
1305         if (byte == '\n') {
1306                 byte = '\r';
1307                 goto write_uart;
1308         }
1309
1310          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1311          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1312 }
1313
1314 void PIE_FUNC(sram_printch)(char byte)
1315 {
1316         uart_printch(byte);
1317 }
1318
1319 static void pll_udelay(u32 udelay);
1320
1321 #ifdef CONFIG_RK_LAST_LOG
1322 extern void rk_last_log_text(char *text, size_t size);
1323 #endif
1324
1325 static void  ddr_printch(char byte)
1326 {
1327         char last_char;
1328
1329         uart_printch(byte);
1330
1331 #ifdef CONFIG_RK_LAST_LOG
1332         last_char=byte;
1333         rk_last_log_text(&last_char,1);
1334
1335         if (byte == '\n') {
1336             last_char='\r';
1337             rk_last_log_text(&last_char,1);
1338          }
1339
1340 #endif
1341         pll_udelay(2);
1342 }
1343 /*******************************gpio func*******************************************/
1344 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1345 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1346 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1347 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1348 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1349 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1350 {
1351         u8 off_set;
1352         bank-=0xa;
1353
1354         if(port==0)
1355         {
1356             if(bank>2)
1357                 return;
1358             off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1359             pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1360         }
1361         else if(port==1||port==2)
1362         {
1363             off_set=port*(4*4)+bank*4;
1364             reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1365         }
1366         else if(port==3)
1367         {
1368             if(bank<=2)
1369             {
1370                 off_set=0x20+bank*4;
1371                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1372
1373             }
1374             else
1375             {
1376                 off_set=0x2c+(b_gpio/4)*4;
1377                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1378             }
1379
1380         }
1381         else if(port==4)
1382         {
1383             if(bank<=1)
1384             {
1385                 off_set=0x34+bank*8+(b_gpio/4)*4;
1386                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1387             }
1388             else
1389             {
1390                 off_set=0x44+(bank-2)*4;
1391                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1392             }
1393
1394         }
1395         else if(port==5||port==6)
1396         {
1397                 off_set=0x4c+(port-5)*4*4+bank*4;
1398                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1399         }
1400         else if(port==7)
1401         {
1402             if(bank<=1)
1403             {
1404                 off_set=0x6c+bank*4;
1405                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1406             }
1407             else
1408             {
1409                 off_set=0x74+(bank-2)*8+(b_gpio/4)*4;
1410                 //rkpm_ddr_printascii("gpio");
1411                 //rkpm_ddr_printhex(off_set);
1412                 //rkpm_ddr_printascii("-");
1413                 //rkpm_ddr_printhex((b_gpio%4)*4);
1414
1415                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1416
1417                 //rkpm_ddr_printhex(reg_readl(RK_GRF_VIRT+0+off_set));
1418                 //rkpm_ddr_printascii("\n");
1419             }
1420
1421         }
1422         else if(port==8)
1423         {
1424             if(bank<=1)
1425             {
1426                 off_set=0x80+bank*4;
1427                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1428             }
1429         }
1430
1431 }
1432
1433
1434 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1435 {
1436     u8 off_set;
1437     bank-=0xa;
1438
1439     if(port==0)
1440     {
1441       if(bank>2)
1442             return 0;
1443         off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1444         return (pmu_readl(off_set)>>(b_gpio*2))&0x3;
1445     }
1446     else
1447     {
1448
1449         off_set=port*(4*4)+bank*4;
1450         //form RK3288_GRF_GPIO1D_IOMUX
1451          return (reg_readl(RK_GRF_VIRT+0+off_set)>>(b_gpio*2))&0x3;
1452     }
1453 }
1454
1455 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1456 {
1457     u8 off_set;
1458
1459     bank-=0xa;
1460
1461     if(port > 0)
1462     {
1463         //gpio1_d st
1464         if(port==1&&bank<3)
1465          return;
1466         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1467         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1468         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1469
1470     }
1471     else
1472     {
1473         if(bank>2)// gpio0_d is not support
1474             return;
1475         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1476     }
1477
1478 }
1479
1480 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1481 {
1482     u8 off_set;
1483
1484     bank-=0xa;
1485
1486     if(port > 0)
1487     {
1488         //gpio1_d st
1489         if(port==1&&bank<3)
1490             return 0;
1491         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1492         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1493         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1494
1495     }
1496     else
1497     {
1498         if(bank>2)// gpio0_d is not support
1499             return 0;
1500         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1501     }
1502
1503 }
1504
1505
1506 //RKPM_GPIOS_INPUT
1507 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1508 {
1509     u32 val;
1510
1511     bank-=0xa;
1512     b_gpio=bank*8+b_gpio;//
1513
1514     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1515
1516     if(type==RKPM_GPIO_OUTPUT)
1517         val|=(0x1<<b_gpio);
1518     else
1519         val&=~(0x1<<b_gpio);
1520
1521     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1522 }
1523
1524 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1525 {
1526     bank-=0xa;
1527     b_gpio=bank*8+b_gpio;
1528     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1529 }
1530
1531 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1532 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1533 {
1534     u32 val;
1535
1536     bank-=0xa;
1537     b_gpio=bank*8+b_gpio;
1538
1539     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1540
1541     if(level==RKPM_GPIO_OUT_H)
1542         val|=(0x1<<b_gpio);
1543     else //
1544         val&=~(0x1<<b_gpio);
1545
1546      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1547 }
1548
1549 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1550 {
1551     bank-=0xa;
1552     b_gpio=bank*8+b_gpio;
1553     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1554 }
1555
1556 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1557 {
1558
1559     bank-=0xa;
1560     b_gpio=bank*8+b_gpio;
1561
1562     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1563 }
1564 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1565 {
1566     u32 val;
1567
1568     bank-=0xa;
1569     b_gpio=bank*8+b_gpio;
1570
1571     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1572     rkpm_ddr_printascii("\n inten:");
1573     rkpm_ddr_printhex(val);
1574
1575     rkpm_ddr_printascii("-");
1576     if(en==1)
1577         val|=(0x1<<b_gpio);
1578     else //
1579         val&=~(0x1<<b_gpio);
1580
1581     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1582     dsb();
1583
1584      rkpm_ddr_printhex(val);
1585      rkpm_ddr_printascii("-");
1586
1587      rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1588
1589     rkpm_ddr_printascii("\n");
1590
1591
1592 }
1593
1594 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1595 {
1596         pin_set_fun(port,bank,b_gpio,fun);
1597 }
1598 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1599 {
1600     return pin_get_funset(port,bank,b_gpio);
1601 }
1602
1603 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1604 {
1605         pin_set_pull(port,bank,b_gpio,fun);
1606 }
1607 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1608 {
1609     return pin_get_pullset(port,bank,b_gpio);
1610 }
1611
1612 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1613 {
1614     gpio_set_in_output(port,bank,b_gpio,type);
1615 }
1616
1617 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1618 {
1619     return gpio_get_in_outputset(port,bank,b_gpio);
1620 }
1621
1622 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1623 {
1624
1625     gpio_set_output_level(port,bank,b_gpio,level);
1626
1627 }
1628
1629 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1630 {
1631     return gpio_get_output_levelset(port,bank,b_gpio);
1632 }
1633
1634 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1635 {
1636     return gpio_get_input_level(port,bank,b_gpio);
1637 }
1638 //ddr
1639 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1640 {
1641         pin_set_fun(port,bank,b_gpio,fun);
1642 }
1643 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1644 {
1645     return pin_get_funset(port,bank,b_gpio);
1646 }
1647
1648 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1649 {
1650         pin_set_pull(port,bank,b_gpio,fun);
1651 }
1652 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1653 {
1654     return pin_get_pullset(port,bank,b_gpio);
1655 }
1656
1657 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1658 {
1659     gpio_set_in_output(port,bank,b_gpio,type);
1660 }
1661
1662 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1663 {
1664     return gpio_get_in_outputset(port,bank,b_gpio);
1665 }
1666
1667 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1668 {
1669     gpio_set_output_level(port,bank,b_gpio,level);
1670 }
1671
1672 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1673 {
1674     return gpio_get_output_levelset(port,bank,b_gpio);
1675 }
1676
1677 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1678 {
1679     return gpio_get_input_level(port,bank,b_gpio);
1680 }
1681
1682
1683
1684 static  void __sramfunc rkpm_pin_gpio_config_sram(u32 pin_gpio_bits,u32 *save_bits)
1685 {
1686
1687     u32 pins;
1688     u8 port,bank,b_gpio,fun,in_out, level, pull;
1689
1690     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1691     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1692     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1693     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1694
1695     port=RKPM_PINBITS_PORT(pins);
1696     bank=RKPM_PINBITS_BANK(pins);
1697     b_gpio=RKPM_PINBITS_BGPIO(pins);
1698     fun=RKPM_PINBITS_FUN(pins);
1699
1700     //save pins info
1701     if(save_bits)
1702     {
1703         pins=RKPM_PINBITS_SET_FUN(pins,sram_pin_get_funset(port,bank,b_gpio));
1704        *save_bits=RKPM_PINGPIO_BITS(pins,sram_pin_get_pullset(port,bank,b_gpio),sram_gpio_get_in_outputset(port,bank,b_gpio),
1705                                                                                         sram_gpio_get_output_levelset(port,bank,b_gpio));
1706     }
1707     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1708    {
1709         if(level==RKPM_GPIO_OUT_L)
1710             pull=RKPM_GPIO_PULL_DN;
1711         else
1712             pull=RKPM_GPIO_PULL_UP;
1713
1714         sram_gpio_set_output_level(port,bank,b_gpio,level);
1715     }
1716
1717     sram_pin_set_pull(port,bank,b_gpio,pull);
1718     sram_pin_set_fun(port,bank,b_gpio,fun);
1719
1720     if(!fun)
1721     {
1722         sram_gpio_set_in_output(port,bank,b_gpio,in_out);
1723     }
1724
1725 }
1726
1727 static inline void rkpm_pin_gpio_config_ddr(u32 pin_gpio_bits,u32 *save_bits)
1728 {
1729
1730     u32 pins;
1731     u8 port,bank,b_gpio,fun,in_out, level, pull;
1732
1733     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1734     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1735     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1736     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1737
1738     port=RKPM_PINBITS_PORT(pins);
1739     bank=RKPM_PINBITS_BANK(pins);
1740     b_gpio=RKPM_PINBITS_BGPIO(pins);
1741     fun=RKPM_PINBITS_FUN(pins);
1742
1743     //save pins info
1744     if(save_bits)
1745     {
1746         pins=RKPM_PINBITS_SET_FUN(pins,ddr_pin_get_funset(port,bank,b_gpio));
1747        *save_bits=RKPM_PINGPIO_BITS(pins,ddr_pin_get_pullset(port,bank,b_gpio),ddr_gpio_get_in_outputset(port,bank,b_gpio),
1748                                                                                         ddr_gpio_get_output_levelset(port,bank,b_gpio));
1749     }
1750     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1751    {
1752         if(level==RKPM_GPIO_OUT_L)
1753             pull=RKPM_GPIO_PULL_DN;
1754         else
1755             pull=RKPM_GPIO_PULL_UP;
1756
1757         ddr_gpio_set_output_level(port,bank,b_gpio,level);
1758     }
1759
1760     ddr_pin_set_pull(port,bank,b_gpio,pull);
1761     ddr_pin_set_fun(port,bank,b_gpio,fun);
1762
1763     if(!fun)
1764     {
1765         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1766     }
1767
1768 }
1769
1770
1771 #define GPIO_DTS_NUM 10
1772
1773 static  u32 gpio_dts_save[GPIO_DTS_NUM];
1774 static  u32 gpio_dts[GPIO_DTS_NUM];
1775
1776 #define PMICGPIO_DTS_NUM 3
1777
1778
1779 u32 DEFINE_PIE_DATA(pmicgpio_dts[PMICGPIO_DTS_NUM]);
1780 static u32 *p_pmicgpio_dts;
1781 static __sramdata u32 pmicgpio_dts_save[PMICGPIO_DTS_NUM];
1782
1783 static void __sramfunc pmic_gpio_suspend(void)
1784 {
1785        int i;
1786        for(i=0;;i++)
1787        {
1788             if(DATA(pmicgpio_dts[i]))
1789                 rkpm_pin_gpio_config_sram(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1790             else
1791             {
1792                     pmicgpio_dts_save[i]=0;
1793                     break;
1794              }
1795        }
1796     #if 0
1797          for(i=0;i<6;i++)
1798         {
1799             rkpm_sram_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1800         }
1801         //
1802         rkpm_sram_reg_dump(RK_GRF_VIRT,0xc,0x84);
1803         rkpm_sram_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1804         rkpm_sram_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1805         rkpm_sram_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1806     #endif
1807
1808 }
1809
1810 static void  __sramfunc pmic_gpio_resume(void)
1811 {
1812        int i;
1813        for(i=0;;i++)
1814        {
1815             if(pmicgpio_dts_save[i])
1816                 rkpm_pin_gpio_config_sram(pmicgpio_dts_save[i],NULL);
1817        }
1818
1819 }
1820
1821 void PIE_FUNC(pmic_suspend)(void)
1822 {
1823     pmic_gpio_suspend();
1824
1825 }
1826
1827 void PIE_FUNC(pmic_resume)(void)
1828 {
1829     pmic_gpio_resume();
1830 }
1831
1832
1833 static void  rkpm_gpio_suspend(void)
1834 {
1835        int i;
1836        for(i=0;;i++)
1837        {
1838             if(DATA(pmicgpio_dts[i]))
1839                 rkpm_pin_gpio_config_ddr(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1840             else
1841             {
1842                     pmicgpio_dts_save[i]=0;
1843                     break;
1844              }
1845        }
1846     #if 0
1847          for(i=0;i<6;i++)
1848         {
1849             rkpm_ddr_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1850         }
1851         //
1852         rkpm_ddr_reg_dump(RK_GRF_VIRT,0xc,0x84);
1853         rkpm_ddr_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1854         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1855         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1856     #endif
1857
1858 }
1859
1860 static void  rkpm_gpio_resume(void)
1861 {
1862        int i;
1863        for(i=0;;i++)
1864        {
1865             if(pmicgpio_dts_save[i])
1866                 rkpm_pin_gpio_config_ddr(pmicgpio_dts_save[i],NULL);
1867        }
1868
1869 }
1870 static void gpio_get_dts_info(struct device_node *parent)
1871 {
1872         int i;
1873
1874         for(i=0;i<PMICGPIO_DTS_NUM;i++)
1875             p_pmicgpio_dts[i]=0;
1876
1877         for(i=0;i<GPIO_DTS_NUM;i++)
1878             gpio_dts[i]=0;
1879
1880
1881         p_pmicgpio_dts= kern_to_pie(rockchip_pie_chunk, &DATA(pmicgpio_dts[0]));
1882
1883        if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",p_pmicgpio_dts,PMICGPIO_DTS_NUM))
1884        {
1885                 p_pmicgpio_dts[0]=0;
1886                PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1887        }
1888
1889        for(i=0;i<PMICGPIO_DTS_NUM;i++)
1890             printk("%s:pmic gpio(%x)\n",__FUNCTION__,p_pmicgpio_dts[i]);
1891
1892         if(of_property_read_u32_array(parent,"rockchip,pm-gpios",gpio_dts,GPIO_DTS_NUM))
1893         {
1894                  gpio_dts[0]=0;
1895                 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1896         }
1897         for(i=0;i<GPIO_DTS_NUM;i++)
1898          printk("%s:pmic gpio(%x)\n",__FUNCTION__,gpio_dts[i]);
1899
1900     rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1901     rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_suspend)),
1902                   fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_resume)));
1903
1904 }
1905
1906
1907 /*******************************clk gating config*******************************************/
1908 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1909 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1910
1911
1912 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1913 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1914 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1915
1916
1917 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1918 static u32 *p_rkpm_clkgt_last_set;
1919
1920 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1921
1922 void PIE_FUNC(gtclks_sram_suspend)(void)
1923 {
1924     int i;
1925    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1926    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1927
1928     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1929     {
1930         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1931         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1932         #if 0
1933         rkpm_sram_printch('\n');
1934         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1935         rkpm_sram_printch('-');
1936         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1937         rkpm_sram_printch('-');
1938         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1939         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1940         rkpm_sram_printch('\n');
1941         #endif
1942     }
1943
1944         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1945         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1946
1947 }
1948
1949 void PIE_FUNC(gtclks_sram_resume)(void)
1950 {
1951     int i;
1952     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1953     {
1954         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1955     }
1956 }
1957 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
1958 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1959
1960 #define gpio7_readl(offset)     readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1961 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1962
1963 int gpio7_pin_data1, gpio7_pin_dir1;
1964 int gpio7_pin_iomux1;
1965
1966 static void gtclks_suspend(void)
1967 {
1968     int i;
1969         gpio7_pin_data1= gpio7_readl(0);
1970         gpio7_pin_dir1 = gpio7_readl(0x04);
1971         gpio7_pin_iomux1 =  gpio7_readl(0x6c);
1972         grf_writel(0x00040000, 0x6c);
1973         gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1974         gpio7_writel((gpio7_pin_data1|2), 0x00);
1975
1976   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1977                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1978     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1979     {
1980             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1981            // 160 1a8
1982            #if 0
1983            if(
1984                // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1985                 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1986                 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1987               //  RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1988                 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1989                // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1990                // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1991
1992
1993                 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1994                // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1995                // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1996                // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1997                 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1998                 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
1999                 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
2000                 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
2001                 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
2002                 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
2003                 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
2004                // RK3288_CRU_CLKGATES_CON(i)==0x1a8
2005                RK3288_CRU_CLKGATES_CON(i)==0xfff
2006             )
2007             {
2008
2009                  cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
2010                // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2011
2012             }
2013            else
2014             #endif
2015             {
2016                // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
2017                CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2018            }
2019            #if 0
2020             rkpm_ddr_printch('\n');
2021             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
2022             rkpm_ddr_printch('-');
2023             rkpm_ddr_printhex(clk_ungt_msk[i]);
2024             rkpm_ddr_printch('-');
2025             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
2026             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
2027             rkpm_ddr_printch('\n');
2028             #endif
2029     }
2030
2031 }
2032
2033 static void gtclks_resume(void)
2034 {
2035     int i;
2036      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2037     {
2038        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2039      }
2040      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
2041                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
2042         grf_writel(0x00040004, 0x6c);
2043
2044 }
2045 /********************************pll power down***************************************/
2046
2047 static void pm_pll_wait_lock(u32 pll_idx)
2048 {
2049         u32 delay = 600000U;
2050        // u32 mode;
2051      //  mode=cru_readl(RK3288_CRU_MODE_CON);
2052         dsb();
2053         dsb();
2054         dsb();
2055         dsb();
2056         dsb();
2057         dsb();
2058         while (delay > 0) {
2059                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
2060                         break;
2061                 delay--;
2062         }
2063         if (delay == 0) {
2064                 rkpm_ddr_printascii("unlock-pll:");
2065                 rkpm_ddr_printhex(pll_idx);
2066                 rkpm_ddr_printch('\n');
2067         }
2068     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
2069 }
2070
2071 static void pll_udelay(u32 udelay)
2072 {
2073     u32 mode;
2074     mode=cru_readl(RK3288_CRU_MODE_CON);
2075     // delay in 24m
2076     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2077
2078     rkpm_udelay(udelay*5);
2079
2080     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2081 }
2082
2083 static u32 plls_con0_save[END_PLL_ID];
2084 static u32 plls_con1_save[END_PLL_ID];
2085 static u32 plls_con2_save[END_PLL_ID];
2086 static u32 plls_con3_save[END_PLL_ID];
2087
2088 static u32 cru_mode_con;
2089
2090 static inline void plls_suspend(u32 pll_id)
2091 {
2092     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
2093     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
2094     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
2095     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
2096
2097     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
2098
2099 }
2100 static inline void plls_resume(u32 pll_id)
2101 {
2102         u32 pllcon0, pllcon1, pllcon2;
2103
2104         if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
2105             return ;
2106
2107         //enter slowmode
2108         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
2109
2110         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
2111         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
2112
2113         pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
2114         pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
2115         pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
2116
2117         //enter rest
2118         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
2119         cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
2120         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
2121         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
2122
2123         pll_udelay(5);
2124         //udelay(5); //timer7 delay
2125
2126         //return form rest
2127         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
2128
2129         //wating lock state
2130         pll_udelay(168);
2131         pm_pll_wait_lock(pll_id);
2132
2133         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
2134
2135 }
2136
2137 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
2138
2139 static void pm_plls_suspend(void)
2140 {
2141
2142    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2143    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2144    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2145
2146     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
2147     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
2148     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
2149     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
2150     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
2151     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
2152     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2153
2154     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2155
2156
2157     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2158     plls_suspend(NPLL_ID);
2159
2160 // cpll
2161     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2162
2163 // gpll
2164     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2165
2166     // set 1,pdbus pll is gpll
2167     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2168
2169     // pd_bus clk
2170     cru_writel(0
2171                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
2172                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
2173                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
2174                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
2175                      , RK3288_CRU_CLKSELS_CON(1));
2176
2177     //crypto for pd_bus
2178     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2179
2180     // peri aclk hclk pclk
2181     cru_writel(0
2182                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2183                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
2184                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
2185                         , RK3288_CRU_CLKSELS_CON(10));
2186     // pmu alive
2187     cru_writel(CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2188
2189     plls_suspend(CPLL_ID);
2190     plls_suspend(GPLL_ID);
2191
2192 //apll
2193    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2194      // core_m0 core_mp a12_core
2195     cru_writel(0
2196                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
2197                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
2198                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2199                       , RK3288_CRU_CLKSELS_CON(0));
2200     // core0 core1 core2 core3
2201     cru_writel(0
2202                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2203                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2204                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2205                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2206                       , RK3288_CRU_CLKSELS_CON(36));
2207     // l2ram atclk pclk
2208     #if 1
2209     cru_writel(0
2210                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2211                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2212                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2213                      , RK3288_CRU_CLKSELS_CON(37));
2214     #else
2215     cru_writel(0
2216                       |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2217                       |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2218                        |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2219                        , RK3288_CRU_CLKSELS_CON(37));
2220     #endif
2221
2222
2223     plls_suspend(APLL_ID);
2224
2225 }
2226
2227 static void pm_plls_resume(void)
2228 {
2229
2230
2231         // core_m0 core_mp a12_core
2232         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
2233         // core0 core1 core2 core3
2234         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
2235                         , RK3288_CRU_CLKSELS_CON(36));
2236         // l2ram atclk pclk
2237         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
2238
2239         plls_resume(APLL_ID);
2240         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2241
2242         // peri aclk hclk pclk
2243         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
2244                                                                             , RK3288_CRU_CLKSELS_CON(10));
2245         //pd bus gpll sel
2246         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
2247         // pd_bus clk
2248         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
2249                     , RK3288_CRU_CLKSELS_CON(1));
2250
2251         // crypto
2252         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
2253
2254
2255           // pmu alive
2256         cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2257
2258         plls_resume(GPLL_ID);
2259         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
2260
2261         plls_resume(CPLL_ID);
2262         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
2263
2264         plls_resume(NPLL_ID);
2265         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2266
2267        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2268        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2269        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2270
2271 }
2272
2273 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2274
2275 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2276 {
2277
2278     int div;
2279     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2280     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2281     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2282
2283
2284     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2285     {
2286         div=3;
2287         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2288         cru_writel(0
2289                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2290                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2291                             , RK3288_CRU_MODE_CON);
2292     }
2293     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2294     {
2295         div=31;
2296     }
2297
2298     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2299     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2300     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2301
2302 }
2303
2304 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2305 {
2306
2307     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2308     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2309     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2310     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2311                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2312                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2313                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2314
2315 }
2316
2317
2318 static void clks_gating_suspend_init(void)
2319 {
2320     // get clk gating info
2321     if(rockchip_pie_chunk)
2322         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2323     else
2324         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2325     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2326         ==RK3288_CRU_CLKGATES_CON(0))
2327     {
2328         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2329         if(rockchip_pie_chunk)
2330             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2331                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2332
2333         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2334
2335     }
2336     if(rockchip_pie_chunk)
2337         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2338                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2339 }
2340
2341 /***************************prepare and finish reg_pread***********************************/
2342
2343
2344
2345 #define GIC_DIST_PENDING_SET            0x200
2346 static noinline void rk3288_pm_dump_irq(void)
2347 {
2348         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2349         u32 irq[4];
2350         int i;
2351
2352         for (i = 0; i < ARRAY_SIZE(irq); i++)
2353                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2354         for (i = 0; i < ARRAY_SIZE(irq); i++) {
2355                 if (irq[i])
2356                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2357         }
2358         printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2359         for (i = 0; i <= 8; i++) {
2360                 if (irq_gpio & (1 << i))
2361                         printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2362         }
2363 }
2364
2365 #if 0
2366 #define DUMP_GPIO_INTEN(ID) \
2367 do { \
2368         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2369         if (en) { \
2370                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2371                 rkpm_ddr_printhex(en); \
2372                 rkpm_ddr_printch('\n'); \
2373                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2374         } \
2375 } while (0)
2376 #else
2377
2378 #define DUMP_GPIO_INTEN(ID) \
2379     do { \
2380         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2381         if (en) { \
2382                 printk("GPIO%d_INTEN: %08x\n", ID, en); \
2383         } \
2384     } while (0)
2385
2386 #endif
2387
2388
2389 //dump while irq is enable
2390 static noinline void rk3288_pm_dump_inten(void)
2391 {
2392         DUMP_GPIO_INTEN(0);
2393         DUMP_GPIO_INTEN(1);
2394         DUMP_GPIO_INTEN(2);
2395         DUMP_GPIO_INTEN(3);
2396         DUMP_GPIO_INTEN(4);
2397         DUMP_GPIO_INTEN(5);
2398         DUMP_GPIO_INTEN(6);
2399         DUMP_GPIO_INTEN(7);
2400         DUMP_GPIO_INTEN(8);
2401 }
2402
2403 static  void rkpm_prepare(void)
2404 {
2405
2406         int i;
2407          for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2408         {
2409            //cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2410          }
2411
2412         #if 0
2413         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2414
2415        // rkpm_ddr_printhex(temp);
2416         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2417         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2418        // rkpm_ddr_printhex(temp);
2419         #endif
2420         // dump GPIO INTEN for debug
2421         rk3288_pm_dump_inten();
2422 }
2423
2424 static void rkpm_finish(void)
2425 {
2426         rk3288_pm_dump_irq();
2427 }
2428
2429
2430 static  void interface_ctr_reg_pread(void)
2431 {
2432         //u32 addr;
2433         flush_cache_all();
2434         outer_flush_all();
2435         local_flush_tlb_all();
2436         #if 0  // do it in ddr suspend
2437         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2438                 readl_relaxed(addr);
2439         #endif
2440         readl_relaxed(RK_PMU_VIRT);
2441         readl_relaxed(RK_GRF_VIRT);
2442         readl_relaxed(RK_DDR_VIRT);
2443         readl_relaxed(RK_GPIO_VIRT(0));
2444         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2445         //readl_relaxed(RK_GPIO_VIRT(3));
2446 }
2447 void PIE_FUNC(ddr_leakage_tst)(void)
2448 {
2449     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2450     rkpm_sram_printch('\n');
2451     rkpm_sram_printch('t');
2452     rkpm_sram_printch('e');
2453     rkpm_sram_printch('s');
2454     rkpm_sram_printch('t');
2455     while(1);
2456 }
2457
2458 static void __init  rk3288_suspend_init(void)
2459 {
2460     struct device_node *parent;
2461     u32 pm_ctrbits;
2462
2463     PM_LOG("%s enter\n",__FUNCTION__);
2464
2465     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2466
2467     if (IS_ERR_OR_NULL(parent)) {
2468                 PM_ERR("%s dev node err\n", __func__);
2469                 return;
2470         }
2471
2472
2473     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2474     {
2475             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2476             return ;
2477     }
2478     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2479     pm_io_base_map();
2480     memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2481     rkpm_set_ctrbits(pm_ctrbits);
2482
2483     clks_gating_suspend_init();
2484
2485     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2486
2487     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2488
2489     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2490
2491     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2492
2493      rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2494      rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2495
2496     if(rockchip_pie_chunk)
2497         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2498
2499     rkpm_set_ops_printch(ddr_printch);
2500 }