2 #include <linux/kernel.h>
3 #include <linux/init.h>
4 #include <asm/cacheflush.h>
5 #include <asm/tlbflush.h>
6 #include <asm/hardware/cache-l2x0.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/wakeup_reason.h>
11 #include <linux/suspend.h>
15 #include <linux/of_address.h>
17 #include <linux/rockchip/cpu.h>
18 //#include <linux/rockchip/cru.h>
19 #include <linux/rockchip/grf.h>
20 #include <linux/rockchip/iomap.h>
22 #include <linux/irqchip/arm-gic.h>
28 __weak void rk_usb_power_down(void);
29 __weak void rk_usb_power_up(void);
31 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
32 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
36 /*************************cru define********************************************/
39 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
40 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
51 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
52 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
53 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
56 #define RK3288_PLL_RESET CRU_W_MSK_SETBITS(1,5,0x1)
57 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
59 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
60 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
61 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
64 /*******************************gpio define **********************************************/
66 /* GPIO control registers */
67 #define GPIO_SWPORT_DR 0x00
68 #define GPIO_SWPORT_DDR 0x04
69 #define GPIO_INTEN 0x30
70 #define GPIO_INTMASK 0x34
71 #define GPIO_INTTYPE_LEVEL 0x38
72 #define GPIO_INT_POLARITY 0x3c
73 #define GPIO_INT_STATUS 0x40
74 #define GPIO_INT_RAWSTATUS 0x44
75 #define GPIO_DEBOUNCE 0x48
76 #define GPIO_PORTS_EOI 0x4c
77 #define GPIO_EXT_PORT 0x50
78 #define GPIO_LS_SYNC 0x60
80 /***********************************sleep func*********************************************/
82 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
83 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
84 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
86 // sys resume code in boot ram
87 #define RKPM_BOOT_CODE_PHY (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
88 #define RKPM_BOOT_CODE_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
91 // sys resume data in boot ram
92 #define RKPM_BOOT_DATA_PHY (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
93 #define RKPM_BOOT_DATA_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
95 // ddr resume data in boot ram
96 #define RKPM_BOOT_DDRCODE_PHY (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
97 #define RKPM_BOOT_DDRCODE_BASE (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
99 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
101 // the value is used to control cpu resume flow
102 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
103 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
104 static char *resume_data_phy= (char *)( RKPM_BOOT_DATA_PHY);
108 #define BOOT_RAM_SIZE (4*1024)
109 #define INT_RAM_SIZE (64*1024)
111 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
112 static char int_ram_data[INT_RAM_SIZE];
114 char * ddr_get_resume_code_info(u32 *size);
115 char * ddr_get_resume_data_info(u32 *size);
125 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
128 char *addr_base,*addr_phy,*data_src,*data_dst;
129 u32 sr_size,data_size;
131 addr_base=(char *)RKPM_BOOTRAM_BASE;
132 addr_phy=(char *)RKPM_BOOTRAM_PHYS;
133 sr_size=RKPM_BOOTRAM_SIZE;
137 memcpy(boot_save,addr_base, sr_size);
139 // move resume code and date to boot sram
141 data_dst=(char *)RKPM_BOOT_CODE_BASE;
142 data_src=(char *)rkpm_slp_cpu_resume;
143 data_size=RKPM_BOOT_CODE_SIZE;
144 memcpy((char *)data_dst,(char *)data_src, data_size);
147 data_dst=(char *)resume_data_base;
148 data_src=(char *)sleep_resume_data;
149 data_size=sizeof(sleep_resume_data);
150 memcpy((char *)data_dst,(char *)data_src, data_size);
154 /*************************ddr code cpy*************************************/
156 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
157 data_src=(char *)ddr_get_resume_code_info(&data_size);
159 data_size=RKPM_ALIGN(data_size,4);
161 memcpy((char *)data_dst,(char *)data_src, data_size);
164 data_dst=(char *)(data_dst+data_size);
166 data_src=(char *)ddr_get_resume_data_info(&data_size);
167 data_size=RKPM_ALIGN(data_size,4);
168 memcpy((char *)data_dst,(char *)data_src, data_size);
170 /*************************ddr code cpy end*************************************/
171 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
172 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
173 /*************************int mem bak*************************************/
175 addr_base=(char *)rockchip_sram_virt;
176 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
177 sr_size=rockchip_sram_size;
178 // rkpm_ddr_printascii("piephy\n");
179 //rkpm_ddr_printhex(addr_phy);
182 memcpy(int_save,addr_base, sr_size);
184 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
185 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
190 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
193 char *addr_base,*addr_phy;
196 addr_base=(char *)RKPM_BOOTRAM_BASE;
197 addr_phy=(char *)RKPM_BOOTRAM_PHYS;
198 sr_size=RKPM_BOOTRAM_SIZE;
201 memcpy(addr_base,boot_save, sr_size);
203 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
204 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
209 addr_base=(char *)rockchip_sram_virt;
210 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
211 sr_size=rockchip_sram_size;
214 memcpy(addr_base, int_save,sr_size);
216 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
217 outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
221 /**************************************gic save and resume**************************/
222 #define RK_GICD_BASE (RK_GIC_VIRT)
223 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
225 #define PM_IRQN_START 32
226 #define PM_IRQN_END 107//107
227 static void pm_gic_enable(u32 irqs)
232 void __iomem *reg_off;
233 unsigned int gic_irqs;
235 gic_irqs = PM_IRQN_END;
236 irqstart=PM_IRQN_START;//PM_IRQN_START;
238 reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
240 writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
245 static void rkpm_gic_disable(u32 irqs)
249 void __iomem *reg_off;
250 unsigned int gic_irqs;
252 gic_irqs = PM_IRQN_END;
253 irqstart=PM_IRQN_START;//PM_IRQN_START;
255 reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
257 writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
261 #define gic_reg_dump(a,b,c) {}//reg_dump((a),(b),(c))
263 static u32 slp_gic_save[260+50];
266 static void rkpm_gic_dist_save(u32 *context)
268 int i = 0,j,irqstart=0;
269 unsigned int gic_irqs;
271 gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
272 gic_irqs = (gic_irqs + 1) * 32;
275 //printk("gic_irqs=%d\n",gic_irqs);
276 //gic_irqs = PM_IRQN_END;
277 irqstart=PM_IRQN_START;//PM_IRQN_START;
281 for (j = irqstart; j < gic_irqs; j += 16)
282 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
283 gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
286 * Set all global interrupts to this CPU only.
288 for(j = 0; j < gic_irqs; j += 4)
289 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET + (j * 4) / 4);
291 gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
294 for (j = 0; j < gic_irqs; j += 4)
295 context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
296 gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
302 for (j = 0; j < gic_irqs; j += 32)
303 context[i++]=readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4) / 32);
304 gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
306 for (j = irqstart; j < gic_irqs; j += 32)
307 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
309 gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
315 for (j = 0; j < gic_irqs; j += 32)
316 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
318 gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
321 for (j = 0; j < gic_irqs; j += 32)
322 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
325 gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
329 gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
330 gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
332 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
333 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
334 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
338 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
339 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
340 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
341 context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
342 context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
344 #if 0 //rk319x is not need
346 for (j = irqstart; j < gic_irqs; j += 32)
348 writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
356 static void rkpm_gic_dist_resume(u32 *context)
359 int i = 0,j,irqstart=0;
360 unsigned int gic_irqs;
363 gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
364 gic_irqs = (gic_irqs + 1) * 32;
369 //gic_irqs = PM_IRQN_END;
370 irqstart=PM_IRQN_START;//PM_IRQN_START;
372 writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
374 writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
376 for (j = irqstart; j < gic_irqs; j += 32)
378 writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
386 for (j = irqstart; j < gic_irqs; j += 16)
388 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
391 gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
394 * Set all global interrupts to this CPU only.
396 for (j = 0; j < gic_irqs; j += 4)
398 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET + (j * 4) / 4);
401 gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
404 for (j = 0; j < gic_irqs; j += 4)
406 writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
410 gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
414 for (j = 0; j < gic_irqs; j += 32)
416 writel_relaxed(context[i++],RK_GICD_BASE + 0x80 + (j * 4 )/ 32);
418 sram_printhex((j * 4 )/ 32);
424 sram_printhex(readl_relaxed(RK_GICD_BASE + 0x80 + (j * 4 )/ 32));
431 gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
435 for (j = irqstart; j < gic_irqs; j += 32)
437 //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
441 gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
446 for (j = 0; j < gic_irqs; j += 32)
448 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
452 gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
455 //for (j = 0; j < gic_irqs; j += 32)
456 // writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
461 for (j = 0; j < gic_irqs; j += 32)
463 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
468 gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
470 writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
472 writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
474 writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
476 gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
477 gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
481 /**************************************regs save and resume**************************/
483 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
486 u32 cnt=(end_offset-st_offset)/4+1;
489 data[i]=readl_relaxed(base+st_offset+i*4);
493 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
496 u32 cnt=(end_offset-st_offset)/4+1;
499 reg_writel(data[i]|w_msk,(base+st_offset+i*4));
503 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
506 u32 cnt=(end_offset-st_offset)/4+1;
509 reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
513 /**************************************uarts save and resume**************************/
515 #define RK3288_UART_NUM (4)
517 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
518 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
520 static u32 slp_uart_data[RK3288_UART_NUM][10];
521 static u32 slp_uart_data_flag[RK3288_UART_NUM];
524 #define UART_DLL 0 /* Out: Divisor Latch Low */
525 #define UART_DLM 1 /* Out: Divisor Latch High */
530 #define UART_LCR 3 /* Out: Line Control Register */
533 void slp_uart_save(int ch)
536 void __iomem *b_addr=slp_uart_base[ch];
537 int idx=RK3288_CLKGATE_PCLK_UART0+ch;
539 if(b_addr==NULL || ch>=RK3288_UART_NUM)
544 idx=RK3288_CLKGATE_PCLK_UART2;
545 b_addr=RK_DEBUG_UART_VIRT;
549 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
550 RK3288_CRU_UNGATING_OPS(idx);
552 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
553 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
555 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
556 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
558 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
559 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
560 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
561 slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
563 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
567 void slp_uart_resume(int ch)
572 void __iomem *b_addr=slp_uart_base[ch];
573 int idx=RK3288_CLKGATE_PCLK_UART0+ch;
576 //rkpm_ddr_printascii("\nch");
577 // rkpm_ddr_printhex(b_addr);
579 if(b_addr==NULL || ch>=RK3288_UART_NUM)
583 idx=RK3288_CLKGATE_PCLK_UART2;
585 //rkpm_ddr_printhex(ch);
587 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
588 RK3288_CRU_UNGATING_OPS(idx);
591 temp=slp_uart_data[ch][i++];
592 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
594 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
595 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
597 writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
599 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
600 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
601 writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
603 writel_relaxed(temp,b_addr+UART_LCR*4);
605 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
608 /**************************************i2c save and resume**************************/
610 //#define RK3288_I2C_REG_DUMP
611 #define RK3288_I2C_NUM (6)
612 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
613 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
615 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
617 void slp_i2c_save(int ch)
620 void __iomem *b_addr=slp_i2c_base[ch];
621 int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
627 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
628 RK3288_CRU_UNGATING_OPS(idx);
630 #ifdef RK3288_I2C_REG_DUMP
631 rkpm_ddr_printascii("i2c save");
632 rkpm_ddr_printhex(ch);
633 rkpm_ddr_printch('\n');
634 rkpm_ddr_regs_dump(b_addr,0x0,0xc);
637 slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
640 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
643 void slp_i2c_resume(int ch)
645 void __iomem *b_addr=slp_i2c_base[ch];
646 int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
651 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
652 RK3288_CRU_UNGATING_OPS(idx);
654 slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
656 #ifdef RK3288_I2C_REG_DUMP
657 rkpm_ddr_printascii("i2c resume");
658 rkpm_ddr_printhex(ch);
659 rkpm_ddr_printch('\n');
660 rkpm_ddr_regs_dump(b_addr,0x0,0xc);
663 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
666 /**************************************gpios save and resume**************************/
667 #define RK3288_GPIO_CH (9)
668 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
669 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
670 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
672 static void gpio_ddr_dump_reg(int ports)
674 void __iomem *b_addr=RK_GPIO_VIRT(ports);
676 rkpm_ddr_printascii("gpio-");
677 rkpm_ddr_printhex(ports);
678 rkpm_ddr_printhex('\n');
680 rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
681 rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
682 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
683 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
684 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
685 rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
686 rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
687 rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
688 rkpm_ddr_printhex('\n');
690 rkpm_ddr_printascii("iomux\n");
691 rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
693 rkpm_ddr_printascii("iomux\n");
694 rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
698 static void slp_pin_gpio_save(int ports)
701 void __iomem *b_addr=RK_GPIO_VIRT(ports);
702 int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
705 if(ports==0||ports>=RK3288_GPIO_CH)
708 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
709 RK3288_CRU_UNGATING_OPS(idx);
711 //gpio_ddr_dump_reg(ports);
713 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
714 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
715 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
716 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
717 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
718 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
719 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
720 slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
724 slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
725 slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
729 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
733 static void slp_pin_gpio_resume (int ports)
736 void __iomem *b_addr=RK_GPIO_VIRT(ports);
737 int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
740 if(ports==0||ports>=RK3288_GPIO_CH)
742 gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
743 RK3288_CRU_UNGATING_OPS(idx);
748 slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
749 slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
753 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
754 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
755 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
756 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
757 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
758 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
759 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
760 writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
762 //gpio_ddr_dump_reg(ports);
763 cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
767 static inline u32 rkpm_l2_config(void)
770 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
773 /**************************************sleep func**************************/
775 void ddr_reg_save(uint32_t *pArg);
776 void fiq_glue_resume(void);
777 void rk30_cpu_resume(void);
778 void rk30_l2_cache_init_pm(void);
779 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
780 void ddr_cfg_to_lp_mode(void);
781 void l2x0_inv_all_pm(void);
782 void rk30_cpu_while_tst(void);
785 static u32 slp_grf_soc_con_data[5];
786 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
788 static u32 slp_grf_cpu_con_data[5];
789 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
791 static u32 slp_grf_uoc0_con_data[4];
792 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
794 static u32 slp_grf_uoc1_con_data[2];
795 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
797 static u32 slp_grf_uoc2_con_data[2];
798 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
800 static u32 slp_grf_uoc3_con_data[2];
801 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
804 static u32 slp_pmu_pwrmode_con_data[1];
807 static u32 slp_nandc_data[8];
808 static void __iomem *rk30_nandc_base=NULL;
813 void inline pm_io_base_map(void)
816 for(i=0;i<RK3288_I2C_NUM;i++)
817 slp_i2c_base[i] = ioremap(slp_i2c_phy[i], 0x1000);
819 for(i=0;i<RK3288_UART_NUM;i++)
821 if(i!=CONFIG_RK_DEBUG_UART)
822 slp_uart_base[i] = ioremap(slp_uart_phy[i], 0x1000);
824 slp_uart_base[i] = RK_DEBUG_UART_VIRT;
828 enum rk3288_pwr_mode_con {
831 pmu_clk_core_src_gate_en,
832 pmu_global_int_disable,
840 pmu_chip_pd_en, // power off pin enable
856 pmu_ddr0io_ret_de_req,
857 pmu_ddr1io_ret_de_req
860 enum rk3288_pwr_mode_con1 {
875 static u32 rk3288_powermode=0;
876 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
878 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
880 static u32 rkpm_slp_mode_set(u32 ctrbits)
882 u32 mode_set,mode_set1;
884 // setting gpio0_a0 arm off pin
886 sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
888 pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
889 pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
891 pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
892 pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
894 ddr_pin_set_fun(0x0,0xa,0x0,0x1);
898 //mode_set1=pmu_pwr_mode_con1;
899 //mode_set=pmu_pwr_mode_con0;
901 //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
902 pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
905 reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
908 reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
911 mode_set= BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
914 if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
916 rkpm_ddr_printascii("-autoidle-");
917 mode_set|=BIT(pmu_clk_core_src_gate_en);
919 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
921 rkpm_ddr_printascii("-armdp-");
922 mode_set|=BIT(pmu_a12_0_pd_en);
924 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
926 rkpm_ddr_printascii("-armoff-");
927 mode_set|=BIT(pmu_scu_en)
928 //|BIT(pmu_a12_0_pd_en)
929 |BIT(pmu_clk_core_src_gate_en) // »½ÐѺóÒì³£
930 |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
931 |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
932 //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
933 |BIT(pmu_chip_pd_en);
934 mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
941 else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
944 rkpm_ddr_printascii("-armoff-logdp-");
946 mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
948 |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
949 |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
950 |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
951 |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
953 mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
968 if(mode_set&BIT(pmu_osc_24m_dis))
970 rkpm_ddr_printascii("osc_off");
971 pmu_writel(32*30,RK3288_PMU_OSC_CNT);
972 pmu_writel(32*30,RK3288_PMU_STABL_CNT);
976 pmu_writel(24*1000*10,RK3288_PMU_STABL_CNT);
978 // pmu_writel(24*1000*20,RK3288_PMU_CORE_PWRDWN_CNT);
981 if(mode_set&BIT(pmu_ddr0io_ret_en))
983 rkpm_ddr_printascii("ddrc_off");
984 ddr_pin_set_fun(0x0,0xa,0x1,0x1);
985 ddr_pin_set_fun(0x0,0xa,0x2,0x1);
986 ddr_pin_set_fun(0x0,0xa,0x3,0x1);
989 pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
990 pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
992 // rkpm_ddr_printhex(mode_set);
993 // rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
995 return (pmu_readl(RK3288_PMU_PWRMODE_CON));
998 static inline void rkpm_slp_mode_set_resume(void)
1001 pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1002 pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1004 pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1005 pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1006 reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1010 static void sram_code_data_save(u32 pwrmode)
1012 char *code_src,*data_src;
1013 u32 code_size,data_size;
1014 u32 ddr_bits= RKPM_CTR_ARMLOGDP_LPMD|RKPM_CTR_ARMOFF_LOGDP_LPMD|RKPM_CTR_ARMLOGOFF_DLPMD;
1017 if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1019 sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1020 sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1021 sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1022 sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1026 sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1030 if(pwrmode&BIT(pmu_bus_pd_en))
1032 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1033 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1034 code_src=(char *)ddr_get_resume_code_info(&code_size);
1035 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1036 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1037 data_src=(char *)ddr_get_resume_data_info(&data_size);
1038 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1042 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1045 sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1049 local_flush_tlb_all();
1053 static inline void sram_code_data_resume(u32 pwrmode)
1055 if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1057 sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1062 static void rkpm_peri_save(u32 power_mode)
1066 if(power_mode&BIT(pmu_scu_en))
1068 rkpm_gic_dist_save(&slp_gic_save[0]);
1071 gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1072 gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1073 RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1074 cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1075 RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1078 if(power_mode&BIT(pmu_bus_pd_en))
1083 ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1084 ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1085 ddr_pin_set_fun(7,0xc,0x6,0);
1087 ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1088 ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1089 ddr_pin_set_fun(7,0xc,0x7,0);
1093 ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1094 ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1095 ddr_pin_set_fun(0,0xb,0x7,0);
1097 ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1098 ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1099 ddr_pin_set_fun(0,0xc,0x0,0);
1101 slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1102 //slp_i2c_save(2);//i2c audio
1106 cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1107 RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1108 cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1113 static inline void rkpm_peri_resume(u32 power_mode)
1115 if(power_mode&BIT(pmu_scu_en))
1117 //fiq_glue_resume();
1118 rkpm_gic_dist_resume(&slp_gic_save[0]);
1120 //rkpm_ddr_printascii("gic res");
1122 if(power_mode&BIT(pmu_bus_pd_en))
1124 slp_i2c_resume(0);// i2c pmu
1125 slp_i2c_resume(2);//i2c audio
1130 static inline void rkpm_peri_resume_first(u32 power_mode)
1132 if(power_mode&BIT(pmu_bus_pd_en))
1136 static void rkpm_slp_setting(void)
1138 rk_usb_power_down();
1140 //rkpm_gic_disable(130);
1141 // rkpm_gic_disable(132);
1143 //rkpm_ddr_printhex(pmu_readl(RK3288_PMU_WAKEUP_CFG1));
1144 //rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1148 static void rkpm_save_setting_resume_first(void)
1150 rk_usb_power_down();
1151 rkpm_peri_resume_first(rk3288_powermode);
1153 // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1155 //rk319x_pm_set_power_domain(PD_PERI,true);
1156 //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1157 slp_pin_gpio_resume(1);
1158 slp_pin_gpio_resume(2);
1159 slp_pin_gpio_resume(3);
1160 slp_pin_gpio_resume(4);
1163 slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1164 slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1166 slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1167 slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1168 slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1169 slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1171 //sram_printch_uart_enable();
1178 static u32 rk3288_ctrbits=0;
1180 static void rkpm_save_setting(u32 ctrbits)
1182 //rk3288_ctrbits=ctrbits;
1183 rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1184 if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1186 sram_code_data_save(rk3288_powermode);
1187 rkpm_peri_save(rk3288_powermode);
1193 static void rkpm_save_setting_resume(void)
1196 if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1198 sram_code_data_resume(rk3288_powermode);
1199 rkpm_peri_resume(rk3288_powermode);
1202 rkpm_slp_mode_set_resume();
1207 /*******************************common code for rkxxx*********************************/
1208 static void inline uart_printch(char byte)
1211 u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1212 u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1214 if(CONFIG_RK_DEBUG_UART==4)
1215 u_clk_id=RK3288_CLKGATE_UART4_SRC;
1216 if(CONFIG_RK_DEBUG_UART==2)
1217 u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1219 reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1220 reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1221 RK3288_CRU_UNGATING_OPS(u_clk_id);
1222 RK3288_CRU_UNGATING_OPS(u_pclk_id);
1226 writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1229 /* loop check LSR[6], Transmitter Empty bit */
1230 while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1233 cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1234 cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1240 void PIE_FUNC(sram_printch)(char byte)
1245 static void pll_udelay(u32 udelay);
1247 static void ddr_printch(char byte)
1252 /*******************************gpio func*******************************************/
1253 //#define RK3288_PMU_GPIO0_A_IOMUX 0x0084
1254 //#define RK3288_PMU_GPIO0_B_IOMUX 0x0088
1255 //#define RK3288_PMU_GPIO0_C_IOMUX 0x008c
1256 //#define RK3288_PMU_GPIO0_D_IOMUX 0x0090
1257 //pin=0x0a21 gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1258 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1268 off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1269 pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1274 off_set=port*(4*4)+bank*4;
1275 //form RK3288_GRF_GPIO1D_IOMUX
1276 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1280 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1289 off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1290 return (pmu_readl(off_set)>>(b_gpio*2))&0x3;
1295 off_set=port*(4*4)+bank*4;
1296 //form RK3288_GRF_GPIO1D_IOMUX
1297 return (reg_readl(RK_GRF_VIRT+0+off_set)>>(b_gpio*2))&0x3;
1301 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1312 //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1313 off_set=0x14c-0x1c+port*(4*4)+bank*4;
1314 reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1319 if(bank>2)// gpio0_d is not support
1321 pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1326 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1337 //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1338 off_set=0x14c-0x1c+port*(4*4)+bank*4;
1339 return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1344 if(bank>2)// gpio0_d is not support
1346 return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1353 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1358 b_gpio=bank*8+b_gpio;//
1360 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1362 if(type==RKPM_GPIO_OUTPUT)
1365 val&=~(0x1<<b_gpio);
1367 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1370 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1373 b_gpio=bank*8+b_gpio;
1374 return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1377 //RKPM_GPIOS_OUT_L RKPM_GPIOS_OUT_H
1378 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1383 b_gpio=bank*8+b_gpio;
1385 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1387 if(level==RKPM_GPIO_OUT_H)
1390 val&=~(0x1<<b_gpio);
1392 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1395 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1398 b_gpio=bank*8+b_gpio;
1399 return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1402 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1406 b_gpio=bank*8+b_gpio;
1408 return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1410 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1415 b_gpio=bank*8+b_gpio;
1417 val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1418 rkpm_ddr_printascii("\n inten:");
1419 rkpm_ddr_printhex(val);
1421 rkpm_ddr_printascii("-");
1425 val&=~(0x1<<b_gpio);
1427 reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1430 rkpm_ddr_printhex(val);
1431 rkpm_ddr_printascii("-");
1433 rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1435 rkpm_ddr_printascii("\n");
1440 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1442 pin_set_fun(port,bank,b_gpio,fun);
1444 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1446 return pin_get_funset(port,bank,b_gpio);
1449 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1451 pin_set_pull(port,bank,b_gpio,fun);
1453 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1455 return pin_get_pullset(port,bank,b_gpio);
1458 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1460 gpio_set_in_output(port,bank,b_gpio,type);
1463 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1465 return gpio_get_in_outputset(port,bank,b_gpio);
1468 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1471 gpio_set_output_level(port,bank,b_gpio,level);
1475 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1477 return gpio_get_output_levelset(port,bank,b_gpio);
1480 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1482 return gpio_get_input_level(port,bank,b_gpio);
1485 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1487 pin_set_fun(port,bank,b_gpio,fun);
1489 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1491 return pin_get_funset(port,bank,b_gpio);
1494 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1496 pin_set_pull(port,bank,b_gpio,fun);
1498 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1500 return pin_get_pullset(port,bank,b_gpio);
1503 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1505 gpio_set_in_output(port,bank,b_gpio,type);
1508 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1510 return gpio_get_in_outputset(port,bank,b_gpio);
1513 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1515 gpio_set_output_level(port,bank,b_gpio,level);
1518 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1520 return gpio_get_output_levelset(port,bank,b_gpio);
1523 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1525 return gpio_get_input_level(port,bank,b_gpio);
1530 static void __sramfunc rkpm_pin_gpio_config_sram(u32 pin_gpio_bits,u32 *save_bits)
1534 u8 port,bank,b_gpio,fun,in_out, level, pull;
1536 pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1537 in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1538 pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1539 level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1541 port=RKPM_PINBITS_PORT(pins);
1542 bank=RKPM_PINBITS_BANK(pins);
1543 b_gpio=RKPM_PINBITS_BGPIO(pins);
1544 fun=RKPM_PINBITS_FUN(pins);
1549 pins=RKPM_PINBITS_SET_FUN(pins,sram_pin_get_funset(port,bank,b_gpio));
1550 *save_bits=RKPM_PINGPIO_BITS(pins,sram_pin_get_pullset(port,bank,b_gpio),sram_gpio_get_in_outputset(port,bank,b_gpio),
1551 sram_gpio_get_output_levelset(port,bank,b_gpio));
1553 if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1555 if(level==RKPM_GPIO_OUT_L)
1556 pull=RKPM_GPIO_PULL_DN;
1558 pull=RKPM_GPIO_PULL_UP;
1560 sram_gpio_set_output_level(port,bank,b_gpio,level);
1563 sram_pin_set_pull(port,bank,b_gpio,pull);
1564 sram_pin_set_fun(port,bank,b_gpio,fun);
1568 sram_gpio_set_in_output(port,bank,b_gpio,in_out);
1573 static inline void rkpm_pin_gpio_config_ddr(u32 pin_gpio_bits,u32 *save_bits)
1577 u8 port,bank,b_gpio,fun,in_out, level, pull;
1579 pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1580 in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1581 pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1582 level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1584 port=RKPM_PINBITS_PORT(pins);
1585 bank=RKPM_PINBITS_BANK(pins);
1586 b_gpio=RKPM_PINBITS_BGPIO(pins);
1587 fun=RKPM_PINBITS_FUN(pins);
1592 pins=RKPM_PINBITS_SET_FUN(pins,ddr_pin_get_funset(port,bank,b_gpio));
1593 *save_bits=RKPM_PINGPIO_BITS(pins,ddr_pin_get_pullset(port,bank,b_gpio),ddr_gpio_get_in_outputset(port,bank,b_gpio),
1594 ddr_gpio_get_output_levelset(port,bank,b_gpio));
1596 if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
1598 if(level==RKPM_GPIO_OUT_L)
1599 pull=RKPM_GPIO_PULL_DN;
1601 pull=RKPM_GPIO_PULL_UP;
1603 ddr_gpio_set_output_level(port,bank,b_gpio,level);
1606 ddr_pin_set_pull(port,bank,b_gpio,pull);
1607 ddr_pin_set_fun(port,bank,b_gpio,fun);
1611 ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1617 #define GPIO_DTS_NUM 10
1619 static u32 gpio_dts_save[GPIO_DTS_NUM];
1620 static u32 gpio_dts[GPIO_DTS_NUM];
1622 #define PMICGPIO_DTS_NUM 3
1625 u32 DEFINE_PIE_DATA(pmicgpio_dts[PMICGPIO_DTS_NUM]);
1626 static u32 *p_pmicgpio_dts;
1627 static __sramdata u32 pmicgpio_dts_save[PMICGPIO_DTS_NUM];
1629 static void __sramfunc pmic_gpio_suspend(void)
1634 if(DATA(pmicgpio_dts[i]))
1635 rkpm_pin_gpio_config_sram(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1638 pmicgpio_dts_save[i]=0;
1645 rkpm_sram_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1648 rkpm_sram_reg_dump(RK_GRF_VIRT,0xc,0x84);
1649 rkpm_sram_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1650 rkpm_sram_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1651 rkpm_sram_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1656 static void __sramfunc pmic_gpio_resume(void)
1661 if(pmicgpio_dts_save[i])
1662 rkpm_pin_gpio_config_sram(pmicgpio_dts_save[i],NULL);
1667 void PIE_FUNC(pmic_suspend)(void)
1669 pmic_gpio_suspend();
1673 void PIE_FUNC(pmic_resume)(void)
1679 static void rkpm_gpio_suspend(void)
1684 if(DATA(pmicgpio_dts[i]))
1685 rkpm_pin_gpio_config_ddr(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
1688 pmicgpio_dts_save[i]=0;
1695 rkpm_ddr_reg_dump(RK_GPIO_VIRT(i),0,0x4);
1698 rkpm_ddr_reg_dump(RK_GRF_VIRT,0xc,0x84);
1699 rkpm_ddr_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
1700 rkpm_ddr_reg_dump(RK_PMU_VIRT,0x64,0x6c);
1701 rkpm_ddr_reg_dump(RK_PMU_VIRT,0x84,0x9c);
1706 static void rkpm_gpio_resume(void)
1711 if(pmicgpio_dts_save[i])
1712 rkpm_pin_gpio_config_ddr(pmicgpio_dts_save[i],NULL);
1716 static void gpio_get_dts_info(struct device_node *parent)
1720 for(i=0;i<PMICGPIO_DTS_NUM;i++)
1721 p_pmicgpio_dts[i]=0;
1723 for(i=0;i<GPIO_DTS_NUM;i++)
1727 p_pmicgpio_dts= kern_to_pie(rockchip_pie_chunk, &DATA(pmicgpio_dts[0]));
1729 if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",p_pmicgpio_dts,PMICGPIO_DTS_NUM))
1731 p_pmicgpio_dts[0]=0;
1732 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1735 for(i=0;i<PMICGPIO_DTS_NUM;i++)
1736 printk("%s:pmic gpio(%x)\n",__FUNCTION__,p_pmicgpio_dts[i]);
1738 if(of_property_read_u32_array(parent,"rockchip,pm-gpios",gpio_dts,GPIO_DTS_NUM))
1741 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1743 for(i=0;i<GPIO_DTS_NUM;i++)
1744 printk("%s:pmic gpio(%x)\n",__FUNCTION__,gpio_dts[i]);
1746 rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1747 rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_suspend)),
1748 fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_resume)));
1753 /*******************************clk gating config*******************************************/
1754 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1755 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1758 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1759 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1760 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1763 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1764 static u32 *p_rkpm_clkgt_last_set;
1766 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1768 void PIE_FUNC(gtclks_sram_suspend)(void)
1771 // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1772 // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1774 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1776 rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1777 CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1779 rkpm_sram_printch('\n');
1780 rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1781 rkpm_sram_printch('-');
1782 rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1783 rkpm_sram_printch('-');
1784 rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1785 if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1786 rkpm_sram_printch('\n');
1790 //RK3288_CRU_UNGATING_OPS(u_clk_id);
1791 //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1795 void PIE_FUNC(gtclks_sram_resume)(void)
1798 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1800 cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1803 #define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + offset)
1804 #define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1806 #define gpio7_readl(offset) readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1807 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1809 int gpio7_pin_data1, gpio7_pin_dir1;
1810 int gpio7_pin_iomux1;
1812 static void gtclks_suspend(void)
1815 gpio7_pin_data1= gpio7_readl(0);
1816 gpio7_pin_dir1 = gpio7_readl(0x04);
1817 gpio7_pin_iomux1 = gpio7_readl(0x6c);
1818 grf_writel(0x00040000, 0x6c);
1819 gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1820 gpio7_writel((gpio7_pin_data1|2), 0x00);
1822 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1823 // ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1824 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1826 clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1830 // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1831 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1832 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1833 // RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1834 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1835 // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1836 // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1839 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1840 // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1841 // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1842 // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1843 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1844 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
1845 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
1846 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
1847 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
1848 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
1849 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
1850 // RK3288_CRU_CLKGATES_CON(i)==0x1a8
1851 RK3288_CRU_CLKGATES_CON(i)==0xfff
1855 cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1856 // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
1862 // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
1863 CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
1866 rkpm_ddr_printch('\n');
1867 rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
1868 rkpm_ddr_printch('-');
1869 rkpm_ddr_printhex(clk_ungt_msk[i]);
1870 rkpm_ddr_printch('-');
1871 rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
1872 if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1873 rkpm_ddr_printch('\n');
1879 static void gtclks_resume(void)
1882 for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1884 cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
1886 //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1887 // ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1888 grf_writel(0x00040004, 0x6c);
1891 /********************************pll power down***************************************/
1893 static void pm_pll_wait_lock(u32 pll_idx)
1895 u32 delay = 600000U;
1897 // mode=cru_readl(RK3288_CRU_MODE_CON);
1905 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
1910 rkpm_ddr_printascii("unlock-pll:");
1911 rkpm_ddr_printhex(pll_idx);
1912 rkpm_ddr_printch('\n');
1914 //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
1917 static void pll_udelay(u32 udelay)
1920 mode=cru_readl(RK3288_CRU_MODE_CON);
1922 cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
1924 rkpm_udelay(udelay*5);
1926 cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
1929 static u32 plls_con0_save[END_PLL_ID];
1930 static u32 plls_con1_save[END_PLL_ID];
1931 static u32 plls_con2_save[END_PLL_ID];
1932 static u32 plls_con3_save[END_PLL_ID];
1934 static u32 cru_mode_con;
1936 static inline void plls_suspend(u32 pll_id)
1938 plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
1939 plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
1940 plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
1941 plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
1943 cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
1946 static inline void plls_resume(u32 pll_id)
1948 u32 pllcon0, pllcon1, pllcon2;
1950 if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
1954 cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
1956 cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
1957 cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
1959 pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
1960 pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
1961 pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
1964 cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
1965 cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
1966 cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
1967 cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
1970 //udelay(5); //timer7 delay
1973 cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
1977 pm_pll_wait_lock(pll_id);
1979 cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
1983 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
1985 static void pm_plls_suspend(void)
1988 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
1989 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
1990 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
1992 clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
1993 clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
1994 clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
1995 clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
1996 clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
1997 clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
1998 clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2000 cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2003 cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2004 plls_suspend(NPLL_ID);
2007 cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2010 cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2012 // set 1,pdbus pll is gpll
2013 cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2017 |CRU_W_MSK_SETBITS(0,0,0x7) // 1 aclk
2018 |CRU_W_MSK_SETBITS(0,3,0x1f) // 1 aclk src
2019 |CRU_W_MSK_SETBITS(0,8,0x3) // 1 hclk 0~1 1 2 4
2020 |CRU_W_MSK_SETBITS(0,12,0x7) // 3 pclk
2021 , RK3288_CRU_CLKSELS_CON(1));
2024 cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2026 // peri aclk hclk pclk
2028 |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2029 |CRU_W_MSK_SETBITS(0,8,0x3) // 2 hclk 0 1:1,1 2:1 ,2 4:1
2030 |CRU_W_MSK_SETBITS(0,12,0x3)// 2 0~3 1 2 4 8 div
2031 , RK3288_CRU_CLKSELS_CON(10));
2033 cru_writel(clk_sel33|CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2035 plls_suspend(CPLL_ID);
2036 plls_suspend(GPLL_ID);
2039 cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2040 // core_m0 core_mp a12_core
2042 |CRU_W_MSK_SETBITS(0,0,0xf) // 1 axi_mo
2043 |CRU_W_MSK_SETBITS(0,4,0xf) // 3 axi mp
2044 |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2045 , RK3288_CRU_CLKSELS_CON(0));
2046 // core0 core1 core2 core3
2048 |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2049 |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2050 |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2051 |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2052 , RK3288_CRU_CLKSELS_CON(36));
2056 |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2057 |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2058 |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2059 , RK3288_CRU_CLKSELS_CON(37));
2062 |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2063 |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2064 |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2065 , RK3288_CRU_CLKSELS_CON(37));
2069 plls_suspend(APLL_ID);
2073 static void pm_plls_resume(void)
2077 // core_m0 core_mp a12_core
2078 cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
2079 // core0 core1 core2 core3
2080 cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
2081 , RK3288_CRU_CLKSELS_CON(36));
2083 cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
2085 plls_resume(APLL_ID);
2086 cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2088 // peri aclk hclk pclk
2089 cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
2090 , RK3288_CRU_CLKSELS_CON(10));
2092 cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
2094 cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
2095 , RK3288_CRU_CLKSELS_CON(1));
2098 cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
2102 cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2104 plls_resume(GPLL_ID);
2105 cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
2107 plls_resume(CPLL_ID);
2108 cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
2110 plls_resume(NPLL_ID);
2111 cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2113 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2114 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2115 // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2119 static __sramdata u32 sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2121 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2125 sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2126 sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2127 sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2130 if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2133 sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2135 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2136 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2137 , RK3288_CRU_MODE_CON);
2139 else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2144 cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2145 cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2146 cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2150 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2153 cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2154 cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2155 cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2156 cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2157 |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2158 |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2159 |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2164 static void clks_gating_suspend_init(void)
2166 // get clk gating info
2167 if(rockchip_pie_chunk)
2168 p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2170 p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2171 if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2172 ==RK3288_CRU_CLKGATES_CON(0))
2174 rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2175 if(rockchip_pie_chunk)
2176 rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2177 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2179 PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2182 if(rockchip_pie_chunk)
2183 rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2184 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2187 /***************************prepare and finish reg_pread***********************************/
2191 #define GIC_DIST_PENDING_SET 0x200
2192 static noinline void rk3288_pm_dump_irq(void)
2194 u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2198 for (i = 0; i < ARRAY_SIZE(irq); i++)
2199 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2200 for (i = 0; i < ARRAY_SIZE(irq); i++) {
2202 log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2204 printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2205 for (i = 0; i <= 8; i++) {
2206 if (irq_gpio & (1 << i))
2207 printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2211 #define DUMP_GPIO_INTEN(ID) \
2213 u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2215 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2216 rkpm_ddr_printhex(en); \
2217 rkpm_ddr_printch('\n'); \
2218 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2222 //dump while irq is enable
2223 static noinline void rk3288_pm_dump_inten(void)
2236 static void rkpm_prepare(void)
2239 u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2241 // rkpm_ddr_printhex(temp);
2242 reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2243 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2244 // rkpm_ddr_printhex(temp);
2246 // dump GPIO INTEN for debug
2247 rk3288_pm_dump_inten();
2250 static void rkpm_finish(void)
2252 rk3288_pm_dump_irq();
2256 static void interface_ctr_reg_pread(void)
2261 local_flush_tlb_all();
2262 #if 0 // do it in ddr suspend
2263 for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2264 readl_relaxed(addr);
2266 readl_relaxed(RK_PMU_VIRT);
2267 readl_relaxed(RK_GRF_VIRT);
2268 readl_relaxed(RK_DDR_VIRT);
2269 readl_relaxed(RK_GPIO_VIRT(0));
2270 //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2271 //readl_relaxed(RK_GPIO_VIRT(3));
2273 void PIE_FUNC(ddr_leakage_tst)(void)
2275 cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2276 rkpm_sram_printch('\n');
2277 rkpm_sram_printch('t');
2278 rkpm_sram_printch('e');
2279 rkpm_sram_printch('s');
2280 rkpm_sram_printch('t');
2284 static void __init rk3288_suspend_init(void)
2286 struct device_node *parent;
2289 PM_LOG("%s enter\n",__FUNCTION__);
2291 parent = of_find_node_by_name(NULL, "rockchip_suspend");
2293 if (IS_ERR_OR_NULL(parent)) {
2294 PM_ERR("%s dev node err\n", __func__);
2299 if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2301 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2304 PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2306 memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2307 rkpm_set_ctrbits(pm_ctrbits);
2309 clks_gating_suspend_init();
2311 rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2313 //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2315 rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2317 //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2319 rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2320 rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2322 if(rockchip_pie_chunk)
2323 rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2325 rkpm_set_ops_printch(ddr_printch);