arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22
  23 //#define CPU 3288
  24 //#include "sram.h"
  25 #include "pm-pie.c"
  26
  27
  28 /*************************cru define********************************************/
  29 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,id%16,0x1),RK3288_CRU_GATEID_CONS(id))
  30 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,id%16,0x1),RK3288_CRU_GATEID_CONS(id))
  31
  32
  33
  34 /*******************************gpio define **********************************************/
  35 #define GPIO_INTEN                      0x30
  36 #define GPIO_INTMASK            0x34
  37 #define GPIO_INTTYPE_LEVEL      0x38
  38 #define GPIO_INT_POLARITY       0x3c
  39 #define GPIO_INT_STATUS         0x40
  40
  41 /*******************************common code  for rkxxx*********************************/
  42
  43 static void  inline uart_printch(char byte)
  44 {
  45         u32 reg_save[2];
  46         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
  47         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
  48
  49         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
  50         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
  51         RK3288_CRU_UNGATING_OPS(u_clk_id);
  52         RK3288_CRU_UNGATING_OPS(u_pclk_id);
  53
  54         rkpm_udelay(1);
  55
  56         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
  57         dsb();
  58
  59         /* loop check LSR[6], Transmitter Empty bit */
  60         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
  61                 barrier();
  62
  63          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
  64          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
  65
  66         if (byte == '\n')
  67                 uart_printch('\r');
  68 }
  69
  70 void PIE_FUNC(sram_printch)(char byte)
  71 {
  72         uart_printch(byte);
  73 }
  74
  75 static void  ddr_printch(char byte)
  76 {
  77         uart_printch(byte);
  78 }
  79 /*******************************gpio func*******************************************/
  80 /* GPIO control registers */
  81 #define GPIO_SWPORT_DR          0x00
  82 #define GPIO_SWPORT_DDR         0x04
  83 #define GPIO_INTEN                      0x30
  84 #define GPIO_INTMASK            0x34
  85 #define GPIO_INTTYPE_LEVEL      0x38
  86 #define GPIO_INT_POLARITY       0x3c
  87 #define GPIO_INT_STATUS         0x40
  88 #define GPIO_INT_RAWSTATUS      0x44
  89 #define GPIO_DEBOUNCE           0x48
  90 #define GPIO_PORTS_EOI          0x4c
  91 #define GPIO_EXT_PORT           0x50
  92 #define GPIO_LS_SYNC            0x60
  93
  94 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
  95 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
  96 {
  97     u8 off_set;
  98     bank-=0xa;
  99     off_set=port*(4*4)+bank*4;
 100
 101     if(off_set<RK3288_GRF_GPIO1D_IOMUX)
 102         return;
 103     reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
 104 }
 105
 106 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
 107 {
 108     u8 off_set;
 109     bank-=0xa;
 110     off_set=port*(4*4)+bank*4;
 111
 112     if(off_set<RK3288_GRF_GPIO1D_IOMUX)
 113         return 0;
 114     return (reg_readl(RK_GRF_VIRT+0+off_set)>>(b_gpio*2))&0x3;
 115 }
 116
 117 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
 118 {
 119     u8 off_set;
 120
 121     bank-=0xa;
 122
 123     if(port > 0)
 124     {
 125         //gpio1_d st
 126         if(port==1&&bank<3)
 127          return;
 128         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
 129         off_set=0x14c-0x1c+port*(4*4)+bank*4;
 130         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
 131
 132     }
 133     else
 134     {
 135         if(bank>2)// gpio0_d is not support
 136             return;
 137         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
 138     }
 139
 140 }
 141
 142 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
 143 {
 144     u8 off_set;
 145
 146     bank-=0xa;
 147
 148     if(port > 0)
 149     {
 150         //gpio1_d st
 151         if(port==1&&bank<3)
 152             return 0;
 153         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
 154         off_set=0x14c-0x1c+port*(4*4)+bank*4;
 155         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
 156
 157     }
 158     else
 159     {
 160         if(bank>2)// gpio0_d is not support
 161             return 0;
 162         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
 163     }
 164
 165 }
 166
 167
 168 //RKPM_GPIOS_INPUT
 169 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
 170 {
 171     u8 val;
 172
 173     bank-=0xa;
 174     b_gpio=bank*8+b_gpio;//
 175
 176     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
 177
 178     if(type==RKPM_GPIO_OUTPUT)
 179         val|=(0x1<<b_gpio);
 180     else
 181         val&=~(0x1<<b_gpio);
 182
 183     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
 184 }
 185
 186 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
 187 {
 188     bank-=0xa;
 189     b_gpio=bank*8+b_gpio;
 190     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
 191 }
 192
 193 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
 194 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
 195 {
 196     u8 val;
 197
 198     bank-=0xa;
 199     b_gpio=bank*8+b_gpio;
 200
 201     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
 202
 203     if(level==RKPM_GPIO_OUT_H)
 204         val|=(0x1<<b_gpio);
 205     else //
 206         val&=~(0x1<<b_gpio);
 207
 208      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
 209 }
 210
 211 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
 212 {
 213     bank-=0xa;
 214     b_gpio=bank*8+b_gpio;
 215     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
 216 }
 217
 218 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
 219 {
 220
 221     bank-=0xa;
 222     b_gpio=bank*8+b_gpio;
 223
 224     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
 225 }
 226
 227 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
 228 {
 229         pin_set_fun(port,bank,b_gpio,fun);
 230 }
 231 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
 232 {
 233     return pin_get_funset(port,bank,b_gpio);
 234 }
 235
 236 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
 237 {
 238         pin_set_pull(port,bank,b_gpio,fun);
 239 }
 240 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
 241 {
 242     return pin_get_pullset(port,bank,b_gpio);
 243 }
 244
 245 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
 246 {
 247     gpio_set_in_output(port,bank,b_gpio,type);
 248 }
 249
 250 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
 251 {
 252     return gpio_get_in_outputset(port,bank,b_gpio);
 253 }
 254
 255 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
 256 {
 257
 258     gpio_set_output_level(port,bank,b_gpio,level);
 259
 260 }
 261
 262 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
 263 {
 264     return gpio_get_output_levelset(port,bank,b_gpio);
 265 }
 266
 267 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
 268 {
 269     return gpio_get_input_level(port,bank,b_gpio);
 270 }
 271 //ddr
 272 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
 273 {
 274         pin_set_fun(port,bank,b_gpio,fun);
 275 }
 276 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
 277 {
 278     return pin_get_funset(port,bank,b_gpio);
 279 }
 280
 281 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
 282 {
 283         pin_set_pull(port,bank,b_gpio,fun);
 284 }
 285 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
 286 {
 287     return pin_get_pullset(port,bank,b_gpio);
 288 }
 289
 290 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
 291 {
 292     gpio_set_in_output(port,bank,b_gpio,type);
 293 }
 294
 295 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
 296 {
 297     return gpio_get_in_outputset(port,bank,b_gpio);
 298 }
 299
 300 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
 301 {
 302     gpio_set_output_level(port,bank,b_gpio,level);
 303 }
 304
 305 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
 306 {
 307     return gpio_get_output_levelset(port,bank,b_gpio);
 308 }
 309
 310 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
 311 {
 312     return gpio_get_input_level(port,bank,b_gpio);
 313 }
 314
 315
 316
 317 static  void __sramfunc rkpm_pin_gpio_config_sram(u32 pin_gpio_bits,u32 *save_bits)
 318 {
 319
 320     u32 pins;
 321     u8 port,bank,b_gpio,fun,in_out, level, pull;
 322
 323     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
 324     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
 325     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
 326     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
 327
 328     port=RKPM_PINBITS_PORT(pins);
 329     bank=RKPM_PINBITS_BANK(pins);
 330     b_gpio=RKPM_PINBITS_BGPIO(pins);
 331     fun=RKPM_PINBITS_FUN(pins);
 332
 333     //save pins info
 334     if(save_bits)
 335     {
 336         pins=RKPM_PINBITS_SET_FUN(pins,sram_pin_get_funset(port,bank,b_gpio));
 337        *save_bits=RKPM_PINGPIO_BITS(pins,sram_pin_get_pullset(port,bank,b_gpio),sram_gpio_get_in_outputset(port,bank,b_gpio),
 338                                                                                         sram_gpio_get_output_levelset(port,bank,b_gpio));
 339     }
 340     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
 341    {
 342         if(level==RKPM_GPIO_OUT_L)
 343             pull=RKPM_GPIO_PULL_DN;
 344         else
 345             pull=RKPM_GPIO_PULL_UP;
 346
 347         sram_gpio_set_output_level(port,bank,b_gpio,level);
 348     }
 349
 350     sram_pin_set_pull(port,bank,b_gpio,pull);
 351     sram_pin_set_fun(port,bank,b_gpio,fun);
 352
 353     if(!fun)
 354     {
 355         sram_gpio_set_in_output(port,bank,b_gpio,in_out);
 356     }
 357
 358 }
 359
 360 static inline void rkpm_pin_gpio_config_ddr(u32 pin_gpio_bits,u32 *save_bits)
 361 {
 362
 363     u32 pins;
 364     u8 port,bank,b_gpio,fun,in_out, level, pull;
 365
 366     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
 367     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
 368     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
 369     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
 370
 371     port=RKPM_PINBITS_PORT(pins);
 372     bank=RKPM_PINBITS_BANK(pins);
 373     b_gpio=RKPM_PINBITS_BGPIO(pins);
 374     fun=RKPM_PINBITS_FUN(pins);
 375
 376     //save pins info
 377     if(save_bits)
 378     {
 379         pins=RKPM_PINBITS_SET_FUN(pins,ddr_pin_get_funset(port,bank,b_gpio));
 380        *save_bits=RKPM_PINGPIO_BITS(pins,ddr_pin_get_pullset(port,bank,b_gpio),ddr_gpio_get_in_outputset(port,bank,b_gpio),
 381                                                                                         ddr_gpio_get_output_levelset(port,bank,b_gpio));
 382     }
 383     if(!fun&&(in_out==RKPM_GPIO_OUTPUT))
 384    {
 385         if(level==RKPM_GPIO_OUT_L)
 386             pull=RKPM_GPIO_PULL_DN;
 387         else
 388             pull=RKPM_GPIO_PULL_UP;
 389
 390         ddr_gpio_set_output_level(port,bank,b_gpio,level);
 391     }
 392
 393     ddr_pin_set_pull(port,bank,b_gpio,pull);
 394     ddr_pin_set_fun(port,bank,b_gpio,fun);
 395
 396     if(!fun)
 397     {
 398         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
 399     }
 400
 401 }
 402
 403
 404 #define GPIO_DTS_NUM 10
 405
 406 static  u32 gpio_dts_save[GPIO_DTS_NUM];
 407 static  u32 gpio_dts[GPIO_DTS_NUM];
 408
 409 #define PMICGPIO_DTS_NUM 3
 410
 411
 412 u32 DEFINE_PIE_DATA(pmicgpio_dts[PMICGPIO_DTS_NUM]);
 413 static u32 *p_pmicgpio_dts;
 414 static __sramdata u32 pmicgpio_dts_save[PMICGPIO_DTS_NUM];
 415
 416 static void __sramfunc pmic_gpio_suspend(void)
 417 {
 418        int i;
 419        for(i=0;;i++)
 420        {
 421             if(DATA(pmicgpio_dts[i]))
 422                 rkpm_pin_gpio_config_sram(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
 423             else
 424             {
 425                     pmicgpio_dts_save[i]=0;
 426                     break;
 427              }
 428        }
 429     #if 0
 430          for(i=0;i<6;i++)
 431         {
 432             rkpm_sram_reg_dump(RK_GPIO_VIRT(i),0,0x4);
 433         }
 434         //
 435         rkpm_sram_reg_dump(RK_GRF_VIRT,0xc,0x84);
 436         rkpm_sram_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
 437         rkpm_sram_reg_dump(RK_PMU_VIRT,0x64,0x6c);
 438         rkpm_sram_reg_dump(RK_PMU_VIRT,0x84,0x9c);
 439     #endif
 440
 441 }
 442
 443 static void  __sramfunc pmic_gpio_resume(void)
 444 {
 445        int i;
 446        for(i=0;;i++)
 447        {
 448             if(pmicgpio_dts_save[i])
 449                 rkpm_pin_gpio_config_sram(pmicgpio_dts_save[i],NULL);
 450        }
 451
 452 }
 453
 454 void PIE_FUNC(pmic_suspend)(void)
 455 {
 456     pmic_gpio_suspend();
 457
 458 }
 459
 460 void PIE_FUNC(pmic_resume)(void)
 461 {
 462     pmic_gpio_resume();
 463 }
 464
 465
 466 static void  rkpm_gpio_suspend(void)
 467 {
 468        int i;
 469        for(i=0;;i++)
 470        {
 471             if(DATA(pmicgpio_dts[i]))
 472                 rkpm_pin_gpio_config_ddr(DATA(pmicgpio_dts[i]),& pmicgpio_dts_save[i]);
 473             else
 474             {
 475                     pmicgpio_dts_save[i]=0;
 476                     break;
 477              }
 478        }
 479     #if 0
 480          for(i=0;i<6;i++)
 481         {
 482             rkpm_ddr_reg_dump(RK_GPIO_VIRT(i),0,0x4);
 483         }
 484         //
 485         rkpm_ddr_reg_dump(RK_GRF_VIRT,0xc,0x84);
 486         rkpm_ddr_reg_dump(RK_GRF_VIRT,0x14c,0x1b4);
 487         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x64,0x6c);
 488         rkpm_ddr_reg_dump(RK_PMU_VIRT,0x84,0x9c);
 489     #endif
 490
 491 }
 492
 493 static void  rkpm_gpio_resume(void)
 494 {
 495        int i;
 496        for(i=0;;i++)
 497        {
 498             if(pmicgpio_dts_save[i])
 499                 rkpm_pin_gpio_config_ddr(pmicgpio_dts_save[i],NULL);
 500        }
 501
 502 }
 503
 504
 505
 506
 507
 508 static void gpio_get_dts_info(struct device_node *parent)
 509 {
 510         int i;
 511
 512         for(i=0;i<PMICGPIO_DTS_NUM;i++)
 513             p_pmicgpio_dts[i]=0;
 514
 515         for(i=0;i<GPIO_DTS_NUM;i++)
 516             gpio_dts[i]=0;
 517
 518
 519         p_pmicgpio_dts= kern_to_pie(rockchip_pie_chunk, &DATA(pmicgpio_dts[0]));
 520
 521        if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",p_pmicgpio_dts,PMICGPIO_DTS_NUM))
 522        {
 523                 p_pmicgpio_dts[0]=0;
 524                PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
 525        }
 526
 527        for(i=0;i<PMICGPIO_DTS_NUM;i++)
 528             printk("%s:pmic gpio(%x)\n",__FUNCTION__,p_pmicgpio_dts[i]);
 529
 530         if(of_property_read_u32_array(parent,"rockchip,pm-gpios",gpio_dts,GPIO_DTS_NUM))
 531         {
 532                  gpio_dts[0]=0;
 533                 PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
 534         }
 535         for(i=0;i<GPIO_DTS_NUM;i++)
 536          printk("%s:pmic gpio(%x)\n",__FUNCTION__,gpio_dts[i]);
 537
 538     rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
 539     rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_suspend)),
 540                   fn_to_pie(rockchip_pie_chunk, &FUNC(pmic_resume)));
 541
 542 }
 543
 544
 545
 546
 547
 548
 549
 550 /*******************************clk gating config*******************************************/
 551 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
 552 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
 553
 554
 555 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
 556 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
 557
 558
 559 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
 560 static u32 *p_rkpm_clkgt_last_set;
 561
 562 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
 563
 564 void PIE_FUNC(gtclks_sram_suspend)(void)
 565 {
 566     int i;
 567    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
 568    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
 569
 570     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
 571     {
 572         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
 573         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
 574         #if 0
 575         rkpm_sram_printch('\n');
 576         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
 577         rkpm_sram_printch('-');
 578         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
 579         rkpm_sram_printch('-');
 580         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
 581         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
 582         rkpm_sram_printch('\n');
 583         #endif
 584     }
 585
 586         //RK3288_CRU_UNGATING_OPS(u_clk_id);
 587         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
 588
 589 }
 590
 591 void PIE_FUNC(gtclks_sram_resume)(void)
 592 {
 593     int i;
 594     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
 595     {
 596         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
 597     }
 598 }
 599
 600 static void gtclks_suspend(void)
 601 {
 602     int i;
 603
 604     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
 605     {
 606
 607         clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
 608         //if(i!=4||i!=0)
 609         CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
 610        #if 0
 611         rkpm_ddr_printch('\n');
 612         rkpm_ddr_printhex(clk_ungt_save[i]);
 613         rkpm_ddr_printch('-');
 614         rkpm_ddr_printhex(clk_ungt_msk[i]);
 615         rkpm_ddr_printch('-');
 616         rkpm_ddr_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i))) ;
 617         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
 618             rkpm_ddr_printch('\n');
 619         #endif
 620     }
 621
 622 }
 623
 624 static void gtclks_resume(void)
 625 {
 626     int i;
 627      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
 628     {
 629        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
 630      }
 631
 632 }
 633 /********************************pll power down***************************************/
 634
 635 enum rk_plls_id {
 636         APLL_ID = 0,
 637         DPLL_ID,
 638         CPLL_ID,
 639         GPLL_ID,
 640         NPLL_ID,
 641         END_PLL_ID,
 642 };
 643
 644 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
 645 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
 646 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
 647
 648
 649 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
 650 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
 651
 652 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
 653 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
 654 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
 655
 656 static void pm_pll_wait_lock(u32 pll_idx)
 657 {
 658         u32 delay = 600000U;
 659         u32 mode;
 660        mode=cru_readl(RK3288_CRU_MODE_CON);
 661         dsb();
 662         dsb();
 663         dsb();
 664         dsb();
 665         dsb();
 666         dsb();
 667         while (delay > 0) {
 668                 if (cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31))
 669                         break;
 670                 delay--;
 671         }
 672         if (delay == 0) {
 673                 rkpm_ddr_printascii("unlock-pll:");
 674                 rkpm_ddr_printhex(pll_idx);
 675                 rkpm_ddr_printch('\n');
 676         }
 677     cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
 678 }
 679
 680 void pll_udelay(u32 udelay)
 681 {
 682     u32 mode;
 683     mode=cru_readl(RK3288_CRU_MODE_CON);
 684     // delay in 24m
 685     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
 686
 687     rkpm_udelay(udelay*5);
 688
 689     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
 690 }
 691
 692 static u32 plls_con3_save[END_PLL_ID];
 693 static u32 cru_mode_con;
 694
 695 static inline void plls_suspend(u32 pll_id)
 696 {
 697     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
 698     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
 699
 700 }
 701 static inline void plls_resume(u32 pll_id)
 702 {
 703         u32 pllcon0, pllcon1, pllcon2;
 704
 705         if(plls_con3_save[pll_id]||RK3288_PLL_PWR_DN_MSK)
 706             return ;
 707         //enter slowmode
 708         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
 709
 710         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
 711         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
 712
 713         pllcon0 = cru_readl(RK3288_PLL_CONS((pll_id),0));
 714         pllcon1 = cru_readl(RK3288_PLL_CONS((pll_id),1));
 715         pllcon2 = cru_readl(RK3288_PLL_CONS((pll_id),2));
 716
 717         //enter rest
 718         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
 719         cru_writel(pllcon0, RK3288_PLL_CONS(pll_id,0));
 720         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
 721         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
 722
 723         pll_udelay(5);
 724         //udelay(5); //timer7 delay
 725
 726         //return form rest
 727         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
 728
 729         //wating lock state
 730         pll_udelay(168);
 731         pm_pll_wait_lock(pll_id);
 732
 733         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
 734 }
 735
 736 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel36, clk_sel37;
 737
 738 static void pm_plls_suspend(void)
 739 {
 740     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
 741     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
 742     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
 743     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
 744     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
 745     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
 746
 747     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
 748
 749
 750     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
 751     plls_suspend(NPLL_ID);
 752
 753
 754 // cpll
 755     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
 756 // gpll
 757     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
 758
 759     // set 1,pdbus pll is gpll
 760     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1));
 761
 762     // pd_bus clk ,aclk ,hclk ,pclk, pd bus pll sel
 763     cru_writel(CRU_W_MSK_SETBITS(1,0,0x7)|CRU_W_MSK_SETBITS(1,3,0x1f)|CRU_W_MSK_SETBITS(1,8,0x3)|CRU_W_MSK_SETBITS(1,12,0x3)
 764                      , RK3288_CRU_CLKSELS_CON(1));
 765     //crypto for pd_bus
 766     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
 767
 768     // peri aclk hclk pclk
 769     cru_writel(CRU_W_MSK_SETBITS(1,0,0x1f)|CRU_W_MSK_SETBITS(1,8,0x3)
 770                           |CRU_W_MSK_SETBITS(2,12,0x7), RK3288_CRU_CLKSELS_CON(10));
 771
 772
 773     plls_suspend(CPLL_ID);
 774     plls_suspend(GPLL_ID);
 775
 776 //apll
 777    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
 778      // core_m0 core_mp a12_core
 779     cru_writel(CRU_W_MSK_SETBITS(1,0,0xf)|CRU_W_MSK_SETBITS(3,4,0xf)
 780                       |CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(0));
 781     // core0 core1 core2 core3
 782     cru_writel(CRU_W_MSK_SETBITS(0,0,0x7)|CRU_W_MSK_SETBITS(0,4,0x7)
 783                       |CRU_W_MSK_SETBITS(0,8,0x7)|CRU_W_MSK_SETBITS(0,12,0x7)
 784                       , RK3288_CRU_CLKSELS_CON(36));
 785     // l2ram atclk pclk
 786     cru_writel((CRU_W_MSK_SETBITS(3,0,0x7)|CRU_W_MSK_SETBITS(0xf,4,0x1f)
 787                                 |CRU_W_MSK_SETBITS(0xf,9,0x1f)), RK3288_CRU_CLKSELS_CON(37));
 788     plls_suspend(APLL_ID);
 789
 790 }
 791
 792 static void pm_plls_resume(void)
 793 {
 794         plls_resume(APLL_ID);
 795         // core_m0 core_mp a12_core
 796         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
 797         // core0 core1 core2 core3
 798         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
 799                         , RK3288_CRU_CLKSELS_CON(36));
 800         // l2ram atclk pclk
 801         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
 802         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
 803
 804         plls_resume(GPLL_ID);
 805         plls_resume(CPLL_ID);
 806         // peri aclk hclk pclk
 807         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
 808                                                                             , RK3288_CRU_CLKSELS_CON(10));
 809         // pd_bus aclk hclk pclk
 810         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
 811                     , RK3288_CRU_CLKSELS_CON(1));
 812         // crypto
 813         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
 814
 815         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
 816
 817         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
 818         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
 819
 820         plls_resume(NPLL_ID);
 821         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
 822
 823 }
 824
 825 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
 826
 827 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
 828 {
 829
 830     int div;
 831     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
 832     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
 833     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
 834
 835
 836     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
 837     {
 838         div=3;
 839         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
 840         cru_writel(0
 841                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
 842                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
 843                             , RK3288_CRU_MODE_CON);
 844     }
 845     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
 846     {
 847         div=31;
 848     }
 849
 850     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
 851     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
 852     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
 853
 854 }
 855
 856 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
 857 {
 858
 859     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
 860     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
 861     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
 862     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
 863                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
 864                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
 865                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
 866
 867 }
 868
 869
 870 static void clks_gating_suspend_init(void)
 871 {
 872     // get clk gating info
 873     p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
 874
 875     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
 876         ==RK3188_CRU_CLKGATES_CON(0))
 877     {
 878         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
 879         rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
 880                         fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
 881
 882         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
 883
 884     }
 885     rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
 886                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
 887 }
 888
 889 /***************************prepare and finish reg_pread***********************************/
 890
 891
 892
 893 #define GIC_DIST_PENDING_SET            0x200
 894 #define DUMP_GPIO_INT_STATUS(ID) \
 895 do { \
 896         if (irq_gpio & (1 << ID)) \
 897                 printk("wakeup gpio" #ID ": %08x\n", readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INT_STATUS)); \
 898 } while (0)
 899 static noinline void rk30_pm_dump_irq(void)
 900 {
 901         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 8) >> 22) & 0x7F;
 902         printk("wakeup irq: %08x %08x %08x %08x\n",
 903                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 4),
 904                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 8),
 905                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12),
 906                 readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 16));
 907         DUMP_GPIO_INT_STATUS(0);
 908         DUMP_GPIO_INT_STATUS(1);
 909         DUMP_GPIO_INT_STATUS(2);
 910         DUMP_GPIO_INT_STATUS(3);
 911         DUMP_GPIO_INT_STATUS(4);
 912         DUMP_GPIO_INT_STATUS(5);
 913         DUMP_GPIO_INT_STATUS(6);
 914         DUMP_GPIO_INT_STATUS(7);
 915         DUMP_GPIO_INT_STATUS(8);
 916
 917 }
 918
 919 #define DUMP_GPIO_INTEN(ID) \
 920 do { \
 921         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
 922         if (en) { \
 923                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
 924                 rkpm_ddr_printhex(en); \
 925                 rkpm_ddr_printch('\n'); \
 926                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
 927         } \
 928 } while (0)
 929
 930 //dump while irq is enable
 931 static noinline void rk30_pm_dump_inten(void)
 932 {
 933         DUMP_GPIO_INTEN(0);
 934         DUMP_GPIO_INTEN(1);
 935         DUMP_GPIO_INTEN(2);
 936         DUMP_GPIO_INTEN(3);
 937         DUMP_GPIO_INTEN(4);
 938         DUMP_GPIO_INTEN(5);
 939         DUMP_GPIO_INTEN(6);
 940         DUMP_GPIO_INTEN(7);
 941         DUMP_GPIO_INTEN(8);
 942 }
 943
 944 static  void rkpm_prepare(void)
 945 {
 946         #if 0
 947         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
 948
 949        // rkpm_ddr_printhex(temp);
 950         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
 951         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
 952        // rkpm_ddr_printhex(temp);
 953         #endif
 954         // dump GPIO INTEN for debug
 955         //rk30_pm_dump_inten();
 956 }
 957
 958 static void rkpm_finish(void)
 959 {
 960         //rk30_pm_dump_irq();
 961 }
 962
 963
 964 static  void interface_ctr_reg_pread(void)
 965 {
 966         //u32 addr;
 967         flush_cache_all();
 968         outer_flush_all();
 969         local_flush_tlb_all();
 970         #if 0  // do it in ddr suspend
 971         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
 972                 readl_relaxed(addr);
 973         #endif
 974         readl_relaxed(RK_PMU_VIRT);
 975         readl_relaxed(RK_GRF_VIRT);
 976         readl_relaxed(RK_DDR_VIRT);
 977         readl_relaxed(RK_GPIO_VIRT(0));
 978         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
 979         //readl_relaxed(RK_GPIO_VIRT(3));
 980 }
 981
 982 static void __init  rk3288_suspend_init(void)
 983 {
 984     struct device_node *parent;
 985     u32 pm_ctrbits;
 986
 987     PM_LOG("%s enter\n",__FUNCTION__);
 988
 989     parent = of_find_node_by_name(NULL, "rockchip_suspend");
 990
 991     if (IS_ERR_OR_NULL(parent)) {
 992                 PM_ERR("%s dev node err\n", __func__);
 993                 return;
 994         }
 995
 996
 997     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
 998     {
 999             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1000             return ;
1001     }
1002     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
1003 #if 0
1004     if(of_property_read_u32_array(parent,"rockchip,pmic-gpios",gpios_data,ARRAY_SIZE(gpios_data)))
1005     {
1006             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
1007             return ;
1008     }
1009 #endif
1010     rkpm_set_ctrbits(pm_ctrbits);
1011
1012     clks_gating_suspend_init();
1013
1014    rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
1015
1016     //rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
1017    // rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
1018     rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
1019     rkpm_set_ops_printch(ddr_printch);
1020 }