arch/arm/mach-rockchip/pm-rk3288.c

   1
   2 #include <linux/kernel.h>
   3 #include <linux/init.h>
   4 #include <asm/cacheflush.h>
   5 #include <asm/tlbflush.h>
   6 #include <asm/hardware/cache-l2x0.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/wakeup_reason.h>
  10 #include <linux/pm.h>
  11 #include <linux/suspend.h>
  12 #include <linux/of.h>
  13 #include <asm/io.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16
  17 #include <linux/rockchip/cpu.h>
  18 //#include <linux/rockchip/cru.h>
  19 #include <linux/rockchip/grf.h>
  20 #include <linux/rockchip/iomap.h>
  21 #include "pm.h"
  22 #include <linux/irqchip/arm-gic.h>
  23
  24 #define CPU 3288
  25 //#include "sram.h"
  26 #include "pm-pie.c"
  27
  28 __weak void rk_usb_power_down(void);
  29 __weak void rk_usb_power_up(void);
  30
  31 //static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun);
  32 //static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type);
  33 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
  34
  35
  36 /*************************cru define********************************************/
  37
  38
  39 #define RK3288_CRU_UNGATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(0,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  40 #define RK3288_CRU_GATING_OPS(id) cru_writel(CRU_W_MSK_SETBITS(1,(id)%16,0x1),RK3288_CRU_GATEID_CONS((id)))
  41
  42 enum rk_plls_id {
  43         APLL_ID = 0,
  44         DPLL_ID,
  45         CPLL_ID,
  46         GPLL_ID,
  47         NPLL_ID,
  48         END_PLL_ID,
  49 };
  50
  51 #define RK3288_PLL_PWR_DN_MSK (0x1<<1)
  52 #define RK3288_PLL_PWR_DN CRU_W_MSK_SETBITS(1,1,0x1)
  53 #define RK3288_PLL_PWR_ON CRU_W_MSK_SETBITS(0,1,0x1)
  54
  55
  56 #define RK3288_PLL_RESET                CRU_W_MSK_SETBITS(1,5,0x1)
  57 #define RK3288_PLL_RESET_RESUME CRU_W_MSK_SETBITS(0,5,0x1)
  58
  59 #define RK3288_PLL_BYPASS_MSK (0x1<<0)
  60 #define RK3288_PLL_BYPASS CRU_W_MSK_SETBITS(1,0,0x1)
  61 #define RK3288_PLL_NO_BYPASS CRU_W_MSK_SETBITS(0,0,0x1)
  62
  63
  64 /*******************************gpio define **********************************************/
  65
  66 /* GPIO control registers */
  67 #define GPIO_SWPORT_DR          0x00
  68 #define GPIO_SWPORT_DDR         0x04
  69 #define GPIO_INTEN                      0x30
  70 #define GPIO_INTMASK            0x34
  71 #define GPIO_INTTYPE_LEVEL      0x38
  72 #define GPIO_INT_POLARITY       0x3c
  73 #define GPIO_INT_STATUS         0x40
  74 #define GPIO_INT_RAWSTATUS      0x44
  75 #define GPIO_DEBOUNCE           0x48
  76 #define GPIO_PORTS_EOI          0x4c
  77 #define GPIO_EXT_PORT           0x50
  78 #define GPIO_LS_SYNC            0x60
  79
  80 /***********************************sleep func*********************************************/
  81
  82 #define RKPM_BOOTRAM_PHYS (RK3288_BOOTRAM_PHYS)
  83 #define RKPM_BOOTRAM_BASE (RK_BOOTRAM_VIRT)
  84 #define RKPM_BOOTRAM_SIZE (RK3288_BOOTRAM_SIZE)
  85
  86 // sys resume code in boot ram
  87 #define  RKPM_BOOT_CODE_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_CODE_OFFSET)
  88 #define  RKPM_BOOT_CODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_CODE_OFFSET)
  89
  90
  91 // sys resume data in boot ram
  92 #define  RKPM_BOOT_DATA_PHY  (RKPM_BOOTRAM_PHYS+RKPM_BOOT_DATA_OFFSET)
  93 #define  RKPM_BOOT_DATA_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DATA_OFFSET)
  94
  95 // ddr resume data in boot ram
  96 #define  RKPM_BOOT_DDRCODE_PHY   (RKPM_BOOTRAM_PHYS + RKPM_BOOT_DDRCODE_OFFSET)
  97 #define  RKPM_BOOT_DDRCODE_BASE  (RKPM_BOOTRAM_BASE+RKPM_BOOT_DDRCODE_OFFSET)
  98
  99 #define RKPM_BOOT_CPUSP_PHY (RKPM_BOOTRAM_PHYS+((RKPM_BOOTRAM_SIZE-1)&~0x7))
 100
 101 // the value is used to control cpu resume flow
 102 static u32 sleep_resume_data[RKPM_BOOTDATA_ARR_SIZE];
 103 static char *resume_data_base=(char *)( RKPM_BOOT_DATA_BASE);
 104 static char *resume_data_phy=  (char *)( RKPM_BOOT_DATA_PHY);
 105
 106
 107
 108 #define BOOT_RAM_SIZE   (4*1024)
 109 #define INT_RAM_SIZE            (64*1024)
 110
 111 static char boot_ram_data[BOOT_RAM_SIZE+4*10];
 112 static char int_ram_data[INT_RAM_SIZE];
 113
 114 char * ddr_get_resume_code_info(u32 *size);
 115 char * ddr_get_resume_data_info(u32 *size);
 116
 117 /**
 118 ddr code and data
 119
 120 *** code start
 121 ---data offset--
 122 ---code----
 123 ---data----
 124 */
 125 static void sram_data_for_sleep(char *boot_save, char *int_save,u32 flag)
 126 {
 127
 128         char *addr_base,*addr_phy,*data_src,*data_dst;
 129         u32 sr_size,data_size;
 130
 131         addr_base=(char *)RKPM_BOOTRAM_BASE;
 132         addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 133         sr_size=RKPM_BOOTRAM_SIZE;
 134
 135         // save boot sram
 136          if(boot_save)
 137                  memcpy(boot_save,addr_base, sr_size);
 138
 139         // move resume code and date to boot sram
 140         // move sys code
 141         data_dst=(char *)RKPM_BOOT_CODE_BASE;
 142         data_src=(char *)rkpm_slp_cpu_resume;
 143         data_size=RKPM_BOOT_CODE_SIZE;
 144         memcpy((char *)data_dst,(char *)data_src, data_size);
 145
 146         // move sys data
 147         data_dst=(char *)resume_data_base;
 148         data_src=(char *)sleep_resume_data;
 149         data_size=sizeof(sleep_resume_data);
 150         memcpy((char *)data_dst,(char *)data_src, data_size);
 151
 152         if(flag)
 153         {
 154                 /*************************ddr code cpy*************************************/
 155                 // ddr code
 156                 data_dst=(char *)(char *)RKPM_BOOT_DDRCODE_BASE;
 157                 data_src=(char *)ddr_get_resume_code_info(&data_size);
 158
 159                 data_size=RKPM_ALIGN(data_size,4);
 160
 161                 memcpy((char *)data_dst,(char *)data_src, data_size);
 162
 163                 // ddr data
 164                 data_dst=(char *)(data_dst+data_size);
 165
 166                 data_src=(char *)ddr_get_resume_data_info(&data_size);
 167                 data_size=RKPM_ALIGN(data_size,4);
 168                 memcpy((char *)data_dst,(char *)data_src, data_size);
 169
 170                 /*************************ddr code cpy  end*************************************/
 171                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 172                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 173                 /*************************int mem bak*************************************/
 174                 // int mem
 175                 addr_base=(char *)rockchip_sram_virt;
 176                 addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 177                 sr_size=rockchip_sram_size;
 178                 //  rkpm_ddr_printascii("piephy\n");
 179                 //rkpm_ddr_printhex(addr_phy);
 180                 //mmap
 181                 if(int_save)
 182                     memcpy(int_save,addr_base, sr_size);
 183
 184                 flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 185                 outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)(addr_phy)+sr_size);
 186         }
 187
 188  }
 189
 190 static void sram_data_resume(char *boot_save, char *int_save,u32 flag)
 191 {
 192
 193     char *addr_base,*addr_phy;
 194     u32 sr_size;
 195
 196     addr_base=(char *)RKPM_BOOTRAM_BASE;
 197     addr_phy=(char *)RKPM_BOOTRAM_PHYS;
 198     sr_size=RKPM_BOOTRAM_SIZE;
 199     // save boot sram
 200     if(boot_save)
 201         memcpy(addr_base,boot_save, sr_size);
 202
 203     flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 204     outer_clean_range((phys_addr_t) addr_phy, (phys_addr_t)addr_phy+sr_size);
 205
 206     if(flag)
 207     {
 208         // int mem
 209         addr_base=(char *)rockchip_sram_virt;
 210         addr_phy=(char *)pie_to_phys(rockchip_pie_chunk,(unsigned long )rockchip_sram_virt);
 211         sr_size=rockchip_sram_size;
 212
 213         if(int_save)
 214         memcpy(addr_base, int_save,sr_size);
 215
 216         flush_icache_range((unsigned long)addr_base, (unsigned long)addr_base + sr_size);
 217         outer_clean_range((phys_addr_t) addr_phy,(unsigned long)addr_phy+sr_size);
 218      }
 219 }
 220
 221 /**************************************gic save and resume**************************/
 222 #define  RK_GICD_BASE (RK_GIC_VIRT)
 223 #define RK_GICC_BASE (RK_GIC_VIRT+RK3288_GIC_DIST_SIZE)
 224
 225 #define PM_IRQN_START 32
 226 #define PM_IRQN_END     107//107
 227 #if 0 //funciton is ok ,but not used
 228 static void pm_gic_enable(u32 irqs)
 229 {
 230
 231         int irqstart=0;
 232         u32 bit_off;
 233         void __iomem *reg_off;
 234         unsigned int gic_irqs;
 235
 236         gic_irqs = PM_IRQN_END;
 237         irqstart=PM_IRQN_START;//PM_IRQN_START;
 238
 239         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_SET+RK_GICD_BASE;
 240         bit_off=irqs%32;
 241         writel_relaxed(readl_relaxed(reg_off)|(1<<bit_off),reg_off);
 242
 243         dsb();
 244 }
 245
 246 static void rkpm_gic_disable(u32 irqs)
 247 {
 248         int irqstart=0;
 249         u32 bit_off;
 250         void __iomem *reg_off;
 251         unsigned int gic_irqs;
 252
 253         gic_irqs = PM_IRQN_END;
 254         irqstart=PM_IRQN_START;//PM_IRQN_START;
 255
 256         reg_off=(irqs/32)*4+GIC_DIST_ENABLE_CLEAR+RK_GICD_BASE;
 257         bit_off=irqs%32;
 258         writel_relaxed(readl_relaxed(reg_off)&~(1<<bit_off),reg_off);
 259         dsb();
 260 }
 261 #endif
 262 #define gic_reg_dump(a,b,c)  {}//reg_dump((a),(b),(c))
 263
 264 static u32 slp_gic_save[260+50];
 265
 266
 267 static void rkpm_gic_dist_save(u32 *context)
 268 {
 269      int i = 0,j,irqstart=0;
 270      unsigned int gic_irqs;
 271
 272      gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 273      gic_irqs = (gic_irqs + 1) * 32;
 274      if (gic_irqs > 1020)
 275      gic_irqs = 1020;
 276      //printk("gic_irqs=%d\n",gic_irqs);
 277      //gic_irqs = PM_IRQN_END;
 278      irqstart=PM_IRQN_START;//PM_IRQN_START;
 279
 280      i = 0;
 281      //level
 282      for (j = irqstart; j < gic_irqs; j += 16)
 283       context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CONFIG + (j * 4) / 16);
 284      gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 285
 286      /*
 287      * Set all global interrupts to this CPU only.
 288      */
 289      for(j = 0; j < gic_irqs; j += 4)
 290          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_TARGET +    (j * 4) / 4);
 291      gic_reg_dump("gic trig",j,RK_GICD_BASE + GIC_DIST_TARGET);
 292
 293      //pri
 294      for (j = 0; j < gic_irqs; j += 4)
 295          context[i++]=readl_relaxed(RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 296      gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 297
 298      //secure
 299      for (j = 0; j < gic_irqs; j += 32)
 300          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4) / 32);
 301      gic_reg_dump("gic secure",j,RK_GICD_BASE + 0x80);
 302
 303      for (j = irqstart; j < gic_irqs; j += 32)
 304          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_PENDING_SET + (j * 4) / 32);
 305      gic_reg_dump("gic PENDING",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 306
 307     #if 0
 308      //disable
 309      for (j = 0; j < gic_irqs; j += 32)
 310          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + (j * 4) / 32);
 311      gic_reg_dump("gic dis",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 312     #endif
 313
 314      //enable
 315      for (j = 0; j < gic_irqs; j += 32)
 316          context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 317      gic_reg_dump("gic en",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 318
 319
 320
 321      gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 322      gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 323
 324      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 325      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 326      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 327
 328     #if 0
 329      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_BINPOINT);
 330      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_PRIMASK);
 331      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_DIST_SOFTINT);
 332      context[i++]=readl_relaxed(RK_GICC_BASE + GIC_CPU_CTRL);
 333      context[i++]=readl_relaxed(RK_GICD_BASE + GIC_DIST_CTRL);
 334     #endif
 335
 336     #if 1
 337     for (j = irqstart; j < gic_irqs; j += 32)
 338     {
 339         writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 340         dsb();
 341     }
 342     writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 343     writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 344
 345     writel_relaxed(0, RK_GICC_BASE + GIC_CPU_CTRL);
 346     writel_relaxed(0, RK_GICD_BASE + GIC_DIST_CTRL);
 347     #endif
 348
 349 }
 350
 351 static void rkpm_gic_dist_resume(u32 *context)
 352 {
 353
 354          int i = 0,j,irqstart=0;
 355          unsigned int gic_irqs;
 356
 357
 358          gic_irqs = readl_relaxed(RK_GICD_BASE + GIC_DIST_CTR) & 0x1f;
 359          gic_irqs = (gic_irqs + 1) * 32;
 360          if (gic_irqs > 1020)
 361                  gic_irqs = 1020;
 362
 363          //gic_irqs = PM_IRQN_END;
 364          irqstart=PM_IRQN_START;//PM_IRQN_START;
 365
 366          writel_relaxed(0,RK_GICC_BASE + GIC_CPU_CTRL);
 367          dsb();
 368          writel_relaxed(0,RK_GICD_BASE + GIC_DIST_CTRL);
 369          dsb();
 370          for (j = irqstart; j < gic_irqs; j += 32)
 371          {
 372                  writel_relaxed(0xffffffff, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 373                  dsb();
 374          }
 375
 376          i = 0;
 377
 378          //trig
 379          for (j = irqstart; j < gic_irqs; j += 16)
 380          {
 381                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CONFIG + j * 4 / 16);
 382                  dsb();
 383          }
 384          gic_reg_dump("gic level",j,RK_GICD_BASE + GIC_DIST_CONFIG);
 385
 386          /*
 387          * Set all global interrupts to this CPU only.
 388          */
 389          for (j = 0; j < gic_irqs; j += 4)
 390          {
 391                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_TARGET +  (j * 4) / 4);
 392                  dsb();
 393          }
 394          gic_reg_dump("gic target",j,RK_GICD_BASE + GIC_DIST_TARGET);
 395
 396          //pri
 397          for (j = 0; j < gic_irqs; j += 4)
 398          {
 399                  writel_relaxed(context[i++],RK_GICD_BASE+ GIC_DIST_PRI + (j * 4) / 4);
 400
 401                  dsb();
 402          }
 403          gic_reg_dump("gic pri",j,RK_GICD_BASE + GIC_DIST_PRI);
 404
 405
 406          //secu
 407          for (j = 0; j < gic_irqs; j += 32)
 408          {
 409                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_IGROUP + (j * 4 )/ 32);
 410                  dsb();
 411          }
 412          gic_reg_dump("gic secu",j,RK_GICD_BASE + 0x80);
 413
 414          //pending
 415          for (j = irqstart; j < gic_irqs; j += 32)
 416          {
 417                  //writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_PENDING_SET + j * 4 / 32);
 418                  i++;
 419                  dsb();
 420          }
 421          gic_reg_dump("gic pending",j,RK_GICD_BASE + GIC_DIST_PENDING_SET);
 422
 423          //disable
 424 #if 0
 425          for (j = 0; j < gic_irqs; j += 32)
 426          {
 427                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 428                  dsb();
 429          }
 430          gic_reg_dump("gic disable",j,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 431
 432 #else
 433         for (j = irqstart; j < gic_irqs; j += 32)
 434             writel_relaxed(0xffffffff,RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR + j * 4 / 32);
 435         writel_relaxed(0xffff0000, RK_GICD_BASE + GIC_DIST_ENABLE_CLEAR);
 436         writel_relaxed(0x0000ffff, RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 437 #endif
 438
 439          //enable
 440          for (j = 0; j < gic_irqs; j += 32)
 441          {
 442                  writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_ENABLE_SET + (j * 4) / 32);
 443
 444                  dsb();
 445          }
 446
 447          gic_reg_dump("gic enable",j,RK_GICD_BASE + GIC_DIST_ENABLE_SET);
 448
 449          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_PRIMASK);
 450          writel_relaxed(context[i++],RK_GICD_BASE + GIC_DIST_CTRL);
 451          writel_relaxed(context[i++],RK_GICC_BASE + GIC_CPU_CTRL);
 452
 453          gic_reg_dump("gicc",0x1c,RK_GICC_BASE);
 454          gic_reg_dump("giccfc",0,RK_GICC_BASE+0xfc);
 455
 456 }
 457
 458 /**************************************regs save and resume**************************/
 459
 460 void slp_regs_save(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset)
 461 {
 462      u32 i;
 463          u32 cnt=(end_offset-st_offset)/4+1;
 464      for(i=0;i<cnt;i++)
 465      {
 466          data[i]=readl_relaxed(base+st_offset+i*4);
 467      }
 468 }
 469
 470 void slp_regs_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 w_msk)
 471 {
 472      u32 i;
 473      u32 cnt=(end_offset-st_offset)/4+1;
 474      for(i=0;i<cnt;i++)
 475      {
 476          reg_writel(data[i]|w_msk,(base+st_offset+i*4));
 477      }
 478 }
 479
 480 void slp_regs_w_msk_resume(u32 *data,void __iomem * base,u32 st_offset,u32 end_offset,u32 *w_msk)
 481 {
 482         u32 i;
 483         u32 cnt=(end_offset-st_offset)/4+1;
 484          for(i=0;i<cnt;i++)
 485          {
 486                  reg_writel(data[i]|w_msk[i],(base+st_offset+i*4));
 487          }
 488 }
 489
 490 /**************************************uarts save and resume**************************/
 491
 492 #define RK3288_UART_NUM (4)
 493
 494 static void __iomem *slp_uart_base[RK3288_UART_NUM]={NULL};
 495 static u32 slp_uart_phy[RK3288_UART_NUM]={(0xff180000),(0xff190000),(0xff690000),(0xff1b0000)};
 496
 497 #define UART_DLL        0       /* Out: Divisor Latch Low */
 498 #define UART_DLM        1       /* Out: Divisor Latch High */
 499
 500 #define UART_IER        1
 501 #define UART_FCR        2
 502
 503 #define UART_LCR        3       /* Out: Line Control Register */
 504 #define UART_MCR        4
 505
 506 #if 0 //
 507 static u32 slp_uart_data[RK3288_UART_NUM][10];
 508 static u32 slp_uart_data_flag[RK3288_UART_NUM];
 509
 510  void slp_uart_save(int ch)
 511  {
 512          int i=0;
 513         void __iomem *b_addr=slp_uart_base[ch];
 514          int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 515          u32 gate_reg;
 516          if(b_addr==NULL || ch>=RK3288_UART_NUM)
 517                 return;
 518
 519         if(ch==2)
 520         {
 521             idx=RK3288_CLKGATE_PCLK_UART2;
 522             b_addr=RK_DEBUG_UART_VIRT;
 523         }
 524
 525
 526         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 527         RK3288_CRU_UNGATING_OPS(idx);
 528          i=0;
 529          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_LCR*4);
 530          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 531
 532          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLL*4);
 533          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_DLM*4);
 534
 535          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 536          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_IER*4);
 537          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_FCR*4);
 538          slp_uart_data[ch][i++]=readl_relaxed(b_addr+UART_MCR*4);
 539
 540         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 541
 542  }
 543
 544  void slp_uart_resume(int ch)
 545  {
 546         int i=0;
 547
 548         u32 temp;
 549         void __iomem *b_addr=slp_uart_base[ch];
 550         int idx=RK3288_CLKGATE_PCLK_UART0+ch;
 551         u32 gate_reg;
 552
 553         //rkpm_ddr_printascii("\nch");
 554      //   rkpm_ddr_printhex(b_addr);
 555
 556         if(b_addr==NULL || ch>=RK3288_UART_NUM)
 557             return;
 558
 559         if(ch==2)
 560             idx=RK3288_CLKGATE_PCLK_UART2;
 561
 562         //rkpm_ddr_printhex(ch);
 563
 564         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 565         RK3288_CRU_UNGATING_OPS(idx);
 566
 567          i=0;
 568          temp=slp_uart_data[ch][i++];
 569          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)|0x80,b_addr+UART_LCR*4);
 570
 571          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLL*4);
 572          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_DLM*4);
 573
 574          writel_relaxed(readl_relaxed(b_addr+UART_LCR*4)&(~0x80),b_addr+UART_LCR*4);
 575
 576          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_IER*4);
 577          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_FCR*4);
 578          writel_relaxed(slp_uart_data[ch][i++],b_addr+UART_MCR*4);
 579
 580          writel_relaxed(temp,b_addr+UART_LCR*4);
 581
 582          cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 583  }
 584 #endif
 585  void slp_uartdbg_resume(void)
 586 {
 587     void __iomem *b_addr=RK_DEBUG_UART_VIRT;
 588     u32 pclk_id=RK3288_CLKGATE_PCLK_UART2,clk_id=(RK3288_CLKGATE_UART0_SRC+2*2);
 589     u32 gate_reg[2];
 590     u32 rfl_reg,lsr_reg;
 591
 592     gate_reg[0]=cru_readl(RK3288_CRU_GATEID_CONS(pclk_id));
 593     gate_reg[1]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id));
 594
 595     RK3288_CRU_UNGATING_OPS(pclk_id);
 596     // 24M is no gating setting
 597     ddr_pin_set_fun(0x7,0xc,0x6,0x0);
 598     ddr_pin_set_fun(0x7,0xc,0x7,0x0);
 599
 600     do{
 601             // out clk sel 24M
 602             cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 603
 604             //uart2 dbg reset
 605             cru_writel(0|CRU_W_MSK_SETBITS(1,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 606             dsb();
 607             dsb();
 608             rkpm_udelay(10);
 609             cru_writel(0|CRU_W_MSK_SETBITS(0,5,0x1), RK3288_CRU_SOFTRSTS_CON(11));
 610
 611         #if 0
 612             //out clk (form pll)  is gating
 613             RK3288_CRU_GATING_OPS(clk_id);
 614             //out clk form pll gating to disable uart clk out
 615             // div 12
 616             cru_writel(CRU_W_MSK_SETBITS(11,0,0x7f), RK3288_CRU_CLKSELS_CON(15));
 617             dsb();
 618             dsb();
 619             dsb();
 620             dsb();
 621             cru_writel(CRU_W_MSK_SETBITS(0,8,0x3) , RK3288_CRU_CLKSELS_CON(15));
 622          #endif
 623
 624
 625             reg_writel(0x83,b_addr+UART_LCR*4);
 626
 627             reg_writel(0xd,b_addr+UART_DLL*4);
 628             reg_writel(0x0,b_addr+UART_DLM*4);
 629
 630             reg_writel(0x3,b_addr+UART_LCR*4);
 631
 632             reg_writel(0x5,b_addr+UART_IER*4);
 633             reg_writel(0xc1,b_addr+UART_FCR*4);
 634
 635             rfl_reg=readl_relaxed(b_addr+0x84);
 636             lsr_reg=readl_relaxed(b_addr+0x14);
 637
 638         }while((rfl_reg&0x1f)||(lsr_reg&0xf));
 639
 640         // out clk sel 24M
 641         cru_writel(CRU_W_MSK_SETBITS(0x2,8,0x3), RK3288_CRU_CLKSELS_CON(15));
 642
 643         ddr_pin_set_fun(0x7,0xc,0x6,0x1);
 644         ddr_pin_set_fun(0x7,0xc,0x7,0x1);
 645         cru_writel(gate_reg[0]|CRU_W_MSK(pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(pclk_id));
 646         cru_writel(gate_reg[1]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
 647 }
 648
 649 /**************************************i2c save and resume**************************/
 650
 651 //#define RK3288_I2C_REG_DUMP
 652 #define RK3288_I2C_NUM (6)
 653 static u32 slp_i2c_phy[RK3288_I2C_NUM]={(0xff650000),(0xff140000),(0xff660000),(0xff150000),(0xff160000),(0xff170000)};
 654 static void __iomem *slp_i2c_base[RK3288_I2C_NUM]={NULL};
 655
 656 static u32 slp_i2c_data[RK3288_I2C_NUM][10];
 657
 658 void slp_i2c_save(int ch)
 659 {
 660
 661         void __iomem *b_addr=slp_i2c_base[ch];
 662         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 663         u32 gate_reg;
 664
 665         if(!b_addr)
 666                 return;
 667
 668         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 669         RK3288_CRU_UNGATING_OPS(idx);
 670
 671         #ifdef RK3288_I2C_REG_DUMP
 672         rkpm_ddr_printascii("i2c save");
 673         rkpm_ddr_printhex(ch);
 674         rkpm_ddr_printch('\n');
 675         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 676         #endif
 677
 678         slp_regs_save(&slp_i2c_data[ch][0],b_addr,0x0,0xc);
 679
 680
 681         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 682
 683 }
 684 void slp_i2c_resume(int ch)
 685 {
 686         void __iomem *b_addr=slp_i2c_base[ch];
 687         int idx= (ch>1) ? (RK3288_CLKGATE_PCLK_I2C2+ch-2):(RK3288_CLKGATE_PCLK_I2C0+ch);
 688         u32 gate_reg;
 689
 690         if(!b_addr)
 691                 return;
 692         gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 693         RK3288_CRU_UNGATING_OPS(idx);
 694
 695         slp_regs_resume(&slp_i2c_data[ch][0],b_addr,0x0,0xc,0x0);
 696
 697         #ifdef RK3288_I2C_REG_DUMP
 698         rkpm_ddr_printascii("i2c resume");
 699         rkpm_ddr_printhex(ch);
 700         rkpm_ddr_printch('\n');
 701         rkpm_ddr_regs_dump(b_addr,0x0,0xc);
 702         #endif
 703
 704         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 705 }
 706
 707 /**************************************gpios save and resume**************************/
 708 #define RK3288_GPIO_CH (9)
 709 #if 0 //fun is ok ,not used
 710
 711 static u32 slp_gpio_data[RK3288_GPIO_CH][10];
 712 static u32 slp_grf_iomux_data[RK3288_GPIO_CH*4];
 713 static u32 slp_grf_io_pull_data[RK3288_GPIO_CH*4];
 714 static void gpio_ddr_dump_reg(int ports)
 715 {
 716     void __iomem *b_addr=RK_GPIO_VIRT(ports);
 717
 718     rkpm_ddr_printascii("gpio-");
 719     rkpm_ddr_printhex(ports);
 720     rkpm_ddr_printhex('\n');
 721
 722     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DR);
 723     rkpm_ddr_reg_offset_dump(b_addr,GPIO_SWPORT_DDR);
 724     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTEN);
 725     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTMASK);
 726     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INTTYPE_LEVEL);
 727     rkpm_ddr_reg_offset_dump(b_addr,GPIO_INT_POLARITY);
 728     rkpm_ddr_reg_offset_dump(b_addr,GPIO_DEBOUNCE);
 729     rkpm_ddr_reg_offset_dump(b_addr,GPIO_LS_SYNC);
 730     rkpm_ddr_printhex('\n');
 731
 732     rkpm_ddr_printascii("iomux\n");
 733     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 734
 735     rkpm_ddr_printascii("iomux\n");
 736     rkpm_ddr_regs_dump(RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 737
 738 }
 739  static void slp_pin_gpio_save(int ports)
 740  {
 741         int i;
 742         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 743         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 744         u32 gate_reg;
 745
 746         if(ports==0||ports>=RK3288_GPIO_CH)
 747                 return;
 748
 749          gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 750          RK3288_CRU_UNGATING_OPS(idx);
 751
 752          //gpio_ddr_dump_reg(ports);
 753          i=0;
 754          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DR);
 755          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_SWPORT_DDR);
 756          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTEN);
 757          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTMASK);
 758          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INTTYPE_LEVEL);
 759          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_INT_POLARITY);
 760          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_DEBOUNCE);
 761          slp_gpio_data[ports][i++]=readl_relaxed(b_addr+GPIO_LS_SYNC);
 762
 763         if(ports>0)
 764         {
 765             slp_regs_save(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4);
 766             slp_regs_save(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4);
 767          }
 768
 769
 770         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 771
 772  }
 773
 774  static void slp_pin_gpio_resume (int ports)
 775  {
 776          int i;
 777         void __iomem *b_addr=RK_GPIO_VIRT(ports);
 778         int idx=RK3288_CLKGATE_PCLK_GPIO1+ports-1;
 779          u32 gate_reg;
 780
 781          if(ports==0||ports>=RK3288_GPIO_CH)
 782                 return;
 783           gate_reg=cru_readl(RK3288_CRU_GATEID_CONS(idx));
 784          RK3288_CRU_UNGATING_OPS(idx);
 785
 786
 787         if(ports>0)
 788         {
 789             slp_regs_resume(&slp_grf_iomux_data[ports*4],RK_GRF_VIRT,0x0+ports*4*4,0x0+ports*4*4+3*4,0xffff0000);
 790             slp_regs_resume(&slp_grf_io_pull_data[ports*4],RK_GRF_VIRT,0x130+ports*4*4,ports*4*4+3*4,0xffff0000);
 791         }
 792
 793         i=0;
 794         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DR);
 795         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_SWPORT_DDR);
 796         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTEN);
 797         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTMASK);
 798         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INTTYPE_LEVEL);
 799         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_INT_POLARITY);
 800         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_DEBOUNCE);
 801         writel_relaxed(slp_gpio_data[ports][i++],b_addr+GPIO_LS_SYNC);
 802
 803         //gpio_ddr_dump_reg(ports);
 804         cru_writel(gate_reg|CRU_W_MSK(idx%16,0x1),RK3288_CRU_GATEID_CONS(idx));
 805
 806  }
 807
 808 #endif
 809  static inline u32 rkpm_l2_config(void)
 810  {
 811      u32 l2ctlr;
 812      asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
 813       return l2ctlr;
 814  }
 815
 816 static inline u32 rkpm_armerrata_818325(void)
 817 {
 818     u32 armerrata;
 819     asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (armerrata));
 820     return armerrata;
 821 }
 822
 823
 824
 825 /**************************************sleep func**************************/
 826
 827 void ddr_reg_save(uint32_t *pArg);
 828 void fiq_glue_resume(void);
 829 void rk30_cpu_resume(void);
 830 void rk30_l2_cache_init_pm(void);
 831 //static void rk319x_pm_set_power_domain(enum pmu_power_domain pd, bool state);
 832 void ddr_cfg_to_lp_mode(void);
 833 void l2x0_inv_all_pm(void);
 834 void rk30_cpu_while_tst(void);
 835
 836 #if 0
 837 static u32 slp_grf_soc_con_data[5];
 838 static u32 slp_grf_soc_con_w_msk[5]={0x70000,0x40ff0000,0xffff0000,0xffff0000,0xffff0000};
 839
 840 static u32 slp_grf_cpu_con_data[5];
 841 static u32 slp_grf_cpu_con_w_msk[5]={0xefff0000,0xffff0000,0xcfff0000,0xffff0000,0x7fff0000};
 842
 843 static u32 slp_grf_uoc0_con_data[4];
 844 static u32 slp_grf_uoc0_con_w_msk[4]={0xffff0000,0xffff0000,0x7dff0000,0x7fff0000};// uoc0_con4 bit 15??
 845
 846 static u32 slp_grf_uoc1_con_data[2];
 847 static u32 slp_grf_uoc1_con_w_msk[2]={0x1fdc0000,0x047f0000};
 848
 849 static u32 slp_grf_uoc2_con_data[2];
 850 static u32 slp_grf_uoc2_con_w_msk[2]={0x7fff0000,0x1f0000};
 851
 852 static u32 slp_grf_uoc3_con_data[2];
 853 static u32 slp_grf_uoc3_con_w_msk[2]={0x3ff0000,0x0fff0000};
 854
 855 #endif
 856 //static u32 slp_pmu_pwrmode_con_data[1];
 857
 858
 859 //static u32 slp_nandc_data[8];
 860 //static void __iomem *rk30_nandc_base=NULL;
 861
 862 #define MS_37K (37)
 863 #define US_24M (24)
 864
 865 void inline pm_io_base_map(void)
 866 {
 867         int i;
 868         for(i=0;i<RK3288_I2C_NUM;i++)
 869             slp_i2c_base[i]  = ioremap(slp_i2c_phy[i], 0x1000);
 870
 871         for(i=0;i<RK3288_UART_NUM;i++)
 872             {
 873                 if(i!=CONFIG_RK_DEBUG_UART)
 874                     slp_uart_base[i]  = ioremap(slp_uart_phy[i], 0x1000);
 875                 else
 876                     slp_uart_base[i] = RK_DEBUG_UART_VIRT;
 877             }
 878
 879 }
 880 enum rk3288_pwr_mode_con {
 881
 882         pmu_pwr_mode_en=0,
 883         pmu_clk_core_src_gate_en,
 884         pmu_global_int_disable,
 885         pmu_l2flush_en,
 886
 887         pmu_bus_pd_en,
 888         pmu_a12_0_pd_en,
 889         pmu_scu_en,
 890         pmu_pll_pd_en,
 891
 892         pmu_chip_pd_en, // power off pin enable
 893         pmu_pwroff_comb,
 894         pmu_alive_use_lf,
 895         pmu_pmu_use_lf,
 896
 897         pmu_osc_24m_dis,
 898         pmu_input_clamp_en,
 899         pmu_wakeup_reset_en,
 900         pmu_sref0_enter_en,
 901
 902         pmu_sref1_enter_en,
 903         pmu_ddr0io_ret_en,
 904         pmu_ddr1io_ret_en,
 905         pmu_ddr0_gating_en,
 906
 907         pmu_ddr1_gating_en,
 908         pmu_ddr0io_ret_de_req,
 909         pmu_ddr1io_ret_de_req
 910
 911 };
 912  enum rk3288_pwr_mode_con1 {
 913
 914         pmu_clr_bus=0,
 915         pmu_clr_core,
 916         pmu_clr_cpup,
 917         pmu_clr_alive,
 918
 919         pmu_clr_dma,
 920         pmu_clr_peri,
 921         pmu_clr_gpu,
 922         pmu_clr_video,
 923         pmu_clr_hevc,
 924         pmu_clr_vio
 925
 926 };
 927  static u32 rk3288_powermode=0;
 928 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun);
 929
 930 static u32 sgrf_soc_con0,pmu_wakeup_cfg0,pmu_wakeup_cfg1,pmu_pwr_mode_con0,pmu_pwr_mode_con1;
 931
 932 static u32  rkpm_slp_mode_set(u32 ctrbits)
 933 {
 934     u32 mode_set,mode_set1;
 935
 936     // setting gpio0_a0 arm off pin
 937
 938     sgrf_soc_con0=reg_readl(RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 939
 940     pmu_wakeup_cfg0=pmu_readl(RK3288_PMU_WAKEUP_CFG0);
 941     pmu_wakeup_cfg1=pmu_readl(RK3288_PMU_WAKEUP_CFG1);
 942
 943     pmu_pwr_mode_con0=pmu_readl(RK3288_PMU_PWRMODE_CON);
 944     pmu_pwr_mode_con1=pmu_readl(RK3288_PMU_PWRMODE_CON1);
 945
 946     ddr_pin_set_fun(0x0,0xa,0x0,0x1);
 947
 948
 949
 950     //mode_set1=pmu_pwr_mode_con1;
 951     //mode_set=pmu_pwr_mode_con0;
 952
 953    //pmu_writel(0x1<<3,RK3188_PMU_WAKEUP_CFG1);
 954    pmu_writel(0x1<<0,RK3188_PMU_WAKEUP_CFG1);
 955
 956     // enable boot ram
 957     reg_writel((0x1<<8)|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
 958     dsb();
 959
 960     reg_writel(RKPM_BOOTRAM_PHYS,RK_SGRF_VIRT+RK3288_SGRF_FAST_BOOT_ADDR);
 961     dsb();
 962
 963     mode_set=  BIT(pmu_pwr_mode_en) |BIT(pmu_global_int_disable) | BIT(pmu_l2flush_en);
 964      mode_set1=0;
 965
 966     if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_IDLEAUTO_MD))
 967     {
 968         rkpm_ddr_printascii("-autoidle-");
 969         mode_set|=BIT(pmu_clk_core_src_gate_en);
 970     }
 971     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMDP_LPMD))
 972     {
 973         rkpm_ddr_printascii("-armdp-");
 974         mode_set|=BIT(pmu_a12_0_pd_en);
 975     }
 976     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LPMD))
 977     {
 978         rkpm_ddr_printascii("-armoff-");
 979         mode_set|=BIT(pmu_scu_en)
 980                             //|BIT(pmu_a12_0_pd_en)
 981                             |BIT(pmu_clk_core_src_gate_en) // »½ÐÑºóÒì³£
 982                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
 983                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
 984                             //|BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
 985                             |BIT(pmu_chip_pd_en);
 986         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
 987                                 |BIT(pmu_clr_alive)
 988                                 |BIT(pmu_clr_peri)
 989                                 |BIT(pmu_clr_bus)
 990                                 |BIT(pmu_clr_dma)
 991                                 ;
 992     }
 993     else if(rkpm_chk_val_ctrbits(ctrbits,RKPM_CTR_ARMOFF_LOGDP_LPMD))
 994     {
 995
 996         rkpm_ddr_printascii("-armoff-logdp-");
 997
 998         mode_set|=BIT(pmu_scu_en)|BIT(pmu_bus_pd_en)
 999                             |BIT(pmu_chip_pd_en)
1000                             |BIT(pmu_sref0_enter_en)|BIT(pmu_sref1_enter_en)
1001                             |BIT(pmu_ddr0_gating_en)|BIT(pmu_ddr1_gating_en)
1002                             |BIT(pmu_ddr1io_ret_en)|BIT(pmu_ddr0io_ret_en)
1003                             |BIT(pmu_osc_24m_dis)|BIT(pmu_pmu_use_lf)|BIT(pmu_alive_use_lf)|BIT(pmu_pll_pd_en)
1004                             ;
1005         mode_set1=BIT(pmu_clr_core)|BIT(pmu_clr_cpup)
1006                            |BIT(pmu_clr_alive)
1007                            |BIT(pmu_clr_peri)
1008                            |BIT(pmu_clr_bus)
1009                            |BIT(pmu_clr_dma)
1010                           ;
1011
1012     }
1013     else
1014     {
1015         mode_set=0;
1016         mode_set1=0;
1017     }
1018
1019
1020     if(mode_set&BIT(pmu_osc_24m_dis))
1021     {
1022         rkpm_ddr_printascii("osc_off");
1023         pmu_writel(32*30,RK3288_PMU_OSC_CNT);
1024         pmu_writel(32*30,RK3288_PMU_STABL_CNT);
1025     }
1026     else
1027     {
1028         pmu_writel(24*1000*10,RK3288_PMU_STABL_CNT);
1029
1030        // pmu_writel(24*1000*20,RK3288_PMU_CORE_PWRDWN_CNT);
1031     }
1032
1033     if(mode_set&BIT(pmu_ddr0io_ret_en))
1034     {
1035         rkpm_ddr_printascii("ddrc_off");
1036         ddr_pin_set_fun(0x0,0xa,0x1,0x1);
1037         ddr_pin_set_fun(0x0,0xa,0x2,0x1);
1038         ddr_pin_set_fun(0x0,0xa,0x3,0x1);
1039     }
1040
1041     pmu_writel(mode_set,RK3288_PMU_PWRMODE_CON);
1042     pmu_writel(mode_set1,RK3288_PMU_PWRMODE_CON1);
1043
1044   //  rkpm_ddr_printhex(mode_set);
1045   //  rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRMODE_CON));
1046
1047     return (pmu_readl(RK3288_PMU_PWRMODE_CON));
1048 }
1049
1050 static inline void  rkpm_slp_mode_set_resume(void)
1051 {
1052
1053     pmu_writel(pmu_wakeup_cfg0,RK3288_PMU_WAKEUP_CFG0);
1054     pmu_writel(pmu_wakeup_cfg1,RK3288_PMU_WAKEUP_CFG1);
1055
1056     pmu_writel(pmu_pwr_mode_con0,RK3288_PMU_PWRMODE_CON);
1057     pmu_writel(pmu_pwr_mode_con1,RK3288_PMU_PWRMODE_CON1);
1058     reg_writel(sgrf_soc_con0|(0x1<<(8+16)),RK_SGRF_VIRT+RK3288_SGRF_SOC_CON0);
1059
1060 }
1061
1062 static void sram_code_data_save(u32 pwrmode)
1063 {
1064         char *code_src,*data_src;
1065         u32 code_size,data_size;
1066
1067
1068         //u32 *p;
1069         if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1070         {
1071             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=1;
1072             sleep_resume_data[RKPM_BOOTDATA_L2LTY]=rkpm_l2_config();// in sys resume ,ddr is need resume
1073
1074             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=1;
1075             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325]=rkpm_armerrata_818325();//
1076
1077             sleep_resume_data[RKPM_BOOTDATA_CPUSP]=RKPM_BOOT_CPUSP_PHY;// in sys resume ,ddr is need resume
1078             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=virt_to_phys(cpu_resume);// in sys resume ,ddr is need resume
1079             #if 0
1080             rkpm_ddr_printascii("l2&arm_errata--");
1081             rkpm_ddr_printhex(rkpm_l2_config());
1082             rkpm_ddr_printhex(rkpm_armerrata_818325());
1083             rkpm_ddr_printascii("\n");
1084             #endif
1085         }
1086         else
1087         {
1088             sleep_resume_data[RKPM_BOOTDATA_L2LTY_F]=0;
1089             sleep_resume_data[RKPM_BOOTDATA_ARM_ERRATA_818325_F]=0;
1090             sleep_resume_data[RKPM_BOOTDATA_CPUCODE]=0;
1091             return ;
1092         }
1093
1094         if(pwrmode&BIT(pmu_bus_pd_en))
1095         {
1096                 sleep_resume_data[RKPM_BOOTDATA_DDR_F]=1;// in sys resume ,ddr is need resume
1097                 sleep_resume_data[RKPM_BOOTDATA_DPLL_F]=1;// in ddr resume ,dpll is need resume
1098                 code_src=(char *)ddr_get_resume_code_info(&code_size);
1099                 sleep_resume_data[RKPM_BOOTDATA_DDRCODE]=RKPM_BOOT_DDRCODE_PHY;
1100                 sleep_resume_data[RKPM_BOOTDATA_DDRDATA]=RKPM_BOOT_DDRCODE_PHY+RKPM_ALIGN(code_size,4);
1101                 data_src=(char *)ddr_get_resume_data_info(&data_size);
1102                 ddr_reg_save((u32 *)(resume_data_phy+RKPM_BOOTDATA_DPLL_F*4));
1103        }
1104         else
1105         {
1106             sleep_resume_data[RKPM_BOOTDATA_DDR_F]=0;
1107         }
1108
1109         sram_data_for_sleep(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1110
1111         flush_cache_all();
1112         outer_flush_all();
1113         local_flush_tlb_all();
1114
1115 }
1116
1117 static inline void sram_code_data_resume(u32 pwrmode)
1118 {
1119          if(pwrmode&(BIT(pmu_scu_en)|BIT(pmu_a12_0_pd_en)))
1120         {
1121              sram_data_resume(boot_ram_data,int_ram_data,sleep_resume_data[RKPM_BOOTDATA_DDR_F]);
1122         }
1123
1124 }
1125
1126 static void  rkpm_peri_save(u32 power_mode)
1127 {
1128 //    u32 gpio_gate[2];
1129
1130     if(power_mode&BIT(pmu_scu_en))
1131     {
1132         rkpm_gic_dist_save(&slp_gic_save[0]);
1133     }
1134 #if 0
1135     gpio_gate[0]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1136     gpio_gate[1]=cru_readl(RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1137     RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_GPIO0);
1138     cru_writel(0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16),
1139                          RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1140 #endif
1141
1142     if(power_mode&BIT(pmu_bus_pd_en))
1143    {
1144        #if 0
1145         //gpio7_c6
1146         //gpio7_c7
1147         ddr_pin_set_pull(7,0xc,0x6,RKPM_GPIO_PULL_UP);
1148         ddr_gpio_set_in_output(7,0xc,0x6,RKPM_GPIO_INPUT);
1149         ddr_pin_set_fun(7,0xc,0x6,0);
1150
1151         ddr_pin_set_pull(7,0xc,0x7,RKPM_GPIO_PULL_UP);
1152         ddr_gpio_set_in_output(7,0xc,0x7,RKPM_GPIO_INPUT);
1153         ddr_pin_set_fun(7,0xc,0x7,0);
1154         #endif
1155         //slp_uart_save(2);
1156         #if 0
1157         ddr_pin_set_pull(0,0xb,0x7,RKPM_GPIO_PULL_UP);
1158         ddr_gpio_set_in_output(0,0xb,0x7,RKPM_GPIO_INPUT);
1159         ddr_pin_set_fun(0,0xb,0x7,0);
1160
1161         ddr_pin_set_pull(0,0xc,0x0,RKPM_GPIO_PULL_UP);
1162         ddr_gpio_set_in_output(0,0xc,0x0,RKPM_GPIO_INPUT);
1163         ddr_pin_set_fun(0,0xc,0x0,0);
1164         #endif
1165         slp_i2c_save(0);// i2c pmu gpio0b7 gpio0_c0
1166         slp_i2c_save(1);//i2c audio
1167     }
1168
1169 #if 0
1170         cru_writel((0xff<<(RK3288_CLKGATE_PCLK_GPIO1%16+16))|gpio_gate[0],
1171                                       RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO1));
1172         cru_writel(gpio_gate[0]|CRU_W_MSK(RK3288_CLKGATE_PCLK_GPIO0%16,0x1),RK3288_CRU_GATEID_CONS(RK3288_CLKGATE_PCLK_GPIO0));
1173 #endif
1174
1175 }
1176
1177 static inline void  rkpm_peri_resume(u32 power_mode)
1178 {
1179     if(power_mode&BIT(pmu_scu_en))
1180     {
1181         //fiq_glue_resume();
1182         rkpm_gic_dist_resume(&slp_gic_save[0]);
1183         fiq_glue_resume();
1184         //rkpm_ddr_printascii("gic res");
1185     }
1186     if(power_mode&BIT(pmu_bus_pd_en))
1187    {
1188         slp_i2c_resume(0);// i2c pmu
1189         slp_i2c_resume(1);//i2c audio
1190     }
1191
1192 }
1193
1194 static u32 pdbus_gate_reg[5];
1195 static inline void  rkpm_peri_resume_first(u32 power_mode)
1196 {
1197
1198     if(power_mode&BIT(pmu_bus_pd_en))
1199     {
1200         cru_writel(0xffff0000|pdbus_gate_reg[0],RK3288_CRU_CLKGATES_CON(0));
1201         cru_writel(0xffff0000|pdbus_gate_reg[1],RK3288_CRU_CLKGATES_CON(4));
1202         cru_writel(0xffff0000|pdbus_gate_reg[2],RK3288_CRU_CLKGATES_CON(5));
1203         cru_writel(0xffff0000|pdbus_gate_reg[3],RK3288_CRU_CLKGATES_CON(10));
1204         cru_writel(0xffff0000|pdbus_gate_reg[4],RK3288_CRU_CLKGATES_CON(11));
1205     }
1206
1207
1208       if(power_mode&BIT(pmu_bus_pd_en))
1209         slp_uartdbg_resume();
1210 }
1211
1212 static void rkpm_slp_setting(void)
1213 {
1214     rk_usb_power_down();
1215
1216     if(rk3288_powermode&BIT(pmu_bus_pd_en))
1217     {
1218         // pd bus will be power down ,but if it reup,ungating clk for its reset
1219         // ungating pdbus clk
1220         pdbus_gate_reg[0]=cru_readl(RK3288_CRU_CLKGATES_CON(0));
1221         pdbus_gate_reg[1]=cru_readl(RK3288_CRU_CLKGATES_CON(4));
1222         pdbus_gate_reg[2]=cru_readl(RK3288_CRU_CLKGATES_CON(5));
1223         pdbus_gate_reg[3]=cru_readl(RK3288_CRU_CLKGATES_CON(10));
1224         pdbus_gate_reg[4]=cru_readl(RK3288_CRU_CLKGATES_CON(11));
1225
1226         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(0));
1227         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(4));
1228         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(5));
1229         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(10));
1230         cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(11));
1231
1232         RK3288_CRU_UNGATING_OPS(RK3288_CLKGATE_PCLK_UART2);
1233        // RK3288_CRU_UNGATING_OPS((RK3288_CLKGATE_UART0_SRC+2*2));
1234        //c2c host
1235        RK3288_CRU_UNGATING_OPS(RK3288_CRU_CONS_GATEID(13)+8);
1236
1237     }
1238
1239 }
1240
1241
1242 static void rkpm_save_setting_resume_first(void)
1243 {
1244         rk_usb_power_up();
1245         rkpm_peri_resume_first(rk3288_powermode);
1246
1247         // rkpm_ddr_printhex(cru_readl(RK3288_CRU_MODE_CON));
1248         #if 0
1249         //rk319x_pm_set_power_domain(PD_PERI,true);
1250         //slp_regs_resume(slp_grf_io_pull_data,(u32)RK_GRF_VIRT+0x144,16,0xffff0000);
1251         slp_pin_gpio_resume(1);
1252         slp_pin_gpio_resume(2);
1253         slp_pin_gpio_resume(3);
1254         slp_pin_gpio_resume(4);
1255
1256         #if 0
1257         slp_regs_w_msk_resume(slp_grf_soc_con_data,(u32)RK_GRF_VIRT+0x60,5,slp_grf_soc_con_w_msk);
1258         slp_regs_w_msk_resume(slp_grf_cpu_con_data,(u32)RK_GRF_VIRT+0x9c,5,slp_grf_cpu_con_w_msk);
1259
1260         slp_regs_w_msk_resume(slp_grf_uoc0_con_data,(u32)RK_GRF_VIRT+0xc4,4,slp_grf_uoc0_con_w_msk);
1261         slp_regs_w_msk_resume(slp_grf_uoc1_con_data,(u32)RK_GRF_VIRT+0xd4,2,slp_grf_uoc1_con_w_msk);
1262         slp_regs_w_msk_resume(slp_grf_uoc2_con_data,(u32)RK_GRF_VIRT+0xe4,2,slp_grf_uoc2_con_w_msk);
1263         slp_regs_w_msk_resume(slp_grf_uoc3_con_data,(u32)RK_GRF_VIRT+0xec,2,slp_grf_uoc3_con_w_msk);
1264         #endif
1265         //sram_printch_uart_enable();
1266         slp_uart_resume(2);
1267        #endif
1268 }
1269
1270 static void rkpm_save_setting(u32 ctrbits)
1271 {
1272
1273 #if 0
1274     rkpm_ddr_regs_dump(RK_DDR_VIRT,0,0x3fc);
1275     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE,0,0x294);
1276
1277     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE+RK3288_DDR_PUBL_SIZE,0,0x3fc);
1278     rkpm_ddr_regs_dump(RK_DDR_VIRT+RK3288_DDR_PCTL_SIZE*2+RK3288_DDR_PUBL_SIZE,0,0x294);
1279 #endif
1280     rk3288_powermode=rkpm_slp_mode_set(ctrbits);
1281     if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1282     {
1283             sram_code_data_save(rk3288_powermode);
1284             rkpm_peri_save(rk3288_powermode);
1285     }
1286     else
1287          return ;
1288
1289 }
1290 static void rkpm_save_setting_resume(void)
1291 {
1292
1293         #if 0
1294         rkpm_ddr_printascii("l2&arm_errata--");
1295         rkpm_ddr_printhex(rkpm_l2_config());
1296         rkpm_ddr_printhex(rkpm_armerrata_818325());
1297         rkpm_ddr_printascii("\n");
1298         #endif
1299
1300          if(rk3288_powermode&BIT(pmu_pwr_mode_en))
1301         {
1302             sram_code_data_resume(rk3288_powermode);
1303             rkpm_peri_resume(rk3288_powermode);
1304         }
1305          rkpm_slp_mode_set_resume();
1306
1307 }
1308
1309 /*******************************common code  for rkxxx*********************************/
1310 static void  inline uart_printch(char byte)
1311 {
1312         u32 reg_save[2];
1313         u32 u_clk_id=(RK3288_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART*2);
1314         u32 u_pclk_id=(RK3288_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1315
1316         if(CONFIG_RK_DEBUG_UART==4)
1317             u_clk_id=RK3288_CLKGATE_UART4_SRC;
1318         if(CONFIG_RK_DEBUG_UART==2)
1319             u_pclk_id=RK3288_CLKGATE_PCLK_UART2;
1320
1321         reg_save[0]=cru_readl(RK3288_CRU_GATEID_CONS(u_clk_id));
1322         reg_save[1]=cru_readl(RK3288_CRU_GATEID_CONS(u_pclk_id));
1323         RK3288_CRU_UNGATING_OPS(u_clk_id);
1324         RK3288_CRU_UNGATING_OPS(u_pclk_id);
1325
1326         rkpm_udelay(1);
1327
1328 write_uart:
1329         writel_relaxed(byte, RK_DEBUG_UART_VIRT);
1330         dsb();
1331
1332         /* loop check LSR[6], Transmitter Empty bit */
1333         while (!(readl_relaxed(RK_DEBUG_UART_VIRT + 0x14) & 0x40))
1334                 barrier();
1335
1336         if (byte == '\n') {
1337                 byte = '\r';
1338                 goto write_uart;
1339         }
1340
1341          cru_writel(reg_save[0]|CRU_W_MSK(u_clk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_clk_id));
1342          cru_writel(reg_save[1]|CRU_W_MSK(u_pclk_id%16,0x1),RK3288_CRU_GATEID_CONS(u_pclk_id));
1343 }
1344
1345 void PIE_FUNC(sram_printch)(char byte)
1346 {
1347         uart_printch(byte);
1348 }
1349
1350 static void pll_udelay(u32 udelay);
1351
1352 #ifdef CONFIG_RK_LAST_LOG
1353 extern void rk_last_log_text(char *text, size_t size);
1354 #endif
1355
1356 static void  ddr_printch(char byte)
1357 {
1358         uart_printch(byte);
1359
1360 #ifdef CONFIG_RK_LAST_LOG
1361         rk_last_log_text(&byte, 1);
1362
1363         if (byte == '\n') {
1364                 byte = '\r';
1365                 rk_last_log_text(&byte, 1);
1366         }
1367 #endif
1368         pll_udelay(2);
1369 }
1370 /*******************************gpio func*******************************************/
1371 //#define RK3288_PMU_GPIO0_A_IOMUX      0x0084
1372 //#define RK3288_PMU_GPIO0_B_IOMUX      0x0088
1373 //#define RK3288_PMU_GPIO0_C_IOMUX      0x008c
1374 //#define RK3288_PMU_GPIO0_D_IOMUX      0x0090
1375 //pin=0x0a21  gpio0a2,port=0,bank=a,b_gpio=2,fun=1
1376 static inline void pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1377 {
1378         u32 off_set;
1379         bank-=0xa;
1380
1381         if(port==0)
1382         {
1383             if(bank>2)
1384                 return;
1385             off_set=RK3288_PMU_GPIO0_A_IOMUX+bank*4;
1386             pmu_writel(RKPM_VAL_SETBITS(pmu_readl(off_set),fun,b_gpio*2,0x3),off_set);
1387         }
1388         else if(port==1||port==2)
1389         {
1390             off_set=port*(4*4)+bank*4;
1391             reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1392         }
1393         else if(port==3)
1394         {
1395             if(bank<=2)
1396             {
1397                 off_set=0x20+bank*4;
1398                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1399
1400             }
1401             else
1402             {
1403                 off_set=0x2c+(b_gpio/4)*4;
1404                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1405             }
1406
1407         }
1408         else if(port==4)
1409         {
1410             if(bank<=1)
1411             {
1412                 off_set=0x34+bank*8+(b_gpio/4)*4;
1413                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1414             }
1415             else
1416             {
1417                 off_set=0x44+(bank-2)*4;
1418                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1419             }
1420
1421         }
1422         else if(port==5||port==6)
1423         {
1424                 off_set=0x4c+(port-5)*4*4+bank*4;
1425                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1426         }
1427         else if(port==7)
1428         {
1429             if(bank<=1)
1430             {
1431                 off_set=0x6c+bank*4;
1432                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1433             }
1434             else
1435             {
1436                 off_set=0x74+(bank-2)*8+(b_gpio/4)*4;
1437                 //rkpm_ddr_printascii("gpio");
1438                 //rkpm_ddr_printhex(off_set);
1439                 //rkpm_ddr_printascii("-");
1440                 //rkpm_ddr_printhex((b_gpio%4)*4);
1441
1442                 reg_writel(RKPM_W_MSK_SETBITS(fun,(b_gpio%4)*4,0x3),RK_GRF_VIRT+0+off_set);
1443
1444                 //rkpm_ddr_printhex(reg_readl(RK_GRF_VIRT+0+off_set));
1445                 //rkpm_ddr_printascii("\n");
1446             }
1447
1448         }
1449         else if(port==8)
1450         {
1451             if(bank<=1)
1452             {
1453                 off_set=0x80+bank*4;
1454                 reg_writel(RKPM_W_MSK_SETBITS(fun,b_gpio*2,0x3),RK_GRF_VIRT+0+off_set);
1455             }
1456         }
1457
1458 }
1459
1460 #if 0
1461 static inline u8 pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1462 {
1463
1464 }
1465 #endif
1466 static inline void pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 pull)
1467 {
1468     u32 off_set;
1469
1470     bank-=0xa;
1471
1472     if(port > 0)
1473     {
1474         //gpio1_d st
1475         //if(port==1&&bank<3)
1476        //  return;
1477         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1478         off_set=(0x14c-0x1c)+port*(4*4)+bank*4;
1479
1480         #if 0
1481         rkpm_ddr_printascii("gpio pull\n");
1482         rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1483         rkpm_ddr_printhex(b_gpio);
1484         rkpm_ddr_printhex(pull);
1485         rkpm_ddr_printhex(off_set);
1486         rkpm_ddr_printhex(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3));
1487         #endif
1488
1489         reg_writel(RKPM_W_MSK_SETBITS(pull,b_gpio*2,0x3),RK_GRF_VIRT+off_set);
1490
1491     }
1492     else
1493     {
1494         if(bank>2)// gpio0_d is not support
1495             return;
1496         pmu_writel(RKPM_VAL_SETBITS(pmu_readl(0x64+bank*4),pull,b_gpio*2,0x3),0x64+bank*4);
1497     }
1498
1499 }
1500
1501 static inline u8 pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1502 {
1503     u32 off_set;
1504
1505     bank-=0xa;
1506
1507     if(port > 0)
1508     {
1509         //gpio1_d st
1510         if(port==1&&bank<3)
1511             return 0;
1512         //gpio1_d==0x14c ,form gpio0_a to gpio1_d offset 1*16+3*4= 0x1c
1513         off_set=0x14c-0x1c+port*(4*4)+bank*4;
1514         return RKPM_GETBITS(reg_readl(RK_GRF_VIRT+off_set),b_gpio*2,0x3);
1515
1516     }
1517     else
1518     {
1519         if(bank>2)// gpio0_d is not support
1520             return 0;
1521         return RKPM_GETBITS(pmu_readl(0x64+bank*4),b_gpio*2,0x3);
1522     }
1523
1524 }
1525
1526
1527 //RKPM_GPIOS_INPUT
1528 static inline void gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1529 {
1530     u32 val;
1531
1532     bank-=0xa;
1533     b_gpio=bank*8+b_gpio;//
1534
1535     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1536
1537     if(type==RKPM_GPIO_OUTPUT)
1538         val|=(0x1<<b_gpio);
1539     else
1540         val&=~(0x1<<b_gpio);
1541     #if 0
1542     rkpm_ddr_printascii("gpio out\n");
1543     rkpm_ddr_printhex((u32)RK_GPIO_VIRT(port));
1544     rkpm_ddr_printhex(b_gpio);
1545
1546     rkpm_ddr_printhex(type);
1547     rkpm_ddr_printhex(val);
1548     #endif
1549     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR);
1550
1551     //rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR));
1552
1553
1554 }
1555
1556 static inline u8 gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1557 {
1558     bank-=0xa;
1559     b_gpio=bank*8+b_gpio;
1560     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DDR)&(0x1<<b_gpio);
1561 }
1562
1563 //RKPM_GPIOS_OUT_L   RKPM_GPIOS_OUT_H
1564 static inline void gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1565 {
1566     u32 val;
1567
1568     bank-=0xa;
1569     b_gpio=bank*8+b_gpio;
1570
1571     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1572
1573     if(level==RKPM_GPIO_OUT_H)
1574         val|=(0x1<<b_gpio);
1575     else //
1576         val&=~(0x1<<b_gpio);
1577
1578      reg_writel(val,RK_GPIO_VIRT(port)+GPIO_SWPORT_DR);
1579 }
1580
1581 static inline u8 gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1582 {
1583     bank-=0xa;
1584     b_gpio=bank*8+b_gpio;
1585     return reg_readl(RK_GPIO_VIRT(port)+GPIO_SWPORT_DR)&(0x1<<b_gpio);
1586 }
1587
1588 static inline u8 gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1589 {
1590
1591     bank-=0xa;
1592     b_gpio=bank*8+b_gpio;
1593
1594     return (reg_readl(RK_GPIO_VIRT(port)+GPIO_EXT_PORT)>>b_gpio)&0x1;
1595 }
1596 static inline void gpio_set_inten(u8 port,u8 bank,u8 b_gpio,u8 en)
1597 {
1598     u32 val;
1599
1600     bank-=0xa;
1601     b_gpio=bank*8+b_gpio;
1602
1603     val=reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN);
1604     rkpm_ddr_printascii("\n inten:");
1605     rkpm_ddr_printhex(val);
1606
1607     rkpm_ddr_printascii("-");
1608     if(en==1)
1609         val|=(0x1<<b_gpio);
1610     else //
1611         val&=~(0x1<<b_gpio);
1612
1613     reg_writel(val,RK_GPIO_VIRT(port)+GPIO_INTEN);
1614     dsb();
1615
1616      rkpm_ddr_printhex(val);
1617      rkpm_ddr_printascii("-");
1618
1619      rkpm_ddr_printhex(reg_readl(RK_GPIO_VIRT(port)+GPIO_INTEN));
1620
1621     rkpm_ddr_printascii("\n");
1622
1623
1624 }
1625 #if 0
1626 static void __sramfunc sram_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1627 {
1628         pin_set_fun(port,bank,b_gpio,fun);
1629 }
1630 static u8 __sramfunc sram_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1631 {
1632     return pin_get_funset(port,bank,b_gpio);
1633 }
1634
1635 static void __sramfunc sram_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1636 {
1637         pin_set_pull(port,bank,b_gpio,fun);
1638 }
1639 static u8 __sramfunc sram_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1640 {
1641     return pin_get_pullset(port,bank,b_gpio);
1642 }
1643
1644 static void __sramfunc sram_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1645 {
1646     gpio_set_in_output(port,bank,b_gpio,type);
1647 }
1648
1649 static u8 __sramfunc sram_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1650 {
1651     return gpio_get_in_outputset(port,bank,b_gpio);
1652 }
1653
1654 static void __sramfunc sram_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1655 {
1656
1657     gpio_set_output_level(port,bank,b_gpio,level);
1658
1659 }
1660
1661 static u8 __sramfunc sram_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1662 {
1663     return gpio_get_output_levelset(port,bank,b_gpio);
1664 }
1665 #endif
1666 #if 0
1667 static u8 __sramfunc sram_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1668 {
1669     return gpio_get_input_level(port,bank,b_gpio);
1670 }
1671 #endif
1672 //ddr
1673 static void ddr_pin_set_fun(u8 port,u8 bank,u8 b_gpio,u8 fun)
1674 {
1675         pin_set_fun(port,bank,b_gpio,fun);
1676 }
1677 #if 0
1678 static u8 ddr_pin_get_funset(u8 port,u8 bank,u8 b_gpio)
1679 {
1680     return pin_get_funset(port,bank,b_gpio);
1681 }
1682 static u8 ddr_pin_get_pullset(u8 port,u8 bank,u8 b_gpio)
1683 {
1684     return pin_get_pullset(port,bank,b_gpio);
1685 }
1686 static u8 ddr_gpio_get_in_outputset(u8 port,u8 bank,u8 b_gpio)
1687 {
1688     return gpio_get_in_outputset(port,bank,b_gpio);
1689 }
1690
1691 static u8 ddr_gpio_get_output_levelset(u8 port,u8 bank,u8 b_gpio)
1692 {
1693     return gpio_get_output_levelset(port,bank,b_gpio);
1694 }
1695 static u8 ddr_gpio_get_input_level(u8 port,u8 bank,u8 b_gpio)
1696 {
1697     return gpio_get_input_level(port,bank,b_gpio);
1698 }
1699
1700
1701 #endif
1702
1703
1704 static void ddr_pin_set_pull(u8 port,u8 bank,u8 b_gpio,u8 fun)
1705 {
1706         pin_set_pull(port,bank,b_gpio,fun);
1707 }
1708
1709 static void ddr_gpio_set_in_output(u8 port,u8 bank,u8 b_gpio,u8 type)
1710 {
1711     gpio_set_in_output(port,bank,b_gpio,type);
1712 }
1713 static void ddr_gpio_set_output_level(u8 port,u8 bank,u8 b_gpio,u8 level)
1714 {
1715     gpio_set_output_level(port,bank,b_gpio,level);
1716 }
1717
1718
1719
1720 #define GPIO_DTS_NUM (20)
1721 static  u32 suspend_gpios[GPIO_DTS_NUM];
1722 static  u32 resume_gpios[GPIO_DTS_NUM];
1723
1724 static int of_find_property_value_getsize(const struct device_node *np,const char *propname)
1725 {
1726         struct property *prop = of_find_property(np, propname, NULL);
1727
1728         if (!prop)
1729                 return 0;
1730         if (!prop->value)
1731                 return 0;
1732         return prop->length;
1733 }
1734
1735 static  void rkpm_pin_gpio_config(u32 pin_gpio_bits)
1736 {
1737
1738     u32 pins;
1739     u8 port,bank,b_gpio,fun,in_out, level, pull;
1740
1741     pins=RKPM_PINGPIO_BITS_PIN(pin_gpio_bits);
1742     in_out=RKPM_PINGPIO_BITS_INOUT(pin_gpio_bits);
1743     pull=RKPM_PINGPIO_BITS_PULL(pin_gpio_bits);
1744     level=RKPM_PINGPIO_BITS_LEVEL(pin_gpio_bits);
1745
1746     port=RKPM_PINBITS_PORT(pins);
1747     bank=RKPM_PINBITS_BANK(pins);
1748     b_gpio=RKPM_PINBITS_BGPIO(pins);
1749     fun=RKPM_PINBITS_FUN(pins);
1750
1751
1752     if(!fun)
1753    {
1754         if(in_out==RKPM_GPIO_OUTPUT)
1755         {
1756             if(level==RKPM_GPIO_OUT_L)
1757                 pull=RKPM_GPIO_PULL_DN;
1758             else
1759                 pull=RKPM_GPIO_PULL_UP;
1760
1761             ddr_gpio_set_output_level(port,bank,b_gpio,level);
1762         }
1763         //rkpm_ddr_printhex(pins);
1764
1765         ddr_gpio_set_in_output(port,bank,b_gpio,in_out);
1766     }
1767
1768     ddr_pin_set_pull(port,bank,b_gpio,pull);
1769     ddr_pin_set_fun(port,bank,b_gpio,fun);
1770
1771
1772
1773 }
1774
1775 #define RKPM_PINGPIO_BITS_PINTOPORT(pin_gpio_bits) RKPM_PINBITS_PORT(RKPM_PINGPIO_BITS_PIN((pin_gpio_bits)))
1776 #define  rkpm_gpio_pclk_idx(port) ((port)==0) ? RK3288_CLKGATE_PCLK_GPIO0 : (RK3288_CLKGATE_PCLK_GPIO1+(port)-1)
1777
1778 //rk3288_powermode
1779 static void rkpm_pins_setting(u32 *gpios,u32 cnt)
1780 {
1781        u32 i,clk_id;
1782        u32 gpio_clk_reg[9];
1783        u8 port;
1784
1785       // rkpm_ddr_printascii("\ngpios");
1786
1787         for(i=0;i<9;i++)
1788         {
1789             gpio_clk_reg[i]=0xffff0000;
1790         }
1791
1792        for(i=0;i<cnt;i++)
1793        {
1794             if(gpios[i]!=0)
1795            {
1796                 port=RKPM_PINGPIO_BITS_PINTOPORT(gpios[i]);
1797                 if(gpio_clk_reg[port]==0xffff0000)
1798                 {
1799                     clk_id=rkpm_gpio_pclk_idx(port);
1800                     gpio_clk_reg[port]=cru_readl(RK3288_CRU_GATEID_CONS(clk_id))&0xffff;
1801                     RK3288_CRU_UNGATING_OPS(clk_id);
1802                 }
1803                // rkpm_ddr_printhex(gpios[i]);
1804                 rkpm_pin_gpio_config(gpios[i]);
1805            }
1806        }
1807       // rkpm_ddr_printascii("\n");
1808
1809  #if 0
1810         for(i=0;i<9;i++)
1811        {
1812            rkpm_ddr_regs_dump(RK_GPIO_VIRT(i),0,0x4);
1813        }
1814        //
1815        rkpm_ddr_regs_dump(RK_GRF_VIRT,0xc,0x84);
1816        rkpm_ddr_regs_dump(RK_GRF_VIRT,0x14c,0x1b4);
1817      //  rkpm_ddr_regs_dump(RK_PMU_VIRT,0x64,0x6c);
1818        //rkpm_ddr_regs_dump(RK_PMU_VIRT,0x84,0x9c);
1819    #endif
1820
1821         for(i=0;i<9;i++)
1822        {
1823             if(gpio_clk_reg[i]!=0xffff0000)
1824             {
1825                 clk_id=rkpm_gpio_pclk_idx(i);
1826                 cru_writel(gpio_clk_reg[i]|CRU_W_MSK(clk_id%16,0x1),RK3288_CRU_GATEID_CONS(clk_id));
1827             }
1828        }
1829
1830 }
1831
1832 static void  rkpm_gpio_suspend(void)
1833 {
1834     rkpm_pins_setting(&suspend_gpios[0],GPIO_DTS_NUM);
1835 }
1836
1837
1838
1839 static void  rkpm_gpio_resume(void)
1840 {
1841      rkpm_pins_setting(&resume_gpios[0],GPIO_DTS_NUM);
1842 }
1843
1844 #if 1
1845 static void gpio_get_dts_info(struct device_node *parent)
1846 {
1847         int i;
1848         size_t temp_len;
1849     //return;
1850
1851         for(i=0;i<GPIO_DTS_NUM;i++)
1852         {
1853             suspend_gpios[i]=0;
1854             resume_gpios[i]=0;
1855         }
1856
1857      #if 1
1858         temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-suspend_gpios");
1859         if(temp_len)
1860         {
1861             printk("%s suspend:%d\n",__FUNCTION__,temp_len);
1862             if(temp_len)
1863             {
1864                 if(of_property_read_u32_array(parent,"rockchip,pmic-suspend_gpios",&suspend_gpios[0],temp_len/4))
1865                 {
1866                         suspend_gpios[0]=0;
1867                        printk("%s:get pm ctr error\n",__FUNCTION__);
1868                 }
1869             }
1870         }
1871
1872        temp_len=of_find_property_value_getsize(parent,"rockchip,pmic-resume_gpios");
1873        if(temp_len)
1874        {
1875            printk("%s resume:%d\n",__FUNCTION__,temp_len);
1876            if(of_property_read_u32_array(parent,"rockchip,pmic-resume_gpios",&resume_gpios[0],temp_len/4))
1877            {
1878                     resume_gpios[0]=0;
1879                    printk("%s:get pm ctr error\n",__FUNCTION__);
1880            }
1881         }
1882      #endif
1883
1884      printk("rockchip,pmic-suspend_gpios:");
1885      for(i=0;i<GPIO_DTS_NUM;i++)
1886      {
1887          printk("%x ",suspend_gpios[i]);
1888          if(i==(GPIO_DTS_NUM-1))
1889              printk("\n");
1890      }
1891
1892      printk("rockchip,pmic-resume_gpios:");
1893      for(i=0;i<GPIO_DTS_NUM;i++)
1894      {
1895           printk("%x ",resume_gpios[i]);
1896           if(i==(GPIO_DTS_NUM-1))
1897               printk("\n");
1898      }
1899
1900    rkpm_set_ops_gpios(rkpm_gpio_suspend,rkpm_gpio_resume);
1901
1902 }
1903 #endif
1904
1905 /*******************************clk gating config*******************************************/
1906 #define CLK_MSK_GATING(msk, con) cru_writel((msk << 16) | 0xffff, con)
1907 #define CLK_MSK_UNGATING(msk, con) cru_writel(((~msk) << 16) | 0xffff, con)
1908
1909
1910 static u32 clk_ungt_msk[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1911 static u32 clk_ungt_msk_1[RK3288_CRU_CLKGATES_CON_CNT];// first clk gating setting
1912 static u32 clk_ungt_save[RK3288_CRU_CLKGATES_CON_CNT]; //first clk gating value saveing
1913
1914
1915 u32 DEFINE_PIE_DATA(rkpm_clkgt_last_set[RK3288_CRU_CLKGATES_CON_CNT]);
1916 static u32 *p_rkpm_clkgt_last_set;
1917
1918 static __sramdata u32 rkpm_clkgt_last_save[RK3288_CRU_CLKGATES_CON_CNT];
1919
1920 void PIE_FUNC(gtclks_sram_suspend)(void)
1921 {
1922     int i;
1923    // u32 u_clk_id=(RK3188_CLKGATE_UART0_SRC+CONFIG_RK_DEBUG_UART);
1924    // u32 u_pclk_id=(RK3188_CLKGATE_PCLK_UART0+CONFIG_RK_DEBUG_UART);
1925
1926     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1927     {
1928         rkpm_clkgt_last_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1929         CLK_MSK_UNGATING( DATA(rkpm_clkgt_last_set[i]), RK3288_CRU_CLKGATES_CON(i));
1930         #if 0
1931         rkpm_sram_printch('\n');
1932         rkpm_sram_printhex(DATA(rkpm_clkgt_last_save[i]));
1933         rkpm_sram_printch('-');
1934         rkpm_sram_printhex(DATA(rkpm_clkgt_last_set[i]));
1935         rkpm_sram_printch('-');
1936         rkpm_sram_printhex(cru_readl(RK3188_CRU_CLKGATES_CON(i)));
1937         if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
1938         rkpm_sram_printch('\n');
1939         #endif
1940     }
1941
1942         //RK3288_CRU_UNGATING_OPS(u_clk_id);
1943         //RK3288_CRU_UNGATING_OPS(u_pclk_id);
1944
1945 }
1946
1947 void PIE_FUNC(gtclks_sram_resume)(void)
1948 {
1949     int i;
1950     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1951     {
1952         cru_writel(rkpm_clkgt_last_save[i]|0xffff0000, RK3288_CRU_CLKGATES_CON(i));
1953     }
1954 }
1955 #define grf_readl(offset)       readl_relaxed(RK_GRF_VIRT + offset)
1956 #define grf_writel(v, offset)   do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
1957
1958 #define gpio7_readl(offset)     readl_relaxed(RK_GPIO_VIRT(7)+ offset)
1959 #define gpio7_writel(v, offset) do { writel_relaxed(v, RK_GPIO_VIRT(7) + offset); dsb(); } while (0)
1960
1961 int gpio7_pin_data1, gpio7_pin_dir1;
1962 int gpio7_pin_iomux1;
1963
1964 static void gtclks_suspend(void)
1965 {
1966     int i;
1967         gpio7_pin_data1= gpio7_readl(0);
1968         gpio7_pin_dir1 = gpio7_readl(0x04);
1969         gpio7_pin_iomux1 =  gpio7_readl(0x6c);
1970         grf_writel(0x00040000, 0x6c);
1971         gpio7_writel(gpio7_pin_dir1|0x2, 0x04);
1972         gpio7_writel((gpio7_pin_data1|2), 0x00);
1973
1974   // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
1975                                           //          ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
1976     for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
1977     {
1978             clk_ungt_save[i]=cru_readl(RK3288_CRU_CLKGATES_CON(i));
1979            // 160 1a8
1980            #if 0
1981            if(
1982                // RK3288_CRU_CLKGATES_CON(i)==0x160 ||
1983                 //RK3288_CRU_CLKGATES_CON(i)==0x164 ||
1984                 //RK3288_CRU_CLKGATES_CON(i)==0x168 ||
1985               //  RK3288_CRU_CLKGATES_CON(i)==0x16c ||
1986                 //RK3288_CRU_CLKGATES_CON(i)==0x170 ||
1987                // RK3288_CRU_CLKGATES_CON(i)==0x174 ||
1988                // RK3288_CRU_CLKGATES_CON(i)==0x178 ||
1989
1990
1991                 //RK3288_CRU_CLKGATES_CON(i)==0x17c ||
1992                // RK3288_CRU_CLKGATES_CON(i)==0x180 ||
1993                // RK3288_CRU_CLKGATES_CON(i)==0x184 ||
1994                // RK3288_CRU_CLKGATES_CON(i)==0x188 ||
1995                 //RK3288_CRU_CLKGATES_CON(i)==0x18c ||
1996                 //RK3288_CRU_CLKGATES_CON(i)==0x190 ||
1997                 //RK3288_CRU_CLKGATES_CON(i)==0x194 ||
1998                 //RK3288_CRU_CLKGATES_CON(i)==0x198 ||
1999                 //RK3288_CRU_CLKGATES_CON(i)==0x19c ||
2000                 //RK3288_CRU_CLKGATES_CON(i)==0x1a0 ||
2001                 //RK3288_CRU_CLKGATES_CON(i)==0x1a4 ||
2002                // RK3288_CRU_CLKGATES_CON(i)==0x1a8
2003                RK3288_CRU_CLKGATES_CON(i)==0xfff
2004             )
2005             {
2006
2007                  cru_writel(0xffff0000, RK3288_CRU_CLKGATES_CON(i));
2008                // CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2009
2010             }
2011            else
2012             #endif
2013             {
2014                // if(RK3288_CRU_CLKGATES_CON(i)!=0x188 )
2015                CLK_MSK_UNGATING(clk_ungt_msk[i],RK3288_CRU_CLKGATES_CON(i));
2016            }
2017            #if 0
2018             rkpm_ddr_printch('\n');
2019             rkpm_ddr_printhex(RK3288_CRU_CLKGATES_CON(i));
2020             rkpm_ddr_printch('-');
2021             rkpm_ddr_printhex(clk_ungt_msk[i]);
2022             rkpm_ddr_printch('-');
2023             rkpm_ddr_printhex(cru_readl(RK3288_CRU_CLKGATES_CON(i))) ;
2024             if(i==(RK3288_CRU_CLKGATES_CON_CNT-1))
2025             rkpm_ddr_printch('\n');
2026             #endif
2027     }
2028
2029 }
2030
2031 static void gtclks_resume(void)
2032 {
2033     int i;
2034      for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2035     {
2036        cru_writel(clk_ungt_save[i]|0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2037      }
2038      //rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKGATES_CON(0)
2039                                                  //   ,RK3288_CRU_CLKGATES_CON(RK3288_CRU_CLKGATES_CON_CNT-1));
2040         grf_writel(0x00040004, 0x6c);
2041
2042 }
2043 /********************************pll power down***************************************/
2044
2045 static void pm_pll_wait_lock(u32 pll_idx)
2046 {
2047         u32 delay = 600000U;
2048        // u32 mode;
2049      //  mode=cru_readl(RK3288_CRU_MODE_CON);
2050         dsb();
2051         dsb();
2052         dsb();
2053         dsb();
2054         dsb();
2055         dsb();
2056         while (delay > 0) {
2057                 if ((cru_readl(RK3288_PLL_CONS(pll_idx,1))&(0x1<<31)))
2058                         break;
2059                 delay--;
2060         }
2061         if (delay == 0) {
2062                 rkpm_ddr_printascii("unlock-pll:");
2063                 rkpm_ddr_printhex(pll_idx);
2064                 rkpm_ddr_printch('\n');
2065         }
2066     //cru_writel(mode|(RK3288_PLL_MODE_MSK(pll_idx)<<16), RK3288_CRU_MODE_CON);
2067 }
2068
2069 static void pll_udelay(u32 udelay)
2070 {
2071     u32 mode;
2072     mode=cru_readl(RK3288_CRU_MODE_CON);
2073     // delay in 24m
2074     cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2075
2076     rkpm_udelay(udelay*5);
2077
2078     cru_writel(mode|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2079 }
2080
2081 static u32 plls_con0_save[END_PLL_ID];
2082 static u32 plls_con1_save[END_PLL_ID];
2083 static u32 plls_con2_save[END_PLL_ID];
2084 static u32 plls_con3_save[END_PLL_ID];
2085
2086 static u32 cru_mode_con;
2087
2088 static inline void plls_suspend(u32 pll_id)
2089 {
2090     plls_con0_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 0));
2091     plls_con1_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 1));
2092     plls_con2_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 2));
2093     plls_con3_save[pll_id]=cru_readl(RK3288_PLL_CONS((pll_id), 3));
2094
2095     cru_writel(RK3288_PLL_PWR_DN, RK3288_PLL_CONS((pll_id), 3));
2096
2097 }
2098 static inline void plls_resume(u32 pll_id)
2099 {
2100         u32 pllcon0, pllcon1, pllcon2;
2101
2102         if((plls_con3_save[pll_id]&RK3288_PLL_PWR_DN_MSK))
2103             return ;
2104
2105         //enter slowmode
2106         cru_writel(RK3288_PLL_MODE_SLOW(pll_id), RK3288_CRU_MODE_CON);
2107
2108         cru_writel(RK3288_PLL_PWR_ON, RK3288_PLL_CONS((pll_id),3));
2109         cru_writel(RK3288_PLL_NO_BYPASS, RK3288_PLL_CONS((pll_id),3));
2110
2111         pllcon0 =plls_con0_save[pll_id];// cru_readl(RK3288_PLL_CONS((pll_id),0));
2112         pllcon1 = plls_con1_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),1));
2113         pllcon2 = plls_con2_save[pll_id];//cru_readl(RK3288_PLL_CONS((pll_id),2));
2114
2115         //enter rest
2116         cru_writel(RK3288_PLL_RESET, RK3288_PLL_CONS(pll_id,3));
2117         cru_writel(pllcon0|CRU_W_MSK(0,0xf)|CRU_W_MSK(8,0x3f), RK3288_PLL_CONS(pll_id,0));
2118         cru_writel(pllcon1, RK3288_PLL_CONS(pll_id,1));
2119         cru_writel(pllcon2, RK3288_PLL_CONS(pll_id,2));
2120
2121         pll_udelay(5);
2122         //udelay(5); //timer7 delay
2123
2124         //return form rest
2125         cru_writel(RK3288_PLL_RESET_RESUME, RK3288_PLL_CONS(pll_id,3));
2126
2127         //wating lock state
2128         pll_udelay(168);
2129         pm_pll_wait_lock(pll_id);
2130
2131         cru_writel(plls_con3_save[pll_id]|(RK3288_PLL_BYPASS_MSK<<16),RK3288_PLL_CONS(pll_id,3));
2132
2133 }
2134
2135 static u32 clk_sel0,clk_sel1, clk_sel10,clk_sel26,clk_sel33,clk_sel36, clk_sel37;
2136
2137 static void pm_plls_suspend(void)
2138 {
2139
2140    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2141    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2142    // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2143
2144     clk_sel0=cru_readl(RK3288_CRU_CLKSELS_CON(0));
2145     clk_sel1=cru_readl(RK3288_CRU_CLKSELS_CON(1));
2146     clk_sel10=cru_readl(RK3288_CRU_CLKSELS_CON(10));
2147     clk_sel26=cru_readl(RK3288_CRU_CLKSELS_CON(26));
2148     clk_sel33=cru_readl(RK3288_CRU_CLKSELS_CON(33));
2149     clk_sel36=cru_readl(RK3288_CRU_CLKSELS_CON(36));
2150     clk_sel37=cru_readl(RK3288_CRU_CLKSELS_CON(37));
2151
2152     cru_mode_con = cru_readl(RK3288_CRU_MODE_CON);
2153
2154
2155     cru_writel(RK3288_PLL_MODE_SLOW(NPLL_ID), RK3288_CRU_MODE_CON);
2156     plls_suspend(NPLL_ID);
2157
2158 // cpll
2159     cru_writel(RK3288_PLL_MODE_SLOW(CPLL_ID), RK3288_CRU_MODE_CON);
2160
2161 // gpll
2162     cru_writel(RK3288_PLL_MODE_SLOW(GPLL_ID), RK3288_CRU_MODE_CON);
2163
2164     // set 1,pdbus pll is gpll
2165     cru_writel(CRU_W_MSK_SETBITS(1,15,0x1), RK3288_CRU_CLKSELS_CON(1)); // 0 cpll 1gpll
2166
2167     // pd_bus clk
2168     cru_writel(0
2169                         |CRU_W_MSK_SETBITS(0,0,0x7)  //  1  aclk
2170                         |CRU_W_MSK_SETBITS(0,3,0x1f) //  1   aclk src
2171                         |CRU_W_MSK_SETBITS(0,8,0x3) // 1   hclk 0~1 1 2 4
2172                         |CRU_W_MSK_SETBITS(0,12,0x7) //  3   pclk
2173                      , RK3288_CRU_CLKSELS_CON(1));
2174
2175     //crypto for pd_bus
2176     cru_writel(CRU_W_MSK_SETBITS(3,6,0x3), RK3288_CRU_CLKSELS_CON(26));
2177
2178     // peri aclk hclk pclk
2179     cru_writel(0
2180                         |CRU_W_MSK_SETBITS(0,0,0x1f) // 1 aclk
2181                         |CRU_W_MSK_SETBITS(0,8,0x3) // 2   hclk 0 1:1,1 2:1 ,2 4:1
2182                         |CRU_W_MSK_SETBITS(0,12,0x3)// 2     0~3  1 2 4 8 div
2183                         , RK3288_CRU_CLKSELS_CON(10));
2184     // pmu alive
2185     cru_writel(CRU_W_MSK_SETBITS(0,0,0x1f)|CRU_W_MSK_SETBITS(0,8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2186
2187     plls_suspend(CPLL_ID);
2188     plls_suspend(GPLL_ID);
2189
2190 //apll
2191    cru_writel(RK3288_PLL_MODE_SLOW(APLL_ID), RK3288_CRU_MODE_CON);
2192      // core_m0 core_mp a12_core
2193     cru_writel(0
2194                         |CRU_W_MSK_SETBITS(0,0,0xf) // 1   axi_mo
2195                         |CRU_W_MSK_SETBITS(0,4,0xf) // 3  axi mp
2196                         |CRU_W_MSK_SETBITS(0,8,0x1f) // 0 a12 core div
2197                       , RK3288_CRU_CLKSELS_CON(0));
2198     // core0 core1 core2 core3
2199     cru_writel(0
2200                         |CRU_W_MSK_SETBITS(0,0,0x7) //core 0 div
2201                         |CRU_W_MSK_SETBITS(0,4,0x7) // core 1
2202                         |CRU_W_MSK_SETBITS(0,8,0x7) // core2
2203                         |CRU_W_MSK_SETBITS(0,12,0x7)//core3
2204                       , RK3288_CRU_CLKSELS_CON(36));
2205     // l2ram atclk pclk
2206     #if 1
2207     cru_writel(0
2208                     |CRU_W_MSK_SETBITS(3,0,0x7) // l2ram
2209                     |CRU_W_MSK_SETBITS(0xf,4,0x1f) // atclk
2210                      |CRU_W_MSK_SETBITS(0xf,9,0x1f) // pclk dbg
2211                      , RK3288_CRU_CLKSELS_CON(37));
2212     #else
2213     cru_writel(0
2214                       |CRU_W_MSK_SETBITS(0,0,0x7) // l2ram
2215                       |CRU_W_MSK_SETBITS(0x2,4,0x1f) // atclk
2216                        |CRU_W_MSK_SETBITS(0x2,9,0x1f) // pclk dbg
2217                        , RK3288_CRU_CLKSELS_CON(37));
2218     #endif
2219
2220
2221     plls_suspend(APLL_ID);
2222
2223 }
2224
2225 static void pm_plls_resume(void)
2226 {
2227
2228
2229         // core_m0 core_mp a12_core
2230         cru_writel(clk_sel0|(CRU_W_MSK(0,0xf)|CRU_W_MSK(4,0xf)|CRU_W_MSK(8,0xf)),RK3288_CRU_CLKSELS_CON(0));
2231         // core0 core1 core2 core3
2232         cru_writel(clk_sel36|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x7)|CRU_W_MSK(8,0x7)|CRU_W_MSK(12,0x7))
2233                         , RK3288_CRU_CLKSELS_CON(36));
2234         // l2ram atclk pclk
2235         cru_writel(clk_sel37|(CRU_W_MSK(0,0x7)|CRU_W_MSK(4,0x1f)|CRU_W_MSK(9,0x1f)) , RK3288_CRU_CLKSELS_CON(37));
2236
2237         plls_resume(APLL_ID);
2238         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16), RK3288_CRU_MODE_CON);
2239
2240         // peri aclk hclk pclk
2241         cru_writel(clk_sel10|(CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x3))
2242                                                                             , RK3288_CRU_CLKSELS_CON(10));
2243         //pd bus gpll sel
2244         cru_writel(clk_sel1|CRU_W_MSK(15,0x1), RK3288_CRU_CLKSELS_CON(1));
2245         // pd_bus clk
2246         cru_writel(clk_sel1|(CRU_W_MSK(0,0x7)|CRU_W_MSK(3,0x1f)|CRU_W_MSK(8,0x3)|CRU_W_MSK(12,0x7))
2247                     , RK3288_CRU_CLKSELS_CON(1));
2248
2249         // crypto
2250         cru_writel(clk_sel26|CRU_W_MSK(6,0x3), RK3288_CRU_CLKSELS_CON(26));
2251
2252
2253           // pmu alive
2254         cru_writel(clk_sel33|CRU_W_MSK(0,0x1f)|CRU_W_MSK(8,0x1f), RK3288_CRU_CLKSELS_CON(33));
2255
2256         plls_resume(GPLL_ID);
2257         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(GPLL_ID)<<16), RK3288_CRU_MODE_CON);
2258
2259         plls_resume(CPLL_ID);
2260         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(CPLL_ID)<<16), RK3288_CRU_MODE_CON);
2261
2262         plls_resume(NPLL_ID);
2263         cru_writel(cru_mode_con|(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2264
2265        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_PLL_CONS((0), 0),RK3288_PLL_CONS((4), 3));
2266        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_MODE_CON,RK3288_CRU_MODE_CON);
2267        // rkpm_ddr_regs_dump(RK_CRU_VIRT,RK3288_CRU_CLKSELS_CON(0),RK3288_CRU_CLKSELS_CON(42));
2268
2269 }
2270
2271 static __sramdata u32  sysclk_clksel0_con,sysclk_clksel1_con,sysclk_clksel10_con,sysclk_mode_con;
2272
2273 void PIE_FUNC(sysclk_suspend)(u32 sel_clk)
2274 {
2275
2276     int div;
2277     sysclk_clksel0_con = cru_readl(RK3288_CRU_CLKSELS_CON(0));
2278     sysclk_clksel1_con = cru_readl(RK3288_CRU_CLKSELS_CON(1));
2279     sysclk_clksel10_con= cru_readl(RK3288_CRU_CLKSELS_CON(10));
2280
2281
2282     if(sel_clk&(RKPM_CTR_SYSCLK_32K))
2283     {
2284         div=3;
2285         sysclk_mode_con= cru_readl(RK3288_CRU_MODE_CON);
2286         cru_writel(0
2287                 |RK3288_PLL_MODE_DEEP(APLL_ID)| RK3288_PLL_MODE_DEEP(CPLL_ID)
2288                 | RK3288_PLL_MODE_DEEP(GPLL_ID)|RK3288_PLL_MODE_DEEP(NPLL_ID)
2289                             , RK3288_CRU_MODE_CON);
2290     }
2291     else if(sel_clk&(RKPM_CTR_SYSCLK_DIV))
2292     {
2293         div=31;
2294     }
2295
2296     cru_writel(CRU_W_MSK_SETBITS(div,8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2297     cru_writel(CRU_W_MSK_SETBITS(div,3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2298     cru_writel(CRU_W_MSK_SETBITS(div,0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2299
2300 }
2301
2302 void PIE_FUNC(sysclk_resume)(u32 sel_clk)
2303 {
2304
2305     cru_writel(sysclk_clksel0_con|CRU_W_MSK(8,0x1f), RK3188_CRU_CLKSELS_CON(0)); //pd core
2306     cru_writel(sysclk_clksel1_con|CRU_W_MSK(3,0x1f), RK3188_CRU_CLKSELS_CON(1));//pd bus
2307     cru_writel(sysclk_clksel10_con|CRU_W_MSK(0,0x1f), RK3188_CRU_CLKSELS_CON(10));//pd peri
2308     cru_writel(sysclk_mode_con|(RK3288_PLL_MODE_MSK(APLL_ID)<<16)
2309                             |(RK3288_PLL_MODE_MSK(CPLL_ID)<<16)
2310                             |(RK3288_PLL_MODE_MSK(GPLL_ID)<<16)
2311                             |(RK3288_PLL_MODE_MSK(NPLL_ID)<<16), RK3288_CRU_MODE_CON);
2312
2313 }
2314
2315
2316 static void clks_gating_suspend_init(void)
2317 {
2318     // get clk gating info
2319     if(rockchip_pie_chunk)
2320         p_rkpm_clkgt_last_set= kern_to_pie(rockchip_pie_chunk, &DATA(rkpm_clkgt_last_set[0]));
2321     else
2322         p_rkpm_clkgt_last_set=&clk_ungt_msk_1[0];
2323     if(clk_suspend_clkgt_info_get(clk_ungt_msk,p_rkpm_clkgt_last_set, RK3288_CRU_CLKGATES_CON_CNT)
2324         ==RK3288_CRU_CLKGATES_CON(0))
2325     {
2326         rkpm_set_ops_gtclks(gtclks_suspend,gtclks_resume);
2327         if(rockchip_pie_chunk)
2328             rkpm_set_sram_ops_gtclks(fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_suspend)),
2329                                 fn_to_pie(rockchip_pie_chunk, &FUNC(gtclks_sram_resume)));
2330
2331         PM_LOG("%s:clkgt info ok\n",__FUNCTION__);
2332
2333     }
2334     if(rockchip_pie_chunk)
2335         rkpm_set_sram_ops_sysclk(fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_suspend))
2336                                                 ,fn_to_pie(rockchip_pie_chunk, &FUNC(sysclk_resume)));
2337 }
2338
2339 /***************************prepare and finish reg_pread***********************************/
2340
2341
2342
2343 #define GIC_DIST_PENDING_SET            0x200
2344 static noinline void rk3288_pm_dump_irq(void)
2345 {
2346         u32 irq_gpio = (readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + 12) >> 17) & 0x1FF;
2347         u32 irq[4];
2348         int i;
2349
2350         for (i = 0; i < ARRAY_SIZE(irq); i++)
2351                 irq[i] = readl_relaxed(RK_GIC_VIRT + GIC_DIST_PENDING_SET + (1 + i) * 4);
2352         for (i = 0; i < ARRAY_SIZE(irq); i++) {
2353                 if (irq[i])
2354                         log_wakeup_reason(32 * (i + 1) + fls(irq[i]) - 1);
2355         }
2356         printk("wakeup irq: %08x %08x %08x %08x\n", irq[0], irq[1], irq[2], irq[3]);
2357         for (i = 0; i <= 8; i++) {
2358                 if (irq_gpio & (1 << i))
2359                         printk("wakeup gpio%d: %08x\n", i, readl_relaxed(RK_GPIO_VIRT(i) + GPIO_INT_STATUS));
2360         }
2361 }
2362
2363 #if 0
2364 #define DUMP_GPIO_INTEN(ID) \
2365 do { \
2366         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2367         if (en) { \
2368                 rkpm_ddr_printascii("GPIO" #ID "_INTEN: "); \
2369                 rkpm_ddr_printhex(en); \
2370                 rkpm_ddr_printch('\n'); \
2371                 printk(KERN_DEBUG "GPIO%d_INTEN: %08x\n", ID, en); \
2372         } \
2373 } while (0)
2374 #else
2375
2376 #define DUMP_GPIO_INTEN(ID) \
2377     do { \
2378         u32 en = readl_relaxed(RK_GPIO_VIRT(ID) + GPIO_INTEN); \
2379         if (en) { \
2380                 printk("GPIO%d_INTEN: %08x\n", ID, en); \
2381         } \
2382     } while (0)
2383
2384 #endif
2385
2386
2387 //dump while irq is enable
2388 static noinline void rk3288_pm_dump_inten(void)
2389 {
2390         DUMP_GPIO_INTEN(0);
2391         DUMP_GPIO_INTEN(1);
2392         DUMP_GPIO_INTEN(2);
2393         DUMP_GPIO_INTEN(3);
2394         DUMP_GPIO_INTEN(4);
2395         DUMP_GPIO_INTEN(5);
2396         DUMP_GPIO_INTEN(6);
2397         DUMP_GPIO_INTEN(7);
2398         DUMP_GPIO_INTEN(8);
2399 }
2400
2401 static  void rkpm_prepare(void)
2402 {
2403
2404         int i;
2405          for(i=0;i<RK3288_CRU_CLKGATES_CON_CNT;i++)
2406         {
2407            //cru_writel(0xffff0000,RK3288_CRU_CLKGATES_CON(i));
2408          }
2409
2410         #if 0
2411         u32 temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2412
2413        // rkpm_ddr_printhex(temp);
2414         reg_writel(temp|0x1<<4,RK_GPIO_VIRT(0)+0x30);
2415         temp =reg_readl(RK_GPIO_VIRT(0)+0x30);
2416        // rkpm_ddr_printhex(temp);
2417         #endif
2418         // dump GPIO INTEN for debug
2419         rk3288_pm_dump_inten();
2420 }
2421
2422 static void rkpm_finish(void)
2423 {
2424         rk3288_pm_dump_irq();
2425 }
2426
2427 #if 0
2428 static  void interface_ctr_reg_pread(void)
2429 {
2430         //u32 addr;
2431         flush_cache_all();
2432         outer_flush_all();
2433         local_flush_tlb_all();
2434         #if 0  // do it in ddr suspend
2435         for (addr = (u32)SRAM_CODE_OFFSET; addr < (u32)(SRAM_CODE_OFFSET+rockchip_sram_size); addr += PAGE_SIZE)
2436                 readl_relaxed(addr);
2437         #endif
2438         readl_relaxed(RK_PMU_VIRT);
2439         readl_relaxed(RK_GRF_VIRT);
2440         readl_relaxed(RK_DDR_VIRT);
2441         readl_relaxed(RK_GPIO_VIRT(0));
2442         //readl_relaxed(RK30_I2C1_BASE+SZ_4K);
2443         //readl_relaxed(RK_GPIO_VIRT(3));
2444 }
2445 #endif
2446 void PIE_FUNC(ddr_leakage_tst)(void)
2447 {
2448     cru_writel(RK3288_PLL_MODE_SLOW(DPLL_ID), RK3288_CRU_MODE_CON);
2449     rkpm_sram_printch('\n');
2450     rkpm_sram_printch('t');
2451     rkpm_sram_printch('e');
2452     rkpm_sram_printch('s');
2453     rkpm_sram_printch('t');
2454     while(1);
2455 }
2456
2457 static void __init  rk3288_suspend_init(void)
2458 {
2459     struct device_node *parent;
2460     u32 pm_ctrbits;
2461
2462     PM_LOG("%s enter\n",__FUNCTION__);
2463
2464     parent = of_find_node_by_name(NULL, "rockchip_suspend");
2465
2466     if (IS_ERR_OR_NULL(parent)) {
2467                 PM_ERR("%s dev node err\n", __func__);
2468                 return;
2469         }
2470
2471
2472     if(of_property_read_u32_array(parent,"rockchip,ctrbits",&pm_ctrbits,1))
2473     {
2474             PM_ERR("%s:get pm ctr error\n",__FUNCTION__);
2475             return ;
2476     }
2477     PM_LOG("%s: pm_ctrbits =%x\n",__FUNCTION__,pm_ctrbits);
2478     pm_io_base_map();
2479     memset(&sleep_resume_data[0],0,sizeof(sleep_resume_data));
2480     rkpm_set_ctrbits(pm_ctrbits);
2481
2482     gpio_get_dts_info(parent);
2483     clks_gating_suspend_init();
2484
2485     rkpm_set_ops_plls(pm_plls_suspend,pm_plls_resume);
2486
2487     //rkpm_set_sram_ops_ddr(fn_to_pie(rockchip_pie_chunk, &FUNC(ddr_leakage_tst)),NULL);
2488
2489     rkpm_set_ops_prepare_finish(rkpm_prepare,rkpm_finish);
2490
2491     //rkpm_set_ops_regs_pread(interface_ctr_reg_pread);
2492
2493      rkpm_set_ops_save_setting(rkpm_save_setting,rkpm_save_setting_resume);
2494      rkpm_set_ops_regs_sleep(rkpm_slp_setting,rkpm_save_setting_resume_first);//rkpm_slp_setting
2495
2496     if(rockchip_pie_chunk)
2497         rkpm_set_sram_ops_printch(fn_to_pie(rockchip_pie_chunk, &FUNC(sram_printch)));
2498
2499     rkpm_set_ops_printch(ddr_printch);
2500 }