arch/arm/mach-rockchip/pm.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Tony Xie <tony.xie@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/regmap.h>
  22 #include <linux/suspend.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regulator/machine.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/tlbflush.h>
  28 #include <asm/suspend.h>
  29
  30 #include "pm.h"
  31
  32 /* These enum are option of low power mode */
  33 enum {
  34         ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
  35         ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
  36 };
  37
  38 struct rockchip_pm_data {
  39         const struct platform_suspend_ops *ops;
  40         int (*init)(struct device_node *np);
  41 };
  42
  43 static void __iomem *rk3288_bootram_base;
  44 static phys_addr_t rk3288_bootram_phy;
  45
  46 static struct regmap *pmu_regmap;
  47 static struct regmap *sgrf_regmap;
  48 static struct regmap *grf_regmap;
  49
  50 static u32 rk3288_pmu_pwr_mode_con;
  51 static u32 rk3288_sgrf_soc_con0;
  52 static u32 rk3288_sgrf_cpu_con0;
  53
  54 static inline u32 rk3288_l2_config(void)
  55 {
  56         u32 l2ctlr;
  57
  58         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
  59         return l2ctlr;
  60 }
  61
  62 static void rk3288_config_bootdata(void)
  63 {
  64         rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
  65         rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
  66
  67         rkpm_bootdata_l2ctlr_f  = 1;
  68         rkpm_bootdata_l2ctlr = rk3288_l2_config();
  69 }
  70
  71 #define GRF_UOC0_CON0                   0x320
  72 #define GRF_UOC1_CON0                   0x334
  73 #define GRF_UOC2_CON0                   0x348
  74 #define GRF_SIDDQ                       BIT(13)
  75
  76 static bool rk3288_slp_disable_osc(void)
  77 {
  78         static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
  79                                           GRF_UOC2_CON0 };
  80         u32 reg, i;
  81
  82         /*
  83          * if any usb phy is still on(GRF_SIDDQ==0), that means we need the
  84          * function of usb wakeup, so do not switch to 32khz, since the usb phy
  85          * clk does not connect to 32khz osc
  86          */
  87         for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
  88                 regmap_read(grf_regmap, reg_offset[i], &reg);
  89                 if (!(reg & GRF_SIDDQ))
  90                         return false;
  91         }
  92
  93         return true;
  94 }
  95
  96 static void rk3288_slp_mode_set(int level)
  97 {
  98         u32 mode_set, mode_set1;
  99         bool osc_switch_to_32k = rk3288_slp_disable_osc();
 100
 101         regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
 102         regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
 103
 104         regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
 105                     &rk3288_pmu_pwr_mode_con);
 106
 107         /*
 108          * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
 109          * PCLK_WDT_GATE - disable WDT during suspend.
 110          */
 111         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
 112                      SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
 113                      | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
 114
 115         /*
 116          * The dapswjdp can not auto reset before resume, that cause it may
 117          * access some illegal address during resume. Let's disable it before
 118          * suspend, and the MASKROM will enable it back.
 119          */
 120         regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
 121
 122         /* booting address of resuming system is from this register value */
 123         regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
 124                      rk3288_bootram_phy);
 125
 126         regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
 127                      PMU_ARMINT_WAKEUP_EN);
 128
 129         mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
 130                    BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
 131                    BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
 132                    BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
 133                    BIT(PMU_SCU_EN);
 134
 135         mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
 136
 137         if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
 138                 /* arm off, logic deep sleep */
 139                 mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
 140                             BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
 141                             BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
 142
 143                 if (osc_switch_to_32k)
 144                         mode_set |= BIT(PMU_OSC_24M_DIS);
 145
 146                 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
 147                              BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
 148         } else {
 149                 /*
 150                  * arm off, logic normal
 151                  * if pmu_clk_core_src_gate_en is not set,
 152                  * wakeup will be error
 153                  */
 154                 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
 155         }
 156
 157         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
 158         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
 159 }
 160
 161 static void rk3288_slp_mode_set_resume(void)
 162 {
 163         regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
 164                      rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
 165
 166         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
 167                      rk3288_pmu_pwr_mode_con);
 168
 169         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
 170                      rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
 171                      | SGRF_FAST_BOOT_EN_WRITE);
 172 }
 173
 174 static int rockchip_lpmode_enter(unsigned long arg)
 175 {
 176         flush_cache_all();
 177
 178         cpu_do_idle();
 179
 180         pr_err("%s: Failed to suspend\n", __func__);
 181
 182         return 1;
 183 }
 184
 185 static int rk3288_suspend_enter(suspend_state_t state)
 186 {
 187         local_fiq_disable();
 188
 189         rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
 190
 191         cpu_suspend(0, rockchip_lpmode_enter);
 192
 193         rk3288_slp_mode_set_resume();
 194
 195         local_fiq_enable();
 196
 197         return 0;
 198 }
 199
 200 static int rk3288_suspend_prepare(void)
 201 {
 202         return regulator_suspend_prepare(PM_SUSPEND_MEM);
 203 }
 204
 205 static void rk3288_suspend_finish(void)
 206 {
 207         if (regulator_suspend_finish())
 208                 pr_err("%s: Suspend finish failed\n", __func__);
 209 }
 210
 211 static int rk3288_suspend_init(struct device_node *np)
 212 {
 213         struct device_node *sram_np;
 214         struct resource res;
 215         int ret;
 216
 217         pmu_regmap = syscon_node_to_regmap(np);
 218         if (IS_ERR(pmu_regmap)) {
 219                 pr_err("%s: could not find pmu regmap\n", __func__);
 220                 return PTR_ERR(pmu_regmap);
 221         }
 222
 223         sgrf_regmap = syscon_regmap_lookup_by_compatible(
 224                                 "rockchip,rk3288-sgrf");
 225         if (IS_ERR(sgrf_regmap)) {
 226                 pr_err("%s: could not find sgrf regmap\n", __func__);
 227                 return PTR_ERR(pmu_regmap);
 228         }
 229
 230         grf_regmap = syscon_regmap_lookup_by_compatible(
 231                                 "rockchip,rk3288-grf");
 232         if (IS_ERR(grf_regmap)) {
 233                 pr_err("%s: could not find grf regmap\n", __func__);
 234                 return PTR_ERR(pmu_regmap);
 235         }
 236
 237         sram_np = of_find_compatible_node(NULL, NULL,
 238                                           "rockchip,rk3288-pmu-sram");
 239         if (!sram_np) {
 240                 pr_err("%s: could not find bootram dt node\n", __func__);
 241                 return -ENODEV;
 242         }
 243
 244         rk3288_bootram_base = of_iomap(sram_np, 0);
 245         if (!rk3288_bootram_base) {
 246                 pr_err("%s: could not map bootram base\n", __func__);
 247                 return -ENOMEM;
 248         }
 249
 250         ret = of_address_to_resource(sram_np, 0, &res);
 251         if (ret) {
 252                 pr_err("%s: could not get bootram phy addr\n", __func__);
 253                 return ret;
 254         }
 255         rk3288_bootram_phy = res.start;
 256
 257         of_node_put(sram_np);
 258
 259         rk3288_config_bootdata();
 260
 261         /* copy resume code and data to bootsram */
 262         memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
 263                rk3288_bootram_sz);
 264
 265         regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
 266         regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
 267
 268         return 0;
 269 }
 270
 271 static const struct platform_suspend_ops rk3288_suspend_ops = {
 272         .enter   = rk3288_suspend_enter,
 273         .valid   = suspend_valid_only_mem,
 274         .prepare = rk3288_suspend_prepare,
 275         .finish  = rk3288_suspend_finish,
 276 };
 277
 278 static const struct rockchip_pm_data rk3288_pm_data __initconst = {
 279         .ops = &rk3288_suspend_ops,
 280         .init = rk3288_suspend_init,
 281 };
 282
 283 static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
 284         {
 285                 .compatible = "rockchip,rk3288-pmu",
 286                 .data = &rk3288_pm_data,
 287         },
 288         { /* sentinel */ },
 289 };
 290
 291 void __init rockchip_suspend_init(void)
 292 {
 293         const struct rockchip_pm_data *pm_data;
 294         const struct of_device_id *match;
 295         struct device_node *np;
 296         int ret;
 297
 298         np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
 299                                              &match);
 300         if (!match) {
 301                 pr_err("Failed to find PMU node\n");
 302                 return;
 303         }
 304         pm_data = (struct rockchip_pm_data *) match->data;
 305
 306         if (pm_data->init) {
 307                 ret = pm_data->init(np);
 308
 309                 if (ret) {
 310                         pr_err("%s: matches init error %d\n", __func__, ret);
 311                         return;
 312                 }
 313         }
 314
 315         suspend_set_ops(pm_data->ops);
 316 }