2 * Device Tree support for Rockchip RK3036
4 * Copyright (C) 2014 ROCKCHIP, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clocksource.h>
19 #include <linux/cpuidle.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/rockchip/common.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/cru.h>
29 #include <linux/rockchip/dvfs.h>
30 #include <linux/rockchip/grf.h>
31 #include <linux/rockchip/iomap.h>
32 #include <linux/rockchip/pmu.h>
33 #include <asm/cpuidle.h>
34 #include <asm/cputype.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
43 #define RK3036_DEVICE(name) \
45 .virtual = (unsigned long) RK_##name##_VIRT, \
46 .pfn = __phys_to_pfn(RK3036_##name##_PHYS), \
47 .length = RK3036_##name##_SIZE, \
51 #define RK3036_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
52 #define RK3036_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
55 static struct map_desc rk3036_io_desc[] __initdata = {
61 RK_DEVICE(RK_DDR_VIRT, RK3036_DDR_PCTL_PHYS, RK3036_DDR_PCTL_SIZE),
62 RK_DEVICE(RK_DDR_VIRT + RK3036_DDR_PCTL_SIZE, RK3036_DDR_PHY_PHYS, RK3036_DDR_PHY_SIZE),
63 RK_DEVICE(RK_GPIO_VIRT(0), RK3036_GPIO0_PHYS, RK3036_GPIO_SIZE),
64 RK_DEVICE(RK_GPIO_VIRT(1), RK3036_GPIO1_PHYS, RK3036_GPIO_SIZE),
65 RK_DEVICE(RK_GPIO_VIRT(2), RK3036_GPIO2_PHYS, RK3036_GPIO_SIZE),
66 RK_DEVICE(RK_DEBUG_UART_VIRT, RK3036_UART2_PHYS, RK3036_UART_SIZE),
67 RK_DEVICE(RK_GIC_VIRT, RK3036_GIC_DIST_PHYS, RK3036_GIC_DIST_SIZE),
68 RK_DEVICE(RK_GIC_VIRT + RK3036_GIC_DIST_SIZE,RK3036_GIC_CPU_PHYS, RK3036_GIC_CPU_SIZE),
69 RK_DEVICE(RK_BOOTRAM_VIRT, RK3036_IMEM_PHYS, RK3036_IMEM_SIZE),
70 RK_DEVICE(RK3036_IMEM_VIRT, RK3036_IMEM_PHYS, SZ_4K),
71 RK_DEVICE(RK_TIMER_VIRT, RK3036_TIMER_PHYS, RK3036_TIMER_SIZE),
74 static void __init rk3036_boot_mode_init(void)
76 u32 flag = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG0);
77 u32 mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_OS_REG1);
78 u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3036_CRU_RST_ST);
80 if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
81 mode = BOOT_MODE_RECOVERY;
82 if (rst_st & ((1 << 2) | (1 << 3)))
83 mode = BOOT_MODE_WATCHDOG;
84 rockchip_boot_mode_init(flag, mode);
87 static void usb_uart_init(void)
92 static void __init rk3036_dt_map_io(void)
94 rockchip_soc_id = ROCKCHIP_SOC_RK3036;
96 iotable_init(rk3036_io_desc, ARRAY_SIZE(rk3036_io_desc));
100 /* enable timer5 for core */
101 writel_relaxed(0, RK3036_TIMER5_VIRT + 0x10);
103 writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x00);
104 writel_relaxed(0xFFFFFFFF, RK3036_TIMER5_VIRT + 0x04);
106 writel_relaxed(1, RK3036_TIMER5_VIRT + 0x10);
109 rk3036_boot_mode_init();
112 static int rk3036_sys_set_power_domain(enum pmu_power_domain pd, bool on)
117 static bool rk3036_pmu_power_domain_is_on(enum pmu_power_domain pd)
122 static int rk3036_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
127 static void __init rk3036_dt_init_timer(void)
129 rockchip_pmu_ops.set_power_domain = rk3036_sys_set_power_domain;
130 rockchip_pmu_ops.power_domain_is_on = rk3036_pmu_power_domain_is_on;
131 rockchip_pmu_ops.set_idle_request = rk3036_pmu_set_idle_request;
133 clocksource_of_init();
136 static void __init rk3036_init_late(void)
138 if (rockchip_jtag_enabled)
139 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
143 static void __init rk3036_reserve(void)
145 /* reserve memory for ION */
146 //rockchip_ion_reserve();
151 static void rk3036_restart(char mode, const char *cmd)
153 u32 boot_flag, boot_mode;
155 rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
157 writel_relaxed(boot_flag, RK_GRF_VIRT + RK3036_GRF_OS_REG0); // for loader
158 writel_relaxed(boot_mode, RK_GRF_VIRT + RK3036_GRF_OS_REG1); // for linux
161 /* pll enter slow mode */
162 //writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON);
164 //writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
168 static const char * const rk3036_dt_compat[] __initconst = {
173 DT_MACHINE_START(RK3036_DT, "Rockchip RK3036")
174 .dt_compat = rk3036_dt_compat,
175 .smp = smp_ops(rockchip_smp_ops),
176 .reserve = rk3036_reserve,
177 .map_io = rk3036_dt_map_io,
178 .init_time = rk3036_dt_init_timer,
179 .init_late = rk3036_init_late,
180 .reserve = rk3036_reserve,
181 .restart = rk3036_restart,