arch/arm/mach-rockchip/rk312x.c

   1 /*
   2  * Device Tree support for Rockchip RK3288
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/cpuidle.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/rockchip/common.h>
  27 #include <linux/rockchip/cpu.h>
  28 #include <linux/rockchip/cru.h>
  29 #include <linux/rockchip/dvfs.h>
  30 #include <linux/rockchip/grf.h>
  31 #include <linux/rockchip/iomap.h>
  32 #include <linux/rockchip/pmu.h>
  33 /*#include <asm/cpuidle.h>*/
  34 #include <asm/cputype.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include "cpu_axi.h"
  38 #include "loader.h"
  39 #define CPU 312x
  40 #include "sram.h"
  41 #include "pm.h"
  42 #include "pm-rk312x.c"
  43 #define RK312X_DEVICE(name) \
  44         { \
  45                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  46                 .pfn            = __phys_to_pfn(RK312X_##name##_PHYS), \
  47                 .length         = RK312X_##name##_SIZE, \
  48                 .type           = MT_DEVICE, \
  49         }
  50
  51 static const char * const rk3126_dt_compat[] __initconst = {
  52         "rockchip,rk3126",
  53         NULL,
  54 };
  55
  56 static const char * const rk3128_dt_compat[] __initconst = {
  57         "rockchip,rk3128",
  58         NULL,
  59 };
  60
  61 #define RK312X_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
  62 #define RK312X_TIMER5_VIRT (RK_TIMER_VIRT + 0xa0)
  63
  64 static struct map_desc rk312x_io_desc[] __initdata = {
  65         RK312X_DEVICE(CRU),
  66         RK312X_DEVICE(GRF),
  67         RK312X_DEVICE(ROM),
  68         RK312X_DEVICE(PMU),
  69         RK312X_DEVICE(EFUSE),
  70         RK312X_DEVICE(TIMER),
  71         RK312X_DEVICE(CPU_AXI_BUS),
  72         RK_DEVICE(RK_DEBUG_UART_VIRT, RK312X_UART2_PHYS, RK312X_UART_SIZE),
  73         RK_DEVICE(RK_DDR_VIRT, RK312X_DDR_PCTL_PHYS, RK312X_DDR_PCTL_SIZE),
  74         RK_DEVICE(RK_DDR_VIRT + RK312X_DDR_PCTL_SIZE, RK312X_DDR_PHY_PHYS, RK312X_DDR_PHY_SIZE),
  75         RK_DEVICE(RK_GPIO_VIRT(0), RK312X_GPIO0_PHYS, RK312X_GPIO_SIZE),
  76         RK_DEVICE(RK_GPIO_VIRT(1), RK312X_GPIO1_PHYS, RK312X_GPIO_SIZE),
  77         RK_DEVICE(RK_GPIO_VIRT(2), RK312X_GPIO2_PHYS, RK312X_GPIO_SIZE),
  78         RK_DEVICE(RK_GPIO_VIRT(3), RK312X_GPIO3_PHYS, RK312X_GPIO_SIZE),
  79         RK_DEVICE(RK_GIC_VIRT, RK312X_GIC_DIST_PHYS, RK312X_GIC_DIST_SIZE),
  80         RK_DEVICE(RK_GIC_VIRT + RK312X_GIC_DIST_SIZE, RK312X_GIC_CPU_PHYS, RK312X_GIC_CPU_SIZE),
  81         RK_DEVICE(RK312X_IMEM_VIRT, RK312X_IMEM_PHYS, RK312X_IMEM_SIZE),
  82         RK_DEVICE(RK_PWM_VIRT, RK312X_PWM_PHYS, RK312X_PWM_SIZE),
  83 };
  84
  85 static void __init rk312x_boot_mode_init(void)
  86 {
  87         u32 flag = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
  88         u32 mode = readl_relaxed(RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
  89         u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_RST_ST);
  90
  91         if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
  92                 mode = BOOT_MODE_RECOVERY;
  93         if (rst_st & ((1 << 2) | (1 << 3)))
  94                 mode = BOOT_MODE_WATCHDOG;
  95
  96         rockchip_boot_mode_init(flag, mode);
  97 }
  98
  99 static void usb_uart_init(void)
 100 {
 101 #ifdef CONFIG_RK_USB_UART
 102         u32 soc_status0 = readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_STATUS0);
 103 #endif
 104         writel_relaxed(0x34000000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 105 #ifdef CONFIG_RK_USB_UART
 106         if (!(soc_status0 & (1 << 5)) && (soc_status0 & (1 << 8))) {
 107                 /* software control usb phy enable */
 108                 writel_relaxed(0x007f0055, RK_GRF_VIRT + RK312X_GRF_UOC0_CON0);
 109                 writel_relaxed(0x34003000, RK_GRF_VIRT + RK312X_GRF_UOC1_CON4);
 110         }
 111 #endif
 112
 113         writel_relaxed(0x07, RK_DEBUG_UART_VIRT + 0x88);
 114         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 115         writel_relaxed(0x83, RK_DEBUG_UART_VIRT + 0x0c);
 116         writel_relaxed(0x0d, RK_DEBUG_UART_VIRT + 0x00);
 117         writel_relaxed(0x00, RK_DEBUG_UART_VIRT + 0x04);
 118         writel_relaxed(0x03, RK_DEBUG_UART_VIRT + 0x0c);
 119 }
 120
 121 static void __init rk312x_dt_map_io(void)
 122 {
 123         u32 v;
 124
 125         iotable_init(rk312x_io_desc, ARRAY_SIZE(rk312x_io_desc));
 126         debug_ll_io_init();
 127         usb_uart_init();
 128
 129         /* pmu reset by second global soft reset */
 130         v = readl_relaxed(RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 131         v &= ~(3 << 12);
 132         v |= 1 << 12;
 133         writel_relaxed(v, RK_CRU_VIRT + RK312X_CRU_GLB_CNT_TH);
 134
 135         /* enable timer5 for core */
 136         writel_relaxed(0, RK312X_TIMER5_VIRT + 0x10);
 137         dsb();
 138         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x00);
 139         writel_relaxed(0xFFFFFFFF, RK312X_TIMER5_VIRT + 0x04);
 140         dsb();
 141         writel_relaxed(1, RK312X_TIMER5_VIRT + 0x10);
 142         dsb();
 143         writel_relaxed(0x80000000, RK_CRU_VIRT + RK312X_CRU_MISC_CON);
 144         dsb();
 145
 146         rk312x_boot_mode_init();
 147 }
 148
 149 static void __init rk3126_dt_map_io(void)
 150 {
 151         rockchip_soc_id = ROCKCHIP_SOC_RK3126;
 152
 153         rk312x_dt_map_io();
 154 }
 155
 156 static void __init rk3128_dt_map_io(void)
 157 {
 158         rockchip_soc_id = ROCKCHIP_SOC_RK3128;
 159
 160         rk312x_dt_map_io();
 161 }
 162 static DEFINE_SPINLOCK(pmu_idle_lock);
 163 static const u8 pmu_idle_map[] = {
 164         [IDLE_REQ_PERI] = 0,
 165         [IDLE_REQ_VIDEO] = 1,
 166         [IDLE_REQ_VIO] = 2,
 167         [IDLE_REQ_GPU] = 3,
 168         [IDLE_REQ_CORE] = 4,
 169         [IDLE_REQ_SYS] = 5,
 170         [IDLE_REQ_MSCH] = 6,
 171         [IDLE_REQ_CRYPTO] = 7,
 172
 173 };
 174 static int rk312x_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
 175 {
 176         u32 val;
 177         unsigned long flags;
 178         u32 bit = pmu_idle_map[req];
 179         u32 idle_mask = BIT(bit) | BIT(bit + 16);
 180         u32 idle_target = (idle << bit) | (idle << (bit + 16));
 181         u32 mask = BIT(bit);
 182
 183         spin_lock_irqsave(&pmu_idle_lock, flags);
 184         val = pmu_readl(RK312X_PMU_IDLE_REQ);
 185         if (idle)
 186                 val |= mask;
 187         else
 188                 val &= ~mask;
 189         pmu_writel(val, RK312X_PMU_IDLE_REQ);
 190         dsb();
 191
 192         while (((pmu_readl(RK312X_PMU_IDLE_ST) & idle_mask) != idle_target))
 193                 ;
 194         spin_unlock_irqrestore(&pmu_idle_lock, flags);
 195         return 0;
 196 }
 197 static const u8 pmu_pd_map[] = {
 198         [PD_GPU] = 1,
 199         [PD_VIDEO] = 2,
 200         [PD_VIO] = 3,
 201 };
 202
 203 static const u8 pmu_st_map[] = {
 204         [PD_GPU] = 1,
 205         [PD_VIDEO] = 2,
 206         [PD_VIO] = 3,
 207 };
 208
 209 static noinline void rk312x_do_pmu_set_power_domain(enum pmu_power_domain domain
 210         , bool on)
 211 {
 212         u8 pd = pmu_pd_map[domain];
 213         u32 val = pmu_readl(RK312X_PMU_PWRDN_CON);
 214
 215         if (on)
 216                 val &= ~BIT(pd);
 217         else
 218                 val |=  BIT(pd);
 219         pmu_writel(val, RK312X_PMU_PWRDN_CON);
 220         dsb();
 221
 222         while ((pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
 223                 ;
 224 }
 225
 226 static bool rk312x_pmu_power_domain_is_on(enum pmu_power_domain pd)
 227 {
 228         /*1"b0: power on, 1'b1: power off*/
 229         return !(pmu_readl(RK312X_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
 230 }
 231 static DEFINE_SPINLOCK(pmu_pd_lock);
 232 static u32 rga_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 233 static u32 ebc_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 234 static u32 iep_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 235 static u32 lcdc0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 236 static u32 vip0_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 237 static u32 gpu_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 238 static u32 video_qos[RK312X_CPU_AXI_QOS_NUM_REGS];
 239
 240 #define SAVE_QOS(array, NAME) RK312X_CPU_AXI_SAVE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 241 #define RESTORE_QOS(array, NAME) RK312X_CPU_AXI_RESTORE_QOS(array, RK312X_CPU_AXI_##NAME##_QOS_VIRT)
 242
 243 static int rk312x_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
 244 {
 245         unsigned long flags;
 246
 247         spin_lock_irqsave(&pmu_pd_lock, flags);
 248         if (rk312x_pmu_power_domain_is_on(pd) == on)
 249                 goto out;
 250         if (!on) {
 251                 if (pd == PD_GPU) {
 252                         SAVE_QOS(gpu_qos, GPU);
 253                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, true);
 254                 } else if (pd == PD_VIO) {
 255                         SAVE_QOS(rga_qos, VIO_RGA);
 256                         SAVE_QOS(ebc_qos, VIO_EBC);
 257                         SAVE_QOS(iep_qos, VIO_IEP);
 258                         SAVE_QOS(lcdc0_qos, VIO_LCDC0);
 259                         SAVE_QOS(vip0_qos, VIO_VIP0);
 260                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, true);
 261                 } else if (pd == PD_VIDEO) {
 262                         SAVE_QOS(video_qos, VIDEO);
 263                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 264                 }
 265         }
 266
 267         rk312x_do_pmu_set_power_domain(pd, on);
 268
 269         if (on) {
 270                 if (pd == PD_GPU) {
 271                         rk312x_pmu_set_idle_request(IDLE_REQ_GPU, false);
 272                         RESTORE_QOS(gpu_qos, GPU);
 273                 } else if (pd == PD_VIO) {
 274                         rk312x_pmu_set_idle_request(IDLE_REQ_VIO, false);
 275                         RESTORE_QOS(rga_qos, VIO_RGA);
 276                         RESTORE_QOS(ebc_qos, VIO_EBC);
 277                         RESTORE_QOS(iep_qos, VIO_IEP);
 278                         RESTORE_QOS(lcdc0_qos, VIO_LCDC0);
 279                         RESTORE_QOS(vip0_qos, VIO_VIP0);
 280                 } else if (pd == PD_VIDEO) {
 281                         rk312x_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 282                         RESTORE_QOS(video_qos, VIDEO);
 283                 }
 284         }
 285 out:
 286         spin_unlock_irqrestore(&pmu_pd_lock, flags);
 287
 288         return 0;
 289 }
 290 extern void secondary_startup(void);
 291 static int rk312x_sys_set_power_domain(enum pmu_power_domain pd, bool on)
 292 {
 293         u32 clks_save[RK312X_CRU_CLKGATES_CON_CNT];
 294         u32 clks_ungating[RK312X_CRU_CLKGATES_CON_CNT];
 295         u32 i, ret = 0;
 296
 297         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 298                 clks_save[i] = cru_readl(RK312X_CRU_CLKGATES_CON(i));
 299                 clks_ungating[i] = 0;
 300         }
 301         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++)
 302                 cru_writel(0xffff0000, RK312X_CRU_CLKGATES_CON(i));
 303
 304         if (on) {
 305 #ifdef CONFIG_SMP
 306                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 307                         writel_relaxed(0x20000 << (pd - PD_CPU_1),
 308                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 309                         dsb();
 310                         udelay(10);
 311                         writel_relaxed(virt_to_phys(secondary_startup),
 312                                        RK312X_IMEM_VIRT + 8);
 313                         writel_relaxed(0xDEADBEAF, RK312X_IMEM_VIRT + 4);
 314                         dsb_sev();
 315                 }
 316 #endif
 317         } else {
 318 #ifdef CONFIG_SMP
 319                 if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
 320                         writel_relaxed(0x20002 << (pd - PD_CPU_1),
 321                                        RK_CRU_VIRT + RK312X_CRU_SOFTRSTS_CON(0));
 322                         dsb();
 323                 }
 324 #endif
 325         }
 326
 327         if (((pd == PD_GPU) || (pd == PD_VIO) || (pd == PD_VIDEO)))
 328                 ret = rk312x_pmu_set_power_domain(pd, on);
 329
 330         for (i = 0; i < RK312X_CRU_CLKGATES_CON_CNT; i++) {
 331                 cru_writel(clks_save[i] | 0xffff0000
 332                         , RK312X_CRU_CLKGATES_CON(i));
 333         }
 334
 335         return ret;
 336 }
 337
 338 static void __init rk312x_dt_init_timer(void)
 339 {
 340         rockchip_pmu_ops.set_power_domain = rk312x_sys_set_power_domain;
 341         rockchip_pmu_ops.power_domain_is_on = rk312x_pmu_power_domain_is_on;
 342         rockchip_pmu_ops.set_idle_request = rk312x_pmu_set_idle_request;
 343         of_clk_init(NULL);
 344         clocksource_of_init();
 345         of_dvfs_init();
 346 }
 347
 348 static void __init rk312x_reserve(void)
 349 {
 350         /* reserve memory for ION */
 351         rockchip_ion_reserve();
 352 }
 353 #ifdef CONFIG_PM
 354 static void __init rk321x_init_suspend(void);
 355 #endif
 356 static void __init rk312x_init_late(void)
 357 {
 358 #ifdef CONFIG_PM
 359         rk321x_init_suspend();
 360 #endif
 361 }
 362
 363 static void rk312x_restart(char mode, const char *cmd)
 364 {
 365         u32 boot_flag, boot_mode;
 366
 367         rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
 368
 369         /* for loader */
 370         writel_relaxed(boot_flag, RK_PMU_VIRT + RK312X_PMU_SYS_REG0);
 371         /* for linux */
 372         writel_relaxed(boot_mode, RK_PMU_VIRT + RK312X_PMU_SYS_REG1);
 373
 374         dsb();
 375
 376         /* pll enter slow mode */
 377         writel_relaxed(0x11010000, RK_CRU_VIRT + RK312X_CRU_MODE_CON);
 378         dsb();
 379         writel_relaxed(0xeca8, RK_CRU_VIRT + RK312X_CRU_GLB_SRST_SND_VALUE);
 380         dsb();
 381 }
 382
 383 DT_MACHINE_START(RK3126_DT, "Rockchip RK3126")
 384         .smp            = smp_ops(rockchip_smp_ops),
 385         .map_io         = rk3126_dt_map_io,
 386         .init_time      = rk312x_dt_init_timer,
 387         .dt_compat      = rk3126_dt_compat,
 388         .init_late      = rk312x_init_late,
 389         .reserve        = rk312x_reserve,
 390         .restart        = rk312x_restart,
 391 MACHINE_END
 392
 393 DT_MACHINE_START(RK3128_DT, "Rockchip RK3128")
 394         .smp            = smp_ops(rockchip_smp_ops),
 395         .map_io         = rk3128_dt_map_io,
 396         .init_time      = rk312x_dt_init_timer,
 397         .dt_compat      = rk3128_dt_compat,
 398         .init_late      = rk312x_init_late,
 399         .reserve        = rk312x_reserve,
 400         .restart        = rk312x_restart,
 401 MACHINE_END
 402
 403
 404 char PIE_DATA(sram_stack)[1024];
 405 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 406
 407 static int __init rk312x_pie_init(void)
 408 {
 409         int err;
 410
 411         if (!cpu_is_rk312x())
 412                 return 0;
 413
 414         err = rockchip_pie_init();
 415         if (err)
 416                 return err;
 417
 418         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk312x);
 419         if (IS_ERR(rockchip_pie_chunk)) {
 420                 err = PTR_ERR(rockchip_pie_chunk);
 421                 pr_err("%s: failed to load section %d\n", __func__, err);
 422                 rockchip_pie_chunk = NULL;
 423                 return err;
 424         }
 425
 426         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 427         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *)DATA(sram_stack) + sizeof(DATA(sram_stack)));
 428
 429         return 0;
 430 }
 431 arch_initcall(rk312x_pie_init);
 432
 433 #include "ddr_rk3126.c"
 434 static int __init rk312x_ddr_init(void)
 435 {
 436         if (cpu_is_rk312x()) {
 437                 ddr_change_freq = _ddr_change_freq;
 438                 ddr_round_rate = _ddr_round_rate;
 439                 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
 440                 ddr_bandwidth_get = _ddr_bandwidth_get;
 441                 ddr_init(DDR3_DEFAULT, 300);
 442                 }
 443         return 0;
 444 }
 445 arch_initcall_sync(rk312x_ddr_init);
 446
 447 #ifdef CONFIG_PM
 448 static u32 rk_pmu_pwrdn_st;
 449 static inline void rk_pm_soc_pd_suspend(void)
 450 {
 451         rk_pmu_pwrdn_st = pmu_readl(RK312X_PMU_PWRDN_ST);
 452         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 453                 rk312x_sys_set_power_domain(PD_GPU, false);
 454
 455         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 456                 rk312x_sys_set_power_domain(PD_VIO, false);
 457
 458         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 459                 rk312x_sys_set_power_domain(PD_VIDEO, false);
 460 }
 461 static inline void rk_pm_soc_pd_resume(void)
 462 {
 463         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIDEO])))
 464                 rk312x_sys_set_power_domain(PD_VIDEO, true);
 465
 466         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_VIO])))
 467                 rk312x_sys_set_power_domain(PD_VIO, true);
 468
 469         if (!(rk_pmu_pwrdn_st & BIT(pmu_st_map[PD_GPU])))
 470                 rk312x_sys_set_power_domain(PD_GPU, true);
 471 }
 472 static void __init rk321x_init_suspend(void)
 473 {
 474         pr_info("%s\n", __func__);
 475         rockchip_suspend_init();
 476         rkpm_pie_init();
 477         rk312x_suspend_init();
 478         rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend, rk_pm_soc_pd_resume);
 479 }
 480 #endif