arch/arm/mach-rockchip/rk3188.c

   1 /*
   2  * Device Tree support for Rockchip RK3188
   3  *
   4  * Copyright (C) 2013 ROCKCHIP, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk-provider.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/init.h>
  20 #include <linux/irqchip.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_platform.h>
  24 #include <asm/mach/arch.h>
  25 #include <asm/mach/map.h>
  26 #include "core.h"
  27 #include "cpu.h"
  28 #include "cpu_axi.h"
  29 #include "grf.h"
  30 #include "iomap.h"
  31 #include "sram.h"
  32
  33 #define RK3188_DEVICE(name) \
  34         { \
  35                 .virtual        = (unsigned long) RK_##name##_VIRT, \
  36                 .pfn            = __phys_to_pfn(RK3188_##name##_PHYS), \
  37                 .length         = RK3188_##name##_SIZE, \
  38                 .type           = MT_DEVICE, \
  39         }
  40
  41 static struct map_desc rk3188_io_desc[] __initdata = {
  42         RK3188_DEVICE(CRU),
  43         RK3188_DEVICE(GRF),
  44         RK3188_DEVICE(PMU),
  45         RK3188_DEVICE(ROM),
  46         RK3188_DEVICE(EFUSE),
  47         RK3188_DEVICE(CPU_AXI_BUS),
  48         {
  49                 .virtual        = (unsigned long) RK_DDR_VIRT,
  50                 .pfn            = __phys_to_pfn(RK3188_DDR_PCTL_PHYS),
  51                 .length         = RK3188_DDR_PCTL_SIZE,
  52                 .type           = MT_DEVICE,
  53         },
  54         {
  55                 .virtual        = (unsigned long) RK_DDR_VIRT + RK3188_DDR_PCTL_SIZE,
  56                 .pfn            = __phys_to_pfn(RK3188_DDR_PUBL_PHYS),
  57                 .length         = RK3188_DDR_PUBL_SIZE,
  58                 .type           = MT_DEVICE,
  59         },
  60         {
  61                 .virtual        = (unsigned long) RK_GPIO_VIRT(0),
  62                 .pfn            = __phys_to_pfn(RK3188_GPIO0_PHYS),
  63                 .length         = RK3188_GPIO_SIZE,
  64                 .type           = MT_DEVICE,
  65         },
  66         {
  67                 .virtual        = (unsigned long) RK_GPIO_VIRT(1),
  68                 .pfn            = __phys_to_pfn(RK3188_GPIO1_PHYS),
  69                 .length         = RK3188_GPIO_SIZE,
  70                 .type           = MT_DEVICE,
  71         },
  72         {
  73                 .virtual        = (unsigned long) RK_GPIO_VIRT(2),
  74                 .pfn            = __phys_to_pfn(RK3188_GPIO2_PHYS),
  75                 .length         = RK3188_GPIO_SIZE,
  76                 .type           = MT_DEVICE,
  77         },
  78         {
  79                 .virtual        = (unsigned long) RK_GPIO_VIRT(3),
  80                 .pfn            = __phys_to_pfn(RK3188_GPIO3_PHYS),
  81                 .length         = RK3188_GPIO_SIZE,
  82                 .type           = MT_DEVICE,
  83         },
  84 };
  85
  86 static void __init rk3188_dt_map_io(void)
  87 {
  88         preset_lpj = 11996091ULL / 2;
  89         iotable_init(rk3188_io_desc, ARRAY_SIZE(rk3188_io_desc));
  90         debug_ll_io_init();
  91
  92         rockchip_soc_id = ROCKCHIP_SOC_RK3188;
  93         if (readl_relaxed(RK_ROM_VIRT + 0x27f0) == 0x33313042
  94          && readl_relaxed(RK_ROM_VIRT + 0x27f4) == 0x32303133
  95          && readl_relaxed(RK_ROM_VIRT + 0x27f8) == 0x30313331
  96          && readl_relaxed(RK_ROM_VIRT + 0x27fc) == 0x56313031)
  97                 rockchip_soc_id = ROCKCHIP_SOC_RK3188PLUS;
  98
  99         /* rki2c is used instead of old i2c */
 100         writel_relaxed(0xF800F800, RK_GRF_VIRT + RK3188_GRF_SOC_CON1);
 101 }
 102
 103 static void __init rk3188_dt_init_timer(void)
 104 {
 105         of_clk_init(NULL);
 106         clocksource_of_init();
 107 }
 108
 109 static const char * const rk3188_dt_compat[] = {
 110         "rockchip,rk3188",
 111         NULL,
 112 };
 113
 114 DT_MACHINE_START(RK3188_DT, "Rockchip RK3188 (Flattened Device Tree)")
 115         .smp            = smp_ops(rockchip_smp_ops),
 116         .map_io         = rk3188_dt_map_io,
 117         .init_time      = rk3188_dt_init_timer,
 118         .dt_compat      = rk3188_dt_compat,
 119 MACHINE_END
 120
 121 #define CPU 3188
 122 char PIE_DATA(sram_stack)[1024];
 123 EXPORT_PIE_SYMBOL(DATA(sram_stack));
 124
 125 static int __init rk3188_pie_init(void)
 126 {
 127         int err;
 128
 129         if (!cpu_is_rk3188())
 130                 return 0;
 131
 132         err = rockchip_pie_init();
 133         if (err)
 134                 return err;
 135
 136         rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3188);
 137         if (IS_ERR(rockchip_pie_chunk)) {
 138                 err = PTR_ERR(rockchip_pie_chunk);
 139                 pr_err("%s: failed to load section %d\n", __func__, err);
 140                 rockchip_pie_chunk = NULL;
 141                 return err;
 142         }
 143
 144         rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
 145         rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
 146
 147         return 0;
 148 }
 149 arch_initcall(rk3188_pie_init);
 150
 151 #define CONFIG_ARCH_RK3188
 152 #define RK30_DDR_PCTL_BASE RK_DDR_VIRT
 153 #define RK30_DDR_PUBL_BASE (RK_DDR_VIRT + RK3188_DDR_PCTL_SIZE)
 154 #define rk_pll_flag() 0 /* FIXME */
 155 #define sram_printascii(s) do {} while (0) /* FIXME */
 156 #include "ddr_rk30.c"
 157
 158 static int rk3188_ddr_init(void)
 159 {
 160         if (cpu_is_rk3188())
 161                 ddr_init(DDR3_DEFAULT, 300);
 162         return 0;
 163 }
 164 arch_initcall_sync(rk3188_ddr_init);