2 * Device Tree support for Rockchip RK3288
4 * Copyright (C) 2014 ROCKCHIP, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk-provider.h>
18 #include <linux/clocksource.h>
19 #include <linux/cpuidle.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_platform.h>
26 #include <linux/rockchip/common.h>
27 #include <linux/rockchip/cpu.h>
28 #include <linux/rockchip/cpu_axi.h>
29 #include <linux/rockchip/cru.h>
30 #include <linux/rockchip/dvfs.h>
31 #include <linux/rockchip/grf.h>
32 #include <linux/rockchip/iomap.h>
33 #include <linux/rockchip/pmu.h>
35 #include <asm/cpuidle.h>
36 #include <asm/cputype.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/map.h>
44 #define RK3288_DEVICE(name) \
46 .virtual = (unsigned long) RK_##name##_VIRT, \
47 .pfn = __phys_to_pfn(RK3288_##name##_PHYS), \
48 .length = RK3288_##name##_SIZE, \
52 #define RK3288_SERVICE_DEVICE(name) \
53 RK_DEVICE(RK3288_SERVICE_##name##_VIRT, RK3288_SERVICE_##name##_PHYS, RK3288_SERVICE_##name##_SIZE)
55 #define RK3288_IMEM_VIRT (RK_BOOTRAM_VIRT + SZ_32K)
56 #define RK3288_TIMER7_VIRT (RK_TIMER_VIRT + 0x20)
58 static struct map_desc rk3288_io_desc[] __initdata = {
65 RK3288_SERVICE_DEVICE(CORE),
66 RK3288_SERVICE_DEVICE(DMAC),
67 RK3288_SERVICE_DEVICE(GPU),
68 RK3288_SERVICE_DEVICE(PERI),
69 RK3288_SERVICE_DEVICE(VIO),
70 RK3288_SERVICE_DEVICE(VIDEO),
71 RK3288_SERVICE_DEVICE(HEVC),
72 RK3288_SERVICE_DEVICE(BUS),
73 RK_DEVICE(RK_DDR_VIRT, RK3288_DDR_PCTL0_PHYS, RK3288_DDR_PCTL_SIZE),
74 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE, RK3288_DDR_PUBL0_PHYS, RK3288_DDR_PUBL_SIZE),
75 RK_DEVICE(RK_DDR_VIRT + RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PCTL1_PHYS, RK3288_DDR_PCTL_SIZE),
76 RK_DEVICE(RK_DDR_VIRT + 2 * RK3288_DDR_PCTL_SIZE + RK3288_DDR_PUBL_SIZE, RK3288_DDR_PUBL1_PHYS, RK3288_DDR_PUBL_SIZE),
77 RK_DEVICE(RK_GPIO_VIRT(0), RK3288_GPIO0_PHYS, RK3288_GPIO_SIZE),
78 RK_DEVICE(RK_GPIO_VIRT(1), RK3288_GPIO1_PHYS, RK3288_GPIO_SIZE),
79 RK_DEVICE(RK_GPIO_VIRT(2), RK3288_GPIO2_PHYS, RK3288_GPIO_SIZE),
80 RK_DEVICE(RK_GPIO_VIRT(3), RK3288_GPIO3_PHYS, RK3288_GPIO_SIZE),
81 RK_DEVICE(RK_GPIO_VIRT(4), RK3288_GPIO4_PHYS, RK3288_GPIO_SIZE),
82 RK_DEVICE(RK_GPIO_VIRT(5), RK3288_GPIO5_PHYS, RK3288_GPIO_SIZE),
83 RK_DEVICE(RK_GPIO_VIRT(6), RK3288_GPIO6_PHYS, RK3288_GPIO_SIZE),
84 RK_DEVICE(RK_GPIO_VIRT(7), RK3288_GPIO7_PHYS, RK3288_GPIO_SIZE),
85 RK_DEVICE(RK_GPIO_VIRT(8), RK3288_GPIO8_PHYS, RK3288_GPIO_SIZE),
86 RK_DEVICE(RK_DEBUG_UART_VIRT, RK3288_UART_DBG_PHYS, RK3288_UART_SIZE),
87 RK_DEVICE(RK_GIC_VIRT, RK3288_GIC_DIST_PHYS, RK3288_GIC_DIST_SIZE),
88 RK_DEVICE(RK_GIC_VIRT + RK3288_GIC_DIST_SIZE, RK3288_GIC_CPU_PHYS, RK3288_GIC_CPU_SIZE),
89 RK_DEVICE(RK_BOOTRAM_VIRT, RK3288_BOOTRAM_PHYS, RK3288_BOOTRAM_SIZE),
90 RK_DEVICE(RK3288_IMEM_VIRT, RK3288_IMEM_PHYS, SZ_4K),
91 RK_DEVICE(RK_TIMER_VIRT, RK3288_TIMER6_PHYS, RK3288_TIMER_SIZE),
94 static void __init rk3288_boot_mode_init(void)
96 u32 flag = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG0);
97 u32 mode = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_SYS_REG1);
98 u32 rst_st = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_ST);
100 if (flag == (SYS_KERNRL_REBOOT_FLAG | BOOT_RECOVER))
101 mode = BOOT_MODE_RECOVERY;
102 if (rst_st & ((1 << 4) | (1 << 5)))
103 mode = BOOT_MODE_WATCHDOG;
104 else if (rst_st & ((1 << 2) | (1 << 3)))
105 mode = BOOT_MODE_TSADC;
106 rockchip_boot_mode_init(flag, mode);
109 static void usb_uart_init(void)
113 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
114 soc_status2 = (readl_relaxed(RK_GRF_VIRT + RK3288_GRF_SOC_STATUS2));
116 #ifdef CONFIG_RK_USB_UART
117 if (!(soc_status2 & (1<<14)) && (soc_status2 & (1<<17))) {
118 /* software control usb phy enable */
119 writel_relaxed(0x00040004, RK_GRF_VIRT + RK3288_GRF_UOC0_CON2);
120 /* usb phy enter suspend */
121 writel_relaxed(0x003f002a, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
122 writel_relaxed(0x00c000c0, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
127 extern void secondary_startup(void);
129 static void __init rk3288_dt_map_io(void)
133 rockchip_soc_id = ROCKCHIP_SOC_RK3288;
135 iotable_init(rk3288_io_desc, ARRAY_SIZE(rk3288_io_desc));
139 /* pmu reset by second global soft reset */
140 v = readl_relaxed(RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
143 writel_relaxed(v, RK_CRU_VIRT + RK3288_CRU_GLB_RST_CON);
145 /* rkpwm is used instead of old pwm */
146 writel_relaxed(0x00010001, RK_GRF_VIRT + RK3288_GRF_SOC_CON2);
148 /* disable address remap */
149 #ifndef CONFIG_ARM_TRUSTZONE
150 writel_relaxed(0x08000000, RK_SGRF_VIRT + RK3288_SGRF_SOC_CON0);
153 /* enable timer7 for core */
154 writel_relaxed(0, RK3288_TIMER7_VIRT + 0x10);
156 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x00);
157 writel_relaxed(0xFFFFFFFF, RK3288_TIMER7_VIRT + 0x04);
159 writel_relaxed(1, RK3288_TIMER7_VIRT + 0x10);
162 /* power up/down GPU domain wait 1us */
163 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRDWN_CNT);
164 writel_relaxed(24, RK_PMU_VIRT + RK3288_PMU_GPU_PWRUP_CNT);
166 rk3288_boot_mode_init();
167 #ifndef CONFIG_ARM_TRUSTZONE
168 rockchip_efuse_init();
172 static const u8 pmu_st_map[] = {
186 static bool rk3288_pmu_power_domain_is_on(enum pmu_power_domain pd)
188 /* 1'b0: power on, 1'b1: power off */
189 return !(readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[pd]));
192 static DEFINE_SPINLOCK(pmu_idle_lock);
194 static const u8 pmu_idle_map[] = {
198 [IDLE_REQ_VIDEO] = 3,
201 [IDLE_REQ_ALIVE] = 6,
207 static int rk3288_pmu_set_idle_request(enum pmu_idle_req req, bool idle)
209 u32 bit = pmu_idle_map[req];
210 u32 idle_mask = BIT(bit) | BIT(bit + 16);
211 u32 idle_target = (idle << bit) | (idle << (bit + 16));
216 spin_lock_irqsave(&pmu_idle_lock, flags);
217 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
222 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_IDLE_REQ);
225 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_IDLE_ST) & idle_mask) != idle_target)
227 spin_unlock_irqrestore(&pmu_idle_lock, flags);
232 static const u8 pmu_pd_map[] = {
246 static DEFINE_SPINLOCK(pmu_pd_lock);
248 static noinline void rk3288_do_pmu_set_power_domain(enum pmu_power_domain domain, bool on)
250 u8 pd = pmu_pd_map[domain];
251 u32 val = readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
256 writel_relaxed(val, RK_PMU_VIRT + RK3288_PMU_PWRDN_CON);
259 while ((readl_relaxed(RK_PMU_VIRT + RK3288_PMU_PWRDN_ST) & BIT(pmu_st_map[domain])) == on)
263 static u32 gpu_r_qos[CPU_AXI_QOS_NUM_REGS];
264 static u32 gpu_w_qos[CPU_AXI_QOS_NUM_REGS];
265 static u32 vio0_iep_qos[CPU_AXI_QOS_NUM_REGS];
266 static u32 vio0_vip_qos[CPU_AXI_QOS_NUM_REGS];
267 static u32 vio0_vop_qos[CPU_AXI_QOS_NUM_REGS];
268 static u32 vio1_isp_r_qos[CPU_AXI_QOS_NUM_REGS];
269 static u32 vio1_isp_w0_qos[CPU_AXI_QOS_NUM_REGS];
270 static u32 vio1_isp_w1_qos[CPU_AXI_QOS_NUM_REGS];
271 static u32 vio1_vop_qos[CPU_AXI_QOS_NUM_REGS];
272 static u32 vio2_rga_r_qos[CPU_AXI_QOS_NUM_REGS];
273 static u32 vio2_rga_w_qos[CPU_AXI_QOS_NUM_REGS];
274 static u32 video_qos[CPU_AXI_QOS_NUM_REGS];
275 static u32 hevc_r_qos[CPU_AXI_QOS_NUM_REGS];
276 static u32 hevc_w_qos[CPU_AXI_QOS_NUM_REGS];
278 #define SAVE_QOS(array, NAME) CPU_AXI_SAVE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
279 #define RESTORE_QOS(array, NAME) CPU_AXI_RESTORE_QOS(array, RK3288_CPU_AXI_##NAME##_QOS_VIRT)
281 static int rk3288_pmu_set_power_domain(enum pmu_power_domain pd, bool on)
285 spin_lock_irqsave(&pmu_pd_lock, flags);
286 if (rk3288_pmu_power_domain_is_on(pd) == on)
290 /* if power down, idle request to NIU first */
292 SAVE_QOS(vio0_iep_qos, VIO0_IEP);
293 SAVE_QOS(vio0_vip_qos, VIO0_VIP);
294 SAVE_QOS(vio0_vop_qos, VIO0_VOP);
295 SAVE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
296 SAVE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
297 SAVE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
298 SAVE_QOS(vio1_vop_qos, VIO1_VOP);
299 SAVE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
300 SAVE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
301 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, true);
302 } else if (pd == PD_VIDEO) {
303 SAVE_QOS(video_qos, VIDEO);
304 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, true);
305 } else if (pd == PD_GPU) {
306 SAVE_QOS(gpu_r_qos, GPU_R);
307 SAVE_QOS(gpu_w_qos, GPU_W);
308 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, true);
309 } else if (pd == PD_HEVC) {
310 SAVE_QOS(hevc_r_qos, HEVC_R);
311 SAVE_QOS(hevc_w_qos, HEVC_W);
312 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, true);
313 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
314 writel_relaxed(0x20002 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
317 else if (pd == PD_PERI) {
318 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, true);
323 rk3288_do_pmu_set_power_domain(pd, on);
326 /* if power up, idle request release to NIU */
328 rk3288_pmu_set_idle_request(IDLE_REQ_VIO, false);
329 RESTORE_QOS(vio0_iep_qos, VIO0_IEP);
330 RESTORE_QOS(vio0_vip_qos, VIO0_VIP);
331 RESTORE_QOS(vio0_vop_qos, VIO0_VOP);
332 RESTORE_QOS(vio1_isp_r_qos, VIO1_ISP_R);
333 RESTORE_QOS(vio1_isp_w0_qos, VIO1_ISP_W0);
334 RESTORE_QOS(vio1_isp_w1_qos, VIO1_ISP_W1);
335 RESTORE_QOS(vio1_vop_qos, VIO1_VOP);
336 RESTORE_QOS(vio2_rga_r_qos, VIO2_RGA_R);
337 RESTORE_QOS(vio2_rga_w_qos, VIO2_RGA_W);
338 } else if (pd == PD_VIDEO) {
339 rk3288_pmu_set_idle_request(IDLE_REQ_VIDEO, false);
340 RESTORE_QOS(video_qos, VIDEO);
341 } else if (pd == PD_GPU) {
342 rk3288_pmu_set_idle_request(IDLE_REQ_GPU, false);
343 RESTORE_QOS(gpu_r_qos, GPU_R);
344 RESTORE_QOS(gpu_w_qos, GPU_W);
345 } else if (pd == PD_HEVC) {
346 rk3288_pmu_set_idle_request(IDLE_REQ_HEVC, false);
347 RESTORE_QOS(hevc_r_qos, HEVC_R);
348 RESTORE_QOS(hevc_w_qos, HEVC_W);
349 } else if (pd >= PD_CPU_1 && pd <= PD_CPU_3) {
351 writel_relaxed(0x20000 << (pd - PD_CPU_1), RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(0));
354 writel_relaxed(virt_to_phys(secondary_startup), RK3288_IMEM_VIRT + 8);
355 writel_relaxed(0xDEADBEAF, RK3288_IMEM_VIRT + 4);
359 else if (pd == PD_PERI) {
360 rk3288_pmu_set_idle_request(IDLE_REQ_PERI, false);
365 spin_unlock_irqrestore(&pmu_pd_lock, flags);
369 static int rk3288_sys_set_power_domain(enum pmu_power_domain pd, bool on)
371 u32 clks_ungating[RK3288_CRU_CLKGATES_CON_CNT];
372 u32 clks_save[RK3288_CRU_CLKGATES_CON_CNT];
375 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
376 clks_save[i] = cru_readl(RK3288_CRU_CLKGATES_CON(i));
377 clks_ungating[i] = 0;
383 clks_ungating[5] = 1 << 7;
385 clks_ungating[18] = 1 << 0;
388 /* aclk_vdpu_src hclk_vpu aclk_vepu_src */
389 clks_ungating[3] = 1 << 11 | 1 << 10 | 1 << 9;
390 /* hclk_video aclk_video */
391 clks_ungating[9] = 1 << 1 | 1 << 0;
394 /* aclk_lcdc0/1_src dclk_lcdc0/1_src rga_core aclk_rga_src */
395 /* edp_24m edp isp isp_jpeg */
397 1 << 0 | 1 << 1 | 1 << 2 | 1 << 3 | 1 << 4 | 1 << 5 |
398 1 << 12 | 1 << 13 | 1 << 14 | 1 << 15;
399 clks_ungating[15] = 0xffff;
400 clks_ungating[16] = 0x0fff;
403 /* hevc_core hevc_cabac aclk_hevc */
404 clks_ungating[13] = 1 << 15 | 1 << 14 | 1 << 13;
408 clks_ungating[12] = 1 << 11 | 1 < 10 | 1 << 9 | 1 << 8;
415 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
416 if (clks_ungating[i])
417 cru_writel(clks_ungating[i] << 16, RK3288_CRU_CLKGATES_CON(i));
420 ret = rk3288_pmu_set_power_domain(pd, on);
422 for (i = 0; i < RK3288_CRU_CLKGATES_CON_CNT; i++) {
423 if (clks_ungating[i])
424 cru_writel(clks_save[i] | 0xffff0000, RK3288_CRU_CLKGATES_CON(i));
430 static void __init rk3288_dt_init_timer(void)
432 rockchip_pmu_ops.set_power_domain = rk3288_sys_set_power_domain;
433 rockchip_pmu_ops.power_domain_is_on = rk3288_pmu_power_domain_is_on;
434 rockchip_pmu_ops.set_idle_request = rk3288_pmu_set_idle_request;
436 clocksource_of_init();
440 static void __init rk3288_reserve(void)
442 /* reserve memory for uboot */
443 rockchip_uboot_mem_reserve();
445 /* reserve memory for ION */
446 rockchip_ion_reserve();
449 static const char * const rk3288_dt_compat[] __initconst = {
454 static void rk3288_restart(char mode, const char *cmd)
456 u32 boot_flag, boot_mode;
458 rockchip_restart_get_boot_mode(cmd, &boot_flag, &boot_mode);
460 writel_relaxed(boot_flag, RK_PMU_VIRT + RK3288_PMU_SYS_REG0); // for loader
461 writel_relaxed(boot_mode, RK_PMU_VIRT + RK3288_PMU_SYS_REG1); // for linux
464 /* pll enter slow mode */
465 writel_relaxed(0xf3030000, RK_CRU_VIRT + RK3288_CRU_MODE_CON);
467 writel_relaxed(0xeca8, RK_CRU_VIRT + RK3288_CRU_GLB_SRST_SND_VALUE);
471 static struct cpuidle_driver rk3288_cpuidle_driver = {
472 .name = "rk3288_cpuidle",
473 .owner = THIS_MODULE,
474 .states[0] = ARM_CPUIDLE_WFI_STATE,
478 static int rk3288_cpuidle_enter(struct cpuidle_device *dev,
479 struct cpuidle_driver *drv, int index)
481 void *sel = RK_CRU_VIRT + RK3288_CRU_CLKSELS_CON(36);
482 u32 con = readl_relaxed(sel);
483 u32 cpu = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 0);
484 writel_relaxed(0x70007 << (cpu << 2), sel);
486 writel_relaxed((0x70000 << (cpu << 2)) | con, sel);
491 static void __init rk3288_init_cpuidle(void)
495 if (!rockchip_jtag_enabled)
496 rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
497 ret = cpuidle_register(&rk3288_cpuidle_driver, NULL);
499 pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
502 static int rk3288_pll_early_suspend_notifier_call(struct notifier_block *self,
503 unsigned long action, void *data)
505 struct fb_event *event = data;
506 static bool enable = false;
508 if (action == FB_EARLY_EVENT_BLANK) {
509 switch (*((int *)event->data)) {
510 case FB_BLANK_UNBLANK:
512 clk_prepare_enable(clk_get_sys(NULL, "clk_cpll"));
513 clk_prepare_enable(clk_get_sys(NULL, "clk_npll"));
520 } else if (action == FB_EVENT_BLANK) {
521 switch (*((int *)event->data)) {
522 case FB_BLANK_POWERDOWN:
524 clk_disable_unprepare(clk_get_sys(NULL, "clk_cpll"));
525 clk_disable_unprepare(clk_get_sys(NULL, "clk_npll"));
537 static struct notifier_block rk3288_pll_early_suspend_notifier = {
538 .notifier_call = rk3288_pll_early_suspend_notifier_call,
542 static void __init rk3288_init_suspend(void);
544 static void __init rk3288_init_late(void)
547 rk3288_init_suspend();
549 #ifdef CONFIG_CPU_IDLE
550 rk3288_init_cpuidle();
552 if (rockchip_jtag_enabled)
553 clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
556 DT_MACHINE_START(RK3288_DT, "Rockchip RK3288 (Flattened Device Tree)")
557 .smp = smp_ops(rockchip_smp_ops),
558 .map_io = rk3288_dt_map_io,
559 .init_time = rk3288_dt_init_timer,
560 .dt_compat = rk3288_dt_compat,
561 .init_late = rk3288_init_late,
562 .reserve = rk3288_reserve,
563 .restart = rk3288_restart,
566 char PIE_DATA(sram_stack)[1024];
567 EXPORT_PIE_SYMBOL(DATA(sram_stack));
569 static int __init rk3288_pie_init(void)
572 if (!cpu_is_rk3288())
575 err = rockchip_pie_init();
579 rockchip_pie_chunk = pie_load_sections(rockchip_sram_pool, rk3288);
580 if (IS_ERR(rockchip_pie_chunk)) {
581 err = PTR_ERR(rockchip_pie_chunk);
582 pr_err("%s: failed to load section %d\n", __func__, err);
583 rockchip_pie_chunk = NULL;
587 rockchip_sram_virt = kern_to_pie(rockchip_pie_chunk, &__pie_common_start[0]);
588 rockchip_sram_stack = kern_to_pie(rockchip_pie_chunk, (char *) DATA(sram_stack) + sizeof(DATA(sram_stack)));
592 arch_initcall(rk3288_pie_init);
594 #include "pm-rk3288.c"
596 static u32 rk_pmu_pwrdn_st;
597 static inline void rk_pm_soc_pd_suspend(void)
599 rk_pmu_pwrdn_st = pmu_readl(RK3288_PMU_PWRDN_ST);
601 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
602 rk3288_sys_set_power_domain(PD_GPU, false);
604 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
605 rk3288_sys_set_power_domain(PD_HEVC, false);
607 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
608 rk3288_sys_set_power_domain(PD_VIO, false);
610 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
611 rk3288_sys_set_power_domain(PD_VIDEO, false);
613 rkpm_ddr_printascii("pd state:");
614 rkpm_ddr_printhex(rk_pmu_pwrdn_st);
615 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
616 rkpm_ddr_printascii("\n");
619 static inline void rk_pm_soc_pd_resume(void)
621 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_GPU])))
622 rk3288_sys_set_power_domain(PD_GPU, true);
624 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_HEVC])))
625 rk3288_sys_set_power_domain(PD_HEVC, true);
627 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIO])))
628 rk3288_sys_set_power_domain(PD_VIO, true);
630 if(!(rk_pmu_pwrdn_st&BIT(pmu_st_map[PD_VIDEO])))
631 rk3288_sys_set_power_domain(PD_VIDEO, true);
634 rkpm_ddr_printascii("pd state:");
635 rkpm_ddr_printhex(pmu_readl(RK3288_PMU_PWRDN_ST));
636 rkpm_ddr_printascii("\n");
639 void inline rkpm_periph_pd_dn(bool on)
641 rk3288_sys_set_power_domain(PD_PERI, on);
644 static void __init rk3288_init_suspend(void)
646 printk("%s\n",__FUNCTION__);
647 fb_register_client(&rk3288_pll_early_suspend_notifier);
648 rockchip_suspend_init();
650 rk3288_suspend_init();
651 rkpm_set_ops_pwr_dmns(rk_pm_soc_pd_suspend,rk_pm_soc_pd_resume);
655 extern bool console_suspend_enabled;
657 static int __init rk3288_pm_dbg(void)
660 console_suspend_enabled=0;
662 pm_suspend(PM_SUSPEND_MEM);
670 //late_initcall_sync(rk3288_pm_dbg);
675 #define sram_printascii(s) do {} while (0) /* FIXME */
676 #include "ddr_rk32.c"
678 static int __init rk3288_ddr_init(void)
681 #ifdef CONFIG_ARM_TRUSTZONE
686 ddr_change_freq = _ddr_change_freq;
687 ddr_round_rate = _ddr_round_rate;
688 ddr_set_auto_self_refresh = _ddr_set_auto_self_refresh;
689 ddr_bandwidth_get = _ddr_bandwidth_get;
691 ddr_init(DDR3_DEFAULT, 0);
696 arch_initcall_sync(rk3288_ddr_init);