arch/arm/mach-rockchip/rk_pm_tests/pvtm_test.c

   1 /* arch/arm/mach-rockchip/rk_pm_tests/pvtm_test.c
   2  *
   3  * Copyright (C) 2014 ROCKCHIP, Inc.
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  */
  15 #include <linux/clk.h>
  16 #include <linux/delay.h>
  17 #include <linux/module.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <asm/cacheflush.h>
  21
  22 #define PVTM_TEST 0
  23
  24 extern int rockchip_tsadc_get_temp(int chn);
  25 extern void rk29_wdt_keepalive(void);
  26 extern u32 pvtm_get_value(u32 ch, u32 time_us);
  27
  28 #if PVTM_TEST
  29 char *pvtm_buf;
  30 static const char pi_result[] = "3141592653589793238462643383279528841971693993751058209749445923078164062862089986280348253421170679821480865132823664709384469555822317253594081284811174502841270193852115559644622948954930381964428810975665933446128475648233786783165271201991456485669234634861045432664821339360726024914127372458706606315588174881520920962829254917153643678925903611330530548820466521384146951941511609433057273657595919530921861173819326117931051185480744623799627495673518857527248912279381830119491298336733624406566438602139494639522473719070217986943702770539217176293176752384674818467669451320005681271452635608277857713427577896091736371787214684409012249534301465495853710579227968925892354201995611212902196864344181598136297747713099605187072113499999983729780499510597317328160963185";
  31 int calc_pi(void)
  32 {
  33         int bit = 0, i = 0;
  34         long a = 10000, b = 0, c = 2800, d = 0, e = 0, g = 0;
  35         int *result;
  36         long *f;
  37         int len = 0;
  38         char *pi_calc, *pi_tmp;
  39         char *pi_just = (char *)&pi_result[0];
  40         size_t pi_just_size = sizeof(pi_result);
  41
  42          result = vmalloc(10000*sizeof(int));
  43          if (result == NULL)
  44                 return -ENOMEM;
  45
  46          f = vmalloc(2801*sizeof(long));
  47           if (f == NULL)
  48                 return -ENOMEM;
  49
  50          pi_calc = vmalloc(1000*sizeof(char));
  51           if (pi_calc == NULL)
  52                 return -ENOMEM;
  53
  54         for (; b-c; )
  55                 f[b++] = a/5;
  56         for (; d = 0, g = c*2; c -= 14, result[bit++] = e+d/a, e = d%a)
  57                 for (b = c; d += f[b]*a, f[b] = d%--g, d /= g--, --b; d *= b)
  58                         ;
  59
  60         pi_tmp = pi_calc;
  61         for (i = 0; i < bit; i++)
  62                 len += sprintf(pi_tmp+len, "%d", result[i]);
  63
  64         if (strncmp(pi_just, pi_calc, pi_just_size) == 0) {
  65                 vfree(result);
  66                 vfree(f);
  67                 vfree(pi_calc);
  68                 return 0;
  69         } else {
  70                 vfree(result);
  71                 vfree(f);
  72                 vfree(pi_calc);
  73
  74                 while (1)
  75                         pr_info("calc_pi error\n");
  76         }
  77 }
  78
  79 void pvtm_repeat_test(void)
  80 {
  81         struct regulator *regulator_arm;
  82         struct clk *clk_core;
  83         u32 pvtm, delta, old_pvtm;
  84         u32 min_pvtm = -1, max_pvtm = 0;
  85         u32 average = 0, sum = 0;
  86         int i, n;
  87
  88         regulator_arm = regulator_get(NULL, "vdd_arm");
  89         if (IS_ERR_OR_NULL(regulator_arm)) {
  90                 pr_err("get regulator err\n");
  91                 return;
  92         }
  93
  94         clk_core = clk_get(NULL, "clk_core");
  95         if (IS_ERR_OR_NULL(clk_core)) {
  96                 pr_err("get clk err\n");
  97                 return;
  98         }
  99
 100         n = 1000;
 101         for (i = 0; i < n; i++) {
 102                 rk29_wdt_keepalive();
 103                 pvtm = pvtm_get_value(0, 1000);
 104
 105                 sum += pvtm;
 106                 if (!old_pvtm)
 107                         old_pvtm = pvtm;
 108
 109                 if (pvtm > max_pvtm)
 110                         max_pvtm = pvtm;
 111
 112                 if (pvtm < min_pvtm)
 113                         min_pvtm = pvtm;
 114         }
 115
 116         average = sum/n;
 117         delta = max_pvtm - min_pvtm;
 118         pr_info("rate %lu volt %d max %u min %u average %u delta %u\n",
 119                 clk_get_rate(clk_core), regulator_get_voltage(regulator_arm),
 120                 max_pvtm, min_pvtm, average, delta);
 121 }
 122
 123 void pvtm_samp_interval_test(void)
 124 {
 125         struct regulator *regulator_arm;
 126         struct clk *clk_core;
 127         u32 pvtm, old_pvtm = 0, samp_interval, times;
 128         int i, n;
 129
 130         regulator_arm = regulator_get(NULL, "vdd_arm");
 131         if (IS_ERR_OR_NULL(regulator_arm)) {
 132                 pr_err("get regulator err\n");
 133                 return;
 134         }
 135
 136         clk_core = clk_get(NULL, "clk_core");
 137         if (IS_ERR_OR_NULL(clk_core)) {
 138                 pr_err("get clk err\n");
 139                 return;
 140         }
 141
 142
 143         n = 10;
 144         for (i = 0; i < n; i++) {
 145                 rk29_wdt_keepalive();
 146                 samp_interval = 10 * (1 << i);
 147                 pvtm = pvtm_get_value(0, samp_interval);
 148
 149                 if (!old_pvtm)
 150                         old_pvtm = pvtm;
 151
 152                 times = (1000*pvtm)/old_pvtm;
 153
 154                 old_pvtm = pvtm;
 155
 156                 pr_info("rate %lu volt %d samp_interval %d pvtm %d times %d\n",
 157                         clk_get_rate(clk_core),
 158                         regulator_get_voltage(regulator_arm),
 159                         samp_interval, pvtm, times);
 160         }
 161 }
 162
 163 void pvtm_temp_test(void)
 164 {
 165         struct regulator *regulator_arm;
 166         struct clk *clk_core;
 167         int temp, old_temp = 0;
 168         int volt;
 169         u32 rate;
 170
 171         regulator_arm = regulator_get(NULL, "vdd_arm");
 172         if (IS_ERR_OR_NULL(regulator_arm)) {
 173                 pr_err("get regulator err\n");
 174                 return;
 175         }
 176
 177         clk_core = clk_get(NULL, "clk_core");
 178         if (IS_ERR_OR_NULL(clk_core)) {
 179                 pr_err("get clk err\n");
 180                 return;
 181         }
 182
 183         volt = 1100000;
 184         rate = 312000000;
 185         regulator_set_voltage(regulator_arm, volt, volt);
 186         clk_set_rate(clk_core, rate);
 187
 188         do {
 189                 rk29_wdt_keepalive();
 190                 temp = rockchip_tsadc_get_temp(1);
 191                 if (!old_temp)
 192                         old_temp = temp;
 193
 194                 if (temp-old_temp >= 2)
 195                         pr_info("rate %lu volt %d temp %d pvtm %u\n",
 196                                 clk_get_rate(clk_core),
 197                                 regulator_get_voltage(regulator_arm),
 198                                 temp, pvtm_get_value(0, 1000));
 199
 200                 old_temp = temp;
 201         } while (1);
 202 }
 203
 204
 205 #define ALL_DONE_FLAG   'a'
 206 #define ONE_DONE_FLAG   'o'
 207 #define ALL_BUF_SIZE    (PAGE_SIZE << 8)
 208 #define ONE_BUF_SIZE    PAGE_SIZE
 209 #define VOLT_STEP       (12500)         /*mv*/
 210 #define VOLT_START      (1300000)       /*mv*/
 211 #define VOLT_END        (1000000)       /*mv*/
 212 #define RATE_STEP       (48000000)      /*hz*/
 213 #define RATE_START      (816000000)     /*hz*/
 214 #define RATE_END        (1200000000)    /*hz*/
 215
 216 void scale_min_pvtm_fix_volt(void)
 217 {
 218         struct regulator *regulator_arm;
 219         struct clk *clk_core;
 220         unsigned long rate;
 221         u32 pvtm, old_pvtm = 0;
 222         int volt, i, ret = 0;
 223
 224         regulator_arm = regulator_get(NULL, "vdd_arm");
 225         if (IS_ERR_OR_NULL(regulator_arm)) {
 226                 pr_info("get regulator err\n");
 227                 return;
 228         }
 229
 230         clk_core = clk_get(NULL, "clk_core");
 231         if (IS_ERR_OR_NULL(clk_core)) {
 232                 pr_info("get clk err\n");
 233                 return;
 234         }
 235
 236         volt = VOLT_START;
 237         rate = RATE_START;
 238         do {
 239                 for (i = 0; i < ALL_BUF_SIZE; i += ONE_BUF_SIZE) {
 240                         if (pvtm_buf[i] == ALL_DONE_FLAG) {
 241                                 pr_info("=============test done!========\n");
 242                                 do {
 243                                         if (i) {
 244                                                 i -= ONE_BUF_SIZE;
 245                                                 pr_info("%s", pvtm_buf+i+1);
 246                                         } else {
 247                                                 pr_info("no item!!!!\n");
 248                                         }
 249                                 } while (i);
 250
 251                                 do {
 252                                         rk29_wdt_keepalive();
 253                                         msleep(1000);
 254                                 } while (1);
 255                         }
 256                         if (pvtm_buf[i] != ONE_DONE_FLAG)
 257                                 break;
 258                         volt -= VOLT_STEP;
 259                 }
 260
 261                 if (volt < VOLT_END) {
 262                         pvtm_buf[i] = ALL_DONE_FLAG;
 263                         continue;
 264                 }
 265
 266                 pvtm_buf[i] = ONE_DONE_FLAG;
 267
 268                 ret = regulator_set_voltage(regulator_arm, volt, volt);
 269                 if (ret) {
 270                         pr_err("set volt(%d) err:%d\n", volt, ret);
 271
 272                         do {
 273                                 rk29_wdt_keepalive();
 274                                 msleep(1000);
 275                         } while (1);
 276                 }
 277
 278                 do {
 279                         rk29_wdt_keepalive();
 280
 281                         flush_cache_all();
 282                         outer_flush_all();
 283
 284                         clk_set_rate(clk_core, rate);
 285
 286                         calc_pi();
 287                         /*fft_test();*/
 288                         mdelay(500);
 289                         rk29_wdt_keepalive();
 290
 291                         pvtm = pvtm_get_value(0, 1000);
 292                         if (!old_pvtm)
 293                                 old_pvtm = pvtm;
 294                         sprintf(pvtm_buf+i+1, "%d %lu %d %d %d\n",
 295                                 volt, clk_get_rate(clk_core), pvtm,
 296                                 rockchip_tsadc_get_temp(1), old_pvtm-pvtm);
 297
 298                         pr_info("%s", pvtm_buf+i+1);
 299
 300                         old_pvtm = pvtm;
 301                         rate += RATE_STEP;
 302                 } while (1);
 303         } while (1);
 304 }
 305
 306 void scale_min_pvtm_fix_rate(void)
 307 {
 308         struct regulator *regulator_arm;
 309         struct clk *clk_core;
 310         unsigned long rate;
 311         u32 pvtm, old_pvtm = 0;
 312         int volt, i, ret = 0;
 313
 314         regulator_arm = regulator_get(NULL, "vdd_arm");
 315         if (IS_ERR_OR_NULL(regulator_arm)) {
 316                 pr_info("get regulator err\n");
 317                 return;
 318         }
 319
 320         clk_core = clk_get(NULL, "clk_core");
 321         if (IS_ERR_OR_NULL(clk_core)) {
 322                 pr_info("get clk err\n");
 323                 return;
 324         }
 325
 326         volt = VOLT_START;
 327         rate = RATE_START;
 328         do {
 329                 for (i = 0; i < ALL_BUF_SIZE; i += ONE_BUF_SIZE) {
 330                         if (pvtm_buf[i] == ALL_DONE_FLAG) {
 331                                 pr_info("=============test done!========\n");
 332                                 do {
 333                                         if (i) {
 334                                                 i -= ONE_BUF_SIZE;
 335                                                 pr_info("%s", pvtm_buf+i+1);
 336                                         } else {
 337                                                 pr_info("no item!!!!\n");
 338                                         }
 339                                 } while (i);
 340
 341                                 do {
 342                                         rk29_wdt_keepalive();
 343                                         msleep(1000);
 344                                 } while (1);
 345                         }
 346                         if (pvtm_buf[i] != ONE_DONE_FLAG)
 347                                 break;
 348
 349                         rate += RATE_STEP;
 350                 }
 351
 352                 if (rate > RATE_END) {
 353                         pvtm_buf[i] = ALL_DONE_FLAG;
 354                         continue;
 355                 }
 356
 357                 pvtm_buf[i] = ONE_DONE_FLAG;
 358
 359                 ret = regulator_set_voltage(regulator_arm, volt, volt);
 360                 if (ret) {
 361                         pr_err("set volt(%d) err:%d\n", volt, ret);
 362
 363                         do {
 364                                 rk29_wdt_keepalive();
 365                                 msleep(1000);
 366                         } while (1);
 367                 }
 368
 369                 ret = clk_set_rate(clk_core, rate);
 370                 do {
 371                         rk29_wdt_keepalive();
 372
 373                         flush_cache_all();
 374                         outer_flush_all();
 375                         regulator_set_voltage(regulator_arm, volt, volt);
 376
 377                         calc_pi();
 378                         mdelay(500);
 379                         rk29_wdt_keepalive();
 380
 381                         pvtm = pvtm_get_value(0, 1000);
 382                         if (!old_pvtm)
 383                                 old_pvtm = pvtm;
 384
 385                         sprintf(pvtm_buf+i+1, "%d %lu %d %d %d\n",
 386                                 volt, clk_get_rate(clk_core), pvtm,
 387                                 rockchip_tsadc_get_temp(1), old_pvtm-pvtm);
 388
 389                         pr_info("%s", pvtm_buf+i+1);
 390                         old_pvtm = pvtm;
 391                         volt -= VOLT_STEP;
 392                 } while (1);
 393         } while (1);
 394 }
 395
 396 #endif
 397
 398 void scale_pvtm_fix_freq(void)
 399 {
 400         struct regulator *regulator_arm;
 401         struct clk *clk_core_b, *clk_core_l;
 402         unsigned long rate;
 403         u32 pvtm, old_pvtm = 0;
 404         int volt, ret = 0;
 405
 406         regulator_arm = regulator_get(NULL, "vdd_arm");
 407         if (IS_ERR_OR_NULL(regulator_arm)) {
 408                 pr_info("get regulator err\n");
 409                 return;
 410         }
 411
 412         clk_core_b = clk_get(NULL, "clk_core_b");
 413         if (IS_ERR_OR_NULL(clk_core_b)) {
 414                 pr_info("get clk err\n");
 415                 return;
 416         }
 417         clk_core_l = clk_get(NULL, "clk_core_l");
 418         if (IS_ERR_OR_NULL(clk_core_l)) {
 419                 pr_info("get clk err\n");
 420                 return;
 421         }
 422
 423         volt = 1300000;
 424         rate = 216000000;
 425         ret = regulator_set_voltage(regulator_arm, volt, volt);
 426         if (ret)
 427                 pr_err("set volt(%d) err:%d\n", volt, ret);
 428
 429         do {
 430                 clk_set_rate(clk_core_b, rate);
 431                 clk_set_rate(clk_core_l, rate);
 432                 mdelay(500);
 433                 pvtm = pvtm_get_value(0, 1000);
 434                 if (!old_pvtm)
 435                         old_pvtm = pvtm;
 436                 pr_info("%d %lu %d %d\n",
 437                         volt, clk_get_rate(clk_core_b), pvtm, old_pvtm-pvtm);
 438
 439                 old_pvtm = pvtm;
 440                 rate += 48000000;
 441                 if (rate > 1200000000)
 442                         break;
 443         } while (1);
 444 }
 445
 446 void scale_pvtm_fix_volt(void)
 447 {
 448         struct regulator *regulator_arm;
 449         struct clk *clk_core_b, *clk_core_l;
 450         unsigned long rate;
 451         u32 pvtm, old_pvtm = 0;
 452         int volt, ret = 0;
 453
 454         regulator_arm = regulator_get(NULL, "vdd_arm");
 455         if (IS_ERR_OR_NULL(regulator_arm)) {
 456                 pr_info("get regulator err\n");
 457                 return;
 458         }
 459
 460         clk_core_b = clk_get(NULL, "clk_core_b");
 461         if (IS_ERR_OR_NULL(clk_core_b)) {
 462                 pr_info("get clk err\n");
 463                 return;
 464         }
 465
 466         clk_core_l = clk_get(NULL, "clk_core_b");
 467         if (IS_ERR_OR_NULL(clk_core_l)) {
 468                 pr_info("get clk err\n");
 469                 return;
 470         }
 471
 472         volt = 1300000;
 473         rate = 816000000;
 474
 475         ret = regulator_set_voltage(regulator_arm, volt, volt);
 476         if (ret)
 477                 pr_err("set volt(%d) err:%d\n", volt, ret);
 478
 479         ret = clk_set_rate(clk_core_b, rate);
 480         ret = clk_set_rate(clk_core_l, rate);
 481         do {
 482                 regulator_set_voltage(regulator_arm, volt, volt);
 483                 mdelay(500);
 484                 pvtm = pvtm_get_value(0, 1000);
 485                 if (!old_pvtm)
 486                         old_pvtm = pvtm;
 487
 488                 pr_info("%d %lu %d %d\n",
 489                         volt, clk_get_rate(clk_core_b), pvtm, old_pvtm-pvtm);
 490                 old_pvtm = pvtm;
 491                 volt -= 12500;
 492                 if (volt < 950000) {
 493                         regulator_set_voltage(regulator_arm, 1300000, 1300000);
 494                         break;
 495                 }
 496         } while (1);
 497 }
 498
 499 ssize_t pvtm_show(struct kobject *kobj, struct kobj_attribute *attr,
 500                   char *buf)
 501 {
 502         char *str = buf;
 503
 504         str += sprintf(str, "core:%d\ngpu:%d\n",
 505                 pvtm_get_value(0, 1000),
 506                 pvtm_get_value(1, 1000));
 507         return (str - buf);
 508 }
 509
 510 ssize_t pvtm_store(struct kobject *kobj, struct kobj_attribute *attr,
 511                    const char *buf, size_t n)
 512 {
 513         return n;
 514 }
 515
 516 int pvtm_buf_init(void)
 517 {
 518 #if PVTM_TEST
 519         pvtm_buf = (char *)__get_free_pages(GFP_KERNEL, 8);
 520
 521 #endif
 522         return 0;
 523 }
 524 fs_initcall(pvtm_buf_init);