arch/arm/mach-rockchip/rockchip.c

   1 /*
   2  * Device Tree support for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/irqchip.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/mfd/syscon.h>
  25 #include <linux/regmap.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include "core.h"
  30 #include "pm.h"
  31
  32 #define RK3288_GRF_SOC_CON0 0x244
  33 #define RK3288_GRF_SOC_CON2 0x24C
  34 #define RK3288_TIMER6_7_PHYS 0xff810000
  35
  36 static void __init rockchip_timer_init(void)
  37 {
  38         if (of_machine_is_compatible("rockchip,rk3288")) {
  39                 struct regmap *grf;
  40                 void __iomem *reg_base;
  41
  42                 /*
  43                  * Most/all uboot versions for rk3288 don't enable timer7
  44                  * which is needed for the architected timer to work.
  45                  * So make sure it is running during early boot.
  46                  */
  47                 reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
  48                 if (reg_base) {
  49                         writel(0, reg_base + 0x30);
  50                         writel(0xffffffff, reg_base + 0x20);
  51                         writel(0xffffffff, reg_base + 0x24);
  52                         writel(1, reg_base + 0x30);
  53                         dsb();
  54                         iounmap(reg_base);
  55                 } else {
  56                         pr_err("rockchip: could not map timer7 registers\n");
  57                 }
  58
  59                 /*
  60                  * Disable auto jtag/sdmmc switching that causes issues
  61                  * with the mmc controllers making them unreliable
  62                  */
  63                 grf = syscon_regmap_lookup_by_compatible("rockchip,rk3288-grf");
  64                 if (!IS_ERR(grf)) {
  65                         regmap_write(grf, RK3288_GRF_SOC_CON0, 0x10000000);
  66
  67                         /* Set pwm_sel to RK design PWM; affects all PWMs */
  68                         regmap_write(grf, RK3288_GRF_SOC_CON2, 0x00010001);
  69                 } else {
  70                         pr_err("rockchip: could not get grf syscon\n");
  71                 }
  72         }
  73
  74         of_clk_init(NULL);
  75         clocksource_probe();
  76 }
  77
  78 static void __init rockchip_dt_init(void)
  79 {
  80         rockchip_suspend_init();
  81         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  82         platform_device_register_simple("cpufreq-dt", 0, NULL, 0);
  83 }
  84
  85 static const char * const rockchip_board_dt_compat[] = {
  86         "rockchip,rk2928",
  87         "rockchip,rk3066a",
  88         "rockchip,rk3066b",
  89         "rockchip,rk3188",
  90         "rockchip,rk3288",
  91         NULL,
  92 };
  93
  94 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
  95         .l2c_aux_val    = 0,
  96         .l2c_aux_mask   = ~0,
  97         .init_time      = rockchip_timer_init,
  98         .dt_compat      = rockchip_board_dt_compat,
  99         .init_machine   = rockchip_dt_init,
 100 MACHINE_END