arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
  47 #define CONFIG_VCODEC_MMU\r
  48 #endif\r
  49 \r
  50 #ifdef CONFIG_VCODEC_MMU\r
  51 #include <linux/rockchip/iovmm.h>\r
  52 #include <linux/rockchip/sysmmu.h>\r
  53 #include <linux/dma-buf.h>\r
  54 #endif\r
  55 \r
  56 #ifdef CONFIG_DEBUG_FS\r
  57 #include <linux/debugfs.h>\r
  58 #endif\r
  59 \r
  60 #if defined(CONFIG_ARCH_RK319X)\r
  61 #include <mach/grf.h>\r
  62 #endif\r
  63 \r
  64 #include "vcodec_service.h"\r
  65 \r
  66 #define HEVC_TEST_ENABLE    0\r
  67 #define HEVC_SIM_ENABLE     0\r
  68 #define VCODEC_CLOCK_ENABLE 1\r
  69 \r
  70 typedef enum {\r
  71         VPU_DEC_ID_9190         = 0x6731,\r
  72         VPU_ID_8270             = 0x8270,\r
  73         VPU_ID_4831             = 0x4831,\r
  74     HEVC_ID         = 0x6867,\r
  75 } VPU_HW_ID;\r
  76 \r
  77 typedef enum {\r
  78         VPU_DEC_TYPE_9190       = 0,\r
  79         VPU_ENC_TYPE_8270       = 0x100,\r
  80         VPU_ENC_TYPE_4831       ,\r
  81 } VPU_HW_TYPE_E;\r
  82 \r
  83 typedef enum VPU_FREQ {\r
  84         VPU_FREQ_200M,\r
  85         VPU_FREQ_266M,\r
  86         VPU_FREQ_300M,\r
  87         VPU_FREQ_400M,\r
  88     VPU_FREQ_500M,\r
  89     VPU_FREQ_600M,\r
  90         VPU_FREQ_DEFAULT,\r
  91         VPU_FREQ_BUT,\r
  92 } VPU_FREQ;\r
  93 \r
  94 typedef struct {\r
  95         VPU_HW_ID               hw_id;\r
  96         unsigned long           hw_addr;\r
  97         unsigned long           enc_offset;\r
  98         unsigned long           enc_reg_num;\r
  99         unsigned long           enc_io_size;\r
 100         unsigned long           dec_offset;\r
 101         unsigned long           dec_reg_num;\r
 102         unsigned long           dec_io_size;\r
 103 } VPU_HW_INFO_E;\r
 104 \r
 105 #define VPU_SERVICE_SHOW_TIME                   0\r
 106 \r
 107 #if VPU_SERVICE_SHOW_TIME\r
 108 static struct timeval enc_start, enc_end;\r
 109 static struct timeval dec_start, dec_end;\r
 110 static struct timeval pp_start,  pp_end;\r
 111 #endif\r
 112 \r
 113 #define MHZ                                     (1000*1000)\r
 114 \r
 115 #define REG_NUM_9190_DEC                        (60)\r
 116 #define REG_NUM_9190_PP                         (41)\r
 117 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 120 \r
 121 #define REG_NUM_ENC_8270                        (96)\r
 122 #define REG_SIZE_ENC_8270                       (0x200)\r
 123 #define REG_NUM_ENC_4831                        (164)\r
 124 #define REG_SIZE_ENC_4831                       (0x400)\r
 125 \r
 126 #define REG_NUM_HEVC_DEC            (68)\r
 127 \r
 128 #define SIZE_REG(reg)                           ((reg)*4)\r
 129 \r
 130 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 131         [0] = {\r
 132                 .hw_id          = VPU_ID_8270,\r
 133                 .hw_addr        = 0,\r
 134                 .enc_offset     = 0x0,\r
 135                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 136                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 137                 .dec_offset     = REG_SIZE_ENC_8270,\r
 138                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 139                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 140         },\r
 141         [1] = {\r
 142                 .hw_id          = VPU_ID_4831,\r
 143                 .hw_addr        = 0,\r
 144                 .enc_offset     = 0x0,\r
 145                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 146                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 147                 .dec_offset     = REG_SIZE_ENC_4831,\r
 148                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 149                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 150         },\r
 151     [2] = {\r
 152         .hw_id      = HEVC_ID,\r
 153         .hw_addr    = 0,\r
 154         .dec_offset = 0x0,\r
 155         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 156         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 157     },\r
 158 };\r
 159 \r
 160 \r
 161 #define DEC_INTERRUPT_REGISTER                  1\r
 162 #define PP_INTERRUPT_REGISTER                   60\r
 163 #define ENC_INTERRUPT_REGISTER                  1\r
 164 \r
 165 #define DEC_INTERRUPT_BIT                       0x100\r
 166 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 167 #define PP_INTERRUPT_BIT                        0x100\r
 168 #define ENC_INTERRUPT_BIT                       0x1\r
 169 \r
 170 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 171 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 172 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 173 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 174 \r
 175 #define VPU_REG_EN_ENC                          14\r
 176 #define VPU_REG_ENC_GATE                        2\r
 177 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 178 \r
 179 #define VPU_REG_EN_DEC                          1\r
 180 #define VPU_REG_DEC_GATE                        2\r
 181 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 182 #define VPU_REG_EN_PP                           0\r
 183 #define VPU_REG_PP_GATE                         1\r
 184 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 185 #define VPU_REG_EN_DEC_PP                       1\r
 186 #define VPU_REG_DEC_PP_GATE                     61\r
 187 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 188 \r
 189 #if defined(CONFIG_VCODEC_MMU)\r
 190 static u8 addr_tbl_vpu_h264dec[] = {\r
 191         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 192 };\r
 193 \r
 194 static u8 addr_tbl_vpu_vp8dec[] = {\r
 195         10,12,13, 14, 18, 19, 27, 40\r
 196 };\r
 197 \r
 198 static u8 addr_tbl_vpu_vp6dec[] = {\r
 199         12, 13, 14, 18, 27, 40\r
 200 };\r
 201 \r
 202 static u8 addr_tbl_vpu_vc1dec[] = {\r
 203         12, 13, 14, 15, 16, 17, 27, 41\r
 204 };\r
 205 \r
 206 static u8 addr_tbl_vpu_jpegdec[] = {\r
 207         12, 40, 66, 67\r
 208 };\r
 209 \r
 210 static u8 addr_tbl_vpu_defaultdec[] = {\r
 211         12, 13, 14, 15, 16, 17, 40, 41\r
 212 };\r
 213 \r
 214 static u8 addr_tbl_vpu_enc[] = {\r
 215         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 216 };\r
 217 \r
 218 static u8 addr_tbl_hevc_dec[] = {\r
 219         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 220 };\r
 221 #endif\r
 222 \r
 223 enum VPU_DEC_FMT {\r
 224         VPU_DEC_FMT_H264,\r
 225         VPU_DEC_FMT_MPEG4,\r
 226         VPU_DEC_FMT_H263,\r
 227         VPU_DEC_FMT_JPEG,\r
 228         VPU_DEC_FMT_VC1,\r
 229         VPU_DEC_FMT_MPEG2,\r
 230         VPU_DEC_FMT_MPEG1,\r
 231         VPU_DEC_FMT_VP6,\r
 232         VPU_DEC_FMT_RV,\r
 233         VPU_DEC_FMT_VP7,\r
 234         VPU_DEC_FMT_VP8,\r
 235         VPU_DEC_FMT_AVS,\r
 236         VPU_DEC_FMT_SVC,\r
 237         VPU_DEC_FMT_VC2,\r
 238         VPU_DEC_FMT_MVC,\r
 239         VPU_DEC_FMT_THEORA,\r
 240         VPU_DEC_FMT_RES\r
 241 };\r
 242 \r
 243 /**\r
 244  * struct for process session which connect to vpu\r
 245  *\r
 246  * @author ChenHengming (2011-5-3)\r
 247  */\r
 248 typedef struct vpu_session {\r
 249         VPU_CLIENT_TYPE         type;\r
 250         /* a linked list of data so we can access them for debugging */\r
 251         struct list_head        list_session;\r
 252         /* a linked list of register data waiting for process */\r
 253         struct list_head        waiting;\r
 254         /* a linked list of register data in processing */\r
 255         struct list_head        running;\r
 256         /* a linked list of register data processed */\r
 257         struct list_head        done;\r
 258         wait_queue_head_t       wait;\r
 259         pid_t                   pid;\r
 260         atomic_t                task_running;\r
 261 } vpu_session;\r
 262 \r
 263 /**\r
 264  * struct for process register set\r
 265  *\r
 266  * @author ChenHengming (2011-5-4)\r
 267  */\r
 268 typedef struct vpu_reg {\r
 269         VPU_CLIENT_TYPE         type;\r
 270         VPU_FREQ                    freq;\r
 271         vpu_session             *session;\r
 272         struct list_head        session_link;           /* link to vpu service session */\r
 273         struct list_head        status_link;            /* link to register set list */\r
 274         unsigned long           size;\r
 275 #if defined(CONFIG_VCODEC_MMU)\r
 276         struct list_head        mem_region_list;\r
 277 #endif\r
 278         unsigned long           *reg;\r
 279 } vpu_reg;\r
 280 \r
 281 typedef struct vpu_device {\r
 282         atomic_t                irq_count_codec;\r
 283         atomic_t                irq_count_pp;\r
 284         unsigned long           iobaseaddr;\r
 285         unsigned int            iosize;\r
 286         volatile u32            *hwregs;\r
 287 } vpu_device;\r
 288 \r
 289 enum vcodec_device_id {\r
 290         VCODEC_DEVICE_ID_VPU,\r
 291         VCODEC_DEVICE_ID_HEVC\r
 292 };\r
 293 \r
 294 struct vcodec_mem_region {\r
 295     struct list_head srv_lnk;\r
 296     struct list_head reg_lnk;\r
 297     struct list_head session_lnk;\r
 298     unsigned long iova;              /* virtual address for iommu */\r
 299     unsigned long len;\r
 300     struct ion_handle *hdl;\r
 301 };\r
 302 \r
 303 typedef struct vpu_service_info {\r
 304         struct wake_lock        wake_lock;\r
 305         struct delayed_work     power_off_work;\r
 306         struct mutex            lock;\r
 307         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 308         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 309         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 310         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 311         atomic_t                total_running;\r
 312         bool                    enabled;\r
 313         vpu_reg                 *reg_codec;\r
 314         vpu_reg                 *reg_pproc;\r
 315         vpu_reg                 *reg_resev;\r
 316         VPUHwDecConfig_t        dec_config;\r
 317         VPUHwEncConfig_t        enc_config;\r
 318         VPU_HW_INFO_E           *hw_info;\r
 319         unsigned long           reg_size;\r
 320         bool                    auto_freq;\r
 321         bool                    bug_dec_addr;\r
 322         atomic_t                freq_status;\r
 323 \r
 324     struct clk *aclk_vcodec;\r
 325     struct clk *hclk_vcodec;\r
 326     struct clk *clk_core;\r
 327     struct clk *clk_cabac;\r
 328     struct clk *pd_video;\r
 329 \r
 330     int irq_dec;\r
 331     int irq_enc;\r
 332 \r
 333     vpu_device enc_dev;\r
 334     vpu_device dec_dev;\r
 335 \r
 336     struct device   *dev;\r
 337 \r
 338     struct cdev     cdev;\r
 339     dev_t           dev_t;\r
 340     struct class    *cls;\r
 341     struct device   *child_dev;\r
 342 \r
 343     struct dentry   *debugfs_dir;\r
 344     struct dentry   *debugfs_file_regs;\r
 345 \r
 346     u32 irq_status;\r
 347 #if defined(CONFIG_VCODEC_MMU)  \r
 348         struct ion_client * ion_client;\r
 349 #endif  \r
 350 \r
 351 #if defined(CONFIG_VCODEC_MMU)\r
 352     struct list_head mem_region_list;\r
 353 #endif\r
 354 \r
 355         enum vcodec_device_id dev_id;\r
 356 \r
 357     struct delayed_work simulate_work;\r
 358 } vpu_service_info;\r
 359 \r
 360 typedef struct vpu_request\r
 361 {\r
 362         unsigned long   *req;\r
 363         unsigned long   size;\r
 364 } vpu_request;\r
 365 \r
 366 /// global variable\r
 367 //static struct clk *pd_video;\r
 368 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 369 \r
 370 #ifdef CONFIG_DEBUG_FS\r
 371 static int vcodec_debugfs_init(void);\r
 372 static void vcodec_debugfs_exit(void);\r
 373 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 374 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 375 \r
 376 static const struct file_operations debug_vcodec_fops = {\r
 377     .open = debug_vcodec_open,\r
 378     .read = seq_read,\r
 379     .llseek = seq_lseek,\r
 380     .release = single_release,\r
 381 };\r
 382 #endif\r
 383 \r
 384 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 385 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 386 \r
 387 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 388 \r
 389 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 390 {\r
 391 #if VCODEC_CLOCK_ENABLE\r
 392     do {\r
 393         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 394         if (IS_ERR(pservice->aclk_vcodec)) {\r
 395             dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 396             break;\r
 397         }\r
 398     \r
 399         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 400         if (IS_ERR(pservice->hclk_vcodec)) {\r
 401             dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 402             break;\r
 403         }\r
 404     \r
 405         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 406             pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 407             if (IS_ERR(pservice->clk_core)) {\r
 408                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 409                 break;\r
 410             }\r
 411     \r
 412             pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 413             if (IS_ERR(pservice->clk_cabac)) {\r
 414                 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 415                 break;\r
 416             }\r
 417             \r
 418             pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 419             if (IS_ERR(pservice->pd_video)) {\r
 420                 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 421                 break;\r
 422             }\r
 423         } else {\r
 424             pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 425             if (IS_ERR(pservice->pd_video)) {\r
 426                 dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 427                 break;\r
 428             }\r
 429         }\r
 430         \r
 431         return 0;\r
 432     } while (0);\r
 433     \r
 434     return -1;\r
 435 #endif\r
 436 }\r
 437 \r
 438 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 439 {\r
 440 #if VCODEC_CLOCK_ENABLE\r
 441     if (pservice->pd_video) {\r
 442         devm_clk_put(pservice->dev, pservice->pd_video);\r
 443     }\r
 444 \r
 445     if (pservice->aclk_vcodec) {\r
 446         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 447     }\r
 448 \r
 449     if (pservice->hclk_vcodec) {\r
 450         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 451     }\r
 452 \r
 453     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 454         if (pservice->clk_core) {\r
 455             devm_clk_put(pservice->dev, pservice->clk_core);\r
 456         }\r
 457         \r
 458         if (pservice->clk_cabac) {\r
 459             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 460         }\r
 461     }\r
 462 #endif\r
 463 }\r
 464 \r
 465 static void vpu_reset(struct vpu_service_info *pservice)\r
 466 {\r
 467 #if defined(CONFIG_ARCH_RK29)\r
 468         clk_disable(aclk_ddr_vepu);\r
 469         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 470         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 471         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 472         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 473         mdelay(10);\r
 474         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 475         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 476         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 477         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 478         clk_enable(aclk_ddr_vepu);\r
 479 #elif defined(CONFIG_ARCH_RK30)\r
 480         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 481         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 482         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 483         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 484         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 485         mdelay(1);\r
 486         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 487         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 488         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 489         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 490         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 491 #endif\r
 492         pservice->reg_codec = NULL;\r
 493         pservice->reg_pproc = NULL;\r
 494         pservice->reg_resev = NULL;\r
 495 }\r
 496 \r
 497 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 498 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 499 {\r
 500         vpu_reg *reg, *n;\r
 501         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 502                 reg_deinit(pservice, reg);\r
 503         }\r
 504         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 505                 reg_deinit(pservice, reg);\r
 506         }\r
 507         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 508                 reg_deinit(pservice, reg);\r
 509         }\r
 510 }\r
 511 \r
 512 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 513 {\r
 514         int running;\r
 515         vpu_reg *reg, *reg_tmp;\r
 516         vpu_session *session, *session_tmp;\r
 517 \r
 518         running = atomic_read(&pservice->total_running);\r
 519         printk("total_running %d\n", running);\r
 520 \r
 521         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 522         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 523         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 524 \r
 525         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 526                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 527                 running = atomic_read(&session->task_running);\r
 528                 printk("task_running %d\n", running);\r
 529                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 530                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 531                 }\r
 532                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 533                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 534                 }\r
 535                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 536                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 537                 }\r
 538         }\r
 539 }\r
 540 \r
 541 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 542 {\r
 543     int total_running;\r
 544     if (!pservice->enabled) {\r
 545         return;\r
 546     }\r
 547 \r
 548     pservice->enabled = false;\r
 549     total_running = atomic_read(&pservice->total_running);\r
 550     if (total_running) {\r
 551         pr_alert("alert: power off when %d task running!!\n", total_running);\r
 552         mdelay(50);\r
 553         pr_alert("alert: delay 50 ms for running task\n");\r
 554         vpu_service_dump(pservice);\r
 555     }\r
 556 \r
 557     printk("%s: power off...", dev_name(pservice->dev));\r
 558     udelay(10);\r
 559 #if VCODEC_CLOCK_ENABLE\r
 560     clk_disable_unprepare(pservice->pd_video);\r
 561     clk_disable_unprepare(pservice->hclk_vcodec);\r
 562     clk_disable_unprepare(pservice->aclk_vcodec);\r
 563     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 564         clk_disable_unprepare(pservice->clk_core);\r
 565         clk_disable_unprepare(pservice->clk_cabac);\r
 566     }\r
 567 #endif\r
 568     wake_unlock(&pservice->wake_lock);\r
 569     printk("done\n");\r
 570 }\r
 571 \r
 572 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 573 {\r
 574         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 575 }\r
 576 \r
 577 static void vpu_power_off_work(struct work_struct *work_s)\r
 578 {\r
 579     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 580     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 581 \r
 582         if (mutex_trylock(&pservice->lock)) {\r
 583                 vpu_service_power_off(pservice);\r
 584                 mutex_unlock(&pservice->lock);\r
 585         } else {\r
 586                 /* Come back later if the device is busy... */\r
 587                 vpu_queue_power_off_work(pservice);\r
 588         }\r
 589 }\r
 590 \r
 591 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 592 {\r
 593     static ktime_t last;\r
 594     ktime_t now = ktime_get();\r
 595     if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 596         cancel_delayed_work_sync(&pservice->power_off_work);\r
 597         vpu_queue_power_off_work(pservice);\r
 598         last = now;\r
 599     }\r
 600     if (pservice->enabled)\r
 601         return ;\r
 602 \r
 603     pservice->enabled = true;\r
 604     printk("%s: power on\n", dev_name(pservice->dev));\r
 605 \r
 606 #if VCODEC_CLOCK_ENABLE\r
 607     clk_prepare_enable(pservice->aclk_vcodec);\r
 608     clk_prepare_enable(pservice->hclk_vcodec);\r
 609 \r
 610     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 611         clk_prepare_enable(pservice->clk_core);\r
 612         clk_prepare_enable(pservice->clk_cabac);\r
 613     }\r
 614     \r
 615     clk_prepare_enable(pservice->pd_video);\r
 616 #endif\r
 617 \r
 618 #if defined(CONFIG_ARCH_RK319X)\r
 619     /// select aclk_vepu as vcodec clock source. \r
 620     #define BIT_VCODEC_SEL  (1<<7)\r
 621     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 622 #endif\r
 623     \r
 624     udelay(10);\r
 625     wake_lock(&pservice->wake_lock);\r
 626 }\r
 627 \r
 628 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 629 {\r
 630         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 631         return ((type == 8) || (type == 4));\r
 632 }\r
 633 \r
 634 static inline bool reg_check_interlace(vpu_reg *reg)\r
 635 {\r
 636         unsigned long type = (reg->reg[3] & (1 << 23));\r
 637         return (type > 0);\r
 638 }\r
 639 \r
 640 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
 641 {\r
 642         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
 643         return type;\r
 644 }\r
 645 \r
 646 static inline int reg_probe_width(vpu_reg *reg)\r
 647 {\r
 648     int width_in_mb = reg->reg[4] >> 23;\r
 649     \r
 650     return width_in_mb * 16;\r
 651 }\r
 652 \r
 653 #if defined(CONFIG_VCODEC_MMU)\r
 654 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 655 {\r
 656         int i;\r
 657         int usr_fd = 0;\r
 658         int offset = 0;\r
 659 \r
 660         if (tbl == NULL || size <= 0) {\r
 661                 dev_err(pservice->dev, "input arguments invalidate\n");\r
 662                 return -1;\r
 663         }\r
 664 \r
 665         vpu_service_power_on(pservice);\r
 666 \r
 667         for (i = 0; i < size; i++) {\r
 668                 usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 669 \r
 670                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID && (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {\r
 671                         /* special for vpu dec num 41 regitster */\r
 672                         offset = reg->reg[tbl[i]] >> 10 << 4;\r
 673                 } else {\r
 674                         offset = reg->reg[tbl[i]] >> 10;\r
 675                 }\r
 676 \r
 677                 if (usr_fd != 0) {\r
 678                         struct ion_handle *hdl;\r
 679                         int ret;\r
 680                         struct vcodec_mem_region *mem_region;\r
 681 \r
 682                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 683                         if (IS_ERR(hdl)) {\r
 684                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 685                                 return PTR_ERR(hdl);\r
 686                         }\r
 687 \r
 688                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 689 \r
 690                         if (mem_region == NULL) {\r
 691                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 692                                 ion_free(pservice->ion_client, hdl);\r
 693                                 return -1;\r
 694                         }\r
 695 \r
 696                         mem_region->hdl = hdl;\r
 697 \r
 698                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 699                         if (ret < 0) {\r
 700                                 dev_err(pservice->dev, "ion map iommu failed\n");\r
 701                                 kfree(mem_region);\r
 702                                 ion_free(pservice->ion_client, hdl);\r
 703                                 return ret;\r
 704                         }\r
 705                         reg->reg[tbl[i]] = mem_region->iova + offset;\r
 706                         INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 707                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 708                 }\r
 709         }\r
 710         return 0;\r
 711 }\r
 712 \r
 713 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 714 {\r
 715         VPU_HW_ID hw_id;\r
 716         u8 *tbl;\r
 717         int size = 0;\r
 718 \r
 719         hw_id = pservice->hw_info->hw_id;\r
 720 \r
 721         if (hw_id == HEVC_ID) {\r
 722                 tbl = addr_tbl_hevc_dec;\r
 723                 size = sizeof(addr_tbl_hevc_dec);\r
 724         } else {\r
 725                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 726                         switch (reg_check_fmt(reg)) {\r
 727                         case VPU_DEC_FMT_H264:\r
 728                                 {\r
 729                                         tbl = addr_tbl_vpu_h264dec;\r
 730                                         size = sizeof(addr_tbl_vpu_h264dec);\r
 731                                         break;\r
 732                                 }\r
 733                         case VPU_DEC_FMT_VP8:\r
 734                         case VPU_DEC_FMT_VP7:\r
 735                                 {\r
 736                                         tbl = addr_tbl_vpu_vp8dec;\r
 737                                         size = sizeof(addr_tbl_vpu_vp8dec);\r
 738                                         break;\r
 739                                 }\r
 740 \r
 741                         case VPU_DEC_FMT_VP6:\r
 742                                 {\r
 743                                         tbl = addr_tbl_vpu_vp6dec;\r
 744                                         size = sizeof(addr_tbl_vpu_vp6dec);\r
 745                                         break;\r
 746                                 }\r
 747                         case VPU_DEC_FMT_VC1:\r
 748                                 {\r
 749                                         tbl = addr_tbl_vpu_vc1dec;\r
 750                                         size = sizeof(addr_tbl_vpu_vc1dec);\r
 751                                         break;\r
 752                                 }\r
 753 \r
 754                         case VPU_DEC_FMT_JPEG:\r
 755                                 {\r
 756                                         tbl = addr_tbl_vpu_jpegdec;\r
 757                                         size = sizeof(addr_tbl_vpu_jpegdec);\r
 758                                         break;\r
 759                                 }\r
 760                         default:\r
 761                                 tbl = addr_tbl_vpu_defaultdec;\r
 762                                 size = sizeof(addr_tbl_vpu_defaultdec);\r
 763                                 break;\r
 764                         }\r
 765                 } else if (reg->type == VPU_ENC) {\r
 766                         tbl = addr_tbl_vpu_enc;\r
 767                         size = sizeof(addr_tbl_vpu_enc);\r
 768                 }\r
 769         }\r
 770 \r
 771         if (size != 0) {\r
 772                 return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 773         } else {\r
 774                 return -1;\r
 775         }\r
 776 }\r
 777 #endif\r
 778 \r
 779 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 780 {\r
 781         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 782         if (NULL == reg) {\r
 783                 pr_err("error: kmalloc fail in reg_init\n");\r
 784                 return NULL;\r
 785         }\r
 786 \r
 787         if (size > pservice->reg_size) {\r
 788                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 789                 size = pservice->reg_size;\r
 790         }\r
 791         reg->session = session;\r
 792         reg->type = session->type;\r
 793         reg->size = size;\r
 794         reg->freq = VPU_FREQ_DEFAULT;\r
 795         reg->reg = (unsigned long *)&reg[1];\r
 796         INIT_LIST_HEAD(&reg->session_link);\r
 797         INIT_LIST_HEAD(&reg->status_link);\r
 798 \r
 799 #if defined(CONFIG_VCODEC_MMU)    \r
 800         INIT_LIST_HEAD(&reg->mem_region_list);\r
 801 #endif\r
 802 \r
 803         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 804                 pr_err("error: copy_from_user failed in reg_init\n");\r
 805                 kfree(reg);\r
 806                 return NULL;\r
 807         }\r
 808 \r
 809 #if defined(CONFIG_VCODEC_MMU)\r
 810         if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
 811                 pr_err("error: translate reg address failed\n");\r
 812                 kfree(reg);\r
 813                 return NULL;\r
 814         }\r
 815 #endif\r
 816 \r
 817         mutex_lock(&pservice->lock);\r
 818         list_add_tail(&reg->status_link, &pservice->waiting);\r
 819         list_add_tail(&reg->session_link, &session->waiting);\r
 820         mutex_unlock(&pservice->lock);\r
 821 \r
 822         if (pservice->auto_freq) {\r
 823                 if (!soc_is_rk2928g()) {\r
 824                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 825                                 if (reg_check_rmvb_wmv(reg)) {\r
 826                                         reg->freq = VPU_FREQ_200M;\r
 827                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
 828                                         if (reg_probe_width(reg) > 3200) {\r
 829                                                 // raise frequency for 4k avc.\r
 830                                                 reg->freq = VPU_FREQ_500M;\r
 831                                         }\r
 832                                 } else {\r
 833                                         if (reg_check_interlace(reg)) {\r
 834                                                 reg->freq = VPU_FREQ_400M;\r
 835                                         }\r
 836                                 }\r
 837                         }\r
 838                         if (reg->type == VPU_PP) {\r
 839                                 reg->freq = VPU_FREQ_400M;\r
 840                         }\r
 841                 }\r
 842         }\r
 843 \r
 844         return reg;\r
 845 }\r
 846 \r
 847 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 848 {\r
 849 #if defined(CONFIG_VCODEC_MMU)\r
 850         struct vcodec_mem_region *mem_region = NULL, *n;\r
 851 #endif\r
 852 \r
 853         list_del_init(&reg->session_link);\r
 854         list_del_init(&reg->status_link);\r
 855         if (reg == pservice->reg_codec)\r
 856                 pservice->reg_codec = NULL;\r
 857         if (reg == pservice->reg_pproc)\r
 858                 pservice->reg_pproc = NULL;\r
 859 \r
 860 #if defined(CONFIG_VCODEC_MMU)\r
 861         // release memory region attach to this registers table.\r
 862         list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 863                 ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
 864                 ion_free(pservice->ion_client, mem_region->hdl);\r
 865                 list_del_init(&mem_region->reg_lnk);\r
 866                 kfree(mem_region);\r
 867         }\r
 868 #endif\r
 869 \r
 870         kfree(reg);\r
 871 }\r
 872 \r
 873 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 874 {\r
 875         list_del_init(&reg->status_link);\r
 876         list_add_tail(&reg->status_link, &pservice->running);\r
 877 \r
 878         list_del_init(&reg->session_link);\r
 879         list_add_tail(&reg->session_link, &reg->session->running);\r
 880 }\r
 881 \r
 882 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 883 {\r
 884         int i;\r
 885         u32 *dst = (u32 *)&reg->reg[0];\r
 886         for (i = 0; i < count; i++)\r
 887                 *dst++ = *src++;\r
 888 }\r
 889 \r
 890 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 891 {\r
 892         int irq_reg = -1;\r
 893         list_del_init(&reg->status_link);\r
 894         list_add_tail(&reg->status_link, &pservice->done);\r
 895 \r
 896         list_del_init(&reg->session_link);\r
 897         list_add_tail(&reg->session_link, &reg->session->done);\r
 898 \r
 899         switch (reg->type) {\r
 900         case VPU_ENC : {\r
 901                 pservice->reg_codec = NULL;\r
 902                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 903                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 904                 break;\r
 905         }\r
 906         case VPU_DEC : {\r
 907                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 908                 pservice->reg_codec = NULL;\r
 909                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 910                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 911                 break;\r
 912         }\r
 913         case VPU_PP : {\r
 914                 pservice->reg_pproc = NULL;\r
 915                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 916                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 917                 break;\r
 918         }\r
 919         case VPU_DEC_PP : {\r
 920                 pservice->reg_codec = NULL;\r
 921                 pservice->reg_pproc = NULL;\r
 922                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 923                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 924                 break;\r
 925         }\r
 926         default : {\r
 927                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 928                 break;\r
 929         }\r
 930         }\r
 931 \r
 932         if (irq_reg != -1) {\r
 933                 reg->reg[irq_reg] = pservice->irq_status;\r
 934         }\r
 935 \r
 936         atomic_sub(1, &reg->session->task_running);\r
 937         atomic_sub(1, &pservice->total_running);\r
 938         wake_up(&reg->session->wait);\r
 939 }\r
 940 \r
 941 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 942 {\r
 943         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 944         if (curr == reg->freq) {\r
 945                 return ;\r
 946         }\r
 947         atomic_set(&pservice->freq_status, reg->freq);\r
 948         switch (reg->freq) {\r
 949         case VPU_FREQ_200M : {\r
 950                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 951                 //printk("default: 200M\n");\r
 952         } break;\r
 953         case VPU_FREQ_266M : {\r
 954                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 955                 //printk("default: 266M\n");\r
 956         } break;\r
 957         case VPU_FREQ_300M : {\r
 958                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 959                 //printk("default: 300M\n");\r
 960         } break;\r
 961         case VPU_FREQ_400M : {\r
 962                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 963                 //printk("default: 400M\n");\r
 964         } break;\r
 965         case VPU_FREQ_500M : {\r
 966                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 967         } break;\r
 968         case VPU_FREQ_600M : {\r
 969                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 970         } break;\r
 971         default : {\r
 972                 if (soc_is_rk2928g()) {\r
 973                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 974                 } else {\r
 975                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 976                 }\r
 977                 //printk("default: 300M\n");\r
 978         } break;\r
 979         }\r
 980 }\r
 981 \r
 982 #if HEVC_SIM_ENABLE\r
 983 static void simulate_start(struct vpu_service_info *pservice);\r
 984 #endif\r
 985 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 986 {\r
 987         int i;\r
 988         u32 *src = (u32 *)&reg->reg[0];\r
 989         atomic_add(1, &pservice->total_running);\r
 990         atomic_add(1, &reg->session->task_running);\r
 991         if (pservice->auto_freq) {\r
 992                 vpu_service_set_freq(pservice, reg);\r
 993         }\r
 994         switch (reg->type) {\r
 995         case VPU_ENC : {\r
 996                 int enc_count = pservice->hw_info->enc_reg_num;\r
 997                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 998 \r
 999                 pservice->reg_codec = reg;\r
1000 \r
1001                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
1002 \r
1003                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
1004                         dst[i] = src[i];\r
1005 \r
1006                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
1007                         dst[i] = src[i];\r
1008 \r
1009                 dsb();\r
1010 \r
1011                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
1012                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
1013 \r
1014 #if VPU_SERVICE_SHOW_TIME\r
1015                 do_gettimeofday(&enc_start);\r
1016 #endif\r
1017 \r
1018         } break;\r
1019         case VPU_DEC : {\r
1020                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1021 \r
1022                 pservice->reg_codec = reg;\r
1023 \r
1024                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1025                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
1026                                 dst[i] = src[i];\r
1027                 } else {\r
1028                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
1029                                 dst[i] = src[i];\r
1030                         }\r
1031                 }\r
1032 \r
1033                 dsb();\r
1034 \r
1035                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1036                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
1037                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
1038                 } else {\r
1039                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
1040                 }\r
1041 \r
1042                 dsb();\r
1043                 dmb();\r
1044 \r
1045 #if VPU_SERVICE_SHOW_TIME\r
1046                 do_gettimeofday(&dec_start);\r
1047 #endif\r
1048 \r
1049         } break;\r
1050         case VPU_PP : {\r
1051                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1052                 pservice->reg_pproc = reg;\r
1053 \r
1054                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1055 \r
1056                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1057                         dst[i] = src[i];\r
1058 \r
1059                 dsb();\r
1060 \r
1061                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1062 \r
1063 #if VPU_SERVICE_SHOW_TIME\r
1064                 do_gettimeofday(&pp_start);\r
1065 #endif\r
1066 \r
1067         } break;\r
1068         case VPU_DEC_PP : {\r
1069                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1070                 pservice->reg_codec = reg;\r
1071                 pservice->reg_pproc = reg;\r
1072 \r
1073                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1074                         dst[i] = src[i];\r
1075 \r
1076                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1077                 dsb();\r
1078 \r
1079                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1080                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1081                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1082 \r
1083 #if VPU_SERVICE_SHOW_TIME\r
1084                 do_gettimeofday(&dec_start);\r
1085 #endif\r
1086 \r
1087         } break;\r
1088         default : {\r
1089                 pr_err("error: unsupport session type %d", reg->type);\r
1090                 atomic_sub(1, &pservice->total_running);\r
1091                 atomic_sub(1, &reg->session->task_running);\r
1092                 break;\r
1093         }\r
1094         }\r
1095 \r
1096 #if HEVC_SIM_ENABLE\r
1097         if (pservice->hw_info->hw_id == HEVC_ID) {\r
1098                 simulate_start(pservice);\r
1099         }\r
1100 #endif\r
1101 }\r
1102 \r
1103 static void try_set_reg(struct vpu_service_info *pservice)\r
1104 {\r
1105         // first get reg from reg list\r
1106         if (!list_empty(&pservice->waiting)) {\r
1107                 int can_set = 0;\r
1108                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1109 \r
1110                 vpu_service_power_on(pservice);\r
1111 \r
1112                 switch (reg->type) {\r
1113                 case VPU_ENC : {\r
1114                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1115                                 can_set = 1;\r
1116                 } break;\r
1117                 case VPU_DEC : {\r
1118                         if (NULL == pservice->reg_codec)\r
1119                                 can_set = 1;\r
1120                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1121                                 can_set = 0;\r
1122                         }\r
1123                 } break;\r
1124                 case VPU_PP : {\r
1125                         if (NULL == pservice->reg_codec) {\r
1126                                 if (NULL == pservice->reg_pproc)\r
1127                                         can_set = 1;\r
1128                         } else {\r
1129                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1130                                         can_set = 1;\r
1131                                 // can not charge frequency when vpu is working\r
1132                                 if (pservice->auto_freq) {\r
1133                                         can_set = 0;\r
1134                                 }\r
1135                         }\r
1136                 } break;\r
1137                 case VPU_DEC_PP : {\r
1138                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1139                                 can_set = 1;\r
1140                         } break;\r
1141                 default : {\r
1142                         printk("undefined reg type %d\n", reg->type);\r
1143                 } break;\r
1144                 }\r
1145                 if (can_set) {\r
1146                         reg_from_wait_to_run(pservice, reg);\r
1147                         reg_copy_to_hw(pservice, reg);\r
1148                 }\r
1149         }\r
1150 }\r
1151 \r
1152 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1153 {\r
1154         int ret = 0;\r
1155         switch (reg->type) {\r
1156         case VPU_ENC : {\r
1157                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1158                         ret = -EFAULT;\r
1159                 break;\r
1160         }\r
1161         case VPU_DEC : {\r
1162                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1163                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1164                         ret = -EFAULT;\r
1165                 break;\r
1166         }\r
1167         case VPU_PP : {\r
1168                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1169                         ret = -EFAULT;\r
1170                 break;\r
1171         }\r
1172         case VPU_DEC_PP : {\r
1173                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1174                         ret = -EFAULT;\r
1175                 break;\r
1176         }\r
1177         default : {\r
1178                 ret = -EFAULT;\r
1179                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1180                 break;\r
1181         }\r
1182         }\r
1183         reg_deinit(pservice, reg);\r
1184         return ret;\r
1185 }\r
1186 \r
1187 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1188 {\r
1189     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1190         vpu_session *session = (vpu_session *)filp->private_data;\r
1191         if (NULL == session) {\r
1192                 return -EINVAL;\r
1193         }\r
1194 \r
1195         switch (cmd) {\r
1196         case VPU_IOC_SET_CLIENT_TYPE : {\r
1197                 session->type = (VPU_CLIENT_TYPE)arg;\r
1198                 break;\r
1199         }\r
1200         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1201                 vpu_request req;\r
1202                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1203                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1204                         return -EFAULT;\r
1205                 } else {\r
1206                         if (VPU_ENC != session->type) {\r
1207                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1208                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1209                                         return -EFAULT;\r
1210                                 }\r
1211                         } else {\r
1212                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1213                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1214                                         return -EFAULT;\r
1215                                 }\r
1216                         }\r
1217                 }\r
1218 \r
1219                 break;\r
1220         }\r
1221         case VPU_IOC_SET_REG : {\r
1222                 vpu_request req;\r
1223                 vpu_reg *reg;\r
1224                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1225                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1226                         return -EFAULT;\r
1227                 }\r
1228                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1229                 if (NULL == reg) {\r
1230                         return -EFAULT;\r
1231                 } else {\r
1232                         mutex_lock(&pservice->lock);\r
1233                         try_set_reg(pservice);\r
1234                         mutex_unlock(&pservice->lock);\r
1235                 }\r
1236 \r
1237                 break;\r
1238         }\r
1239         case VPU_IOC_GET_REG : {\r
1240                 vpu_request req;\r
1241                 vpu_reg *reg;\r
1242                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1243                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1244                         return -EFAULT;\r
1245                 } else {\r
1246                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1247                         if (!list_empty(&session->done)) {\r
1248                                 if (ret < 0) {\r
1249                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1250                                 }\r
1251                                 ret = 0;\r
1252                         } else {\r
1253                                 if (unlikely(ret < 0)) {\r
1254                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1255                                 } else if (0 == ret) {\r
1256                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1257                                         ret = -ETIMEDOUT;\r
1258                                 }\r
1259                         }\r
1260                         if (ret < 0) {\r
1261                                 int task_running = atomic_read(&session->task_running);\r
1262                                 mutex_lock(&pservice->lock);\r
1263                                 vpu_service_dump(pservice);\r
1264                                 if (task_running) {\r
1265                                         atomic_set(&session->task_running, 0);\r
1266                                         atomic_sub(task_running, &pservice->total_running);\r
1267                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1268                                         vpu_reset(pservice);\r
1269                                         printk("done\n");\r
1270                                 }\r
1271                                 vpu_service_session_clear(pservice, session);\r
1272                                 mutex_unlock(&pservice->lock);\r
1273                                 return ret;\r
1274                         }\r
1275                 }\r
1276                 mutex_lock(&pservice->lock);\r
1277                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1278                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1279                 mutex_unlock(&pservice->lock);\r
1280                 break;\r
1281         }\r
1282         case VPU_IOC_PROBE_IOMMU_STATUS: {\r
1283 #if defined(CONFIG_VCODEC_MMU)\r
1284                 int iommu_enable = 1;\r
1285 #else\r
1286                 int iommu_enable = 0;\r
1287 #endif\r
1288                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
1289                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
1290                         return -EFAULT;\r
1291                 }\r
1292                 break;\r
1293         }\r
1294         default : {\r
1295                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1296                 break;\r
1297         }\r
1298         }\r
1299 \r
1300         return 0;\r
1301 }\r
1302 \r
1303 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1304 {\r
1305         int ret = -EINVAL, i = 0;\r
1306         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1307         u32 enc_id = *tmp;\r
1308 \r
1309 #if HEVC_SIM_ENABLE\r
1310         /// temporary, hevc driver test.\r
1311         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1312                 p->hw_info = &vpu_hw_set[2];\r
1313                 return 0;\r
1314         }\r
1315 #endif\r
1316 \r
1317         enc_id = (enc_id >> 16) & 0xFFFF;\r
1318         pr_info("checking hw id %x\n", enc_id);\r
1319         p->hw_info = NULL;\r
1320         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1321                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1322                         p->hw_info = &vpu_hw_set[i];\r
1323                         ret = 0;\r
1324                         break;\r
1325                 }\r
1326         }\r
1327         iounmap((void *)tmp);\r
1328         return ret;\r
1329 }\r
1330 \r
1331 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1332 {\r
1333         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1334         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1335         if (NULL == session) {\r
1336                 pr_err("error: unable to allocate memory for vpu_session.");\r
1337                 return -ENOMEM;\r
1338         }\r
1339 \r
1340         session->type   = VPU_TYPE_BUTT;\r
1341         session->pid    = current->pid;\r
1342         INIT_LIST_HEAD(&session->waiting);\r
1343         INIT_LIST_HEAD(&session->running);\r
1344         INIT_LIST_HEAD(&session->done);\r
1345         INIT_LIST_HEAD(&session->list_session);\r
1346         init_waitqueue_head(&session->wait);\r
1347         atomic_set(&session->task_running, 0);\r
1348         mutex_lock(&pservice->lock);\r
1349         list_add_tail(&session->list_session, &pservice->session);\r
1350         filp->private_data = (void *)session;\r
1351         mutex_unlock(&pservice->lock);\r
1352 \r
1353         pr_debug("dev opened\n");\r
1354         return nonseekable_open(inode, filp);\r
1355 }\r
1356 \r
1357 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1358 {\r
1359         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1360         int task_running;\r
1361         vpu_session *session = (vpu_session *)filp->private_data;\r
1362         if (NULL == session)\r
1363                 return -EINVAL;\r
1364 \r
1365         task_running = atomic_read(&session->task_running);\r
1366         if (task_running) {\r
1367                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1368                 msleep(50);\r
1369         }\r
1370         wake_up(&session->wait);\r
1371 \r
1372         mutex_lock(&pservice->lock);\r
1373         /* remove this filp from the asynchronusly notified filp's */\r
1374         list_del_init(&session->list_session);\r
1375         vpu_service_session_clear(pservice, session);\r
1376         kfree(session);\r
1377         filp->private_data = NULL;\r
1378         mutex_unlock(&pservice->lock);\r
1379 \r
1380         pr_debug("dev closed\n");\r
1381         return 0;\r
1382 }\r
1383 \r
1384 static const struct file_operations vpu_service_fops = {\r
1385         .unlocked_ioctl = vpu_service_ioctl,\r
1386         .open           = vpu_service_open,\r
1387         .release        = vpu_service_release,\r
1388         //.fasync       = vpu_service_fasync,\r
1389 };\r
1390 \r
1391 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1392 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1393 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1394 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1395 static void get_hw_info(struct vpu_service_info *pservice);\r
1396 \r
1397 #if HEVC_SIM_ENABLE\r
1398 static void simulate_work(struct work_struct *work_s)\r
1399 {\r
1400     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1401     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1402     vpu_device *dev = &pservice->dec_dev;\r
1403 \r
1404     if (!list_empty(&pservice->running)) {\r
1405         atomic_add(1, &dev->irq_count_codec);\r
1406         vdpu_isr(0, (void*)pservice);\r
1407     } else {\r
1408         //simulate_start(pservice);\r
1409         pr_err("empty running queue\n");\r
1410     }\r
1411 }\r
1412 \r
1413 static void simulate_init(struct vpu_service_info *pservice)\r
1414 {\r
1415     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1416 }\r
1417 \r
1418 static void simulate_start(struct vpu_service_info *pservice)\r
1419 {\r
1420     cancel_delayed_work_sync(&pservice->power_off_work);\r
1421     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1422 }\r
1423 #endif\r
1424 \r
1425 #if HEVC_TEST_ENABLE\r
1426 static int hevc_test_case0(vpu_service_info *pservice);\r
1427 #endif\r
1428 #if defined(CONFIG_ION_ROCKCHIP)\r
1429 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1430 #endif\r
1431 static int vcodec_probe(struct platform_device *pdev)\r
1432 {\r
1433     int ret = 0;\r
1434     struct resource *res = NULL;\r
1435     struct device *dev = &pdev->dev;\r
1436     void __iomem *regs = NULL;\r
1437     struct device_node *np = pdev->dev.of_node;\r
1438     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1439     char *prop = (char*)dev_name(dev);\r
1440 #if defined(CONFIG_VCODEC_MMU)\r
1441     struct device *mmu_dev = NULL;\r
1442     char mmu_dev_dts_name[40];\r
1443 #endif\r
1444 \r
1445     pr_info("probe device %s\n", dev_name(dev));\r
1446 \r
1447     of_property_read_string(np, "name", (const char**)&prop);\r
1448     dev_set_name(dev, prop);\r
1449 \r
1450     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1451         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1452     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1453         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1454     } else {\r
1455         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1456         return -1;\r
1457     }\r
1458 \r
1459     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1460     INIT_LIST_HEAD(&pservice->waiting);\r
1461     INIT_LIST_HEAD(&pservice->running);\r
1462     INIT_LIST_HEAD(&pservice->done);\r
1463     INIT_LIST_HEAD(&pservice->session);\r
1464     mutex_init(&pservice->lock);\r
1465     pservice->reg_codec = NULL;\r
1466     pservice->reg_pproc = NULL;\r
1467     atomic_set(&pservice->total_running, 0);\r
1468     pservice->enabled = false;\r
1469 \r
1470     pservice->dev = dev;\r
1471 \r
1472     if (0 > vpu_get_clk(pservice)) {\r
1473         goto err;\r
1474     }\r
1475 \r
1476     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1477 \r
1478     vpu_service_power_on(pservice);\r
1479     \r
1480     mdelay(1);\r
1481 \r
1482     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1483 \r
1484     regs = devm_ioremap_resource(pservice->dev, res);\r
1485     if (IS_ERR(regs)) {\r
1486         ret = PTR_ERR(regs);\r
1487         goto err;\r
1488     }\r
1489 \r
1490     ret = vpu_service_check_hw(pservice, res->start);\r
1491     if (ret < 0) {\r
1492         pr_err("error: hw info check faild\n");\r
1493         goto err;\r
1494     }\r
1495 \r
1496     /// define regs address.\r
1497     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1498     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1499 \r
1500     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1501 \r
1502     pservice->reg_size   = pservice->dec_dev.iosize;\r
1503 \r
1504     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1505         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1506         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1507 \r
1508         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1509 \r
1510         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1511 \r
1512         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1513         if (pservice->irq_enc < 0) {\r
1514             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1515             ret = -ENXIO;\r
1516             goto err;\r
1517         }\r
1518 \r
1519         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1520         if (ret) {\r
1521             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1522             goto err;\r
1523         }\r
1524     }\r
1525 \r
1526     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1527     if (pservice->irq_dec < 0) {\r
1528         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1529         ret = -ENXIO;\r
1530         goto err;\r
1531     }\r
1532 \r
1533     /* get the IRQ line */\r
1534     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1535     if (ret) {\r
1536         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1537         goto err;\r
1538     }\r
1539 \r
1540     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1541     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1542     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1543     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1544 \r
1545     /// create device\r
1546     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1547     if (ret) {\r
1548         dev_err(dev, "alloc dev_t failed\n");\r
1549         goto err;\r
1550     }\r
1551 \r
1552     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1553 \r
1554     pservice->cdev.owner = THIS_MODULE;\r
1555     pservice->cdev.ops = &vpu_service_fops;\r
1556 \r
1557     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1558 \r
1559     if (ret) {\r
1560         dev_err(dev, "add dev_t failed\n");\r
1561         goto err;\r
1562     }\r
1563 \r
1564     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1565 \r
1566     if (IS_ERR(pservice->cls)) {\r
1567         ret = PTR_ERR(pservice->cls);\r
1568         dev_err(dev, "class_create err:%d\n", ret);\r
1569         goto err;\r
1570     }\r
1571 \r
1572     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1573 \r
1574     platform_set_drvdata(pdev, pservice);\r
1575 \r
1576     get_hw_info(pservice);\r
1577 \r
1578 \r
1579 #ifdef CONFIG_DEBUG_FS\r
1580     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1581     \r
1582     if (pservice->debugfs_dir == NULL) {\r
1583         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1584     }\r
1585 \r
1586     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1587                     pservice->debugfs_dir, pservice,\r
1588                     &debug_vcodec_fops);\r
1589 #endif\r
1590 \r
1591 #if defined(CONFIG_VCODEC_MMU)\r
1592     pservice->ion_client = rockchip_ion_client_create("vpu");\r
1593     if (IS_ERR(pservice->ion_client)) {\r
1594         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1595         return PTR_ERR(pservice->ion_client);\r
1596     } else {\r
1597         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1598     }\r
1599     \r
1600     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1601         sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1602     } else {\r
1603         sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1604     }\r
1605     \r
1606     mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1607     \r
1608     if (mmu_dev) {\r
1609         platform_set_sysmmu(mmu_dev, pservice->dev);\r
1610         iovmm_activate(pservice->dev);\r
1611     }\r
1612 #endif\r
1613 \r
1614     vpu_service_power_off(pservice);\r
1615     pr_info("init success\n");\r
1616 \r
1617 #if HEVC_SIM_ENABLE\r
1618     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1619         simulate_init(pservice);\r
1620     }\r
1621 #endif\r
1622 \r
1623 #if HEVC_TEST_ENABLE\r
1624     hevc_test_case0(pservice);\r
1625 #endif\r
1626 \r
1627     return 0;\r
1628 \r
1629 err:\r
1630     pr_info("init failed\n");\r
1631     vpu_service_power_off(pservice);\r
1632     vpu_put_clk(pservice);\r
1633     wake_lock_destroy(&pservice->wake_lock);\r
1634 \r
1635     if (res) {\r
1636         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1637     }\r
1638 \r
1639     if (pservice->irq_enc > 0) {\r
1640         free_irq(pservice->irq_enc, (void *)pservice);\r
1641     }\r
1642 \r
1643     if (pservice->irq_dec > 0) {\r
1644         free_irq(pservice->irq_dec, (void *)pservice);\r
1645     }\r
1646 \r
1647     if (pservice->child_dev) {\r
1648         device_destroy(pservice->cls, pservice->dev_t);\r
1649         cdev_del(&pservice->cdev);\r
1650         unregister_chrdev_region(pservice->dev_t, 1);\r
1651     }\r
1652 \r
1653     if (pservice->cls) {\r
1654         class_destroy(pservice->cls);\r
1655     }\r
1656 \r
1657     return ret;\r
1658 }\r
1659 \r
1660 static int vcodec_remove(struct platform_device *pdev)\r
1661 {\r
1662     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1663     struct resource *res;\r
1664 \r
1665     device_destroy(pservice->cls, pservice->dev_t);\r
1666     class_destroy(pservice->cls);\r
1667     cdev_del(&pservice->cdev);\r
1668     unregister_chrdev_region(pservice->dev_t, 1);\r
1669 \r
1670     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1671     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1672     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1673     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1674     vpu_put_clk(pservice);\r
1675     wake_lock_destroy(&pservice->wake_lock);\r
1676     \r
1677 #ifdef CONFIG_DEBUG_FS\r
1678     if (pservice->debugfs_file_regs) {\r
1679         debugfs_remove(pservice->debugfs_file_regs);\r
1680     }\r
1681 \r
1682     if (pservice->debugfs_dir) {\r
1683         debugfs_remove(pservice->debugfs_dir);\r
1684     }\r
1685 #endif\r
1686 \r
1687     return 0;\r
1688 }\r
1689 \r
1690 #if defined(CONFIG_OF)\r
1691 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1692     {.compatible = "vpu_service",},\r
1693     {.compatible = "rockchip,hevc_service",},\r
1694     {},\r
1695 };\r
1696 #endif\r
1697 \r
1698 static struct platform_driver vcodec_driver = {\r
1699     .probe     = vcodec_probe,\r
1700     .remove        = vcodec_remove,\r
1701     .driver = {\r
1702         .name = "vcodec",\r
1703         .owner = THIS_MODULE,\r
1704 #if defined(CONFIG_OF)\r
1705         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1706 #endif\r
1707     },\r
1708 };\r
1709 \r
1710 static void get_hw_info(struct vpu_service_info *pservice)\r
1711 {\r
1712     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1713     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1714 \r
1715     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1716         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1717         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1718     \r
1719         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1720         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1721         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1722             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1723         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1724         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1725         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1726         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1727         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1728         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1729     \r
1730         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1731             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1732         } else {\r
1733             dec->maxDecPicWidth = 4096;\r
1734         }\r
1735     \r
1736         /* 2nd Config register */\r
1737         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1738         if (dec->refBufSupport) {\r
1739             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1740                 dec->refBufSupport |= 2;\r
1741             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1742                 dec->refBufSupport |= 4;\r
1743         }\r
1744         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1745         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1746         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1747         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1748     \r
1749         /* JPEG xtensions */\r
1750         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1751             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1752         } else {\r
1753             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1754         }\r
1755     \r
1756         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1757             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1758         } else {\r
1759             dec->rvSupport = RV_NOT_SUPPORTED;\r
1760         }\r
1761     \r
1762         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1763     \r
1764         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1765             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1766         }\r
1767     \r
1768         /// invalidate fuse register value in rk319x vpu and following.\r
1769         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1770             VPUHwFuseStatus_t hwFuseSts;\r
1771             /* Decoder fuse configuration */\r
1772             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1773     \r
1774             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1775             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1776             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1777             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1778             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1779             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1780             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1781             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1782             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1783             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1784             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1785             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1786             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1787             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1788     \r
1789             /* check max. decoder output width */\r
1790     \r
1791             if (fuseReg & 0x8000U)\r
1792                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1793             else if (fuseReg & 0x4000U)\r
1794                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1795             else if (fuseReg & 0x2000U)\r
1796                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1797             else if (fuseReg & 0x1000U)\r
1798                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1799             else    /* remove warning */\r
1800                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1801     \r
1802             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1803     \r
1804             /* Pp configuration */\r
1805             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1806     \r
1807             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1808                 dec->ppSupport = 1;\r
1809                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1810                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1811                 dec->ppConfig = configReg;\r
1812             } else {\r
1813                 dec->ppSupport = 0;\r
1814                 dec->maxPpOutPicWidth = 0;\r
1815                 dec->ppConfig = 0;\r
1816             }\r
1817     \r
1818             /* check the HW versio */\r
1819             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1820                 /* Pp configuration */\r
1821                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1822     \r
1823                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1824                     /* Pp fuse configuration */\r
1825                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1826     \r
1827                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1828                         hwFuseSts.ppSupportFuse = 1;\r
1829                         /* check max. pp output width */\r
1830                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1831                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1832                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1833                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1834                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1835                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1836                     } else {\r
1837                         hwFuseSts.ppSupportFuse = 0;\r
1838                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1839                         hwFuseSts.ppConfigFuse = 0;\r
1840                     }\r
1841                 } else {\r
1842                     hwFuseSts.ppSupportFuse = 0;\r
1843                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1844                     hwFuseSts.ppConfigFuse = 0;\r
1845                 }\r
1846     \r
1847                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1848                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1849                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1850                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1851                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1852                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1853                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1854                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1855                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1856                     dec->jpegSupport = JPEG_BASELINE;\r
1857                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1858                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1859                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1860                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1861                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1862                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1863     \r
1864                 /* check the pp config vs fuse status */\r
1865                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1866                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1867                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1868                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1869                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1870     \r
1871                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1872                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1873                 }\r
1874                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1875                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1876                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1877                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1878                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1879             }\r
1880         }\r
1881     \r
1882         configReg = pservice->enc_dev.hwregs[63];\r
1883         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1884         enc->h264Enabled = (configReg >> 27) & 1;\r
1885         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1886         enc->jpegEnabled = (configReg >> 25) & 1;\r
1887         enc->vsEnabled = (configReg >> 24) & 1;\r
1888         enc->rgbEnabled = (configReg >> 28) & 1;\r
1889         //enc->busType = (configReg >> 20) & 15;\r
1890         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1891         //enc->busWidth = (configReg >> 12) & 15;\r
1892         enc->reg_size = pservice->reg_size;\r
1893         enc->reserv[0] = enc->reserv[1] = 0;\r
1894     \r
1895         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1896         if (pservice->auto_freq) {\r
1897             pr_info("vpu_service set to auto frequency mode\n");\r
1898             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1899         }\r
1900         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1901         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1902     } else {\r
1903         // disable frequency switch in hevc.\r
1904         pservice->auto_freq = false;\r
1905     }\r
1906 }\r
1907 \r
1908 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1909 {\r
1910     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1911     vpu_device *dev = &pservice->dec_dev;\r
1912     u32 raw_status;\r
1913     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1914 \r
1915         pr_debug("dec_irq\n");\r
1916 \r
1917         if (irq_status & DEC_INTERRUPT_BIT) {\r
1918                 pr_debug("dec_isr dec %x\n", irq_status);\r
1919                 if ((irq_status & 0x40001) == 0x40001)\r
1920                 {\r
1921                         do {\r
1922                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1923                         } while ((irq_status & 0x40001) == 0x40001);\r
1924                 }\r
1925 \r
1926                 /* clear dec IRQ */\r
1927         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1928             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1929         } else {\r
1930             /*writel(irq_status \r
1931               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1932                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1933 \r
1934             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1935         }\r
1936                 atomic_add(1, &dev->irq_count_codec);\r
1937         }\r
1938 \r
1939     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1940         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1941         if (irq_status & PP_INTERRUPT_BIT) {\r
1942             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1943             /* clear pp IRQ */\r
1944             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1945             atomic_add(1, &dev->irq_count_pp);\r
1946         }\r
1947     }\r
1948 \r
1949     pservice->irq_status = raw_status;\r
1950 \r
1951         return IRQ_WAKE_THREAD;\r
1952 }\r
1953 \r
1954 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1955 {\r
1956     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1957     vpu_device *dev = &pservice->dec_dev;\r
1958 \r
1959         mutex_lock(&pservice->lock);\r
1960         if (atomic_read(&dev->irq_count_codec)) {\r
1961 #if VPU_SERVICE_SHOW_TIME\r
1962                 do_gettimeofday(&dec_end);\r
1963                 pr_info("dec task: %ld ms\n",\r
1964                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1965                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1966 #endif\r
1967                 atomic_sub(1, &dev->irq_count_codec);\r
1968                 if (NULL == pservice->reg_codec) {\r
1969                         pr_err("error: dec isr with no task waiting\n");\r
1970                 } else {\r
1971                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1972                 }\r
1973         }\r
1974 \r
1975         if (atomic_read(&dev->irq_count_pp)) {\r
1976 \r
1977 #if VPU_SERVICE_SHOW_TIME\r
1978                 do_gettimeofday(&pp_end);\r
1979                 printk("pp  task: %ld ms\n",\r
1980                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1981                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1982 #endif\r
1983 \r
1984                 atomic_sub(1, &dev->irq_count_pp);\r
1985                 if (NULL == pservice->reg_pproc) {\r
1986                         pr_err("error: pp isr with no task waiting\n");\r
1987                 } else {\r
1988                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1989                 }\r
1990         }\r
1991         try_set_reg(pservice);\r
1992         mutex_unlock(&pservice->lock);\r
1993         return IRQ_HANDLED;\r
1994 }\r
1995 \r
1996 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1997 {\r
1998         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1999     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2000     vpu_device *dev = &pservice->enc_dev;\r
2001         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2002 \r
2003         pr_debug("vepu_irq irq status %x\n", irq_status);\r
2004 \r
2005 #if VPU_SERVICE_SHOW_TIME\r
2006         do_gettimeofday(&enc_end);\r
2007         pr_info("enc task: %ld ms\n",\r
2008                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
2009                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
2010 #endif\r
2011     \r
2012         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
2013                 /* clear enc IRQ */\r
2014                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2015                 atomic_add(1, &dev->irq_count_codec);\r
2016         }\r
2017     \r
2018     pservice->irq_status = irq_status;\r
2019 \r
2020         return IRQ_WAKE_THREAD;\r
2021 }\r
2022 \r
2023 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
2024 {\r
2025         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2026     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2027     vpu_device *dev = &pservice->enc_dev;\r
2028 \r
2029         mutex_lock(&pservice->lock);\r
2030         if (atomic_read(&dev->irq_count_codec)) {\r
2031                 atomic_sub(1, &dev->irq_count_codec);\r
2032                 if (NULL == pservice->reg_codec) {\r
2033                         pr_err("error: enc isr with no task waiting\n");\r
2034                 } else {\r
2035                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2036                 }\r
2037         }\r
2038         try_set_reg(pservice);\r
2039         mutex_unlock(&pservice->lock);\r
2040         return IRQ_HANDLED;\r
2041 }\r
2042 \r
2043 static int __init vcodec_service_init(void)\r
2044 {\r
2045     int ret;\r
2046 \r
2047     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
2048         pr_err("Platform device register failed (%d).\n", ret);\r
2049         return ret;\r
2050     }\r
2051 \r
2052 #ifdef CONFIG_DEBUG_FS\r
2053     vcodec_debugfs_init();\r
2054 #endif\r
2055 \r
2056     return ret;\r
2057 }\r
2058 \r
2059 static void __exit vcodec_service_exit(void)\r
2060 {\r
2061 #ifdef CONFIG_DEBUG_FS\r
2062     vcodec_debugfs_exit();\r
2063 #endif\r
2064 \r
2065         platform_driver_unregister(&vcodec_driver);\r
2066 }\r
2067 \r
2068 module_init(vcodec_service_init);\r
2069 module_exit(vcodec_service_exit);\r
2070 \r
2071 #ifdef CONFIG_DEBUG_FS\r
2072 #include <linux/seq_file.h>\r
2073 \r
2074 static int vcodec_debugfs_init()\r
2075 {\r
2076     parent = debugfs_create_dir("vcodec", NULL);\r
2077     if (!parent)\r
2078         return -1;\r
2079 \r
2080     return 0;\r
2081 }\r
2082 \r
2083 static void vcodec_debugfs_exit()\r
2084 {\r
2085     debugfs_remove(parent);\r
2086 }\r
2087 \r
2088 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2089 {\r
2090     return debugfs_create_dir(dirname, parent);\r
2091 }\r
2092 \r
2093 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2094 {\r
2095         struct vpu_service_info *pservice = s->private;\r
2096     unsigned int i, n;\r
2097         vpu_reg *reg, *reg_tmp;\r
2098         vpu_session *session, *session_tmp;\r
2099 \r
2100         mutex_lock(&pservice->lock);\r
2101         vpu_service_power_on(pservice);\r
2102     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2103         seq_printf(s, "\nENC Registers:\n");\r
2104         n = pservice->enc_dev.iosize >> 2;\r
2105         for (i = 0; i < n; i++) {\r
2106             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2107         }\r
2108     }\r
2109         seq_printf(s, "\nDEC Registers:\n");\r
2110         n = pservice->dec_dev.iosize >> 2;\r
2111         for (i = 0; i < n; i++) {\r
2112                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2113         }\r
2114 \r
2115         seq_printf(s, "\nvpu service status:\n");\r
2116         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2117                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2118                 //seq_printf(s, "waiting reg set %d\n");\r
2119                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2120                         seq_printf(s, "waiting register set\n");\r
2121                 }\r
2122                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2123                         seq_printf(s, "running register set\n");\r
2124                 }\r
2125                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2126                         seq_printf(s, "done    register set\n");\r
2127                 }\r
2128         }\r
2129         mutex_unlock(&pservice->lock);\r
2130 \r
2131     return 0;\r
2132 }\r
2133 \r
2134 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2135 {\r
2136         return single_open(file, debug_vcodec_show, inode->i_private);\r
2137 }\r
2138 \r
2139 #endif\r
2140 \r
2141 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2142 #include "hevc_test_inc/pps_00.h"\r
2143 #include "hevc_test_inc/register_00.h"\r
2144 #include "hevc_test_inc/rps_00.h"\r
2145 #include "hevc_test_inc/scaling_list_00.h"\r
2146 #include "hevc_test_inc/stream_00.h"\r
2147 \r
2148 #include "hevc_test_inc/pps_01.h"\r
2149 #include "hevc_test_inc/register_01.h"\r
2150 #include "hevc_test_inc/rps_01.h"\r
2151 #include "hevc_test_inc/scaling_list_01.h"\r
2152 #include "hevc_test_inc/stream_01.h"\r
2153 \r
2154 #include "hevc_test_inc/cabac.h"\r
2155 \r
2156 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2157 \r
2158 static struct ion_client *ion_client = NULL;\r
2159 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2160 {\r
2161         int size = (len+15) & (~15);\r
2162     struct ion_handle *handle;\r
2163         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2164 \r
2165     if (ion_client == NULL) {\r
2166         ion_client = rockchip_ion_client_create("vcodec");\r
2167     }\r
2168 \r
2169     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2170 \r
2171     ptr = ion_map_kernel(ion_client, handle);\r
2172 \r
2173     ion_phys(ion_client, handle, phy, &size);\r
2174 \r
2175         memcpy(ptr, tbl, len);\r
2176 \r
2177         return ptr;\r
2178 }\r
2179 \r
2180 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2181 {\r
2182         int size = (len+15) & (~15);\r
2183     struct ion_handle *handle;\r
2184         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2185 \r
2186     if (ion_client == NULL) {\r
2187         ion_client = rockchip_ion_client_create("vcodec");\r
2188     }\r
2189 \r
2190     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2191 \r
2192     ptr = ion_map_kernel(ion_client, handle);\r
2193 \r
2194     ion_phys(ion_client, handle, phy, &size);\r
2195 \r
2196         return ptr;\r
2197 }\r
2198 \r
2199 #define TEST_CNT    2\r
2200 static int hevc_test_case0(vpu_service_info *pservice)\r
2201 {\r
2202     vpu_session session;\r
2203     vpu_reg *reg; \r
2204     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2205     int testidx = 0;\r
2206     int ret = 0;\r
2207 \r
2208     u8 *pps_tbl[TEST_CNT];\r
2209     u8 *register_tbl[TEST_CNT];\r
2210     u8 *rps_tbl[TEST_CNT];\r
2211     u8 *scaling_list_tbl[TEST_CNT];\r
2212     u8 *stream_tbl[TEST_CNT];\r
2213 \r
2214         int stream_size[2];\r
2215         int pps_size[2];\r
2216         int rps_size[2];\r
2217         int scl_size[2];\r
2218         int cabac_size[2];\r
2219         \r
2220     u32 phy_pps;\r
2221     u32 phy_rps;\r
2222     u32 phy_scl;\r
2223     u32 phy_str;\r
2224     u32 phy_yuv;\r
2225     u32 phy_ref;\r
2226     u32 phy_cabac;\r
2227 \r
2228         volatile u8 *stream_buf;\r
2229         volatile u8 *pps_buf;\r
2230         volatile u8 *rps_buf;\r
2231         volatile u8 *scl_buf;\r
2232         volatile u8 *yuv_buf;\r
2233         volatile u8 *cabac_buf;\r
2234         volatile u8 *ref_buf;\r
2235 \r
2236     u8 *pps;\r
2237     u8 *yuv[2];\r
2238     int i;\r
2239     \r
2240     pps_tbl[0] = pps_00;\r
2241     pps_tbl[1] = pps_01;\r
2242 \r
2243     register_tbl[0] = register_00;\r
2244     register_tbl[1] = register_01;\r
2245     \r
2246     rps_tbl[0] = rps_00;\r
2247     rps_tbl[1] = rps_01;\r
2248     \r
2249     scaling_list_tbl[0] = scaling_list_00;\r
2250     scaling_list_tbl[1] = scaling_list_01;\r
2251 \r
2252     stream_tbl[0] = stream_00;\r
2253     stream_tbl[1] = stream_01;\r
2254 \r
2255     stream_size[0] = sizeof(stream_00);\r
2256     stream_size[1] = sizeof(stream_01);\r
2257 \r
2258         pps_size[0] = sizeof(pps_00);\r
2259         pps_size[1] = sizeof(pps_01);\r
2260 \r
2261         rps_size[0] = sizeof(rps_00);\r
2262         rps_size[1] = sizeof(rps_01);\r
2263 \r
2264         scl_size[0] = sizeof(scaling_list_00);\r
2265         scl_size[1] = sizeof(scaling_list_01);\r
2266         \r
2267         cabac_size[0] = sizeof(Cabac_table);\r
2268         cabac_size[1] = sizeof(Cabac_table);\r
2269 \r
2270     // create session\r
2271     session.pid = current->pid;\r
2272     session.type = VPU_DEC;\r
2273     INIT_LIST_HEAD(&session.waiting);\r
2274         INIT_LIST_HEAD(&session.running);\r
2275         INIT_LIST_HEAD(&session.done);\r
2276         INIT_LIST_HEAD(&session.list_session);\r
2277         init_waitqueue_head(&session.wait);\r
2278         atomic_set(&session.task_running, 0);\r
2279         list_add_tail(&session.list_session, &pservice->session);\r
2280 \r
2281     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2282     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2283 \r
2284         while (testidx < TEST_CNT) {\r
2285         \r
2286         // create registers\r
2287         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2288         if (NULL == reg) {\r
2289             pr_err("error: kmalloc fail in reg_init\n");\r
2290             return -1;\r
2291         }\r
2292 \r
2293 \r
2294         if (size > pservice->reg_size) {\r
2295             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2296             size = pservice->reg_size;\r
2297         }\r
2298         reg->session = &session;\r
2299         reg->type = session.type;\r
2300         reg->size = size;\r
2301         reg->freq = VPU_FREQ_DEFAULT;\r
2302         reg->reg = (unsigned long *)&reg[1];\r
2303         INIT_LIST_HEAD(&reg->session_link);\r
2304         INIT_LIST_HEAD(&reg->status_link);\r
2305 \r
2306         // TODO: stuff registers\r
2307         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2308 \r
2309                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2310                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2311                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2312                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2313                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2314 \r
2315                 pps = pps_buf;\r
2316 \r
2317         // TODO: replace reigster address\r
2318 \r
2319         for (i=0; i<64; i++) {\r
2320             u32 scaling_offset;\r
2321             u32 tmp;\r
2322 \r
2323             scaling_offset = (u32)pps[i*80+74];\r
2324             scaling_offset += (u32)pps[i*80+75] << 8;\r
2325             scaling_offset += (u32)pps[i*80+76] << 16;\r
2326             scaling_offset += (u32)pps[i*80+77] << 24;\r
2327 \r
2328             tmp = phy_scl + scaling_offset;\r
2329 \r
2330             pps[i*80+74] = tmp & 0xff;\r
2331             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2332             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2333             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2334         }\r
2335 \r
2336         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2337 \r
2338         reg->reg[1] = 0x21;\r
2339         reg->reg[4] = phy_str;\r
2340         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2341         reg->reg[6] = phy_cabac;\r
2342         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2343         reg->reg[42] = phy_pps;\r
2344         reg->reg[43] = phy_rps;\r
2345         for (i = 10; i <= 24; i++) {\r
2346             reg->reg[i] = phy_yuv;\r
2347         }\r
2348 \r
2349         mutex_lock(&pservice->lock);\r
2350         list_add_tail(&reg->status_link, &pservice->waiting);\r
2351         list_add_tail(&reg->session_link, &session.waiting);\r
2352         mutex_unlock(&pservice->lock);\r
2353 \r
2354         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2355 \r
2356         // stuff hardware\r
2357         try_set_reg(pservice);\r
2358 \r
2359         // wait for result\r
2360         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2361         if (!list_empty(&session.done)) {\r
2362             if (ret < 0) {\r
2363                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2364             }\r
2365             ret = 0;\r
2366         } else {\r
2367             if (unlikely(ret < 0)) {\r
2368                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2369             } else if (0 == ret) {\r
2370                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2371                 ret = -ETIMEDOUT;\r
2372             }\r
2373         }\r
2374         if (ret < 0) {\r
2375             int task_running = atomic_read(&session.task_running);\r
2376             int n;\r
2377             mutex_lock(&pservice->lock);\r
2378             vpu_service_dump(pservice);\r
2379             if (task_running) {\r
2380                 atomic_set(&session.task_running, 0);\r
2381                 atomic_sub(task_running, &pservice->total_running);\r
2382                 printk("%d task is running but not return, reset hardware...", task_running);\r
2383                 vpu_reset(pservice);\r
2384                 printk("done\n");\r
2385             }\r
2386             vpu_service_session_clear(pservice, &session);\r
2387             mutex_unlock(&pservice->lock);\r
2388 \r
2389             printk("\nDEC Registers:\n");\r
2390                 n = pservice->dec_dev.iosize >> 2;\r
2391                 for (i=0; i<n; i++) {\r
2392                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2393                 }\r
2394 \r
2395             pr_err("test index %d failed\n", testidx);\r
2396             break;\r
2397         } else {\r
2398             pr_info("test index %d success\n", testidx);\r
2399 \r
2400             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2401 \r
2402             for (i=0; i<68; i++) {\r
2403                 if (i % 4 == 0) {\r
2404                     printk("%02d: ", i);\r
2405                 }\r
2406                 printk("%08x ", reg->reg[i]);\r
2407                 if ((i+1) % 4 == 0) {\r
2408                     printk("\n");\r
2409                 }\r
2410             }\r
2411 \r
2412             testidx++;\r
2413         }\r
2414 \r
2415         reg_deinit(pservice, reg);\r
2416     }\r
2417 \r
2418     return 0;\r
2419 }\r
2420 \r
2421 #endif\r
2422 \r