2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/clk.h>
20 #include <linux/compat.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/miscdevice.h>
31 #include <linux/poll.h>
32 #include <linux/platform_device.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/wakelock.h>
36 #include <linux/cdev.h>
38 #include <linux/of_platform.h>
39 #include <linux/of_irq.h>
40 #include <linux/rockchip/cpu.h>
41 #include <linux/rockchip/cru.h>
42 #include <linux/rockchip/pmu.h>
43 #ifdef CONFIG_MFD_SYSCON
44 #include <linux/regmap.h>
46 #include <linux/mfd/syscon.h>
48 #include <asm/cacheflush.h>
49 #include <linux/uaccess.h>
50 #include <linux/rockchip/grf.h>
52 #if defined(CONFIG_ION_ROCKCHIP)
53 #include <linux/rockchip_ion.h>
56 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
57 #define CONFIG_VCODEC_MMU
60 #ifdef CONFIG_VCODEC_MMU
61 #include <linux/rockchip-iovmm.h>
62 #include <linux/dma-buf.h>
65 #ifdef CONFIG_DEBUG_FS
66 #include <linux/debugfs.h>
69 #if defined(CONFIG_ARCH_RK319X)
73 #include "vcodec_service.h"
77 * +------+-------------------+
79 * +------+-------------------+
80 * 0~23 bit is for different information type
81 * 24~31 bit is for information print format
84 #define DEBUG_POWER 0x00000001
85 #define DEBUG_CLOCK 0x00000002
86 #define DEBUG_IRQ_STATUS 0x00000004
87 #define DEBUG_IOMMU 0x00000008
88 #define DEBUG_IOCTL 0x00000010
89 #define DEBUG_FUNCTION 0x00000020
90 #define DEBUG_REGISTER 0x00000040
91 #define DEBUG_EXTRA_INFO 0x00000080
92 #define DEBUG_TIMING 0x00000100
94 #define PRINT_FUNCTION 0x80000000
95 #define PRINT_LINE 0x40000000
98 module_param(debug, int, S_IRUGO | S_IWUSR);
99 MODULE_PARM_DESC(debug,
100 "Debug level - higher value produces more verbose messages");
102 #define HEVC_TEST_ENABLE 0
103 #define VCODEC_CLOCK_ENABLE 1
106 VPU_DEC_ID_9190 = 0x6731,
107 VPU_ID_8270 = 0x8270,
108 VPU_ID_4831 = 0x4831,
115 VPU_TYPE_COMBO_NOENC,
120 VPU_DEC_TYPE_9190 = 0,
121 VPU_ENC_TYPE_8270 = 0x100,
125 typedef enum VPU_FREQ {
138 unsigned long hw_addr;
139 unsigned long enc_offset;
140 unsigned long enc_reg_num;
141 unsigned long enc_io_size;
142 unsigned long dec_offset;
143 unsigned long dec_reg_num;
144 unsigned long dec_io_size;
147 struct extra_info_elem {
152 #define EXTRA_INFO_MAGIC 0x4C4A46
154 struct extra_info_for_iommu {
157 struct extra_info_elem elem[20];
160 #define MHZ (1000*1000)
162 #define REG_NUM_9190_DEC (60)
163 #define REG_NUM_9190_PP (41)
164 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
166 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
168 #define REG_NUM_ENC_8270 (96)
169 #define REG_SIZE_ENC_8270 (0x200)
170 #define REG_NUM_ENC_4831 (164)
171 #define REG_SIZE_ENC_4831 (0x400)
173 #define REG_NUM_HEVC_DEC (68)
175 #define SIZE_REG(reg) ((reg)*4)
177 static VPU_HW_INFO_E vpu_hw_set[] = {
179 .hw_id = VPU_ID_8270,
182 .enc_reg_num = REG_NUM_ENC_8270,
183 .enc_io_size = REG_NUM_ENC_8270 * 4,
184 .dec_offset = REG_SIZE_ENC_8270,
185 .dec_reg_num = REG_NUM_9190_DEC_PP,
186 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
189 .hw_id = VPU_ID_4831,
192 .enc_reg_num = REG_NUM_ENC_4831,
193 .enc_io_size = REG_NUM_ENC_4831 * 4,
194 .dec_offset = REG_SIZE_ENC_4831,
195 .dec_reg_num = REG_NUM_9190_DEC_PP,
196 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
202 .dec_reg_num = REG_NUM_HEVC_DEC,
203 .dec_io_size = REG_NUM_HEVC_DEC * 4,
206 .hw_id = VPU_DEC_ID_9190,
212 .dec_reg_num = REG_NUM_9190_DEC_PP,
213 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
218 #define BIT(x) (1<<(x))
221 // interrupt and error status register
222 #define DEC_INTERRUPT_REGISTER 1
223 #define DEC_INTERRUPT_BIT BIT(8)
224 #define DEC_READY_BIT BIT(12)
225 #define DEC_BUS_ERROR_BIT BIT(13)
226 #define DEC_BUFFER_EMPTY_BIT BIT(14)
227 #define DEC_ASO_ERROR_BIT BIT(15)
228 #define DEC_STREAM_ERROR_BIT BIT(16)
229 #define DEC_SLICE_DONE_BIT BIT(17)
230 #define DEC_TIMEOUT_BIT BIT(18)
231 #define DEC_ERR_MASK DEC_BUS_ERROR_BIT \
232 |DEC_BUFFER_EMPTY_BIT \
233 |DEC_STREAM_ERROR_BIT \
236 #define PP_INTERRUPT_REGISTER 60
237 #define PP_INTERRUPT_BIT BIT(8)
238 #define PP_READY_BIT BIT(12)
239 #define PP_BUS_ERROR_BIT BIT(13)
240 #define PP_ERR_MASK PP_BUS_ERROR_BIT
242 #define ENC_INTERRUPT_REGISTER 1
243 #define ENC_INTERRUPT_BIT BIT(0)
244 #define ENC_READY_BIT BIT(2)
245 #define ENC_BUS_ERROR_BIT BIT(3)
246 #define ENC_BUFFER_FULL_BIT BIT(5)
247 #define ENC_TIMEOUT_BIT BIT(6)
248 #define ENC_ERR_MASK ENC_BUS_ERROR_BIT \
249 |ENC_BUFFER_FULL_BIT \
252 #define HEVC_INTERRUPT_REGISTER 1
253 #define HEVC_DEC_INT_RAW_BIT BIT(9)
254 #define HEVC_DEC_BUS_ERROR_BIT BIT(13)
255 #define HEVC_DEC_STR_ERROR_BIT BIT(14)
256 #define HEVC_DEC_TIMEOUT_BIT BIT(15)
257 #define HEVC_DEC_BUFFER_EMPTY_BIT BIT(16)
258 #define HEVC_DEC_COLMV_ERROR_BIT BIT(17)
259 #define HEVC_DEC_ERR_MASK HEVC_DEC_BUS_ERROR_BIT \
260 |HEVC_DEC_STR_ERROR_BIT \
261 |HEVC_DEC_TIMEOUT_BIT \
262 |HEVC_DEC_BUFFER_EMPTY_BIT \
263 |HEVC_DEC_COLMV_ERROR_BIT
266 // gating configuration set
267 #define VPU_REG_EN_ENC 14
268 #define VPU_REG_ENC_GATE 2
269 #define VPU_REG_ENC_GATE_BIT (1<<4)
271 #define VPU_REG_EN_DEC 1
272 #define VPU_REG_DEC_GATE 2
273 #define VPU_REG_DEC_GATE_BIT (1<<10)
274 #define VPU_REG_EN_PP 0
275 #define VPU_REG_PP_GATE 1
276 #define VPU_REG_PP_GATE_BIT (1<<8)
277 #define VPU_REG_EN_DEC_PP 1
278 #define VPU_REG_DEC_PP_GATE 61
279 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
283 #define vpu_debug_func(type, fmt, args...) \
285 if (unlikely(debug & type)) { \
286 pr_info("%s:%d: " fmt, \
287 __func__, __LINE__, ##args); \
290 #define vpu_debug(type, fmt, args...) \
292 if (unlikely(debug & type)) { \
293 pr_info(fmt, ##args); \
297 #define vpu_debug_func(level, fmt, args...)
298 #define vpu_debug(level, fmt, args...)
301 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
302 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
304 #define vpu_err(fmt, args...) \
305 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
307 #if defined(CONFIG_VCODEC_MMU)
308 static u8 addr_tbl_vpu_h264dec[] = {
309 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
310 25, 26, 27, 28, 29, 40, 41
313 static u8 addr_tbl_vpu_vp8dec[] = {
314 10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
317 static u8 addr_tbl_vpu_vp6dec[] = {
318 12, 13, 14, 18, 27, 40
321 static u8 addr_tbl_vpu_vc1dec[] = {
322 12, 13, 14, 15, 16, 17, 27, 41
325 static u8 addr_tbl_vpu_jpegdec[] = {
329 static u8 addr_tbl_vpu_defaultdec[] = {
330 12, 13, 14, 15, 16, 17, 40, 41
333 static u8 addr_tbl_vpu_enc[] = {
334 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
337 static u8 addr_tbl_hevc_dec[] = {
338 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
339 21, 22, 23, 24, 42, 43
364 * struct for process session which connect to vpu
366 * @author ChenHengming (2011-5-3)
368 typedef struct vpu_session {
369 enum VPU_CLIENT_TYPE type;
370 /* a linked list of data so we can access them for debugging */
371 struct list_head list_session;
372 /* a linked list of register data waiting for process */
373 struct list_head waiting;
374 /* a linked list of register data in processing */
375 struct list_head running;
376 /* a linked list of register data processed */
377 struct list_head done;
378 wait_queue_head_t wait;
380 atomic_t task_running;
384 * struct for process register set
386 * @author ChenHengming (2011-5-4)
388 typedef struct vpu_reg {
389 enum VPU_CLIENT_TYPE type;
391 vpu_session *session;
392 struct vpu_subdev_data *data;
393 struct list_head session_link; /* link to vpu service session */
394 struct list_head status_link; /* link to register set list */
396 #if defined(CONFIG_VCODEC_MMU)
397 struct list_head mem_region_list;
402 typedef struct vpu_device {
403 atomic_t irq_count_codec;
404 atomic_t irq_count_pp;
405 unsigned long iobaseaddr;
407 volatile u32 *hwregs;
410 enum vcodec_device_id {
411 VCODEC_DEVICE_ID_VPU,
412 VCODEC_DEVICE_ID_HEVC,
413 VCODEC_DEVICE_ID_COMBO
416 enum VCODEC_RUNNING_MODE {
417 VCODEC_RUNNING_MODE_NONE = -1,
418 VCODEC_RUNNING_MODE_VPU,
419 VCODEC_RUNNING_MODE_HEVC,
422 struct vcodec_mem_region {
423 struct list_head srv_lnk;
424 struct list_head reg_lnk;
425 struct list_head session_lnk;
426 unsigned long iova; /* virtual address for iommu */
429 struct ion_handle *hdl;
433 MMU_ACTIVATED = BIT(0)
436 struct vpu_subdev_data {
440 struct device *child_dev;
444 struct vpu_service_info *pservice;
447 enum VCODEC_RUNNING_MODE mode;
448 struct list_head lnk_service;
454 VPU_HW_INFO_E *hw_info;
459 #ifdef CONFIG_DEBUG_FS
460 struct dentry *debugfs_dir;
461 struct dentry *debugfs_file_regs;
464 #if defined(CONFIG_VCODEC_MMU)
465 struct device *mmu_dev;
469 typedef struct vpu_service_info {
470 struct wake_lock wake_lock;
471 struct delayed_work power_off_work;
473 struct list_head waiting; /* link to link_reg in struct vpu_reg */
474 struct list_head running; /* link to link_reg in struct vpu_reg */
475 struct list_head done; /* link to link_reg in struct vpu_reg */
476 struct list_head session; /* link to list_session in struct vpu_session */
477 atomic_t total_running;
479 atomic_t power_on_cnt;
480 atomic_t power_off_cnt;
484 struct vpu_dec_config dec_config;
485 struct vpu_enc_config enc_config;
489 atomic_t freq_status;
491 struct clk *aclk_vcodec;
492 struct clk *hclk_vcodec;
493 struct clk *clk_core;
494 struct clk *clk_cabac;
495 struct clk *pd_video;
500 atomic_t reset_request;
501 #if defined(CONFIG_VCODEC_MMU)
502 struct ion_client *ion_client;
503 struct list_head mem_region_list;
506 enum vcodec_device_id dev_id;
508 enum VCODEC_RUNNING_MODE curr_mode;
511 struct delayed_work simulate_work;
517 #ifdef CONFIG_MFD_SYSCON
518 struct regmap *grf_base;
525 struct list_head subdev_list;
528 struct vcodec_combo {
529 struct vpu_service_info *vpu_srv;
530 struct vpu_service_info *hevc_srv;
531 struct list_head waiting;
532 struct list_head running;
533 struct mutex run_lock;
535 enum vcodec_device_id current_hw_mode;
544 struct compat_vpu_request {
550 /* debugfs root directory for all device (vpu, hevc).*/
551 static struct dentry *parent;
553 #ifdef CONFIG_DEBUG_FS
554 static int vcodec_debugfs_init(void);
555 static void vcodec_debugfs_exit(void);
556 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
557 static int debug_vcodec_open(struct inode *inode, struct file *file);
559 static const struct file_operations debug_vcodec_fops = {
560 .open = debug_vcodec_open,
563 .release = single_release,
567 #define VDPU_SOFT_RESET_REG 101
568 #define VDPU_CLEAN_CACHE_REG 516
569 #define VEPU_CLEAN_CACHE_REG 772
570 #define HEVC_CLEAN_CACHE_REG 260
572 #define VPU_REG_ENABLE(base, reg) do { \
576 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
577 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
578 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
579 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
581 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
582 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
586 struct timeval start;
599 task_info tasks[TASK_TYPE_BUTT] = {
602 .error_mask = ENC_ERR_MASK
606 .error_mask = DEC_ERR_MASK
610 .error_mask = PP_ERR_MASK
614 .error_mask = HEVC_DEC_ERR_MASK
618 static void time_record(task_info *task, int is_end)
620 if (unlikely(debug & DEBUG_TIMING)) {
621 do_gettimeofday((is_end)?(&task->end):(&task->start));
625 static void time_diff(task_info *task)
627 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
628 (task->end.tv_sec - task->start.tv_sec) * 1000 +
629 (task->end.tv_usec - task->start.tv_usec) / 1000);
632 static void vcodec_enter_mode(struct vpu_subdev_data *data)
636 struct vpu_service_info *pservice = data->pservice;
637 struct vpu_subdev_data *subdata, *n;
638 if (pservice->subcnt < 2) {
639 #if defined(CONFIG_VCODEC_MMU)
640 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
641 set_bit(MMU_ACTIVATED, &data->state);
642 if (atomic_read(&pservice->enabled))
643 rockchip_iovmm_activate(data->dev);
645 BUG_ON(!atomic_read(&pservice->enabled));
651 if (pservice->curr_mode == data->mode)
654 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
655 #if defined(CONFIG_VCODEC_MMU)
656 list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
657 if (data != subdata && subdata->mmu_dev &&
658 test_bit(MMU_ACTIVATED, &subdata->state)) {
659 clear_bit(MMU_ACTIVATED, &subdata->state);
660 rockchip_iovmm_deactivate(subdata->dev);
664 bits = 1 << pservice->mode_bit;
665 #ifdef CONFIG_MFD_SYSCON
666 regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
668 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
669 regmap_write(pservice->grf_base, pservice->mode_ctrl,
670 raw | bits | (bits << 16));
672 regmap_write(pservice->grf_base, pservice->mode_ctrl,
673 (raw & (~bits)) | (bits << 16));
675 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
676 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
677 writel_relaxed(raw | bits | (bits << 16),
678 pservice->grf_base + pservice->mode_ctrl / 4);
680 writel_relaxed((raw & (~bits)) | (bits << 16),
681 pservice->grf_base + pservice->mode_ctrl / 4);
683 #if defined(CONFIG_VCODEC_MMU)
684 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
685 set_bit(MMU_ACTIVATED, &data->state);
686 if (atomic_read(&pservice->enabled))
687 rockchip_iovmm_activate(data->dev);
689 BUG_ON(!atomic_read(&pservice->enabled));
692 pservice->prev_mode = pservice->curr_mode;
693 pservice->curr_mode = data->mode;
696 static void vcodec_exit_mode(struct vpu_subdev_data *data)
698 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
699 clear_bit(MMU_ACTIVATED, &data->state);
700 rockchip_iovmm_deactivate(data->dev);
701 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
705 static int vpu_get_clk(struct vpu_service_info *pservice)
707 #if VCODEC_CLOCK_ENABLE
708 switch (pservice->dev_id) {
709 case VCODEC_DEVICE_ID_HEVC:
710 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
711 if (IS_ERR(pservice->pd_video)) {
712 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
715 case VCODEC_DEVICE_ID_COMBO:
716 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
717 if (IS_ERR(pservice->clk_cabac)) {
718 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
719 pservice->clk_cabac = NULL;
721 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
722 if (IS_ERR(pservice->clk_core)) {
723 dev_err(pservice->dev, "failed on clk_get clk_core\n");
726 case VCODEC_DEVICE_ID_VPU:
727 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
728 if (IS_ERR(pservice->aclk_vcodec)) {
729 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
733 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
734 if (IS_ERR(pservice->hclk_vcodec)) {
735 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
738 if (pservice->pd_video == NULL) {
739 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
740 if (IS_ERR(pservice->pd_video)) {
741 pservice->pd_video = NULL;
742 dev_info(pservice->dev, "do not have pd_video\n");
756 static void vpu_put_clk(struct vpu_service_info *pservice)
758 #if VCODEC_CLOCK_ENABLE
759 if (pservice->pd_video)
760 devm_clk_put(pservice->dev, pservice->pd_video);
761 if (pservice->aclk_vcodec)
762 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
763 if (pservice->hclk_vcodec)
764 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
765 if (pservice->clk_core)
766 devm_clk_put(pservice->dev, pservice->clk_core);
767 if (pservice->clk_cabac)
768 devm_clk_put(pservice->dev, pservice->clk_cabac);
772 static const u8 pmu_idle_map[] = {
773 [IDLE_REQ_VIDEO] = 7,
776 extern void __iomem *rk_cru_base;
777 static void cru_writel(u32 val, u32 offset)
779 writel_relaxed(val, rk_cru_base + (offset));
783 extern int rk3368_pmu_set_idle_request(enum pmu_idle_req req, bool idle);
784 static inline void rk3368_cru_set_soft_reset(u32 idx, bool on)
786 u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
787 cru_writel(val, 0x31c);
789 #define SOFT_RST_VCODEC_AXI (7*16)
790 #define SOFT_RST_VCODEC_AHB (7*16+1)
792 static void vpu_reset(struct vpu_subdev_data *data)
794 struct vpu_service_info *pservice = data->pservice;
795 pr_info("%s: resetting...", dev_name(pservice->dev));
797 #if defined(CONFIG_ARCH_RK29)
798 clk_disable(aclk_ddr_vepu);
799 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
800 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
801 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
802 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
804 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
805 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
806 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
807 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
808 clk_enable(aclk_ddr_vepu);
809 #elif defined(CONFIG_ARCH_RK30)
810 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
811 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
812 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
813 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
814 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
816 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
817 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
818 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
819 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
820 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
823 WARN_ON(pservice->reg_codec != NULL);
824 WARN_ON(pservice->reg_pproc != NULL);
825 WARN_ON(pservice->reg_resev != NULL);
826 pservice->reg_codec = NULL;
827 pservice->reg_pproc = NULL;
828 pservice->reg_resev = NULL;
830 pr_info("for 3288/3368...");
831 /**rk3368_pmu_set_idle_request(IDLE_REQ_VIDEO, true);*/
832 /*rockchip_pmu_ops.set_idle_request(IDLE_REQ_VIDEO, true);*/
833 /**rockchip_pmu_ops.set_power_domain(PD_VIDEO, false);*/
834 /*rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
835 rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
837 rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
838 rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);*/
839 /**rockchip_pmu_ops.set_power_domain(PD_VIDEO, true);*/
840 /*rockchip_pmu_ops.set_idle_request(IDLE_REQ_VIDEO, false);*/
841 /**rk3368_pmu_set_idle_request(IDLE_REQ_VIDEO, false);*/
843 #if defined(CONFIG_VCODEC_MMU)
844 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
845 clear_bit(MMU_ACTIVATED, &data->state);
846 if (atomic_read(&pservice->enabled))
847 rockchip_iovmm_deactivate(data->dev);
849 BUG_ON(!atomic_read(&pservice->enabled));
852 atomic_set(&pservice->reset_request, 0);
856 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
857 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
860 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
861 reg_deinit(data, reg);
863 list_for_each_entry_safe(reg, n, &session->running, session_link) {
864 reg_deinit(data, reg);
866 list_for_each_entry_safe(reg, n, &session->done, session_link) {
867 reg_deinit(data, reg);
871 static void vpu_service_dump(struct vpu_service_info *pservice)
875 static void vpu_service_power_off(struct vpu_service_info *pservice)
878 struct vpu_subdev_data *data = NULL, *n;
879 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
883 total_running = atomic_read(&pservice->total_running);
885 pr_alert("alert: power off when %d task running!!\n", total_running);
887 pr_alert("alert: delay 50 ms for running task\n");
888 vpu_service_dump(pservice);
891 pr_info("%s: power off...", dev_name(pservice->dev));
893 #if defined(CONFIG_VCODEC_MMU)
894 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
895 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
896 clear_bit(MMU_ACTIVATED, &data->state);
897 rockchip_iovmm_deactivate(data->dev);
900 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
903 #if VCODEC_CLOCK_ENABLE
904 if (pservice->pd_video)
905 clk_disable_unprepare(pservice->pd_video);
906 if (pservice->hclk_vcodec)
907 clk_disable_unprepare(pservice->hclk_vcodec);
908 if (pservice->aclk_vcodec)
909 clk_disable_unprepare(pservice->aclk_vcodec);
910 if (pservice->clk_core)
911 clk_disable_unprepare(pservice->clk_core);
912 if (pservice->clk_cabac)
913 clk_disable_unprepare(pservice->clk_cabac);
916 atomic_add(1, &pservice->power_off_cnt);
917 wake_unlock(&pservice->wake_lock);
921 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
923 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
926 static void vpu_power_off_work(struct work_struct *work_s)
928 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
929 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
931 if (mutex_trylock(&pservice->lock)) {
932 vpu_service_power_off(pservice);
933 mutex_unlock(&pservice->lock);
935 /* Come back later if the device is busy... */
936 vpu_queue_power_off_work(pservice);
940 static void vpu_service_power_on(struct vpu_service_info *pservice)
944 ktime_t now = ktime_get();
945 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
946 cancel_delayed_work_sync(&pservice->power_off_work);
947 vpu_queue_power_off_work(pservice);
950 ret = atomic_add_unless(&pservice->enabled, 1, 1);
954 pr_info("%s: power on\n", dev_name(pservice->dev));
956 #define BIT_VCODEC_CLK_SEL (1<<10)
958 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
959 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
960 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
962 #if VCODEC_CLOCK_ENABLE
963 if (pservice->aclk_vcodec)
964 clk_prepare_enable(pservice->aclk_vcodec);
965 if (pservice->hclk_vcodec)
966 clk_prepare_enable(pservice->hclk_vcodec);
967 if (pservice->clk_core)
968 clk_prepare_enable(pservice->clk_core);
969 if (pservice->clk_cabac)
970 clk_prepare_enable(pservice->clk_cabac);
971 if (pservice->pd_video)
972 clk_prepare_enable(pservice->pd_video);
976 atomic_add(1, &pservice->power_on_cnt);
977 wake_lock(&pservice->wake_lock);
980 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
982 u32 type = (reg->reg[3] & 0xF0000000) >> 28;
983 return ((type == 8) || (type == 4));
986 static inline bool reg_check_interlace(vpu_reg *reg)
988 u32 type = (reg->reg[3] & (1 << 23));
992 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
994 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
998 static inline int reg_probe_width(vpu_reg *reg)
1000 int width_in_mb = reg->reg[4] >> 23;
1001 return width_in_mb * 16;
1004 #if defined(CONFIG_VCODEC_MMU)
1005 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
1007 struct vpu_service_info *pservice = data->pservice;
1008 struct ion_handle *hdl;
1010 struct vcodec_mem_region *mem_region;
1012 hdl = ion_import_dma_buf(pservice->ion_client, fd);
1014 vpu_err("import dma-buf from fd %d failed\n", fd);
1015 return PTR_ERR(hdl);
1017 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1019 if (mem_region == NULL) {
1020 vpu_err("allocate memory for iommu memory region failed\n");
1021 ion_free(pservice->ion_client, hdl);
1025 mem_region->hdl = hdl;
1026 ret = ion_map_iommu(data->dev, pservice->ion_client,
1027 mem_region->hdl, &mem_region->iova, &mem_region->len);
1030 vpu_err("ion map iommu failed\n");
1032 ion_free(pservice->ion_client, hdl);
1035 INIT_LIST_HEAD(&mem_region->reg_lnk);
1036 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1037 return mem_region->iova;
1040 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1041 int size, vpu_reg *reg,
1042 struct extra_info_for_iommu *ext_inf)
1044 struct vpu_service_info *pservice = data->pservice;
1049 if (tbl == NULL || size <= 0) {
1050 dev_err(pservice->dev, "input arguments invalidate\n");
1054 for (i = 0; i < size; i++) {
1055 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1057 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1058 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1059 /* special for vpu dec num 41 regitster */
1060 offset = reg->reg[tbl[i]] >> 10 << 4;
1062 offset = reg->reg[tbl[i]] >> 10;
1065 struct ion_handle *hdl;
1067 struct vcodec_mem_region *mem_region;
1069 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1071 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1072 return PTR_ERR(hdl);
1075 if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1078 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1079 for (i=0; i<64; i++) {
1083 scaling_offset = (u32)pps[i*80+74];
1084 scaling_offset += (u32)pps[i*80+75] << 8;
1085 scaling_offset += (u32)pps[i*80+76] << 16;
1086 scaling_offset += (u32)pps[i*80+77] << 24;
1087 scaling_fd = scaling_offset&0x3ff;
1088 scaling_offset = scaling_offset >> 10;
1089 if(scaling_fd > 0) {
1090 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1091 tmp += scaling_offset;
1092 pps[i*80+74] = tmp & 0xff;
1093 pps[i*80+75] = (tmp >> 8) & 0xff;
1094 pps[i*80+76] = (tmp >> 16) & 0xff;
1095 pps[i*80+77] = (tmp >> 24) & 0xff;
1100 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1102 if (mem_region == NULL) {
1103 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1104 ion_free(pservice->ion_client, hdl);
1108 mem_region->hdl = hdl;
1109 mem_region->reg_idx = tbl[i];
1110 ret = ion_map_iommu(data->dev,
1111 pservice->ion_client,
1117 dev_err(pservice->dev, "ion map iommu failed\n");
1119 ion_free(pservice->ion_client, hdl);
1122 reg->reg[tbl[i]] = mem_region->iova + offset;
1123 INIT_LIST_HEAD(&mem_region->reg_lnk);
1124 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1128 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1129 for (i=0; i<ext_inf->cnt; i++) {
1130 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1131 ext_inf->elem[i].index,
1132 ext_inf->elem[i].offset);
1133 reg->reg[ext_inf->elem[i].index] +=
1134 ext_inf->elem[i].offset;
1141 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1143 struct extra_info_for_iommu *ext_inf)
1149 hw_id = data->hw_info->hw_id;
1151 if (hw_id == HEVC_ID) {
1152 tbl = addr_tbl_hevc_dec;
1153 size = sizeof(addr_tbl_hevc_dec);
1155 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1156 switch (reg_check_fmt(reg)) {
1157 case VPU_DEC_FMT_H264:
1159 tbl = addr_tbl_vpu_h264dec;
1160 size = sizeof(addr_tbl_vpu_h264dec);
1163 case VPU_DEC_FMT_VP8:
1164 case VPU_DEC_FMT_VP7:
1166 tbl = addr_tbl_vpu_vp8dec;
1167 size = sizeof(addr_tbl_vpu_vp8dec);
1171 case VPU_DEC_FMT_VP6:
1173 tbl = addr_tbl_vpu_vp6dec;
1174 size = sizeof(addr_tbl_vpu_vp6dec);
1177 case VPU_DEC_FMT_VC1:
1179 tbl = addr_tbl_vpu_vc1dec;
1180 size = sizeof(addr_tbl_vpu_vc1dec);
1184 case VPU_DEC_FMT_JPEG:
1186 tbl = addr_tbl_vpu_jpegdec;
1187 size = sizeof(addr_tbl_vpu_jpegdec);
1191 tbl = addr_tbl_vpu_defaultdec;
1192 size = sizeof(addr_tbl_vpu_defaultdec);
1195 } else if (reg->type == VPU_ENC) {
1196 tbl = addr_tbl_vpu_enc;
1197 size = sizeof(addr_tbl_vpu_enc);
1202 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1209 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1210 vpu_session *session, void __user *src, u32 size)
1212 struct vpu_service_info *pservice = data->pservice;
1214 struct extra_info_for_iommu extra_info;
1215 vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1220 vpu_err("error: kmalloc fail in reg_init\n");
1224 if (size > data->reg_size) {
1225 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1226 size, data->reg_size);*/
1227 extra_size = size - data->reg_size;
1228 size = data->reg_size;
1230 reg->session = session;
1232 reg->type = session->type;
1234 reg->freq = VPU_FREQ_DEFAULT;
1235 reg->reg = (u32 *)®[1];
1236 INIT_LIST_HEAD(®->session_link);
1237 INIT_LIST_HEAD(®->status_link);
1239 #if defined(CONFIG_VCODEC_MMU)
1241 INIT_LIST_HEAD(®->mem_region_list);
1244 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1245 vpu_err("error: copy_from_user failed in reg_init\n");
1250 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1251 vpu_err("error: copy_from_user failed in reg_init\n");
1256 #if defined(CONFIG_VCODEC_MMU)
1257 if (data->mmu_dev &&
1258 0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1259 vpu_err("error: translate reg address failed\n");
1265 mutex_lock(&pservice->lock);
1266 list_add_tail(®->status_link, &pservice->waiting);
1267 list_add_tail(®->session_link, &session->waiting);
1268 mutex_unlock(&pservice->lock);
1270 if (pservice->auto_freq) {
1271 if (!soc_is_rk2928g()) {
1272 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1273 if (reg_check_rmvb_wmv(reg)) {
1274 reg->freq = VPU_FREQ_200M;
1275 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1276 if (reg_probe_width(reg) > 3200) {
1277 /*raise frequency for 4k avc.*/
1278 reg->freq = VPU_FREQ_500M;
1281 if (reg_check_interlace(reg)) {
1282 reg->freq = VPU_FREQ_400M;
1286 if (reg->type == VPU_PP) {
1287 reg->freq = VPU_FREQ_400M;
1295 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1297 struct vpu_service_info *pservice = data->pservice;
1298 #if defined(CONFIG_VCODEC_MMU)
1299 struct vcodec_mem_region *mem_region = NULL, *n;
1302 list_del_init(®->session_link);
1303 list_del_init(®->status_link);
1304 if (reg == pservice->reg_codec)
1305 pservice->reg_codec = NULL;
1306 if (reg == pservice->reg_pproc)
1307 pservice->reg_pproc = NULL;
1309 #if defined(CONFIG_VCODEC_MMU)
1310 /* release memory region attach to this registers table. */
1311 if (data->mmu_dev) {
1312 list_for_each_entry_safe(mem_region, n,
1313 ®->mem_region_list, reg_lnk) {
1314 /* do not unmap iommu manually,
1315 unmap will proccess when memory release */
1316 /*vcodec_enter_mode(data);
1317 ion_unmap_iommu(data->dev,
1318 pservice->ion_client,
1320 vcodec_exit_mode();*/
1321 ion_free(pservice->ion_client, mem_region->hdl);
1322 list_del_init(&mem_region->reg_lnk);
1331 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1334 list_del_init(®->status_link);
1335 list_add_tail(®->status_link, &pservice->running);
1337 list_del_init(®->session_link);
1338 list_add_tail(®->session_link, ®->session->running);
1342 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1345 u32 *dst = (u32 *)®->reg[0];
1347 for (i = 0; i < count; i++)
1352 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1355 struct vpu_service_info *pservice = data->pservice;
1360 list_del_init(®->status_link);
1361 list_add_tail(®->status_link, &pservice->done);
1363 list_del_init(®->session_link);
1364 list_add_tail(®->session_link, ®->session->done);
1366 /*vcodec_enter_mode(data);*/
1367 switch (reg->type) {
1369 pservice->reg_codec = NULL;
1370 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1371 irq_reg = ENC_INTERRUPT_REGISTER;
1375 int reg_len = REG_NUM_9190_DEC;
1376 pservice->reg_codec = NULL;
1377 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1378 irq_reg = DEC_INTERRUPT_REGISTER;
1382 pservice->reg_pproc = NULL;
1383 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1384 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1388 pservice->reg_codec = NULL;
1389 pservice->reg_pproc = NULL;
1390 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1391 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1395 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1399 vcodec_exit_mode(data);
1402 reg->reg[irq_reg] = pservice->irq_status;
1404 atomic_sub(1, ®->session->task_running);
1405 atomic_sub(1, &pservice->total_running);
1406 wake_up(®->session->wait);
1411 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1413 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1414 if (curr == reg->freq)
1416 atomic_set(&pservice->freq_status, reg->freq);
1417 switch (reg->freq) {
1418 case VPU_FREQ_200M : {
1419 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1421 case VPU_FREQ_266M : {
1422 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1424 case VPU_FREQ_300M : {
1425 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1427 case VPU_FREQ_400M : {
1428 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1430 case VPU_FREQ_500M : {
1431 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1433 case VPU_FREQ_600M : {
1434 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1437 if (soc_is_rk2928g())
1438 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1440 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1445 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1447 struct vpu_service_info *pservice = data->pservice;
1449 u32 *src = (u32 *)®->reg[0];
1452 atomic_add(1, &pservice->total_running);
1453 atomic_add(1, ®->session->task_running);
1454 if (pservice->auto_freq)
1455 vpu_service_set_freq(pservice, reg);
1457 vcodec_enter_mode(data);
1459 switch (reg->type) {
1461 int enc_count = data->hw_info->enc_reg_num;
1462 u32 *dst = (u32 *)data->enc_dev.hwregs;
1464 pservice->reg_codec = reg;
1466 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1468 for (i = 0; i < VPU_REG_EN_ENC; i++)
1471 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1474 VEPU_CLEAN_CACHE(dst);
1478 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1479 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1481 time_record(&tasks[TASK_VPU_ENC], 0);
1484 u32 *dst = (u32 *)data->dec_dev.hwregs;
1486 pservice->reg_codec = reg;
1488 if (data->hw_info->hw_id != HEVC_ID) {
1489 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1491 VDPU_CLEAN_CACHE(dst);
1493 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1495 HEVC_CLEAN_CACHE(dst);
1500 if (data->hw_info->hw_id != HEVC_ID) {
1501 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1502 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1504 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1509 time_record(&tasks[TASK_VPU_DEC], 0);
1512 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1513 pservice->reg_pproc = reg;
1515 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1517 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1522 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1524 time_record(&tasks[TASK_VPU_PP], 0);
1527 u32 *dst = (u32 *)data->dec_dev.hwregs;
1528 pservice->reg_codec = reg;
1529 pservice->reg_pproc = reg;
1531 VDPU_SOFT_RESET(dst);
1532 VDPU_CLEAN_CACHE(dst);
1534 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1537 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1540 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1541 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1542 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1544 time_record(&tasks[TASK_VPU_DEC], 0);
1547 vpu_err("error: unsupport session type %d", reg->type);
1548 atomic_sub(1, &pservice->total_running);
1549 atomic_sub(1, ®->session->task_running);
1553 /*vcodec_exit_mode(data);*/
1557 static void try_set_reg(struct vpu_subdev_data *data)
1559 struct vpu_service_info *pservice = data->pservice;
1561 if (!list_empty(&pservice->waiting)) {
1563 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1564 int reset_request = atomic_read(&pservice->reset_request);
1565 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1567 vpu_service_power_on(pservice);
1569 // first check can_set flag
1570 if (change_able || !reset_request) {
1571 switch (reg->type) {
1577 if (NULL == pservice->reg_codec)
1579 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1583 if (NULL == pservice->reg_codec) {
1584 if (NULL == pservice->reg_pproc)
1587 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1589 /* can not charge frequency when vpu is working */
1590 if (pservice->auto_freq)
1599 printk("undefined reg type %d\n", reg->type);
1604 // then check reset request
1605 if (reset_request && !change_able)
1608 // do reset before setting registers
1613 reg_from_wait_to_run(pservice, reg);
1614 reg_copy_to_hw(reg->data, reg);
1620 static int return_reg(struct vpu_subdev_data *data,
1621 vpu_reg *reg, u32 __user *dst)
1625 switch (reg->type) {
1627 if (copy_to_user(dst, ®->reg[0], data->hw_info->enc_io_size))
1632 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1633 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1638 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1643 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1649 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1653 reg_deinit(data, reg);
1658 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1661 struct vpu_subdev_data *data =
1662 container_of(filp->f_dentry->d_inode->i_cdev,
1663 struct vpu_subdev_data, cdev);
1664 struct vpu_service_info *pservice = data->pservice;
1665 vpu_session *session = (vpu_session *)filp->private_data;
1667 if (NULL == session)
1671 case VPU_IOC_SET_CLIENT_TYPE : {
1672 session->type = (enum VPU_CLIENT_TYPE)arg;
1673 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1676 case VPU_IOC_GET_HW_FUSE_STATUS : {
1677 struct vpu_request req;
1678 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1679 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1680 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1683 if (VPU_ENC != session->type) {
1684 if (copy_to_user((void __user *)req.req,
1685 &pservice->dec_config,
1686 sizeof(struct vpu_dec_config))) {
1687 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1692 if (copy_to_user((void __user *)req.req,
1693 &pservice->enc_config,
1694 sizeof(struct vpu_enc_config ))) {
1695 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1704 case VPU_IOC_SET_REG : {
1705 struct vpu_request req;
1707 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1708 if (copy_from_user(&req, (void __user *)arg,
1709 sizeof(struct vpu_request))) {
1710 vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1713 reg = reg_init(data, session,
1714 (void __user *)req.req, req.size);
1718 mutex_lock(&pservice->lock);
1720 mutex_unlock(&pservice->lock);
1725 case VPU_IOC_GET_REG : {
1726 struct vpu_request req;
1728 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1729 if (copy_from_user(&req, (void __user *)arg,
1730 sizeof(struct vpu_request))) {
1731 vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1734 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1735 if (!list_empty(&session->done)) {
1737 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1741 if (unlikely(ret < 0)) {
1742 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1743 } else if (0 == ret) {
1744 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1749 int task_running = atomic_read(&session->task_running);
1750 mutex_lock(&pservice->lock);
1751 vpu_service_dump(pservice);
1753 atomic_set(&session->task_running, 0);
1754 atomic_sub(task_running, &pservice->total_running);
1755 printk("%d task is running but not return, reset hardware...", task_running);
1759 vpu_service_session_clear(data, session);
1760 mutex_unlock(&pservice->lock);
1764 mutex_lock(&pservice->lock);
1765 reg = list_entry(session->done.next, vpu_reg, session_link);
1766 return_reg(data, reg, (u32 __user *)req.req);
1767 mutex_unlock(&pservice->lock);
1770 case VPU_IOC_PROBE_IOMMU_STATUS: {
1771 int iommu_enable = 0;
1773 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1775 #if defined(CONFIG_VCODEC_MMU)
1776 iommu_enable = data->mmu_dev ? 1 : 0;
1779 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1780 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1786 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1794 #ifdef CONFIG_COMPAT
1795 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1798 struct vpu_subdev_data *data =
1799 container_of(filp->f_dentry->d_inode->i_cdev,
1800 struct vpu_subdev_data, cdev);
1801 struct vpu_service_info *pservice = data->pservice;
1802 vpu_session *session = (vpu_session *)filp->private_data;
1804 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1805 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1806 if (NULL == session)
1810 case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1811 session->type = (enum VPU_CLIENT_TYPE)arg;
1812 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1815 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1816 struct compat_vpu_request req;
1817 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1818 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1819 sizeof(struct compat_vpu_request))) {
1820 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1821 " copy_from_user failed\n");
1824 if (VPU_ENC != session->type) {
1825 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1826 &pservice->dec_config,
1827 sizeof(struct vpu_dec_config))) {
1828 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1829 "copy_to_user failed type %d\n",
1834 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1835 &pservice->enc_config,
1836 sizeof(struct vpu_enc_config ))) {
1837 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1838 " copy_to_user failed type %d\n",
1847 case COMPAT_VPU_IOC_SET_REG : {
1848 struct compat_vpu_request req;
1850 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1851 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1852 sizeof(struct compat_vpu_request))) {
1853 vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1856 reg = reg_init(data, session,
1857 compat_ptr((compat_uptr_t)req.req), req.size);
1861 mutex_lock(&pservice->lock);
1863 mutex_unlock(&pservice->lock);
1868 case COMPAT_VPU_IOC_GET_REG : {
1869 struct compat_vpu_request req;
1871 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1872 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1873 sizeof(struct compat_vpu_request))) {
1874 vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1877 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1878 if (!list_empty(&session->done)) {
1880 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1884 if (unlikely(ret < 0)) {
1885 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1886 } else if (0 == ret) {
1887 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1892 int task_running = atomic_read(&session->task_running);
1893 mutex_lock(&pservice->lock);
1894 vpu_service_dump(pservice);
1896 atomic_set(&session->task_running, 0);
1897 atomic_sub(task_running, &pservice->total_running);
1898 printk("%d task is running but not return, reset hardware...", task_running);
1902 vpu_service_session_clear(data, session);
1903 mutex_unlock(&pservice->lock);
1907 mutex_lock(&pservice->lock);
1908 reg = list_entry(session->done.next, vpu_reg, session_link);
1909 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1910 mutex_unlock(&pservice->lock);
1913 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1914 int iommu_enable = 0;
1916 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1917 #if defined(CONFIG_VCODEC_MMU)
1918 iommu_enable = data->mmu_dev ? 1 : 0;
1921 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1922 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1928 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1937 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1939 int ret = -EINVAL, i = 0;
1940 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1943 enc_id = (enc_id >> 16) & 0xFFFF;
1944 pr_info("checking hw id %x\n", enc_id);
1945 data->hw_info = NULL;
1946 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1947 if (enc_id == vpu_hw_set[i].hw_id) {
1948 data->hw_info = &vpu_hw_set[i];
1953 iounmap((void *)tmp);
1957 static int vpu_service_open(struct inode *inode, struct file *filp)
1959 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1960 struct vpu_service_info *pservice = data->pservice;
1961 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1965 if (NULL == session) {
1966 vpu_err("error: unable to allocate memory for vpu_session.");
1970 session->type = VPU_TYPE_BUTT;
1971 session->pid = current->pid;
1972 INIT_LIST_HEAD(&session->waiting);
1973 INIT_LIST_HEAD(&session->running);
1974 INIT_LIST_HEAD(&session->done);
1975 INIT_LIST_HEAD(&session->list_session);
1976 init_waitqueue_head(&session->wait);
1977 atomic_set(&session->task_running, 0);
1978 mutex_lock(&pservice->lock);
1979 list_add_tail(&session->list_session, &pservice->session);
1980 filp->private_data = (void *)session;
1981 mutex_unlock(&pservice->lock);
1983 pr_debug("dev opened\n");
1985 return nonseekable_open(inode, filp);
1988 static int vpu_service_release(struct inode *inode, struct file *filp)
1990 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1991 struct vpu_service_info *pservice = data->pservice;
1993 vpu_session *session = (vpu_session *)filp->private_data;
1995 if (NULL == session)
1998 task_running = atomic_read(&session->task_running);
2000 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
2003 wake_up(&session->wait);
2005 mutex_lock(&pservice->lock);
2006 /* remove this filp from the asynchronusly notified filp's */
2007 list_del_init(&session->list_session);
2008 vpu_service_session_clear(data, session);
2010 filp->private_data = NULL;
2011 mutex_unlock(&pservice->lock);
2013 pr_debug("dev closed\n");
2018 static const struct file_operations vpu_service_fops = {
2019 .unlocked_ioctl = vpu_service_ioctl,
2020 .open = vpu_service_open,
2021 .release = vpu_service_release,
2022 #ifdef CONFIG_COMPAT
2023 .compat_ioctl = compat_vpu_service_ioctl,
2027 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2028 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2029 static irqreturn_t vepu_irq(int irq, void *dev_id);
2030 static irqreturn_t vepu_isr(int irq, void *dev_id);
2031 static void get_hw_info(struct vpu_subdev_data *data);
2033 #ifdef CONFIG_VCODEC_MMU
2034 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2036 struct device_node *dn = NULL;
2037 struct platform_device *pd = NULL;
2038 struct device *ret = NULL ;
2040 dn = of_find_compatible_node(NULL,NULL,compt);
2042 printk("can't find device node %s \r\n",compt);
2046 pd = of_find_device_by_node(dn);
2048 printk("can't find platform device in device node %s\n",compt);
2056 #ifdef CONFIG_IOMMU_API
2057 static inline void platform_set_sysmmu(struct device *iommu,
2060 dev->archdata.iommu = iommu;
2063 static inline void platform_set_sysmmu(struct device *iommu,
2069 int vcodec_sysmmu_fault_hdl(struct device *dev,
2070 enum rk_iommu_inttype itype,
2071 unsigned long pgtable_base,
2072 unsigned long fault_addr, unsigned int status)
2074 struct platform_device *pdev;
2075 struct vpu_subdev_data *data;
2076 struct vpu_service_info *pservice;
2080 pdev = container_of(dev, struct platform_device, dev);
2082 data = platform_get_drvdata(pdev);
2083 pservice = data->pservice;
2085 if (pservice->reg_codec) {
2086 struct vcodec_mem_region *mem, *n;
2088 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2089 list_for_each_entry_safe(mem, n,
2090 &pservice->reg_codec->mem_region_list,
2092 vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2093 mem->reg_idx, i, (u32)mem->iova, mem->len);
2097 pr_alert("vcodec, page fault occur, reset hw\n");
2098 pservice->reg_codec->reg[101] = 1;
2106 #if HEVC_TEST_ENABLE
2107 static int hevc_test_case0(vpu_service_info *pservice);
2109 #if defined(CONFIG_ION_ROCKCHIP)
2110 extern struct ion_client *rockchip_ion_client_create(const char * name);
2113 static int vcodec_subdev_probe(struct platform_device *pdev,
2114 struct vpu_service_info *pservice)
2117 struct resource *res = NULL;
2119 struct device *dev = &pdev->dev;
2120 char *name = (char*)dev_name(dev);
2121 struct device_node *np = pdev->dev.of_node;
2122 struct vpu_subdev_data *data =
2123 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2124 #if defined(CONFIG_VCODEC_MMU)
2126 char mmu_dev_dts_name[40];
2127 of_property_read_u32(np, "iommu_enabled", &iommu_en);
2129 pr_info("probe device %s\n", dev_name(dev));
2131 data->pservice = pservice;
2134 of_property_read_string(np, "name", (const char**)&name);
2135 of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2136 /*dev_set_name(dev, name);*/
2138 if (pservice->reg_base == 0) {
2139 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2140 data->regs = devm_ioremap_resource(dev, res);
2141 if (IS_ERR(data->regs)) {
2142 ret = PTR_ERR(data->regs);
2145 ioaddr = res->start;
2147 data->regs = pservice->reg_base;
2148 ioaddr = pservice->ioaddr;
2151 clear_bit(MMU_ACTIVATED, &data->state);
2152 vcodec_enter_mode(data);
2153 ret = vpu_service_check_hw(data, ioaddr);
2155 vpu_err("error: hw info check faild\n");
2159 data->dec_dev.iosize = data->hw_info->dec_io_size;
2160 data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2161 data->reg_size = data->dec_dev.iosize;
2163 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2164 data->enc_dev.iosize = data->hw_info->enc_io_size;
2165 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2166 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2169 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2170 if (data->irq_enc > 0) {
2171 ret = devm_request_threaded_irq(dev,
2172 data->irq_enc, vepu_irq, vepu_isr,
2173 IRQF_SHARED, dev_name(dev),
2177 "error: can't request vepu irq %d\n",
2182 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2183 if (data->irq_dec > 0) {
2184 ret = devm_request_threaded_irq(dev,
2185 data->irq_dec, vdpu_irq, vdpu_isr,
2186 IRQF_SHARED, dev_name(dev),
2190 "error: can't request vdpu irq %d\n",
2195 atomic_set(&data->dec_dev.irq_count_codec, 0);
2196 atomic_set(&data->dec_dev.irq_count_pp, 0);
2197 atomic_set(&data->enc_dev.irq_count_codec, 0);
2198 atomic_set(&data->enc_dev.irq_count_pp, 0);
2199 #if defined(CONFIG_VCODEC_MMU)
2201 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2202 sprintf(mmu_dev_dts_name,
2203 HEVC_IOMMU_COMPATIBLE_NAME);
2205 sprintf(mmu_dev_dts_name,
2206 VPU_IOMMU_COMPATIBLE_NAME);
2209 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2212 platform_set_sysmmu(data->mmu_dev, dev);
2214 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2217 vcodec_exit_mode(data);
2218 /* create device node */
2219 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2221 dev_err(dev, "alloc dev_t failed\n");
2225 cdev_init(&data->cdev, &vpu_service_fops);
2227 data->cdev.owner = THIS_MODULE;
2228 data->cdev.ops = &vpu_service_fops;
2230 ret = cdev_add(&data->cdev, data->dev_t, 1);
2233 dev_err(dev, "add dev_t failed\n");
2237 data->cls = class_create(THIS_MODULE, name);
2239 if (IS_ERR(data->cls)) {
2240 ret = PTR_ERR(data->cls);
2241 dev_err(dev, "class_create err:%d\n", ret);
2245 data->child_dev = device_create(data->cls, dev,
2246 data->dev_t, NULL, name);
2250 platform_set_drvdata(pdev, data);
2252 INIT_LIST_HEAD(&data->lnk_service);
2253 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2255 #ifdef CONFIG_DEBUG_FS
2257 vcodec_debugfs_create_device_dir((char*)name, parent);
2258 if (data->debugfs_dir == NULL)
2259 vpu_err("create debugfs dir %s failed\n", name);
2261 data->debugfs_file_regs =
2262 debugfs_create_file("regs", 0664,
2263 data->debugfs_dir, data,
2264 &debug_vcodec_fops);
2268 if (data->irq_enc > 0)
2269 free_irq(data->irq_enc, (void *)data);
2270 if (data->irq_dec > 0)
2271 free_irq(data->irq_dec, (void *)data);
2273 if (data->child_dev) {
2274 device_destroy(data->cls, data->dev_t);
2275 cdev_del(&data->cdev);
2276 unregister_chrdev_region(data->dev_t, 1);
2280 class_destroy(data->cls);
2284 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2286 device_destroy(data->cls, data->dev_t);
2287 class_destroy(data->cls);
2288 cdev_del(&data->cdev);
2289 unregister_chrdev_region(data->dev_t, 1);
2291 free_irq(data->irq_enc, (void *)&data);
2292 free_irq(data->irq_dec, (void *)&data);
2294 #ifdef CONFIG_DEBUG_FS
2295 debugfs_remove_recursive(data->debugfs_dir);
2299 static void vcodec_read_property(struct device_node *np,
2300 struct vpu_service_info *pservice)
2302 pservice->mode_bit = 0;
2303 pservice->mode_ctrl = 0;
2304 pservice->subcnt = 0;
2306 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2308 if (pservice->subcnt > 1) {
2309 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2310 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2312 #ifdef CONFIG_MFD_SYSCON
2313 pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2315 pservice->grf_base = (u32*)RK_GRF_VIRT;
2317 if (IS_ERR(pservice->grf_base)) {
2319 pservice->grf_base = RK_GRF_VIRT;
2321 vpu_err("can't find vpu grf property\n");
2325 of_property_read_string(np, "name", (const char**)&pservice->name);
2328 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2330 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2331 pservice->curr_mode = -1;
2333 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2334 INIT_LIST_HEAD(&pservice->waiting);
2335 INIT_LIST_HEAD(&pservice->running);
2336 mutex_init(&pservice->lock);
2338 INIT_LIST_HEAD(&pservice->done);
2339 INIT_LIST_HEAD(&pservice->session);
2340 INIT_LIST_HEAD(&pservice->subdev_list);
2342 pservice->reg_pproc = NULL;
2343 atomic_set(&pservice->total_running, 0);
2344 atomic_set(&pservice->enabled, 0);
2345 atomic_set(&pservice->power_on_cnt, 0);
2346 atomic_set(&pservice->power_off_cnt, 0);
2347 atomic_set(&pservice->reset_request, 0);
2349 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2351 pservice->ion_client = rockchip_ion_client_create("vpu");
2352 if (IS_ERR(pservice->ion_client)) {
2353 vpu_err("failed to create ion client for vcodec ret %ld\n",
2354 PTR_ERR(pservice->ion_client));
2356 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2360 static int vcodec_probe(struct platform_device *pdev)
2364 struct resource *res = NULL;
2365 struct device *dev = &pdev->dev;
2366 struct device_node *np = pdev->dev.of_node;
2367 struct vpu_service_info *pservice =
2368 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2370 pr_info("probe device %s\n", dev_name(dev));
2372 vcodec_read_property(np, pservice);
2373 vcodec_init_drvdata(pservice);
2375 if (strncmp(pservice->name, "hevc_service", 12) == 0)
2376 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2377 else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2378 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2380 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2382 pservice->dev = dev;
2384 if (0 > vpu_get_clk(pservice))
2387 vpu_service_power_on(pservice);
2389 if (of_property_read_bool(np, "reg")) {
2390 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2392 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2393 if (IS_ERR(pservice->reg_base)) {
2394 vpu_err("ioremap registers base failed\n");
2395 ret = PTR_ERR(pservice->reg_base);
2398 pservice->ioaddr = res->start;
2400 pservice->reg_base = 0;
2403 if (of_property_read_bool(np, "subcnt")) {
2404 for (i = 0; i<pservice->subcnt; i++) {
2405 struct device_node *sub_np;
2406 struct platform_device *sub_pdev;
2407 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2408 sub_pdev = of_find_device_by_node(sub_np);
2410 vcodec_subdev_probe(sub_pdev, pservice);
2413 vcodec_subdev_probe(pdev, pservice);
2415 platform_set_drvdata(pdev, pservice);
2417 vpu_service_power_off(pservice);
2419 pr_info("init success\n");
2424 pr_info("init failed\n");
2425 vpu_service_power_off(pservice);
2426 vpu_put_clk(pservice);
2427 wake_lock_destroy(&pservice->wake_lock);
2430 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2435 static int vcodec_remove(struct platform_device *pdev)
2437 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2438 struct resource *res;
2439 struct vpu_subdev_data *data, *n;
2441 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2442 vcodec_subdev_remove(data);
2445 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2446 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2447 vpu_put_clk(pservice);
2448 wake_lock_destroy(&pservice->wake_lock);
2453 #if defined(CONFIG_OF)
2454 static const struct of_device_id vcodec_service_dt_ids[] = {
2455 {.compatible = "vpu_service",},
2456 {.compatible = "rockchip,hevc_service",},
2457 {.compatible = "rockchip,vpu_combo",},
2462 static struct platform_driver vcodec_driver = {
2463 .probe = vcodec_probe,
2464 .remove = vcodec_remove,
2467 .owner = THIS_MODULE,
2468 #if defined(CONFIG_OF)
2469 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2474 static void get_hw_info(struct vpu_subdev_data *data)
2476 struct vpu_service_info *pservice = data->pservice;
2477 struct vpu_dec_config *dec = &pservice->dec_config;
2478 struct vpu_enc_config *enc = &pservice->enc_config;
2479 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2480 u32 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2481 u32 asicID = data->dec_dev.hwregs[0];
2483 dec->h264_support = (configReg >> DWL_H264_E) & 0x3U;
2484 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2485 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2486 dec->jpegSupport = JPEG_PROGRESSIVE;
2487 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2488 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2489 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2490 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2491 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2492 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2494 dec->maxDecPicWidth = 4096;
2496 /* 2nd Config register */
2497 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2498 if (dec->refBufSupport) {
2499 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2500 dec->refBufSupport |= 2;
2501 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2502 dec->refBufSupport |= 4;
2504 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2505 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2506 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2507 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2509 /* JPEG xtensions */
2510 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2511 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2513 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2515 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2516 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2518 dec->rvSupport = RV_NOT_SUPPORTED;
2519 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2521 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2522 dec->refBufSupport |= 8; /* enable HW support for offset */
2524 if (!cpu_is_rk3036()) {
2525 configReg = data->enc_dev.hwregs[63];
2526 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2527 enc->h264Enabled = (configReg >> 27) & 1;
2528 enc->mpeg4Enabled = (configReg >> 26) & 1;
2529 enc->jpegEnabled = (configReg >> 25) & 1;
2530 enc->vsEnabled = (configReg >> 24) & 1;
2531 enc->rgbEnabled = (configReg >> 28) & 1;
2532 enc->reg_size = data->reg_size;
2533 enc->reserv[0] = enc->reserv[1] = 0;
2535 pservice->auto_freq = true;
2536 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2537 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2539 pservice->bug_dec_addr = cpu_is_rk30xx();
2541 if (cpu_is_rk3036() || cpu_is_rk312x())
2542 dec->maxDecPicWidth = 1920;
2544 dec->maxDecPicWidth = 4096;
2545 /* disable frequency switch in hevc.*/
2546 pservice->auto_freq = false;
2550 static bool check_irq_err(task_info *task, u32 irq_status)
2552 return (task->error_mask & irq_status) ? true : false;
2555 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2557 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2558 struct vpu_service_info *pservice = data->pservice;
2559 vpu_device *dev = &data->dec_dev;
2563 /*vcodec_enter_mode(data);*/
2565 dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2567 if (dec_status & DEC_INTERRUPT_BIT) {
2568 time_record(&tasks[TASK_VPU_DEC], 1);
2569 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2570 if ((dec_status & 0x40001) == 0x40001) {
2574 DEC_INTERRUPT_REGISTER);
2575 } while ((dec_status & 0x40001) == 0x40001);
2578 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2579 (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2581 atomic_add(1, &pservice->reset_request);
2584 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2585 atomic_add(1, &dev->irq_count_codec);
2586 time_diff(&tasks[TASK_VPU_DEC]);
2589 if (data->hw_info->hw_id != HEVC_ID) {
2590 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2591 if (pp_status & PP_INTERRUPT_BIT) {
2592 time_record(&tasks[TASK_VPU_PP], 1);
2593 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2595 if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2596 atomic_add(1, &pservice->reset_request);
2599 writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2600 atomic_add(1, &dev->irq_count_pp);
2601 time_diff(&tasks[TASK_VPU_PP]);
2605 pservice->irq_status = raw_status;
2607 /*vcodec_exit_mode(pservice);*/
2609 if (atomic_read(&dev->irq_count_pp) ||
2610 atomic_read(&dev->irq_count_codec))
2611 return IRQ_WAKE_THREAD;
2616 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2618 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2619 struct vpu_service_info *pservice = data->pservice;
2620 vpu_device *dev = &data->dec_dev;
2622 mutex_lock(&pservice->lock);
2623 if (atomic_read(&dev->irq_count_codec)) {
2624 atomic_sub(1, &dev->irq_count_codec);
2625 if (NULL == pservice->reg_codec) {
2626 vpu_err("error: dec isr with no task waiting\n");
2628 reg_from_run_to_done(data, pservice->reg_codec);
2629 /* avoid vpu timeout and can't recover problem */
2630 VDPU_SOFT_RESET(data->regs);
2634 if (atomic_read(&dev->irq_count_pp)) {
2635 atomic_sub(1, &dev->irq_count_pp);
2636 if (NULL == pservice->reg_pproc) {
2637 vpu_err("error: pp isr with no task waiting\n");
2639 reg_from_run_to_done(data, pservice->reg_pproc);
2643 mutex_unlock(&pservice->lock);
2647 static irqreturn_t vepu_irq(int irq, void *dev_id)
2649 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2650 struct vpu_service_info *pservice = data->pservice;
2651 vpu_device *dev = &data->enc_dev;
2654 /*vcodec_enter_mode(data);*/
2655 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2657 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2659 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2660 time_record(&tasks[TASK_VPU_ENC], 1);
2662 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2663 atomic_add(1, &pservice->reset_request);
2666 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2667 atomic_add(1, &dev->irq_count_codec);
2668 time_diff(&tasks[TASK_VPU_ENC]);
2671 pservice->irq_status = irq_status;
2673 /*vcodec_exit_mode(pservice);*/
2675 if (atomic_read(&dev->irq_count_codec))
2676 return IRQ_WAKE_THREAD;
2681 static irqreturn_t vepu_isr(int irq, void *dev_id)
2683 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2684 struct vpu_service_info *pservice = data->pservice;
2685 vpu_device *dev = &data->enc_dev;
2687 mutex_lock(&pservice->lock);
2688 if (atomic_read(&dev->irq_count_codec)) {
2689 atomic_sub(1, &dev->irq_count_codec);
2690 if (NULL == pservice->reg_codec) {
2691 vpu_err("error: enc isr with no task waiting\n");
2693 reg_from_run_to_done(data, pservice->reg_codec);
2697 mutex_unlock(&pservice->lock);
2701 static int __init vcodec_service_init(void)
2705 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2706 vpu_err("Platform device register failed (%d).\n", ret);
2710 #ifdef CONFIG_DEBUG_FS
2711 vcodec_debugfs_init();
2717 static void __exit vcodec_service_exit(void)
2719 #ifdef CONFIG_DEBUG_FS
2720 vcodec_debugfs_exit();
2723 platform_driver_unregister(&vcodec_driver);
2726 module_init(vcodec_service_init);
2727 module_exit(vcodec_service_exit);
2729 #ifdef CONFIG_DEBUG_FS
2730 #include <linux/seq_file.h>
2732 static int vcodec_debugfs_init()
2734 parent = debugfs_create_dir("vcodec", NULL);
2741 static void vcodec_debugfs_exit()
2743 debugfs_remove(parent);
2746 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2748 return debugfs_create_dir(dirname, parent);
2751 static int debug_vcodec_show(struct seq_file *s, void *unused)
2753 struct vpu_subdev_data *data = s->private;
2754 struct vpu_service_info *pservice = data->pservice;
2756 vpu_reg *reg, *reg_tmp;
2757 vpu_session *session, *session_tmp;
2759 mutex_lock(&pservice->lock);
2760 vpu_service_power_on(pservice);
2761 if (data->hw_info->hw_id != HEVC_ID) {
2762 seq_printf(s, "\nENC Registers:\n");
2763 n = data->enc_dev.iosize >> 2;
2764 for (i = 0; i < n; i++)
2765 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2767 seq_printf(s, "\nDEC Registers:\n");
2768 n = data->dec_dev.iosize >> 2;
2769 for (i = 0; i < n; i++)
2770 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2772 seq_printf(s, "\nvpu service status:\n");
2773 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2774 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2775 /*seq_printf(s, "waiting reg set %d\n");*/
2776 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2777 seq_printf(s, "waiting register set\n");
2779 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2780 seq_printf(s, "running register set\n");
2782 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2783 seq_printf(s, "done register set\n");
2787 seq_printf(s, "\npower counter: on %d off %d\n",
2788 atomic_read(&pservice->power_on_cnt),
2789 atomic_read(&pservice->power_off_cnt));
2790 mutex_unlock(&pservice->lock);
2791 vpu_service_power_off(pservice);
2796 static int debug_vcodec_open(struct inode *inode, struct file *file)
2798 return single_open(file, debug_vcodec_show, inode->i_private);
2803 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2804 #include "hevc_test_inc/pps_00.h"
2805 #include "hevc_test_inc/register_00.h"
2806 #include "hevc_test_inc/rps_00.h"
2807 #include "hevc_test_inc/scaling_list_00.h"
2808 #include "hevc_test_inc/stream_00.h"
2810 #include "hevc_test_inc/pps_01.h"
2811 #include "hevc_test_inc/register_01.h"
2812 #include "hevc_test_inc/rps_01.h"
2813 #include "hevc_test_inc/scaling_list_01.h"
2814 #include "hevc_test_inc/stream_01.h"
2816 #include "hevc_test_inc/cabac.h"
2818 extern struct ion_client *rockchip_ion_client_create(const char * name);
2820 static struct ion_client *ion_client = NULL;
2821 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2823 int size = (len+15) & (~15);
2824 struct ion_handle *handle;
2827 if (ion_client == NULL)
2828 ion_client = rockchip_ion_client_create("vcodec");
2830 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2832 ptr = ion_map_kernel(ion_client, handle);
2834 ion_phys(ion_client, handle, phy, &size);
2836 memcpy(ptr, tbl, len);
2841 u8* get_align_ptr_no_copy(int len, u32 *phy)
2843 int size = (len+15) & (~15);
2844 struct ion_handle *handle;
2847 if (ion_client == NULL)
2848 ion_client = rockchip_ion_client_create("vcodec");
2850 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2852 ptr = ion_map_kernel(ion_client, handle);
2854 ion_phys(ion_client, handle, phy, &size);
2860 static int hevc_test_case0(vpu_service_info *pservice)
2862 vpu_session session;
2864 unsigned long size = 272;
2867 u8 *pps_tbl[TEST_CNT];
2868 u8 *register_tbl[TEST_CNT];
2869 u8 *rps_tbl[TEST_CNT];
2870 u8 *scaling_list_tbl[TEST_CNT];
2871 u8 *stream_tbl[TEST_CNT];
2887 volatile u8 *stream_buf;
2888 volatile u8 *pps_buf;
2889 volatile u8 *rps_buf;
2890 volatile u8 *scl_buf;
2891 volatile u8 *yuv_buf;
2892 volatile u8 *cabac_buf;
2893 volatile u8 *ref_buf;
2899 pps_tbl[0] = pps_00;
2900 pps_tbl[1] = pps_01;
2902 register_tbl[0] = register_00;
2903 register_tbl[1] = register_01;
2905 rps_tbl[0] = rps_00;
2906 rps_tbl[1] = rps_01;
2908 scaling_list_tbl[0] = scaling_list_00;
2909 scaling_list_tbl[1] = scaling_list_01;
2911 stream_tbl[0] = stream_00;
2912 stream_tbl[1] = stream_01;
2914 stream_size[0] = sizeof(stream_00);
2915 stream_size[1] = sizeof(stream_01);
2917 pps_size[0] = sizeof(pps_00);
2918 pps_size[1] = sizeof(pps_01);
2920 rps_size[0] = sizeof(rps_00);
2921 rps_size[1] = sizeof(rps_01);
2923 scl_size[0] = sizeof(scaling_list_00);
2924 scl_size[1] = sizeof(scaling_list_01);
2926 cabac_size[0] = sizeof(Cabac_table);
2927 cabac_size[1] = sizeof(Cabac_table);
2929 /* create session */
2930 session.pid = current->pid;
2931 session.type = VPU_DEC;
2932 INIT_LIST_HEAD(&session.waiting);
2933 INIT_LIST_HEAD(&session.running);
2934 INIT_LIST_HEAD(&session.done);
2935 INIT_LIST_HEAD(&session.list_session);
2936 init_waitqueue_head(&session.wait);
2937 atomic_set(&session.task_running, 0);
2938 list_add_tail(&session.list_session, &pservice->session);
2940 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2941 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2943 while (testidx < TEST_CNT) {
2944 /* create registers */
2945 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2947 vpu_err("error: kmalloc fail in reg_init\n");
2951 if (size > pservice->reg_size) {
2952 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2953 size = pservice->reg_size;
2955 reg->session = &session;
2956 reg->type = session.type;
2958 reg->freq = VPU_FREQ_DEFAULT;
2959 reg->reg = (unsigned long *)®[1];
2960 INIT_LIST_HEAD(®->session_link);
2961 INIT_LIST_HEAD(®->status_link);
2963 /* TODO: stuff registers */
2964 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2966 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2967 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2968 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2969 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2970 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2974 /* TODO: replace reigster address */
2975 for (i=0; i<64; i++) {
2979 scaling_offset = (u32)pps[i*80+74];
2980 scaling_offset += (u32)pps[i*80+75] << 8;
2981 scaling_offset += (u32)pps[i*80+76] << 16;
2982 scaling_offset += (u32)pps[i*80+77] << 24;
2984 tmp = phy_scl + scaling_offset;
2986 pps[i*80+74] = tmp & 0xff;
2987 pps[i*80+75] = (tmp >> 8) & 0xff;
2988 pps[i*80+76] = (tmp >> 16) & 0xff;
2989 pps[i*80+77] = (tmp >> 24) & 0xff;
2992 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2993 __func__, __LINE__, phy_str, phy_pps, phy_rps);
2996 reg->reg[4] = phy_str;
2997 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2998 reg->reg[6] = phy_cabac;
2999 reg->reg[7] = testidx?phy_ref:phy_yuv;
3000 reg->reg[42] = phy_pps;
3001 reg->reg[43] = phy_rps;
3002 for (i = 10; i <= 24; i++)
3003 reg->reg[i] = phy_yuv;
3005 mutex_lock(pservice->lock);
3006 list_add_tail(®->status_link, &pservice->waiting);
3007 list_add_tail(®->session_link, &session.waiting);
3008 mutex_unlock(pservice->lock);
3010 /* stuff hardware */
3013 /* wait for result */
3014 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3015 if (!list_empty(&session.done)) {
3017 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3020 if (unlikely(ret < 0)) {
3021 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3022 } else if (0 == ret) {
3023 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3028 int task_running = atomic_read(&session.task_running);
3030 mutex_lock(pservice->lock);
3031 vpu_service_dump(pservice);
3033 atomic_set(&session.task_running, 0);
3034 atomic_sub(task_running, &pservice->total_running);
3035 printk("%d task is running but not return, reset hardware...", task_running);
3039 vpu_service_session_clear(pservice, &session);
3040 mutex_unlock(pservice->lock);
3042 printk("\nDEC Registers:\n");
3043 n = data->dec_dev.iosize >> 2;
3045 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3047 vpu_err("test index %d failed\n", testidx);
3050 vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3052 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3054 for (i=0; i<68; i++) {
3056 printk("%02d: ", i);
3057 printk("%08x ", reg->reg[i]);
3065 reg_deinit(data, reg);