2 /* arch/arm/mach-rk29/vpu.c
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4 * Copyright (C) 2010 ROCKCHIP, Inc.
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5 * author: chenhengming chm@rock-chips.com
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7 * This software is licensed under the terms of the GNU General Public
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8 * License version 2, as published by the Free Software Foundation, and
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9 * may be copied, distributed, and modified under those terms.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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18 #include <linux/clk.h>
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19 #include <linux/delay.h>
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20 #include <linux/init.h>
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21 #include <linux/interrupt.h>
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22 #include <linux/io.h>
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23 #include <linux/kernel.h>
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24 #include <linux/module.h>
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25 #include <linux/fs.h>
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26 #include <linux/ioport.h>
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27 #include <linux/miscdevice.h>
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28 #include <linux/mm.h>
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29 #include <linux/poll.h>
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30 #include <linux/platform_device.h>
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31 #include <linux/sched.h>
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32 #include <linux/slab.h>
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33 #include <linux/wakelock.h>
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34 #include <linux/cdev.h>
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35 #include <linux/of.h>
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36 #include <linux/rockchip/cpu.h>
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37 #include <linux/rockchip/cru.h>
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39 #include <asm/cacheflush.h>
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40 #include <asm/uaccess.h>
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42 #if defined(CONFIG_ION_ROCKCHIP)
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43 #include <linux/rockchip_ion.h>
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46 //#define CONFIG_VCODEC_MMU
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48 #ifdef CONFIG_VCODEC_MMU
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49 #include <linux/rockchip/iovmm.h>
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50 #include <linux/rockchip/sysmmu.h>
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51 #include <linux/dma-buf.h>
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54 #ifdef CONFIG_DEBUG_FS
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55 #include <linux/debugfs.h>
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58 #if defined(CONFIG_ARCH_RK319X)
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59 #include <mach/grf.h>
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62 #include "vcodec_service.h"
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64 #define HEVC_TEST_ENABLE 0
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65 #define HEVC_SIM_ENABLE 0
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66 #define VCODEC_CLOCK_ENABLE 1
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69 VPU_DEC_ID_9190 = 0x6731,
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70 VPU_ID_8270 = 0x8270,
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71 VPU_ID_4831 = 0x4831,
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76 VPU_DEC_TYPE_9190 = 0,
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77 VPU_ENC_TYPE_8270 = 0x100,
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81 typedef enum VPU_FREQ {
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94 unsigned long hw_addr;
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95 unsigned long enc_offset;
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96 unsigned long enc_reg_num;
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97 unsigned long enc_io_size;
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98 unsigned long dec_offset;
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99 unsigned long dec_reg_num;
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100 unsigned long dec_io_size;
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103 #define VPU_SERVICE_SHOW_TIME 0
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105 #if VPU_SERVICE_SHOW_TIME
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106 static struct timeval enc_start, enc_end;
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107 static struct timeval dec_start, dec_end;
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108 static struct timeval pp_start, pp_end;
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111 #define MHZ (1000*1000)
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113 #define REG_NUM_9190_DEC (60)
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114 #define REG_NUM_9190_PP (41)
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115 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
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117 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
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119 #define REG_NUM_ENC_8270 (96)
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120 #define REG_SIZE_ENC_8270 (0x200)
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121 #define REG_NUM_ENC_4831 (164)
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122 #define REG_SIZE_ENC_4831 (0x400)
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124 #define REG_NUM_HEVC_DEC (68)
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126 #define SIZE_REG(reg) ((reg)*4)
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128 static VPU_HW_INFO_E vpu_hw_set[] = {
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130 .hw_id = VPU_ID_8270,
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133 .enc_reg_num = REG_NUM_ENC_8270,
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134 .enc_io_size = REG_NUM_ENC_8270 * 4,
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135 .dec_offset = REG_SIZE_ENC_8270,
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136 .dec_reg_num = REG_NUM_9190_DEC_PP,
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137 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
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140 .hw_id = VPU_ID_4831,
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143 .enc_reg_num = REG_NUM_ENC_4831,
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144 .enc_io_size = REG_NUM_ENC_4831 * 4,
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145 .dec_offset = REG_SIZE_ENC_4831,
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146 .dec_reg_num = REG_NUM_9190_DEC_PP,
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147 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
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153 .dec_reg_num = REG_NUM_HEVC_DEC,
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154 .dec_io_size = REG_NUM_HEVC_DEC * 4,
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159 #define DEC_INTERRUPT_REGISTER 1
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160 #define PP_INTERRUPT_REGISTER 60
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161 #define ENC_INTERRUPT_REGISTER 1
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163 #define DEC_INTERRUPT_BIT 0x100
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164 #define DEC_BUFFER_EMPTY_BIT 0x4000
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165 #define PP_INTERRUPT_BIT 0x100
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166 #define ENC_INTERRUPT_BIT 0x1
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168 #define HEVC_DEC_INT_RAW_BIT 0x200
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169 #define HEVC_DEC_STR_ERROR_BIT 0x4000
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170 #define HEVC_DEC_BUS_ERROR_BIT 0x2000
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171 #define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000
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173 #define VPU_REG_EN_ENC 14
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174 #define VPU_REG_ENC_GATE 2
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175 #define VPU_REG_ENC_GATE_BIT (1<<4)
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177 #define VPU_REG_EN_DEC 1
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178 #define VPU_REG_DEC_GATE 2
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179 #define VPU_REG_DEC_GATE_BIT (1<<10)
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180 #define VPU_REG_EN_PP 0
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181 #define VPU_REG_PP_GATE 1
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182 #define VPU_REG_PP_GATE_BIT (1<<8)
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183 #define VPU_REG_EN_DEC_PP 1
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184 #define VPU_REG_DEC_PP_GATE 61
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185 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
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187 static u8 addr_tbl_vpu_dec[] = {
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188 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41
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191 static u8 addr_tbl_vpu_enc[] = {
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192 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
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195 static u8 addr_tbl_hevc_dec[] = {
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196 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43
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200 * struct for process session which connect to vpu
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202 * @author ChenHengming (2011-5-3)
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204 typedef struct vpu_session {
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205 VPU_CLIENT_TYPE type;
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206 /* a linked list of data so we can access them for debugging */
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207 struct list_head list_session;
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208 /* a linked list of register data waiting for process */
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209 struct list_head waiting;
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210 /* a linked list of register data in processing */
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211 struct list_head running;
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212 /* a linked list of register data processed */
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213 struct list_head done;
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214 wait_queue_head_t wait;
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216 atomic_t task_running;
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220 * struct for process register set
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222 * @author ChenHengming (2011-5-4)
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224 typedef struct vpu_reg {
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225 VPU_CLIENT_TYPE type;
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227 vpu_session *session;
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228 struct list_head session_link; /* link to vpu service session */
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229 struct list_head status_link; /* link to register set list */
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230 unsigned long size;
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231 #if defined(CONFIG_VCODEC_MMU)
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232 struct list_head mem_region_list;
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234 unsigned long *reg;
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237 typedef struct vpu_device {
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238 atomic_t irq_count_codec;
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239 atomic_t irq_count_pp;
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240 unsigned long iobaseaddr;
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241 unsigned int iosize;
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242 volatile u32 *hwregs;
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245 enum vcodec_device_id {
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246 VCODEC_DEVICE_ID_VPU,
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247 VCODEC_DEVICE_ID_HEVC
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250 struct vcodec_mem_region {
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251 struct list_head srv_lnk;
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252 struct list_head reg_lnk;
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253 struct list_head session_lnk;
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254 dma_addr_t iova; /* virtual address for iommu */
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255 struct dma_buf *buf;
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256 struct dma_buf_attachment *attachment;
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257 struct sg_table *sg_table;
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258 struct ion_handle *hdl;
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261 typedef struct vpu_service_info {
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262 struct wake_lock wake_lock;
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263 struct delayed_work power_off_work;
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265 struct list_head waiting; /* link to link_reg in struct vpu_reg */
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266 struct list_head running; /* link to link_reg in struct vpu_reg */
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267 struct list_head done; /* link to link_reg in struct vpu_reg */
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268 struct list_head session; /* link to list_session in struct vpu_session */
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269 atomic_t total_running;
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271 vpu_reg *reg_codec;
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272 vpu_reg *reg_pproc;
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273 vpu_reg *reg_resev;
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274 VPUHwDecConfig_t dec_config;
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275 VPUHwEncConfig_t enc_config;
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276 VPU_HW_INFO_E *hw_info;
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277 unsigned long reg_size;
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280 atomic_t freq_status;
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282 struct clk *aclk_vcodec;
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283 struct clk *hclk_vcodec;
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284 struct clk *clk_core;
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285 struct clk *clk_cabac;
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290 vpu_device enc_dev;
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291 vpu_device dec_dev;
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293 struct device *dev;
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298 struct device *child_dev;
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300 struct dentry *debugfs_dir;
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301 struct dentry *debugfs_file_regs;
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304 #if defined(CONFIG_ION_ROCKCHIP)
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305 struct ion_client * ion_client;
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308 #if defined(CONFIG_VCODEC_MMU)
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309 struct list_head mem_region_list;
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312 enum vcodec_device_id dev_id;
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314 struct delayed_work simulate_work;
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315 } vpu_service_info;
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317 typedef struct vpu_request
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319 unsigned long *req;
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320 unsigned long size;
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323 /// global variable
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324 //static struct clk *pd_video;
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325 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
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327 #ifdef CONFIG_DEBUG_FS
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328 static int vcodec_debugfs_init(void);
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329 static void vcodec_debugfs_exit(void);
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330 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
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331 static int debug_vcodec_open(struct inode *inode, struct file *file);
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333 static const struct file_operations debug_vcodec_fops = {
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334 .open = debug_vcodec_open,
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336 .llseek = seq_lseek,
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337 .release = single_release,
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341 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
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342 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
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344 #define VPU_SIMULATE_DELAY msecs_to_jiffies(15)
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346 static void vpu_get_clk(struct vpu_service_info *pservice)
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348 #if VCODEC_CLOCK_ENABLE
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349 /*pd_video = clk_get(NULL, "pd_video");
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350 if (IS_ERR(pd_video)) {
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351 pr_err("failed on clk_get pd_video\n");
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354 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
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355 if (IS_ERR(pservice->aclk_vcodec)) {
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356 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
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359 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
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360 if (IS_ERR(pservice->hclk_vcodec)) {
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361 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
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364 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
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365 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
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366 if (IS_ERR(pservice->clk_core)) {
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367 dev_err(pservice->dev, "failed on clk_get clk_core\n");
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370 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
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371 if (IS_ERR(pservice->clk_cabac)) {
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372 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
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378 static void vpu_put_clk(struct vpu_service_info *pservice)
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380 #if VCODEC_CLOCK_ENABLE
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381 //clk_put(pd_video);
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383 if (pservice->aclk_vcodec) {
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384 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
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387 if (pservice->hclk_vcodec) {
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388 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
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391 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
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392 if (pservice->clk_core) {
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393 devm_clk_put(pservice->dev, pservice->clk_core);
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396 if (pservice->clk_cabac) {
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397 devm_clk_put(pservice->dev, pservice->clk_cabac);
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403 static void vpu_reset(struct vpu_service_info *pservice)
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405 #if defined(CONFIG_ARCH_RK29)
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406 clk_disable(aclk_ddr_vepu);
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407 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
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408 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
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409 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
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410 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
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412 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
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413 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
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414 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
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415 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
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416 clk_enable(aclk_ddr_vepu);
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417 #elif defined(CONFIG_ARCH_RK30)
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418 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
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419 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
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420 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
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421 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
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422 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
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424 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
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425 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
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426 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
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427 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
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428 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
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430 pservice->reg_codec = NULL;
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431 pservice->reg_pproc = NULL;
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432 pservice->reg_resev = NULL;
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435 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
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436 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
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439 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
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440 reg_deinit(pservice, reg);
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442 list_for_each_entry_safe(reg, n, &session->running, session_link) {
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443 reg_deinit(pservice, reg);
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445 list_for_each_entry_safe(reg, n, &session->done, session_link) {
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446 reg_deinit(pservice, reg);
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450 static void vpu_service_dump(struct vpu_service_info *pservice)
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453 vpu_reg *reg, *reg_tmp;
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454 vpu_session *session, *session_tmp;
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456 running = atomic_read(&pservice->total_running);
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457 printk("total_running %d\n", running);
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459 printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);
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460 printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
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461 printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
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463 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
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464 printk("session pid %d type %d:\n", session->pid, session->type);
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465 running = atomic_read(&session->task_running);
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466 printk("task_running %d\n", running);
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467 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
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468 printk("waiting register set 0x%.8x\n", (unsigned int)reg);
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470 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
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471 printk("running register set 0x%.8x\n", (unsigned int)reg);
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473 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
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474 printk("done register set 0x%.8x\n", (unsigned int)reg);
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479 static void vpu_service_power_off(struct vpu_service_info *pservice)
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482 if (!pservice->enabled) {
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486 pservice->enabled = false;
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487 total_running = atomic_read(&pservice->total_running);
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488 if (total_running) {
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489 pr_alert("alert: power off when %d task running!!\n", total_running);
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491 pr_alert("alert: delay 50 ms for running task\n");
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492 vpu_service_dump(pservice);
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495 printk("%s: power off...", dev_name(pservice->dev));
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496 #ifdef CONFIG_ARCH_RK29
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497 pmu_set_power_domain(PD_VCODEC, false);
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499 //clk_disable(pd_video);
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502 #if VCODEC_CLOCK_ENABLE
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503 clk_disable_unprepare(pservice->hclk_vcodec);
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504 clk_disable_unprepare(pservice->aclk_vcodec);
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505 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
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506 clk_disable_unprepare(pservice->clk_core);
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507 clk_disable_unprepare(pservice->clk_cabac);
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510 wake_unlock(&pservice->wake_lock);
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514 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
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516 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
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519 static void vpu_power_off_work(struct work_struct *work_s)
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521 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
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522 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
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524 if (mutex_trylock(&pservice->lock)) {
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525 vpu_service_power_off(pservice);
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526 mutex_unlock(&pservice->lock);
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528 /* Come back later if the device is busy... */
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529 vpu_queue_power_off_work(pservice);
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533 static void vpu_service_power_on(struct vpu_service_info *pservice)
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535 static ktime_t last;
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536 ktime_t now = ktime_get();
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537 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
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538 cancel_delayed_work_sync(&pservice->power_off_work);
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539 vpu_queue_power_off_work(pservice);
\r
542 if (pservice->enabled)
\r
545 pservice->enabled = true;
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546 printk("%s: power on\n", dev_name(pservice->dev));
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548 #if VCODEC_CLOCK_ENABLE
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549 clk_prepare_enable(pservice->aclk_vcodec);
\r
550 clk_prepare_enable(pservice->hclk_vcodec);
\r
552 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
\r
553 clk_prepare_enable(pservice->clk_core);
\r
554 clk_prepare_enable(pservice->clk_cabac);
\r
558 #if defined(CONFIG_ARCH_RK319X)
\r
559 /// select aclk_vepu as vcodec clock source.
\r
560 #define BIT_VCODEC_SEL (1<<7)
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561 writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);
\r
564 #ifdef CONFIG_ARCH_RK29
\r
565 pmu_set_power_domain(PD_VCODEC, true);
\r
567 //clk_enable(pd_video);
\r
570 wake_lock(&pservice->wake_lock);
\r
573 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
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575 unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
\r
576 return ((type == 8) || (type == 4));
\r
579 static inline bool reg_check_interlace(vpu_reg *reg)
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581 unsigned long type = (reg->reg[3] & (1 << 23));
\r
585 static inline bool reg_check_avc(vpu_reg *reg)
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587 unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
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588 return (type == 0);
\r
591 static inline int reg_probe_width(vpu_reg *reg)
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593 int width_in_mb = reg->reg[4] >> 23;
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595 return width_in_mb * 16;
\r
598 #if defined(CONFIG_VCODEC_MMU)
\r
600 static unsigned int vcodec_map_ion_handle(vpu_service_info *pservice,
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602 struct ion_handle *ion_handle,
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603 struct dma_buf *buf, int offset)
\r
605 struct vcodec_mem_region *mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
\r
606 if (mem_region == NULL) {
\r
607 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
\r
611 mem_region->buf = buf;
\r
612 mem_region->hdl = ion_handle;
\r
614 mem_region->attachment = dma_buf_attach(buf, pservice->dev);
\r
615 if (IS_ERR_OR_NULL(mem_region->attachment)) {
\r
616 dev_err(pservice->dev, "dma_buf_attach() failed: %ld\n", PTR_ERR(mem_region->attachment));
\r
617 goto err_buf_map_attach;
\r
620 mem_region->sg_table = dma_buf_map_attachment(mem_region->attachment, DMA_BIDIRECTIONAL);
\r
621 if (IS_ERR_OR_NULL(mem_region->sg_table)) {
\r
622 dev_err(pservice->dev, "dma_buf_map_attachment() failed: %ld\n", PTR_ERR(mem_region->sg_table));
\r
623 goto err_buf_map_attachment;
\r
626 mem_region->iova = iovmm_map(pservice->dev, mem_region->sg_table->sgl, offset, buf->size);
\r
627 if (mem_region->iova == 0 || IS_ERR_VALUE(mem_region->iova)) {
\r
628 dev_err(pservice->dev, "iovmm_map() failed: %d\n", mem_region->iova);
\r
629 goto err_iovmm_map;
\r
632 INIT_LIST_HEAD(&mem_region->reg_lnk);
\r
633 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
\r
635 return mem_region->iova;
\r
638 dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);
\r
639 err_buf_map_attachment:
\r
640 dma_buf_detach(buf, mem_region->attachment);
\r
641 err_buf_map_attach:
\r
646 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)
\r
651 hw_id = pservice->hw_info->hw_id;
\r
653 if (hw_id == HEVC_ID) {
\r
656 if (reg->type == VPU_DEC) {
\r
657 for (i=0; i<sizeof(addr_tbl_vpu_dec); i++) {
\r
659 struct ion_handle *hdl;
\r
660 //ion_phys_addr_t phy_addr;
\r
661 struct dma_buf *buf;
\r
666 if (copy_from_user(&usr_fd, ®->reg[addr_tbl_vpu_dec[i]], sizeof(usr_fd)))
\r
669 usr_fd = reg->reg[addr_tbl_vpu_dec[i]] & 0xFF;
\r
670 offset = reg->reg[addr_tbl_vpu_dec[i]] >> 8;
\r
674 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
\r
676 pr_err("import dma-buf from fd %d failed\n", usr_fd);
\r
677 return PTR_ERR(hdl);
\r
681 ion_phys(pservice->ion_client, hdl, &phy_addr, &len);
\r
683 reg->reg[addr_tbl_vpu_dec[i]] = phy_addr + offset;
\r
685 ion_free(pservice->ion_client, hdl);
\r
687 buf = ion_share_dma_buf(pservice->ion_client, hdl);
\r
688 if (IS_ERR_OR_NULL(buf)) {
\r
689 dev_err(pservice->dev, "ion_share_dma_buf() failed\n");
\r
690 ion_free(pservice->ion_client, hdl);
\r
691 return PTR_ERR(buf);
\r
694 reg->reg[addr_tbl_vpu_dec[i]] = vcodec_map_ion_handle(pservice, reg, hdl, buf, offset);
\r
699 } else if (reg->type == VPU_ENC) {
\r
708 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
\r
710 vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
\r
712 pr_err("error: kmalloc fail in reg_init\n");
\r
716 if (size > pservice->reg_size) {
\r
717 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
\r
718 size = pservice->reg_size;
\r
720 reg->session = session;
\r
721 reg->type = session->type;
\r
723 reg->freq = VPU_FREQ_DEFAULT;
\r
724 reg->reg = (unsigned long *)®[1];
\r
725 INIT_LIST_HEAD(®->session_link);
\r
726 INIT_LIST_HEAD(®->status_link);
\r
728 #if defined(CONFIG_VCODEC_MMU)
\r
729 INIT_LIST_HEAD(®->mem_region_list);
\r
732 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
\r
733 pr_err("error: copy_from_user failed in reg_init\n");
\r
738 #if defined(CONFIG_VCODEC_MMU)
\r
739 if (0 > vcodec_reg_address_translate(pservice, reg)) {
\r
740 pr_err("error: translate reg address failed\n");
\r
746 mutex_lock(&pservice->lock);
\r
747 list_add_tail(®->status_link, &pservice->waiting);
\r
748 list_add_tail(®->session_link, &session->waiting);
\r
749 mutex_unlock(&pservice->lock);
\r
751 if (pservice->auto_freq) {
\r
752 if (!soc_is_rk2928g()) {
\r
753 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
\r
754 if (reg_check_rmvb_wmv(reg)) {
\r
755 reg->freq = VPU_FREQ_200M;
\r
756 } else if (reg_check_avc(reg)) {
\r
757 if (reg_probe_width(reg) > 3200) {
\r
758 // raise frequency for 4k avc.
\r
759 reg->freq = VPU_FREQ_500M;
\r
762 if (reg_check_interlace(reg)) {
\r
763 reg->freq = VPU_FREQ_400M;
\r
767 if (reg->type == VPU_PP) {
\r
768 reg->freq = VPU_FREQ_400M;
\r
776 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
\r
778 #if defined(CONFIG_VCODEC_MMU)
\r
779 struct vcodec_mem_region *mem_region = NULL, *n;
\r
782 list_del_init(®->session_link);
\r
783 list_del_init(®->status_link);
\r
784 if (reg == pservice->reg_codec) pservice->reg_codec = NULL;
\r
785 if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;
\r
787 #if defined(CONFIG_VCODEC_MMU)
\r
788 // release memory region attach to this registers table.
\r
789 list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {
\r
790 iovmm_unmap(pservice->dev, mem_region->iova);
\r
792 dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);
\r
793 dma_buf_detach(mem_region->buf, mem_region->attachment);
\r
795 dma_buf_put(mem_region->buf);
\r
796 ion_free(pservice->ion_client, mem_region->hdl);
\r
798 list_del_init(&mem_region->reg_lnk);
\r
807 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
\r
809 list_del_init(®->status_link);
\r
810 list_add_tail(®->status_link, &pservice->running);
\r
812 list_del_init(®->session_link);
\r
813 list_add_tail(®->session_link, ®->session->running);
\r
816 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
\r
819 u32 *dst = (u32 *)®->reg[0];
\r
820 for (i = 0; i < count; i++)
\r
824 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
\r
827 list_del_init(®->status_link);
\r
828 list_add_tail(®->status_link, &pservice->done);
\r
830 list_del_init(®->session_link);
\r
831 list_add_tail(®->session_link, ®->session->done);
\r
833 switch (reg->type) {
\r
835 pservice->reg_codec = NULL;
\r
836 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
\r
837 irq_reg = ENC_INTERRUPT_REGISTER;
\r
841 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
\r
842 pservice->reg_codec = NULL;
\r
843 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);
\r
844 irq_reg = DEC_INTERRUPT_REGISTER;
\r
848 pservice->reg_pproc = NULL;
\r
849 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
\r
850 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
\r
853 case VPU_DEC_PP : {
\r
854 pservice->reg_codec = NULL;
\r
855 pservice->reg_pproc = NULL;
\r
856 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
\r
857 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
\r
861 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
\r
866 if (irq_reg != -1) {
\r
867 reg->reg[irq_reg] = pservice->irq_status;
\r
870 atomic_sub(1, ®->session->task_running);
\r
871 atomic_sub(1, &pservice->total_running);
\r
872 wake_up(®->session->wait);
\r
875 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
\r
877 VPU_FREQ curr = atomic_read(&pservice->freq_status);
\r
878 if (curr == reg->freq) {
\r
881 atomic_set(&pservice->freq_status, reg->freq);
\r
882 switch (reg->freq) {
\r
883 case VPU_FREQ_200M : {
\r
884 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
\r
885 //printk("default: 200M\n");
\r
887 case VPU_FREQ_266M : {
\r
888 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
\r
889 //printk("default: 266M\n");
\r
891 case VPU_FREQ_300M : {
\r
892 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
\r
893 //printk("default: 300M\n");
\r
895 case VPU_FREQ_400M : {
\r
896 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
\r
897 //printk("default: 400M\n");
\r
899 case VPU_FREQ_500M : {
\r
900 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
\r
902 case VPU_FREQ_600M : {
\r
903 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
\r
906 if (soc_is_rk2928g()) {
\r
907 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
\r
909 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
\r
911 //printk("default: 300M\n");
\r
916 #if HEVC_SIM_ENABLE
\r
917 static void simulate_start(struct vpu_service_info *pservice);
\r
919 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
\r
922 u32 *src = (u32 *)®->reg[0];
\r
923 atomic_add(1, &pservice->total_running);
\r
924 atomic_add(1, ®->session->task_running);
\r
925 if (pservice->auto_freq) {
\r
926 vpu_service_set_freq(pservice, reg);
\r
928 switch (reg->type) {
\r
930 int enc_count = pservice->hw_info->enc_reg_num;
\r
931 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
\r
933 if (pservice->bug_dec_addr) {
\r
934 #if !defined(CONFIG_ARCH_RK319X)
\r
935 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
\r
937 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
\r
938 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
\r
939 #if !defined(CONFIG_ARCH_RK319X)
\r
940 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
\r
944 pservice->reg_codec = reg;
\r
946 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
\r
948 for (i = 0; i < VPU_REG_EN_ENC; i++)
\r
951 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
\r
956 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
\r
957 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
\r
959 #if VPU_SERVICE_SHOW_TIME
\r
960 do_gettimeofday(&enc_start);
\r
965 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
\r
967 pservice->reg_codec = reg;
\r
969 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
970 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
\r
973 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {
\r
980 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
981 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
\r
982 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
\r
984 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
\r
990 #if VPU_SERVICE_SHOW_TIME
\r
991 do_gettimeofday(&dec_start);
\r
996 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
\r
997 pservice->reg_pproc = reg;
\r
999 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
\r
1001 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
\r
1006 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
\r
1008 #if VPU_SERVICE_SHOW_TIME
\r
1009 do_gettimeofday(&pp_start);
\r
1013 case VPU_DEC_PP : {
\r
1014 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
\r
1015 pservice->reg_codec = reg;
\r
1016 pservice->reg_pproc = reg;
\r
1018 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
\r
1021 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
\r
1024 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
\r
1025 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
\r
1026 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
\r
1028 #if VPU_SERVICE_SHOW_TIME
\r
1029 do_gettimeofday(&dec_start);
\r
1034 pr_err("error: unsupport session type %d", reg->type);
\r
1035 atomic_sub(1, &pservice->total_running);
\r
1036 atomic_sub(1, ®->session->task_running);
\r
1041 #if HEVC_SIM_ENABLE
\r
1042 if (pservice->hw_info->hw_id == HEVC_ID) {
\r
1043 simulate_start(pservice);
\r
1048 static void try_set_reg(struct vpu_service_info *pservice)
\r
1050 // first get reg from reg list
\r
1051 if (!list_empty(&pservice->waiting)) {
\r
1053 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
\r
1055 vpu_service_power_on(pservice);
\r
1057 switch (reg->type) {
\r
1059 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
\r
1063 if (NULL == pservice->reg_codec)
\r
1065 if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
\r
1070 if (NULL == pservice->reg_codec) {
\r
1071 if (NULL == pservice->reg_pproc)
\r
1074 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
\r
1076 // can not charge frequency when vpu is working
\r
1077 if (pservice->auto_freq) {
\r
1082 case VPU_DEC_PP : {
\r
1083 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
\r
1087 printk("undefined reg type %d\n", reg->type);
\r
1091 reg_from_wait_to_run(pservice, reg);
\r
1092 reg_copy_to_hw(pservice, reg);
\r
1097 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
\r
1100 switch (reg->type) {
\r
1102 if (copy_to_user(dst, ®->reg[0], pservice->hw_info->enc_io_size))
\r
1107 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
\r
1108 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
\r
1113 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
\r
1117 case VPU_DEC_PP : {
\r
1118 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
\r
1124 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
\r
1128 reg_deinit(pservice, reg);
\r
1132 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
\r
1134 struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
\r
1135 vpu_session *session = (vpu_session *)filp->private_data;
\r
1136 if (NULL == session) {
\r
1141 case VPU_IOC_SET_CLIENT_TYPE : {
\r
1142 session->type = (VPU_CLIENT_TYPE)arg;
\r
1145 case VPU_IOC_GET_HW_FUSE_STATUS : {
\r
1147 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
1148 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
\r
1151 if (VPU_ENC != session->type) {
\r
1152 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
\r
1153 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
\r
1157 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
\r
1158 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
\r
1166 case VPU_IOC_SET_REG : {
\r
1169 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
1170 pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
\r
1173 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
\r
1174 if (NULL == reg) {
\r
1177 mutex_lock(&pservice->lock);
\r
1178 try_set_reg(pservice);
\r
1179 mutex_unlock(&pservice->lock);
\r
1184 case VPU_IOC_GET_REG : {
\r
1187 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
1188 pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
\r
1191 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
\r
1192 if (!list_empty(&session->done)) {
\r
1194 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
\r
1198 if (unlikely(ret < 0)) {
\r
1199 pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
\r
1200 } else if (0 == ret) {
\r
1201 pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
\r
1206 int task_running = atomic_read(&session->task_running);
\r
1207 mutex_lock(&pservice->lock);
\r
1208 vpu_service_dump(pservice);
\r
1209 if (task_running) {
\r
1210 atomic_set(&session->task_running, 0);
\r
1211 atomic_sub(task_running, &pservice->total_running);
\r
1212 printk("%d task is running but not return, reset hardware...", task_running);
\r
1213 vpu_reset(pservice);
\r
1216 vpu_service_session_clear(pservice, session);
\r
1217 mutex_unlock(&pservice->lock);
\r
1221 mutex_lock(&pservice->lock);
\r
1222 reg = list_entry(session->done.next, vpu_reg, session_link);
\r
1223 return_reg(pservice, reg, (u32 __user *)req.req);
\r
1224 mutex_unlock(&pservice->lock);
\r
1228 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
\r
1236 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
\r
1238 int ret = -EINVAL, i = 0;
\r
1239 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
\r
1240 u32 enc_id = *tmp;
\r
1242 #if HEVC_SIM_ENABLE
\r
1243 /// temporary, hevc driver test.
\r
1244 if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
\r
1245 p->hw_info = &vpu_hw_set[2];
\r
1250 enc_id = (enc_id >> 16) & 0xFFFF;
\r
1251 pr_info("checking hw id %x\n", enc_id);
\r
1252 p->hw_info = NULL;
\r
1253 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
\r
1254 if (enc_id == vpu_hw_set[i].hw_id) {
\r
1255 p->hw_info = &vpu_hw_set[i];
\r
1260 iounmap((void *)tmp);
\r
1264 static int vpu_service_open(struct inode *inode, struct file *filp)
\r
1266 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
\r
1267 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
\r
1268 if (NULL == session) {
\r
1269 pr_err("error: unable to allocate memory for vpu_session.");
\r
1273 session->type = VPU_TYPE_BUTT;
\r
1274 session->pid = current->pid;
\r
1275 INIT_LIST_HEAD(&session->waiting);
\r
1276 INIT_LIST_HEAD(&session->running);
\r
1277 INIT_LIST_HEAD(&session->done);
\r
1278 INIT_LIST_HEAD(&session->list_session);
\r
1279 init_waitqueue_head(&session->wait);
\r
1280 atomic_set(&session->task_running, 0);
\r
1281 mutex_lock(&pservice->lock);
\r
1282 list_add_tail(&session->list_session, &pservice->session);
\r
1283 filp->private_data = (void *)session;
\r
1284 mutex_unlock(&pservice->lock);
\r
1286 pr_debug("dev opened\n");
\r
1287 return nonseekable_open(inode, filp);
\r
1290 static int vpu_service_release(struct inode *inode, struct file *filp)
\r
1292 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
\r
1294 vpu_session *session = (vpu_session *)filp->private_data;
\r
1295 if (NULL == session)
\r
1298 task_running = atomic_read(&session->task_running);
\r
1299 if (task_running) {
\r
1300 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
\r
1303 wake_up(&session->wait);
\r
1305 mutex_lock(&pservice->lock);
\r
1306 /* remove this filp from the asynchronusly notified filp's */
\r
1307 list_del_init(&session->list_session);
\r
1308 vpu_service_session_clear(pservice, session);
\r
1310 filp->private_data = NULL;
\r
1311 mutex_unlock(&pservice->lock);
\r
1313 pr_debug("dev closed\n");
\r
1317 static const struct file_operations vpu_service_fops = {
\r
1318 .unlocked_ioctl = vpu_service_ioctl,
\r
1319 .open = vpu_service_open,
\r
1320 .release = vpu_service_release,
\r
1321 //.fasync = vpu_service_fasync,
\r
1324 static irqreturn_t vdpu_irq(int irq, void *dev_id);
\r
1325 static irqreturn_t vdpu_isr(int irq, void *dev_id);
\r
1326 static irqreturn_t vepu_irq(int irq, void *dev_id);
\r
1327 static irqreturn_t vepu_isr(int irq, void *dev_id);
\r
1328 static void get_hw_info(struct vpu_service_info *pservice);
\r
1330 #if HEVC_SIM_ENABLE
\r
1331 static void simulate_work(struct work_struct *work_s)
\r
1333 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
\r
1334 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
\r
1335 vpu_device *dev = &pservice->dec_dev;
\r
1337 if (!list_empty(&pservice->running)) {
\r
1338 atomic_add(1, &dev->irq_count_codec);
\r
1339 vdpu_isr(0, (void*)pservice);
\r
1341 //simulate_start(pservice);
\r
1342 pr_err("empty running queue\n");
\r
1346 static void simulate_init(struct vpu_service_info *pservice)
\r
1348 INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
\r
1351 static void simulate_start(struct vpu_service_info *pservice)
\r
1353 cancel_delayed_work_sync(&pservice->power_off_work);
\r
1354 queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
\r
1358 #if HEVC_TEST_ENABLE
\r
1359 static int hevc_test_case0(vpu_service_info *pservice);
\r
1361 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)
\r
1362 extern struct ion_client *rockchip_ion_client_create(const char * name);
\r
1364 static int vcodec_probe(struct platform_device *pdev)
\r
1367 struct resource *res = NULL;
\r
1368 struct device *dev = &pdev->dev;
\r
1369 void __iomem *regs = NULL;
\r
1370 struct device_node *np = pdev->dev.of_node;
\r
1371 struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
\r
1372 char *prop = (char*)dev_name(dev);
\r
1373 #if defined(CONFIG_VCODEC_MMU)
\r
1374 struct device *mmu_dev = NULL;
\r
1375 char mmu_dev_dts_name[40];
\r
1378 pr_info("probe device %s\n", dev_name(dev));
\r
1380 of_property_read_string(np, "name", (const char**)&prop);
\r
1381 dev_set_name(dev, prop);
\r
1383 if (strcmp(dev_name(dev), "hevc_service") == 0) {
\r
1384 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
\r
1385 } else if (strcmp(dev_name(dev), "vpu_service") == 0) {
\r
1386 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
\r
1388 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));
\r
1392 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
\r
1393 INIT_LIST_HEAD(&pservice->waiting);
\r
1394 INIT_LIST_HEAD(&pservice->running);
\r
1395 INIT_LIST_HEAD(&pservice->done);
\r
1396 INIT_LIST_HEAD(&pservice->session);
\r
1397 mutex_init(&pservice->lock);
\r
1398 pservice->reg_codec = NULL;
\r
1399 pservice->reg_pproc = NULL;
\r
1400 atomic_set(&pservice->total_running, 0);
\r
1401 pservice->enabled = false;
\r
1403 pservice->dev = dev;
\r
1405 vpu_get_clk(pservice);
\r
1407 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
\r
1409 vpu_service_power_on(pservice);
\r
1411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1413 regs = devm_ioremap_resource(pservice->dev, res);
\r
1414 if (IS_ERR(regs)) {
\r
1415 ret = PTR_ERR(regs);
\r
1419 ret = vpu_service_check_hw(pservice, res->start);
\r
1421 pr_err("error: hw info check faild\n");
\r
1425 /// define regs address.
\r
1426 pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
\r
1427 pservice->dec_dev.iosize = pservice->hw_info->dec_io_size;
\r
1429 pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
\r
1431 pservice->reg_size = pservice->dec_dev.iosize;
\r
1433 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1434 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
\r
1435 pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;
\r
1437 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
\r
1439 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
\r
1441 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
\r
1442 if (pservice->irq_enc < 0) {
\r
1443 dev_err(pservice->dev, "cannot find IRQ encoder\n");
\r
1448 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);
\r
1450 dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
\r
1455 pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
\r
1456 if (pservice->irq_dec < 0) {
\r
1457 dev_err(pservice->dev, "cannot find IRQ decoder\n");
\r
1462 /* get the IRQ line */
\r
1463 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
\r
1465 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
\r
1469 atomic_set(&pservice->dec_dev.irq_count_codec, 0);
\r
1470 atomic_set(&pservice->dec_dev.irq_count_pp, 0);
\r
1471 atomic_set(&pservice->enc_dev.irq_count_codec, 0);
\r
1472 atomic_set(&pservice->enc_dev.irq_count_pp, 0);
\r
1475 ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
\r
1477 dev_err(dev, "alloc dev_t failed\n");
\r
1481 cdev_init(&pservice->cdev, &vpu_service_fops);
\r
1483 pservice->cdev.owner = THIS_MODULE;
\r
1484 pservice->cdev.ops = &vpu_service_fops;
\r
1486 ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
\r
1489 dev_err(dev, "add dev_t failed\n");
\r
1493 pservice->cls = class_create(THIS_MODULE, dev_name(dev));
\r
1495 if (IS_ERR(pservice->cls)) {
\r
1496 ret = PTR_ERR(pservice->cls);
\r
1497 dev_err(dev, "class_create err:%d\n", ret);
\r
1501 pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
\r
1503 platform_set_drvdata(pdev, pservice);
\r
1505 get_hw_info(pservice);
\r
1508 #ifdef CONFIG_DEBUG_FS
\r
1509 pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
\r
1511 if (pservice->debugfs_dir == NULL) {
\r
1512 pr_err("create debugfs dir %s failed\n", dev_name(dev));
\r
1515 pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,
\r
1516 pservice->debugfs_dir, pservice,
\r
1517 &debug_vcodec_fops);
\r
1520 vpu_service_power_off(pservice);
\r
1521 pr_info("init success\n");
\r
1523 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)
\r
1524 pservice->ion_client = rockchip_ion_client_create("vpu");
\r
1525 if (IS_ERR(pservice->ion_client)) {
\r
1526 dev_err(&pdev->dev, "failed to create ion client for vcodec");
\r
1527 return PTR_ERR(pservice->ion_client);
\r
1529 dev_info(&pdev->dev, "vcodec ion client create success!\n");
\r
1532 sprintf(mmu_dev_dts_name, "iommu,%s", dev_name(dev));
\r
1534 mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);
\r
1535 platform_set_sysmmu(mmu_dev, pservice->dev);
\r
1537 iovmm_activate(pservice->dev);
\r
1540 #if HEVC_SIM_ENABLE
\r
1541 if (pservice->hw_info->hw_id == HEVC_ID) {
\r
1542 simulate_init(pservice);
\r
1546 #if HEVC_TEST_ENABLE
\r
1547 hevc_test_case0(pservice);
\r
1553 pr_info("init failed\n");
\r
1554 vpu_service_power_off(pservice);
\r
1555 vpu_put_clk(pservice);
\r
1556 wake_lock_destroy(&pservice->wake_lock);
\r
1560 devm_ioremap_release(&pdev->dev, res);
\r
1562 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
\r
1565 if (pservice->irq_enc > 0) {
\r
1566 free_irq(pservice->irq_enc, (void *)pservice);
\r
1569 if (pservice->irq_dec > 0) {
\r
1570 free_irq(pservice->irq_dec, (void *)pservice);
\r
1573 if (pservice->child_dev) {
\r
1574 device_destroy(pservice->cls, pservice->dev_t);
\r
1575 cdev_del(&pservice->cdev);
\r
1576 unregister_chrdev_region(pservice->dev_t, 1);
\r
1579 if (pservice->cls) {
\r
1580 class_destroy(pservice->cls);
\r
1586 static int vcodec_remove(struct platform_device *pdev)
\r
1588 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
\r
1589 struct resource *res;
\r
1591 device_destroy(pservice->cls, pservice->dev_t);
\r
1592 class_destroy(pservice->cls);
\r
1593 cdev_del(&pservice->cdev);
\r
1594 unregister_chrdev_region(pservice->dev_t, 1);
\r
1596 free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
\r
1597 free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
\r
1598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1599 devm_ioremap_release(&pdev->dev, res);
\r
1600 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
\r
1601 vpu_put_clk(pservice);
\r
1602 wake_lock_destroy(&pservice->wake_lock);
\r
1604 #ifdef CONFIG_DEBUG_FS
\r
1605 if (pservice->debugfs_file_regs) {
\r
1606 debugfs_remove(pservice->debugfs_file_regs);
\r
1609 if (pservice->debugfs_dir) {
\r
1610 debugfs_remove(pservice->debugfs_dir);
\r
1617 #if defined(CONFIG_OF)
\r
1618 static const struct of_device_id vcodec_service_dt_ids[] = {
\r
1619 {.compatible = "vpu_service",},
\r
1620 {.compatible = "rockchip,hevc_service",},
\r
1625 static struct platform_driver vcodec_driver = {
\r
1626 .probe = vcodec_probe,
\r
1627 .remove = vcodec_remove,
\r
1630 .owner = THIS_MODULE,
\r
1631 #if defined(CONFIG_OF)
\r
1632 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
\r
1637 static void get_hw_info(struct vpu_service_info *pservice)
\r
1639 VPUHwDecConfig_t *dec = &pservice->dec_config;
\r
1640 VPUHwEncConfig_t *enc = &pservice->enc_config;
\r
1642 if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {
\r
1643 u32 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
\r
1644 u32 asicID = pservice->dec_dev.hwregs[0];
\r
1646 dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;
\r
1647 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
\r
1648 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
\r
1649 dec->jpegSupport = JPEG_PROGRESSIVE;
\r
1650 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
\r
1651 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
\r
1652 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
\r
1653 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
\r
1654 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
\r
1655 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
\r
1657 if (!soc_is_rk3190() && !soc_is_rk3288()) {
\r
1658 dec->maxDecPicWidth = configReg & 0x07FFU;
\r
1660 dec->maxDecPicWidth = 4096;
\r
1663 /* 2nd Config register */
\r
1664 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
\r
1665 if (dec->refBufSupport) {
\r
1666 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
\r
1667 dec->refBufSupport |= 2;
\r
1668 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
\r
1669 dec->refBufSupport |= 4;
\r
1671 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
\r
1672 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
\r
1673 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
\r
1674 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
\r
1676 /* JPEG xtensions */
\r
1677 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
\r
1678 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
\r
1680 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
\r
1683 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {
\r
1684 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
\r
1686 dec->rvSupport = RV_NOT_SUPPORTED;
\r
1689 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
\r
1691 if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {
\r
1692 dec->refBufSupport |= 8; /* enable HW support for offset */
\r
1695 /// invalidate fuse register value in rk319x vpu and following.
\r
1696 if (!soc_is_rk3190() && !soc_is_rk3288()) {
\r
1697 VPUHwFuseStatus_t hwFuseSts;
\r
1698 /* Decoder fuse configuration */
\r
1699 u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
\r
1701 hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
\r
1702 hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
\r
1703 hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
\r
1704 hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
\r
1705 hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
\r
1706 hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
\r
1707 hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
\r
1708 hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
\r
1709 hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
\r
1710 hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
\r
1711 hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
\r
1712 hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
\r
1713 hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
\r
1714 hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
\r
1716 /* check max. decoder output width */
\r
1718 if (fuseReg & 0x8000U)
\r
1719 hwFuseSts.maxDecPicWidthFuse = 1920;
\r
1720 else if (fuseReg & 0x4000U)
\r
1721 hwFuseSts.maxDecPicWidthFuse = 1280;
\r
1722 else if (fuseReg & 0x2000U)
\r
1723 hwFuseSts.maxDecPicWidthFuse = 720;
\r
1724 else if (fuseReg & 0x1000U)
\r
1725 hwFuseSts.maxDecPicWidthFuse = 352;
\r
1726 else /* remove warning */
\r
1727 hwFuseSts.maxDecPicWidthFuse = 352;
\r
1729 hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
\r
1731 /* Pp configuration */
\r
1732 configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
\r
1734 if ((configReg >> DWL_PP_E) & 0x01U) {
\r
1735 dec->ppSupport = 1;
\r
1736 dec->maxPpOutPicWidth = configReg & 0x07FFU;
\r
1737 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
\r
1738 dec->ppConfig = configReg;
\r
1740 dec->ppSupport = 0;
\r
1741 dec->maxPpOutPicWidth = 0;
\r
1742 dec->ppConfig = 0;
\r
1745 /* check the HW versio */
\r
1746 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
\r
1747 /* Pp configuration */
\r
1748 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
\r
1750 if ((configReg >> DWL_PP_E) & 0x01U) {
\r
1751 /* Pp fuse configuration */
\r
1752 u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
\r
1754 if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
\r
1755 hwFuseSts.ppSupportFuse = 1;
\r
1756 /* check max. pp output width */
\r
1757 if (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;
\r
1758 else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;
\r
1759 else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;
\r
1760 else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;
\r
1761 else hwFuseSts.maxPpOutPicWidthFuse = 352;
\r
1762 hwFuseSts.ppConfigFuse = fuseRegPp;
\r
1764 hwFuseSts.ppSupportFuse = 0;
\r
1765 hwFuseSts.maxPpOutPicWidthFuse = 0;
\r
1766 hwFuseSts.ppConfigFuse = 0;
\r
1769 hwFuseSts.ppSupportFuse = 0;
\r
1770 hwFuseSts.maxPpOutPicWidthFuse = 0;
\r
1771 hwFuseSts.ppConfigFuse = 0;
\r
1774 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
\r
1775 dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
\r
1776 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
\r
1777 dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
\r
1778 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
\r
1779 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
\r
1780 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
\r
1781 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
\r
1782 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
\r
1783 dec->jpegSupport = JPEG_BASELINE;
\r
1784 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
\r
1785 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
\r
1786 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
\r
1787 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
\r
1788 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
\r
1789 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
\r
1791 /* check the pp config vs fuse status */
\r
1792 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
\r
1793 u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
\r
1794 u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
\r
1795 u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
\r
1796 u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
\r
1798 if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
\r
1799 if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
\r
1801 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
\r
1802 if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
\r
1803 if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;
\r
1804 if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;
\r
1805 if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;
\r
1809 configReg = pservice->enc_dev.hwregs[63];
\r
1810 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
\r
1811 enc->h264Enabled = (configReg >> 27) & 1;
\r
1812 enc->mpeg4Enabled = (configReg >> 26) & 1;
\r
1813 enc->jpegEnabled = (configReg >> 25) & 1;
\r
1814 enc->vsEnabled = (configReg >> 24) & 1;
\r
1815 enc->rgbEnabled = (configReg >> 28) & 1;
\r
1816 //enc->busType = (configReg >> 20) & 15;
\r
1817 //enc->synthesisLanguage = (configReg >> 16) & 15;
\r
1818 //enc->busWidth = (configReg >> 12) & 15;
\r
1819 enc->reg_size = pservice->reg_size;
\r
1820 enc->reserv[0] = enc->reserv[1] = 0;
\r
1822 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
\r
1823 if (pservice->auto_freq) {
\r
1824 pr_info("vpu_service set to auto frequency mode\n");
\r
1825 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
\r
1827 pservice->bug_dec_addr = cpu_is_rk30xx();
\r
1828 //printk("cpu 3066b bug %d\n", service.bug_dec_addr);
\r
1830 // disable frequency switch in hevc.
\r
1831 pservice->auto_freq = false;
\r
1835 static irqreturn_t vdpu_irq(int irq, void *dev_id)
\r
1837 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1838 vpu_device *dev = &pservice->dec_dev;
\r
1840 u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1842 pr_debug("dec_irq\n");
\r
1844 if (irq_status & DEC_INTERRUPT_BIT) {
\r
1845 pr_debug("dec_isr dec %x\n", irq_status);
\r
1846 if ((irq_status & 0x40001) == 0x40001)
\r
1849 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1850 } while ((irq_status & 0x40001) == 0x40001);
\r
1853 /* clear dec IRQ */
\r
1854 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1855 writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1857 /*writel(irq_status
\r
1858 & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)),
\r
1859 dev->hwregs + DEC_INTERRUPT_REGISTER);*/
\r
1861 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1863 atomic_add(1, &dev->irq_count_codec);
\r
1866 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1867 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
\r
1868 if (irq_status & PP_INTERRUPT_BIT) {
\r
1869 pr_debug("vdpu_isr pp %x\n", irq_status);
\r
1870 /* clear pp IRQ */
\r
1871 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
\r
1872 atomic_add(1, &dev->irq_count_pp);
\r
1876 pservice->irq_status = raw_status;
\r
1878 return IRQ_WAKE_THREAD;
\r
1881 static irqreturn_t vdpu_isr(int irq, void *dev_id)
\r
1883 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1884 vpu_device *dev = &pservice->dec_dev;
\r
1886 mutex_lock(&pservice->lock);
\r
1887 if (atomic_read(&dev->irq_count_codec)) {
\r
1888 #if VPU_SERVICE_SHOW_TIME
\r
1889 do_gettimeofday(&dec_end);
\r
1890 pr_info("dec task: %ld ms\n",
\r
1891 (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
\r
1892 (dec_end.tv_usec - dec_start.tv_usec) / 1000);
\r
1894 atomic_sub(1, &dev->irq_count_codec);
\r
1895 if (NULL == pservice->reg_codec) {
\r
1896 pr_err("error: dec isr with no task waiting\n");
\r
1898 reg_from_run_to_done(pservice, pservice->reg_codec);
\r
1902 if (atomic_read(&dev->irq_count_pp)) {
\r
1904 #if VPU_SERVICE_SHOW_TIME
\r
1905 do_gettimeofday(&pp_end);
\r
1906 printk("pp task: %ld ms\n",
\r
1907 (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
\r
1908 (pp_end.tv_usec - pp_start.tv_usec) / 1000);
\r
1911 atomic_sub(1, &dev->irq_count_pp);
\r
1912 if (NULL == pservice->reg_pproc) {
\r
1913 pr_err("error: pp isr with no task waiting\n");
\r
1915 reg_from_run_to_done(pservice, pservice->reg_pproc);
\r
1918 try_set_reg(pservice);
\r
1919 mutex_unlock(&pservice->lock);
\r
1920 return IRQ_HANDLED;
\r
1923 static irqreturn_t vepu_irq(int irq, void *dev_id)
\r
1925 //struct vpu_device *dev = (struct vpu_device *) dev_id;
\r
1926 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1927 vpu_device *dev = &pservice->enc_dev;
\r
1928 u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
\r
1930 pr_debug("vepu_irq irq status %x\n", irq_status);
\r
1932 #if VPU_SERVICE_SHOW_TIME
\r
1933 do_gettimeofday(&enc_end);
\r
1934 pr_info("enc task: %ld ms\n",
\r
1935 (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
\r
1936 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
\r
1939 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
\r
1940 /* clear enc IRQ */
\r
1941 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
\r
1942 atomic_add(1, &dev->irq_count_codec);
\r
1945 pservice->irq_status = irq_status;
\r
1947 return IRQ_WAKE_THREAD;
\r
1950 static irqreturn_t vepu_isr(int irq, void *dev_id)
\r
1952 //struct vpu_device *dev = (struct vpu_device *) dev_id;
\r
1953 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1954 vpu_device *dev = &pservice->enc_dev;
\r
1956 mutex_lock(&pservice->lock);
\r
1957 if (atomic_read(&dev->irq_count_codec)) {
\r
1958 atomic_sub(1, &dev->irq_count_codec);
\r
1959 if (NULL == pservice->reg_codec) {
\r
1960 pr_err("error: enc isr with no task waiting\n");
\r
1962 reg_from_run_to_done(pservice, pservice->reg_codec);
\r
1965 try_set_reg(pservice);
\r
1966 mutex_unlock(&pservice->lock);
\r
1967 return IRQ_HANDLED;
\r
1970 static int __init vcodec_service_init(void)
\r
1974 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
\r
1975 pr_err("Platform device register failed (%d).\n", ret);
\r
1979 #ifdef CONFIG_DEBUG_FS
\r
1980 vcodec_debugfs_init();
\r
1986 static void __exit vcodec_service_exit(void)
\r
1988 #ifdef CONFIG_DEBUG_FS
\r
1989 vcodec_debugfs_exit();
\r
1992 platform_driver_unregister(&vcodec_driver);
\r
1995 module_init(vcodec_service_init);
\r
1996 module_exit(vcodec_service_exit);
\r
1998 #ifdef CONFIG_DEBUG_FS
\r
1999 #include <linux/seq_file.h>
\r
2001 static int vcodec_debugfs_init()
\r
2003 parent = debugfs_create_dir("vcodec", NULL);
\r
2010 static void vcodec_debugfs_exit()
\r
2012 debugfs_remove(parent);
\r
2015 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
\r
2017 return debugfs_create_dir(dirname, parent);
\r
2020 static int debug_vcodec_show(struct seq_file *s, void *unused)
\r
2022 struct vpu_service_info *pservice = s->private;
\r
2023 unsigned int i, n;
\r
2024 vpu_reg *reg, *reg_tmp;
\r
2025 vpu_session *session, *session_tmp;
\r
2027 mutex_lock(&pservice->lock);
\r
2028 vpu_service_power_on(pservice);
\r
2029 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
2030 seq_printf(s, "\nENC Registers:\n");
\r
2031 n = pservice->enc_dev.iosize >> 2;
\r
2032 for (i = 0; i < n; i++) {
\r
2033 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
\r
2036 seq_printf(s, "\nDEC Registers:\n");
\r
2037 n = pservice->dec_dev.iosize >> 2;
\r
2038 for (i = 0; i < n; i++) {
\r
2039 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
\r
2042 seq_printf(s, "\nvpu service status:\n");
\r
2043 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
\r
2044 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
\r
2045 //seq_printf(s, "waiting reg set %d\n");
\r
2046 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
\r
2047 seq_printf(s, "waiting register set\n");
\r
2049 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
\r
2050 seq_printf(s, "running register set\n");
\r
2052 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
\r
2053 seq_printf(s, "done register set\n");
\r
2056 mutex_unlock(&pservice->lock);
\r
2061 static int debug_vcodec_open(struct inode *inode, struct file *file)
\r
2063 return single_open(file, debug_vcodec_show, inode->i_private);
\r
2068 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
\r
2069 #include "hevc_test_inc/pps_00.h"
\r
2070 #include "hevc_test_inc/register_00.h"
\r
2071 #include "hevc_test_inc/rps_00.h"
\r
2072 #include "hevc_test_inc/scaling_list_00.h"
\r
2073 #include "hevc_test_inc/stream_00.h"
\r
2075 #include "hevc_test_inc/pps_01.h"
\r
2076 #include "hevc_test_inc/register_01.h"
\r
2077 #include "hevc_test_inc/rps_01.h"
\r
2078 #include "hevc_test_inc/scaling_list_01.h"
\r
2079 #include "hevc_test_inc/stream_01.h"
\r
2081 #include "hevc_test_inc/cabac.h"
\r
2083 extern struct ion_client *rockchip_ion_client_create(const char * name);
\r
2085 static struct ion_client *ion_client = NULL;
\r
2086 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
\r
2088 int size = (len+15) & (~15);
\r
2089 struct ion_handle *handle;
\r
2090 u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
\r
2092 if (ion_client == NULL) {
\r
2093 ion_client = rockchip_ion_client_create("vcodec");
\r
2096 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
\r
2098 ptr = ion_map_kernel(ion_client, handle);
\r
2100 ion_phys(ion_client, handle, phy, &size);
\r
2102 memcpy(ptr, tbl, len);
\r
2107 u8* get_align_ptr_no_copy(int len, u32 *phy)
\r
2109 int size = (len+15) & (~15);
\r
2110 struct ion_handle *handle;
\r
2111 u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
\r
2113 if (ion_client == NULL) {
\r
2114 ion_client = rockchip_ion_client_create("vcodec");
\r
2117 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
\r
2119 ptr = ion_map_kernel(ion_client, handle);
\r
2121 ion_phys(ion_client, handle, phy, &size);
\r
2126 #define TEST_CNT 2
\r
2127 static int hevc_test_case0(vpu_service_info *pservice)
\r
2129 vpu_session session;
\r
2131 unsigned long size = 272;//sizeof(register_00); // registers array length
\r
2135 u8 *pps_tbl[TEST_CNT];
\r
2136 u8 *register_tbl[TEST_CNT];
\r
2137 u8 *rps_tbl[TEST_CNT];
\r
2138 u8 *scaling_list_tbl[TEST_CNT];
\r
2139 u8 *stream_tbl[TEST_CNT];
\r
2141 int stream_size[2];
\r
2145 int cabac_size[2];
\r
2155 volatile u8 *stream_buf;
\r
2156 volatile u8 *pps_buf;
\r
2157 volatile u8 *rps_buf;
\r
2158 volatile u8 *scl_buf;
\r
2159 volatile u8 *yuv_buf;
\r
2160 volatile u8 *cabac_buf;
\r
2161 volatile u8 *ref_buf;
\r
2167 pps_tbl[0] = pps_00;
\r
2168 pps_tbl[1] = pps_01;
\r
2170 register_tbl[0] = register_00;
\r
2171 register_tbl[1] = register_01;
\r
2173 rps_tbl[0] = rps_00;
\r
2174 rps_tbl[1] = rps_01;
\r
2176 scaling_list_tbl[0] = scaling_list_00;
\r
2177 scaling_list_tbl[1] = scaling_list_01;
\r
2179 stream_tbl[0] = stream_00;
\r
2180 stream_tbl[1] = stream_01;
\r
2182 stream_size[0] = sizeof(stream_00);
\r
2183 stream_size[1] = sizeof(stream_01);
\r
2185 pps_size[0] = sizeof(pps_00);
\r
2186 pps_size[1] = sizeof(pps_01);
\r
2188 rps_size[0] = sizeof(rps_00);
\r
2189 rps_size[1] = sizeof(rps_01);
\r
2191 scl_size[0] = sizeof(scaling_list_00);
\r
2192 scl_size[1] = sizeof(scaling_list_01);
\r
2194 cabac_size[0] = sizeof(Cabac_table);
\r
2195 cabac_size[1] = sizeof(Cabac_table);
\r
2198 session.pid = current->pid;
\r
2199 session.type = VPU_DEC;
\r
2200 INIT_LIST_HEAD(&session.waiting);
\r
2201 INIT_LIST_HEAD(&session.running);
\r
2202 INIT_LIST_HEAD(&session.done);
\r
2203 INIT_LIST_HEAD(&session.list_session);
\r
2204 init_waitqueue_head(&session.wait);
\r
2205 atomic_set(&session.task_running, 0);
\r
2206 list_add_tail(&session.list_session, &pservice->session);
\r
2208 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
\r
2209 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
\r
2211 while (testidx < TEST_CNT) {
\r
2213 // create registers
\r
2214 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
\r
2215 if (NULL == reg) {
\r
2216 pr_err("error: kmalloc fail in reg_init\n");
\r
2221 if (size > pservice->reg_size) {
\r
2222 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
\r
2223 size = pservice->reg_size;
\r
2225 reg->session = &session;
\r
2226 reg->type = session.type;
\r
2228 reg->freq = VPU_FREQ_DEFAULT;
\r
2229 reg->reg = (unsigned long *)®[1];
\r
2230 INIT_LIST_HEAD(®->session_link);
\r
2231 INIT_LIST_HEAD(®->status_link);
\r
2233 // TODO: stuff registers
\r
2234 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
\r
2236 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
\r
2237 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
\r
2238 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
\r
2239 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
\r
2240 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
\r
2244 // TODO: replace reigster address
\r
2246 for (i=0; i<64; i++) {
\r
2247 u32 scaling_offset;
\r
2250 scaling_offset = (u32)pps[i*80+74];
\r
2251 scaling_offset += (u32)pps[i*80+75] << 8;
\r
2252 scaling_offset += (u32)pps[i*80+76] << 16;
\r
2253 scaling_offset += (u32)pps[i*80+77] << 24;
\r
2255 tmp = phy_scl + scaling_offset;
\r
2257 pps[i*80+74] = tmp & 0xff;
\r
2258 pps[i*80+75] = (tmp >> 8) & 0xff;
\r
2259 pps[i*80+76] = (tmp >> 16) & 0xff;
\r
2260 pps[i*80+77] = (tmp >> 24) & 0xff;
\r
2263 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);
\r
2265 reg->reg[1] = 0x21;
\r
2266 reg->reg[4] = phy_str;
\r
2267 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
\r
2268 reg->reg[6] = phy_cabac;
\r
2269 reg->reg[7] = testidx?phy_ref:phy_yuv;
\r
2270 reg->reg[42] = phy_pps;
\r
2271 reg->reg[43] = phy_rps;
\r
2272 for (i = 10; i <= 24; i++) {
\r
2273 reg->reg[i] = phy_yuv;
\r
2276 mutex_lock(&pservice->lock);
\r
2277 list_add_tail(®->status_link, &pservice->waiting);
\r
2278 list_add_tail(®->session_link, &session.waiting);
\r
2279 mutex_unlock(&pservice->lock);
\r
2281 printk("%s %d %p\n", __func__, __LINE__, pservice);
\r
2284 try_set_reg(pservice);
\r
2286 // wait for result
\r
2287 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
\r
2288 if (!list_empty(&session.done)) {
\r
2290 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
\r
2294 if (unlikely(ret < 0)) {
\r
2295 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
\r
2296 } else if (0 == ret) {
\r
2297 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
\r
2302 int task_running = atomic_read(&session.task_running);
\r
2304 mutex_lock(&pservice->lock);
\r
2305 vpu_service_dump(pservice);
\r
2306 if (task_running) {
\r
2307 atomic_set(&session.task_running, 0);
\r
2308 atomic_sub(task_running, &pservice->total_running);
\r
2309 printk("%d task is running but not return, reset hardware...", task_running);
\r
2310 vpu_reset(pservice);
\r
2313 vpu_service_session_clear(pservice, &session);
\r
2314 mutex_unlock(&pservice->lock);
\r
2316 printk("\nDEC Registers:\n");
\r
2317 n = pservice->dec_dev.iosize >> 2;
\r
2318 for (i=0; i<n; i++) {
\r
2319 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
\r
2322 pr_err("test index %d failed\n", testidx);
\r
2325 pr_info("test index %d success\n", testidx);
\r
2327 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
\r
2329 for (i=0; i<68; i++) {
\r
2331 printk("%02d: ", i);
\r
2333 printk("%08x ", reg->reg[i]);
\r
2334 if ((i+1) % 4 == 0) {
\r
2342 reg_deinit(pservice, reg);
\r