arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/fs.h>
  25 #include <linux/ioport.h>
  26 #include <linux/miscdevice.h>
  27 #include <linux/mm.h>
  28 #include <linux/poll.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/wakelock.h>
  33 #include <linux/cdev.h>
  34 #include <linux/of.h>
  35 #include <linux/of_platform.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39 #ifdef CONFIG_MFD_SYSCON
  40 #include <linux/regmap.h>
  41 #endif
  42 #include <linux/mfd/syscon.h>
  43
  44 #include <asm/cacheflush.h>
  45 #include <linux/uaccess.h>
  46 #include <linux/rockchip/grf.h>
  47
  48 #if defined(CONFIG_ION_ROCKCHIP)
  49 #include <linux/rockchip_ion.h>
  50 #endif
  51
  52 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  53 #define CONFIG_VCODEC_MMU
  54 #endif
  55
  56 #ifdef CONFIG_VCODEC_MMU
  57 #include <linux/rockchip-iovmm.h>
  58 #include <linux/dma-buf.h>
  59 #endif
  60
  61 #ifdef CONFIG_DEBUG_FS
  62 #include <linux/debugfs.h>
  63 #endif
  64
  65 #if defined(CONFIG_ARCH_RK319X)
  66 #include <mach/grf.h>
  67 #endif
  68
  69 #include "vcodec_service.h"
  70
  71 static int debug;
  72 module_param(debug, int, S_IRUGO | S_IWUSR);
  73 MODULE_PARM_DESC(debug,
  74                  "Debug level - higher value produces more verbose messages");
  75
  76 #define HEVC_TEST_ENABLE        0
  77 #define VCODEC_CLOCK_ENABLE     1
  78
  79 typedef enum {
  80         VPU_DEC_ID_9190         = 0x6731,
  81         VPU_ID_8270             = 0x8270,
  82         VPU_ID_4831             = 0x4831,
  83         HEVC_ID                 = 0x6867,
  84 } VPU_HW_ID;
  85
  86 enum VPU_HW_SPEC {
  87         VPU_TYPE_VPU,
  88         VPU_TYPE_HEVC,
  89         VPU_TYPE_COMBO_NOENC,
  90         VPU_TYPE_COMBO
  91 };
  92
  93 typedef enum {
  94         VPU_DEC_TYPE_9190       = 0,
  95         VPU_ENC_TYPE_8270       = 0x100,
  96         VPU_ENC_TYPE_4831       ,
  97 } VPU_HW_TYPE_E;
  98
  99 typedef enum VPU_FREQ {
 100         VPU_FREQ_200M,
 101         VPU_FREQ_266M,
 102         VPU_FREQ_300M,
 103         VPU_FREQ_400M,
 104         VPU_FREQ_500M,
 105         VPU_FREQ_600M,
 106         VPU_FREQ_DEFAULT,
 107         VPU_FREQ_BUT,
 108 } VPU_FREQ;
 109
 110 typedef struct {
 111         VPU_HW_ID               hw_id;
 112         unsigned long           hw_addr;
 113         unsigned long           enc_offset;
 114         unsigned long           enc_reg_num;
 115         unsigned long           enc_io_size;
 116         unsigned long           dec_offset;
 117         unsigned long           dec_reg_num;
 118         unsigned long           dec_io_size;
 119 } VPU_HW_INFO_E;
 120
 121 struct extra_info_elem {
 122         u32 index;
 123         u32 offset;
 124 };
 125
 126 #define EXTRA_INFO_MAGIC        0x4C4A46
 127
 128 struct extra_info_for_iommu {
 129         u32 magic;
 130         u32 cnt;
 131         struct extra_info_elem elem[20];
 132 };
 133
 134 #define VPU_SERVICE_SHOW_TIME                   0
 135
 136 #if VPU_SERVICE_SHOW_TIME
 137 static struct timeval enc_start, enc_end;
 138 static struct timeval dec_start, dec_end;
 139 static struct timeval pp_start,  pp_end;
 140 #endif
 141
 142 #define MHZ                                     (1000*1000)
 143
 144 #define REG_NUM_9190_DEC                        (60)
 145 #define REG_NUM_9190_PP                         (41)
 146 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 147
 148 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 149
 150 #define REG_NUM_ENC_8270                        (96)
 151 #define REG_SIZE_ENC_8270                       (0x200)
 152 #define REG_NUM_ENC_4831                        (164)
 153 #define REG_SIZE_ENC_4831                       (0x400)
 154
 155 #define REG_NUM_HEVC_DEC                        (68)
 156
 157 #define SIZE_REG(reg)                           ((reg)*4)
 158
 159 static VPU_HW_INFO_E vpu_hw_set[] = {
 160         [0] = {
 161                 .hw_id          = VPU_ID_8270,
 162                 .hw_addr        = 0,
 163                 .enc_offset     = 0x0,
 164                 .enc_reg_num    = REG_NUM_ENC_8270,
 165                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 166                 .dec_offset     = REG_SIZE_ENC_8270,
 167                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 168                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 169         },
 170         [1] = {
 171                 .hw_id          = VPU_ID_4831,
 172                 .hw_addr        = 0,
 173                 .enc_offset     = 0x0,
 174                 .enc_reg_num    = REG_NUM_ENC_4831,
 175                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 176                 .dec_offset     = REG_SIZE_ENC_4831,
 177                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 178                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 179         },
 180         [2] = {
 181                 .hw_id          = HEVC_ID,
 182                 .hw_addr        = 0,
 183                 .dec_offset     = 0x0,
 184                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 185                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 186         },
 187         [3] = {
 188                 .hw_id          = VPU_DEC_ID_9190,
 189                 .hw_addr        = 0,
 190                 .enc_offset     = 0x0,
 191                 .enc_reg_num    = 0,
 192                 .enc_io_size    = 0,
 193                 .dec_offset     = 0,
 194                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 195                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 196         },
 197 };
 198
 199
 200 #define DEC_INTERRUPT_REGISTER                  1
 201 #define PP_INTERRUPT_REGISTER                   60
 202 #define ENC_INTERRUPT_REGISTER                  1
 203
 204 #define DEC_INTERRUPT_BIT                       0x100
 205 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 206 #define PP_INTERRUPT_BIT                        0x100
 207 #define ENC_INTERRUPT_BIT                       0x1
 208
 209 #define HEVC_DEC_INT_RAW_BIT                    0x200
 210 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 211 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 212 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 213
 214 #define VPU_REG_EN_ENC                          14
 215 #define VPU_REG_ENC_GATE                        2
 216 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 217
 218 #define VPU_REG_EN_DEC                          1
 219 #define VPU_REG_DEC_GATE                        2
 220 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 221 #define VPU_REG_EN_PP                           0
 222 #define VPU_REG_PP_GATE                         1
 223 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 224 #define VPU_REG_EN_DEC_PP                       1
 225 #define VPU_REG_DEC_PP_GATE                     61
 226 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 227
 228 #define DEBUG
 229 #ifdef DEBUG
 230 #define vpu_debug(level, fmt, args...)                          \
 231         do {                                                    \
 232                 if (debug >= level)                             \
 233                         pr_info("%s:%d: " fmt,                  \
 234                                  __func__, __LINE__, ##args);   \
 235         } while (0)
 236 #else
 237 #define vpu_debug(level, fmt, args...)
 238 #endif
 239
 240 #define vpu_debug_enter() vpu_debug(4, "enter\n")
 241 #define vpu_debug_leave() vpu_debug(4, "leave\n")
 242
 243 #define vpu_err(fmt, args...)                           \
 244                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 245
 246 #if defined(CONFIG_VCODEC_MMU)
 247 static u8 addr_tbl_vpu_h264dec[] = {
 248         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 249         25, 26, 27, 28, 29, 40, 41
 250 };
 251
 252 static u8 addr_tbl_vpu_vp8dec[] = {
 253         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 254 };
 255
 256 static u8 addr_tbl_vpu_vp6dec[] = {
 257         12, 13, 14, 18, 27, 40
 258 };
 259
 260 static u8 addr_tbl_vpu_vc1dec[] = {
 261         12, 13, 14, 15, 16, 17, 27, 41
 262 };
 263
 264 static u8 addr_tbl_vpu_jpegdec[] = {
 265         12, 40, 66, 67
 266 };
 267
 268 static u8 addr_tbl_vpu_defaultdec[] = {
 269         12, 13, 14, 15, 16, 17, 40, 41
 270 };
 271
 272 static u8 addr_tbl_vpu_enc[] = {
 273         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 274 };
 275
 276 static u8 addr_tbl_hevc_dec[] = {
 277         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 278         21, 22, 23, 24, 42, 43
 279 };
 280 #endif
 281
 282 enum VPU_DEC_FMT {
 283         VPU_DEC_FMT_H264,
 284         VPU_DEC_FMT_MPEG4,
 285         VPU_DEC_FMT_H263,
 286         VPU_DEC_FMT_JPEG,
 287         VPU_DEC_FMT_VC1,
 288         VPU_DEC_FMT_MPEG2,
 289         VPU_DEC_FMT_MPEG1,
 290         VPU_DEC_FMT_VP6,
 291         VPU_DEC_FMT_RV,
 292         VPU_DEC_FMT_VP7,
 293         VPU_DEC_FMT_VP8,
 294         VPU_DEC_FMT_AVS,
 295         VPU_DEC_FMT_SVC,
 296         VPU_DEC_FMT_VC2,
 297         VPU_DEC_FMT_MVC,
 298         VPU_DEC_FMT_THEORA,
 299         VPU_DEC_FMT_RES
 300 };
 301
 302 /**
 303  * struct for process session which connect to vpu
 304  *
 305  * @author ChenHengming (2011-5-3)
 306  */
 307 typedef struct vpu_session {
 308         enum VPU_CLIENT_TYPE type;
 309         /* a linked list of data so we can access them for debugging */
 310         struct list_head list_session;
 311         /* a linked list of register data waiting for process */
 312         struct list_head waiting;
 313         /* a linked list of register data in processing */
 314         struct list_head running;
 315         /* a linked list of register data processed */
 316         struct list_head done;
 317         wait_queue_head_t wait;
 318         pid_t pid;
 319         atomic_t task_running;
 320 } vpu_session;
 321
 322 /**
 323  * struct for process register set
 324  *
 325  * @author ChenHengming (2011-5-4)
 326  */
 327 typedef struct vpu_reg {
 328         enum VPU_CLIENT_TYPE type;
 329         VPU_FREQ freq;
 330         vpu_session *session;
 331         struct list_head session_link;          /* link to vpu service session */
 332         struct list_head status_link;           /* link to register set list */
 333         unsigned long size;
 334 #if defined(CONFIG_VCODEC_MMU)
 335         struct list_head mem_region_list;
 336 #endif
 337         u32 *reg;
 338 } vpu_reg;
 339
 340 typedef struct vpu_device {
 341         atomic_t                irq_count_codec;
 342         atomic_t                irq_count_pp;
 343         unsigned long           iobaseaddr;
 344         unsigned int            iosize;
 345         volatile u32            *hwregs;
 346 } vpu_device;
 347
 348 enum vcodec_device_id {
 349         VCODEC_DEVICE_ID_VPU,
 350         VCODEC_DEVICE_ID_HEVC,
 351         VCODEC_DEVICE_ID_COMBO
 352 };
 353
 354 enum VCODEC_RUNNING_MODE {
 355         VCODEC_RUNNING_MODE_NONE = -1,
 356         VCODEC_RUNNING_MODE_VPU,
 357         VCODEC_RUNNING_MODE_HEVC,
 358 };
 359
 360 struct vcodec_mem_region {
 361         struct list_head srv_lnk;
 362         struct list_head reg_lnk;
 363         struct list_head session_lnk;
 364         unsigned long iova;     /* virtual address for iommu */
 365         unsigned long len;
 366         u32 reg_idx;
 367         struct ion_handle *hdl;
 368 };
 369
 370 enum vpu_ctx_state {
 371         MMU_ACTIVATED   = BIT(0)
 372 };
 373
 374 struct vpu_subdev_data {
 375         struct cdev cdev;
 376         dev_t dev_t;
 377         struct class *cls;
 378         struct device *child_dev;
 379
 380         int irq_enc;
 381         int irq_dec;
 382         struct vpu_service_info *pservice;
 383
 384         u32 *regs;
 385         enum VCODEC_RUNNING_MODE mode;
 386         struct list_head lnk_service;
 387
 388         struct device *dev;
 389
 390         vpu_device enc_dev;
 391         vpu_device dec_dev;
 392         VPU_HW_INFO_E *hw_info;
 393
 394         u32 reg_size;
 395         unsigned long state;
 396
 397 #ifdef CONFIG_DEBUG_FS
 398         struct dentry *debugfs_dir;
 399         struct dentry *debugfs_file_regs;
 400 #endif
 401
 402 #if defined(CONFIG_VCODEC_MMU)
 403         struct device *mmu_dev;
 404 #endif
 405 };
 406
 407 typedef struct vpu_service_info {
 408         struct wake_lock wake_lock;
 409         struct delayed_work power_off_work;
 410         struct mutex lock;
 411         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 412         struct list_head running;               /* link to link_reg in struct vpu_reg */
 413         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 414         struct list_head session;               /* link to list_session in struct vpu_session */
 415         atomic_t total_running;
 416         bool enabled;
 417         vpu_reg *reg_codec;
 418         vpu_reg *reg_pproc;
 419         vpu_reg *reg_resev;
 420         struct vpu_dec_config dec_config;
 421         struct vpu_enc_config enc_config;
 422
 423         bool auto_freq;
 424         bool bug_dec_addr;
 425         atomic_t freq_status;
 426
 427         struct clk *aclk_vcodec;
 428         struct clk *hclk_vcodec;
 429         struct clk *clk_core;
 430         struct clk *clk_cabac;
 431         struct clk *pd_video;
 432
 433         struct device *dev;
 434
 435         u32 irq_status;
 436 #if defined(CONFIG_VCODEC_MMU)
 437         struct ion_client *ion_client;
 438         struct list_head mem_region_list;
 439 #endif
 440
 441         enum vcodec_device_id dev_id;
 442
 443         enum VCODEC_RUNNING_MODE curr_mode;
 444         u32 prev_mode;
 445
 446         struct delayed_work simulate_work;
 447
 448         u32 mode_bit;
 449         u32 mode_ctrl;
 450         u32 *reg_base;
 451         u32 ioaddr;
 452 #ifdef CONFIG_MFD_SYSCON
 453         struct regmap *grf_base;
 454 #else
 455         u32 *grf_base;
 456 #endif
 457         char *name;
 458
 459         u32 subcnt;
 460         struct list_head subdev_list;
 461 } vpu_service_info;
 462
 463 struct vcodec_combo {
 464         struct vpu_service_info *vpu_srv;
 465         struct vpu_service_info *hevc_srv;
 466         struct list_head waiting;
 467         struct list_head running;
 468         struct mutex run_lock;
 469         vpu_reg *reg_codec;
 470         enum vcodec_device_id current_hw_mode;
 471 };
 472
 473 typedef struct vpu_request {
 474         u64 req;
 475         u32 size;
 476 } vpu_request;
 477
 478 /* debugfs root directory for all device (vpu, hevc).*/
 479 static struct dentry *parent;
 480
 481 #ifdef CONFIG_DEBUG_FS
 482 static int vcodec_debugfs_init(void);
 483 static void vcodec_debugfs_exit(void);
 484 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 485 static int debug_vcodec_open(struct inode *inode, struct file *file);
 486
 487 static const struct file_operations debug_vcodec_fops = {
 488         .open = debug_vcodec_open,
 489         .read = seq_read,
 490         .llseek = seq_lseek,
 491         .release = single_release,
 492 };
 493 #endif
 494
 495 #define VDPU_SOFT_RESET_REG     101
 496 #define VDPU_CLEAN_CACHE_REG    516
 497 #define VEPU_CLEAN_CACHE_REG    772
 498 #define HEVC_CLEAN_CACHE_REG    260
 499
 500 #define VPU_REG_ENABLE(base, reg)       do { \
 501                                                 base[reg] = 1; \
 502                                         } while (0)
 503
 504 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 505 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 506 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 507 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 508
 509 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 510 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 511
 512 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 513 {
 514         int bits;
 515         u32 raw = 0;
 516         struct vpu_service_info *pservice = data->pservice;
 517         struct vpu_subdev_data *subdata, *n;
 518         if (pservice->subcnt < 2 || pservice->curr_mode == data->mode) {
 519                 pservice->prev_mode = pservice->curr_mode;
 520                 return;
 521         }
 522         vpu_debug(3, "vcodec enter mode %d\n", data->mode);
 523 #if defined(CONFIG_VCODEC_MMU)
 524         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 525                 if (data != subdata && subdata->mmu_dev &&
 526                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 527                         clear_bit(MMU_ACTIVATED, &subdata->state);
 528                         rockchip_iovmm_deactivate(subdata->dev);
 529                 }
 530         }
 531 #endif
 532         bits = 1 << pservice->mode_bit;
 533 #ifdef CONFIG_MFD_SYSCON
 534         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 535
 536         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 537                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 538                         raw | bits | (bits << 16));
 539         else
 540                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 541                         (raw & (~bits)) | (bits << 16));
 542 #else
 543         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 544         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 545                 writel_relaxed(raw | bits | (bits << 16),
 546                         pservice->grf_base + pservice->mode_ctrl / 4);
 547         else
 548                 writel_relaxed((raw & (~bits)) | (bits << 16),
 549                         pservice->grf_base + pservice->mode_ctrl / 4);
 550 #endif
 551 #if defined(CONFIG_VCODEC_MMU)
 552         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 553                 set_bit(MMU_ACTIVATED, &data->state);
 554                 BUG_ON(!pservice->enabled);
 555                 if (pservice->enabled)
 556                         rockchip_iovmm_activate(data->dev);
 557         }
 558 #endif
 559         pservice->prev_mode = pservice->curr_mode;
 560         pservice->curr_mode = data->mode;
 561 }
 562
 563 static void vcodec_exit_mode(struct vpu_service_info *pservice)
 564 {
 565
 566 }
 567
 568 static int vpu_get_clk(struct vpu_service_info *pservice)
 569 {
 570 #if VCODEC_CLOCK_ENABLE
 571         switch (pservice->dev_id) {
 572         case VCODEC_DEVICE_ID_HEVC:
 573                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 574                 if (IS_ERR(pservice->pd_video)) {
 575                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 576                         return -1;
 577                 }
 578         case VCODEC_DEVICE_ID_COMBO:
 579                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 580                 if (IS_ERR(pservice->clk_cabac)) {
 581                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 582                         pservice->clk_cabac = NULL;
 583                 }
 584                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 585                 if (IS_ERR(pservice->clk_core)) {
 586                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 587                         return -1;
 588                 }
 589         case VCODEC_DEVICE_ID_VPU:
 590                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 591                 if (IS_ERR(pservice->aclk_vcodec)) {
 592                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 593                         return -1;
 594                 }
 595
 596                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 597                 if (IS_ERR(pservice->hclk_vcodec)) {
 598                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 599                         return -1;
 600                 }
 601                 if (pservice->pd_video == NULL) {
 602                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 603                         if (IS_ERR(pservice->pd_video))
 604                                 pservice->pd_video = NULL;
 605                 }
 606                 break;
 607         default:
 608                 ;
 609         }
 610
 611         return 0;
 612 #else
 613         return 0;
 614 #endif
 615 }
 616
 617 static void vpu_put_clk(struct vpu_service_info *pservice)
 618 {
 619 #if VCODEC_CLOCK_ENABLE
 620         if (pservice->pd_video)
 621                 devm_clk_put(pservice->dev, pservice->pd_video);
 622         if (pservice->aclk_vcodec)
 623                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 624         if (pservice->hclk_vcodec)
 625                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 626         if (pservice->clk_core)
 627                 devm_clk_put(pservice->dev, pservice->clk_core);
 628         if (pservice->clk_cabac)
 629                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 630 #endif
 631 }
 632
 633 static void vpu_reset(struct vpu_subdev_data *data)
 634 {
 635         struct vpu_service_info *pservice = data->pservice;
 636 #if defined(CONFIG_ARCH_RK29)
 637         clk_disable(aclk_ddr_vepu);
 638         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 639         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 640         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 641         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 642         mdelay(10);
 643         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 644         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 645         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 646         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 647         clk_enable(aclk_ddr_vepu);
 648 #elif defined(CONFIG_ARCH_RK30)
 649         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 650         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 651         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 652         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 653         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 654         mdelay(1);
 655         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 656         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 657         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 658         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 659         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 660 #endif
 661         pservice->reg_codec = NULL;
 662         pservice->reg_pproc = NULL;
 663         pservice->reg_resev = NULL;
 664
 665 #if defined(CONFIG_VCODEC_MMU)
 666         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 667                 set_bit(MMU_ACTIVATED, &data->state);
 668                 BUG_ON(!pservice->enabled);
 669                 if (pservice->enabled)
 670                         rockchip_iovmm_activate(data->dev);
 671         }
 672 #endif
 673 }
 674
 675 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 676 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 677 {
 678         vpu_reg *reg, *n;
 679         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 680                 reg_deinit(data, reg);
 681         }
 682         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 683                 reg_deinit(data, reg);
 684         }
 685         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 686                 reg_deinit(data, reg);
 687         }
 688 }
 689
 690 static void vpu_service_dump(struct vpu_service_info *pservice)
 691 {
 692 }
 693
 694 static void vpu_service_power_off(struct vpu_service_info *pservice)
 695 {
 696         int total_running;
 697         struct vpu_subdev_data *data = NULL, *n;
 698         if (!pservice->enabled)
 699                 return;
 700
 701         pservice->enabled = false;
 702         total_running = atomic_read(&pservice->total_running);
 703         if (total_running) {
 704                 pr_alert("alert: power off when %d task running!!\n", total_running);
 705                 mdelay(50);
 706                 pr_alert("alert: delay 50 ms for running task\n");
 707                 vpu_service_dump(pservice);
 708         }
 709
 710         pr_info("%s: power off...", dev_name(pservice->dev));
 711         udelay(10);
 712 #if defined(CONFIG_VCODEC_MMU)
 713         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 714                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 715                         clear_bit(MMU_ACTIVATED, &data->state);
 716                         rockchip_iovmm_deactivate(data->dev);
 717                 }
 718         }
 719         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 720 #endif
 721
 722 #if VCODEC_CLOCK_ENABLE
 723         if (pservice->pd_video)
 724                 clk_disable_unprepare(pservice->pd_video);
 725         if (pservice->hclk_vcodec)
 726                 clk_disable_unprepare(pservice->hclk_vcodec);
 727         if (pservice->aclk_vcodec)
 728                 clk_disable_unprepare(pservice->aclk_vcodec);
 729         if (pservice->clk_core)
 730                 clk_disable_unprepare(pservice->clk_core);
 731         if (pservice->clk_cabac)
 732                 clk_disable_unprepare(pservice->clk_cabac);
 733 #endif
 734
 735         wake_unlock(&pservice->wake_lock);
 736         pr_info("done\n");
 737 }
 738
 739 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 740 {
 741         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 742 }
 743
 744 static void vpu_power_off_work(struct work_struct *work_s)
 745 {
 746         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 747         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 748
 749         if (mutex_trylock(&pservice->lock)) {
 750                 vpu_service_power_off(pservice);
 751                 mutex_unlock(&pservice->lock);
 752         } else {
 753                 /* Come back later if the device is busy... */
 754                 vpu_queue_power_off_work(pservice);
 755         }
 756 }
 757
 758 static void vpu_service_power_on(struct vpu_service_info *pservice)
 759 {
 760         static ktime_t last;
 761         ktime_t now = ktime_get();
 762         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 763                 cancel_delayed_work_sync(&pservice->power_off_work);
 764                 vpu_queue_power_off_work(pservice);
 765                 last = now;
 766         }
 767         if (pservice->enabled)
 768                 return ;
 769
 770         pservice->enabled = true;
 771         pr_info("%s: power on\n", dev_name(pservice->dev));
 772
 773 #define BIT_VCODEC_CLK_SEL      (1<<10)
 774         if (cpu_is_rk312x())
 775                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 776                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 777                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 778
 779 #if VCODEC_CLOCK_ENABLE
 780         if (pservice->aclk_vcodec)
 781                 clk_prepare_enable(pservice->aclk_vcodec);
 782         if (pservice->hclk_vcodec)
 783                 clk_prepare_enable(pservice->hclk_vcodec);
 784         if (pservice->clk_core)
 785                 clk_prepare_enable(pservice->clk_core);
 786         if (pservice->clk_cabac)
 787                 clk_prepare_enable(pservice->clk_cabac);
 788         if (pservice->pd_video)
 789                 clk_prepare_enable(pservice->pd_video);
 790 #endif
 791
 792         udelay(10);
 793         wake_lock(&pservice->wake_lock);
 794 }
 795
 796 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 797 {
 798         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 799         return ((type == 8) || (type == 4));
 800 }
 801
 802 static inline bool reg_check_interlace(vpu_reg *reg)
 803 {
 804         u32 type = (reg->reg[3] & (1 << 23));
 805         return (type > 0);
 806 }
 807
 808 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 809 {
 810         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 811         return type;
 812 }
 813
 814 static inline int reg_probe_width(vpu_reg *reg)
 815 {
 816         int width_in_mb = reg->reg[4] >> 23;
 817         return width_in_mb * 16;
 818 }
 819
 820 #if defined(CONFIG_VCODEC_MMU)
 821 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 822 {
 823         struct vpu_service_info *pservice = data->pservice;
 824         struct ion_handle *hdl;
 825         int ret = 0;
 826         struct vcodec_mem_region *mem_region;
 827
 828         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 829         if (IS_ERR(hdl)) {
 830                 vpu_err("import dma-buf from fd %d failed\n", fd);
 831                 return PTR_ERR(hdl);
 832         }
 833         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 834
 835         if (mem_region == NULL) {
 836                 vpu_err("allocate memory for iommu memory region failed\n");
 837                 ion_free(pservice->ion_client, hdl);
 838                 return -1;
 839         }
 840
 841         mem_region->hdl = hdl;
 842         vcodec_enter_mode(data);
 843         ret = ion_map_iommu(data->dev, pservice->ion_client,
 844                 mem_region->hdl, &mem_region->iova, &mem_region->len);
 845         vcodec_exit_mode(pservice);
 846
 847         if (ret < 0) {
 848                 vpu_err("ion map iommu failed\n");
 849                 kfree(mem_region);
 850                 ion_free(pservice->ion_client, hdl);
 851                 return ret;
 852         }
 853         INIT_LIST_HEAD(&mem_region->reg_lnk);
 854         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 855         return mem_region->iova;
 856 }
 857
 858 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
 859                                 int size, vpu_reg *reg,
 860                                 struct extra_info_for_iommu *ext_inf)
 861 {
 862         struct vpu_service_info *pservice = data->pservice;
 863         int i;
 864         int usr_fd = 0;
 865         int offset = 0;
 866
 867         if (tbl == NULL || size <= 0) {
 868                 dev_err(pservice->dev, "input arguments invalidate\n");
 869                 return -1;
 870         }
 871
 872         vpu_service_power_on(pservice);
 873
 874         for (i = 0; i < size; i++) {
 875                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 876
 877                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
 878                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 879                         /* special for vpu dec num 41 regitster */
 880                         offset = reg->reg[tbl[i]] >> 10 << 4;
 881                 else
 882                         offset = reg->reg[tbl[i]] >> 10;
 883
 884                 if (usr_fd != 0) {
 885                         struct ion_handle *hdl;
 886                         int ret = 0;
 887                         struct vcodec_mem_region *mem_region;
 888
 889                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 890                         if (IS_ERR(hdl)) {
 891                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 892                                 return PTR_ERR(hdl);
 893                         }
 894
 895                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
 896                                 int i = 0;
 897                                 char *pps;
 898                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 899                                 for (i=0; i<64; i++) {
 900                                         u32 scaling_offset;
 901                                         u32 tmp;
 902                                         int scaling_fd= 0;
 903                                         scaling_offset = (u32)pps[i*80+74];
 904                                         scaling_offset += (u32)pps[i*80+75] << 8;
 905                                         scaling_offset += (u32)pps[i*80+76] << 16;
 906                                         scaling_offset += (u32)pps[i*80+77] << 24;
 907                                         scaling_fd = scaling_offset&0x3ff;
 908                                         scaling_offset = scaling_offset >> 10;
 909                                         if(scaling_fd > 0) {
 910                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
 911                                                 tmp += scaling_offset;
 912                                                 pps[i*80+74] = tmp & 0xff;
 913                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 914                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 915                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 916                                         }
 917                                 }
 918                         }
 919
 920                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 921
 922                         if (mem_region == NULL) {
 923                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 924                                 ion_free(pservice->ion_client, hdl);
 925                                 return -1;
 926                         }
 927
 928                         mem_region->hdl = hdl;
 929                         mem_region->reg_idx = tbl[i];
 930                         vcodec_enter_mode(data);
 931                         ret = ion_map_iommu(data->dev,
 932                                             pservice->ion_client,
 933                                             mem_region->hdl,
 934                                             &mem_region->iova,
 935                                             &mem_region->len);
 936                         vcodec_exit_mode(pservice);
 937
 938                         if (ret < 0) {
 939                                 dev_err(pservice->dev, "ion map iommu failed\n");
 940                                 kfree(mem_region);
 941                                 ion_free(pservice->ion_client, hdl);
 942                                 return ret;
 943                         }
 944                         reg->reg[tbl[i]] = mem_region->iova + offset;
 945                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 946                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 947                 }
 948         }
 949
 950         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 951                 for (i=0; i<ext_inf->cnt; i++) {
 952                         vpu_debug(3, "reg[%d] + offset %d\n",
 953                                   ext_inf->elem[i].index,
 954                                   ext_inf->elem[i].offset);
 955                         reg->reg[ext_inf->elem[i].index] +=
 956                                 ext_inf->elem[i].offset;
 957                 }
 958         }
 959
 960         return 0;
 961 }
 962
 963 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
 964                                         vpu_reg *reg,
 965                                         struct extra_info_for_iommu *ext_inf)
 966 {
 967         VPU_HW_ID hw_id;
 968         u8 *tbl;
 969         int size = 0;
 970
 971         hw_id = data->hw_info->hw_id;
 972
 973         if (hw_id == HEVC_ID) {
 974                 tbl = addr_tbl_hevc_dec;
 975                 size = sizeof(addr_tbl_hevc_dec);
 976         } else {
 977                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 978                         switch (reg_check_fmt(reg)) {
 979                         case VPU_DEC_FMT_H264:
 980                                 {
 981                                         tbl = addr_tbl_vpu_h264dec;
 982                                         size = sizeof(addr_tbl_vpu_h264dec);
 983                                         break;
 984                                 }
 985                         case VPU_DEC_FMT_VP8:
 986                         case VPU_DEC_FMT_VP7:
 987                                 {
 988                                         tbl = addr_tbl_vpu_vp8dec;
 989                                         size = sizeof(addr_tbl_vpu_vp8dec);
 990                                         break;
 991                                 }
 992
 993                         case VPU_DEC_FMT_VP6:
 994                                 {
 995                                         tbl = addr_tbl_vpu_vp6dec;
 996                                         size = sizeof(addr_tbl_vpu_vp6dec);
 997                                         break;
 998                                 }
 999                         case VPU_DEC_FMT_VC1:
1000                                 {
1001                                         tbl = addr_tbl_vpu_vc1dec;
1002                                         size = sizeof(addr_tbl_vpu_vc1dec);
1003                                         break;
1004                                 }
1005
1006                         case VPU_DEC_FMT_JPEG:
1007                                 {
1008                                         tbl = addr_tbl_vpu_jpegdec;
1009                                         size = sizeof(addr_tbl_vpu_jpegdec);
1010                                         break;
1011                                 }
1012                         default:
1013                                 tbl = addr_tbl_vpu_defaultdec;
1014                                 size = sizeof(addr_tbl_vpu_defaultdec);
1015                                 break;
1016                         }
1017                 } else if (reg->type == VPU_ENC) {
1018                         tbl = addr_tbl_vpu_enc;
1019                         size = sizeof(addr_tbl_vpu_enc);
1020                 }
1021         }
1022
1023         if (size != 0) {
1024                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1025         } else {
1026                 return -1;
1027         }
1028 }
1029 #endif
1030
1031 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1032         vpu_session *session, void __user *src, u32 size)
1033 {
1034         struct vpu_service_info *pservice = data->pservice;
1035         int extra_size = 0;
1036         struct extra_info_for_iommu extra_info;
1037         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1038
1039         vpu_debug_enter();
1040
1041         if (NULL == reg) {
1042                 vpu_err("error: kmalloc fail in reg_init\n");
1043                 return NULL;
1044         }
1045
1046         if (size > data->reg_size) {
1047                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1048                   size, pservice->reg_size);
1049                 size = pservice->reg_size;*/
1050                 extra_size = size - data->reg_size;
1051                 size = data->reg_size;
1052         }
1053         reg->session = session;
1054         reg->type = session->type;
1055         reg->size = size;
1056         reg->freq = VPU_FREQ_DEFAULT;
1057         reg->reg = (u32 *)&reg[1];
1058         INIT_LIST_HEAD(&reg->session_link);
1059         INIT_LIST_HEAD(&reg->status_link);
1060
1061 #if defined(CONFIG_VCODEC_MMU)
1062         if (data->mmu_dev)
1063                 INIT_LIST_HEAD(&reg->mem_region_list);
1064 #endif
1065
1066         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1067                 vpu_err("error: copy_from_user failed in reg_init\n");
1068                 kfree(reg);
1069                 return NULL;
1070         }
1071
1072         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1073                 vpu_err("error: copy_from_user failed in reg_init\n");
1074                 kfree(reg);
1075                 return NULL;
1076         }
1077
1078 #if defined(CONFIG_VCODEC_MMU)
1079         if (data->mmu_dev &&
1080             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1081                 vpu_err("error: translate reg address failed\n");
1082                 kfree(reg);
1083                 return NULL;
1084         }
1085 #endif
1086
1087         mutex_lock(&pservice->lock);
1088         list_add_tail(&reg->status_link, &pservice->waiting);
1089         list_add_tail(&reg->session_link, &session->waiting);
1090         mutex_unlock(&pservice->lock);
1091
1092         if (pservice->auto_freq) {
1093                 if (!soc_is_rk2928g()) {
1094                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1095                                 if (reg_check_rmvb_wmv(reg)) {
1096                                         reg->freq = VPU_FREQ_200M;
1097                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1098                                         if (reg_probe_width(reg) > 3200) {
1099                                                 // raise frequency for 4k avc.
1100                                                 reg->freq = VPU_FREQ_500M;
1101                                         }
1102                                 } else {
1103                                         if (reg_check_interlace(reg)) {
1104                                                 reg->freq = VPU_FREQ_400M;
1105                                         }
1106                                 }
1107                         }
1108                         if (reg->type == VPU_PP) {
1109                                 reg->freq = VPU_FREQ_400M;
1110                         }
1111                 }
1112         }
1113         vpu_debug_leave();
1114         return reg;
1115 }
1116
1117 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1118 {
1119         struct vpu_service_info *pservice = data->pservice;
1120 #if defined(CONFIG_VCODEC_MMU)
1121         struct vcodec_mem_region *mem_region = NULL, *n;
1122 #endif
1123
1124         list_del_init(&reg->session_link);
1125         list_del_init(&reg->status_link);
1126         if (reg == pservice->reg_codec)
1127                 pservice->reg_codec = NULL;
1128         if (reg == pservice->reg_pproc)
1129                 pservice->reg_pproc = NULL;
1130
1131 #if defined(CONFIG_VCODEC_MMU)
1132         /* release memory region attach to this registers table. */
1133         if (data->mmu_dev) {
1134                 list_for_each_entry_safe(mem_region, n,
1135                         &reg->mem_region_list, reg_lnk) {
1136                         /* do not unmap iommu manually,
1137                            unmap will proccess when memory release */
1138                         /*vcodec_enter_mode(data);
1139                         ion_unmap_iommu(data->dev,
1140                                         pservice->ion_client,
1141                                         mem_region->hdl);
1142                         vcodec_exit_mode();*/
1143                         ion_free(pservice->ion_client, mem_region->hdl);
1144                         list_del_init(&mem_region->reg_lnk);
1145                         kfree(mem_region);
1146                 }
1147         }
1148 #endif
1149
1150         kfree(reg);
1151 }
1152
1153 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1154 {
1155         vpu_debug_enter();
1156         list_del_init(&reg->status_link);
1157         list_add_tail(&reg->status_link, &pservice->running);
1158
1159         list_del_init(&reg->session_link);
1160         list_add_tail(&reg->session_link, &reg->session->running);
1161         vpu_debug_leave();
1162 }
1163
1164 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1165 {
1166         int i;
1167         u32 *dst = (u32 *)&reg->reg[0];
1168         vpu_debug_enter();
1169         for (i = 0; i < count; i++)
1170                 *dst++ = *src++;
1171         vpu_debug_leave();
1172 }
1173
1174 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1175         vpu_reg *reg)
1176 {
1177         struct vpu_service_info *pservice = data->pservice;
1178         int irq_reg = -1;
1179
1180         vpu_debug_enter();
1181
1182         list_del_init(&reg->status_link);
1183         list_add_tail(&reg->status_link, &pservice->done);
1184
1185         list_del_init(&reg->session_link);
1186         list_add_tail(&reg->session_link, &reg->session->done);
1187
1188         vcodec_enter_mode(data);
1189         switch (reg->type) {
1190         case VPU_ENC : {
1191                 pservice->reg_codec = NULL;
1192                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1193                 irq_reg = ENC_INTERRUPT_REGISTER;
1194                 break;
1195         }
1196         case VPU_DEC : {
1197                 int reg_len = REG_NUM_9190_DEC;
1198                 pservice->reg_codec = NULL;
1199                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1200                 irq_reg = DEC_INTERRUPT_REGISTER;
1201                 break;
1202         }
1203         case VPU_PP : {
1204                 pservice->reg_pproc = NULL;
1205                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1206                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1207                 break;
1208         }
1209         case VPU_DEC_PP : {
1210                 pservice->reg_codec = NULL;
1211                 pservice->reg_pproc = NULL;
1212                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1213                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1214                 break;
1215         }
1216         default : {
1217                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1218                 break;
1219         }
1220         }
1221         vcodec_exit_mode(pservice);
1222
1223         if (irq_reg != -1)
1224                 reg->reg[irq_reg] = pservice->irq_status;
1225
1226         atomic_sub(1, &reg->session->task_running);
1227         atomic_sub(1, &pservice->total_running);
1228         wake_up(&reg->session->wait);
1229
1230         vpu_debug_leave();
1231 }
1232
1233 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1234 {
1235         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1236         if (curr == reg->freq)
1237                 return;
1238         atomic_set(&pservice->freq_status, reg->freq);
1239         switch (reg->freq) {
1240         case VPU_FREQ_200M : {
1241                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1242         } break;
1243         case VPU_FREQ_266M : {
1244                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1245         } break;
1246         case VPU_FREQ_300M : {
1247                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1248         } break;
1249         case VPU_FREQ_400M : {
1250                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1251         } break;
1252         case VPU_FREQ_500M : {
1253                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1254         } break;
1255         case VPU_FREQ_600M : {
1256                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1257         } break;
1258         default : {
1259                 if (soc_is_rk2928g())
1260                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1261                 else
1262                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1263         } break;
1264         }
1265 }
1266
1267 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1268 {
1269         struct vpu_service_info *pservice = data->pservice;
1270         int i;
1271         u32 *src = (u32 *)&reg->reg[0];
1272         vpu_debug_enter();
1273
1274         atomic_add(1, &pservice->total_running);
1275         atomic_add(1, &reg->session->task_running);
1276         if (pservice->auto_freq)
1277                 vpu_service_set_freq(pservice, reg);
1278
1279         vcodec_enter_mode(data);
1280
1281         switch (reg->type) {
1282         case VPU_ENC : {
1283                 int enc_count = data->hw_info->enc_reg_num;
1284                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1285
1286                 pservice->reg_codec = reg;
1287
1288                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1289
1290                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1291                         dst[i] = src[i];
1292
1293                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1294                         dst[i] = src[i];
1295
1296                 VEPU_CLEAN_CACHE(dst);
1297
1298                 dsb(sy);
1299
1300                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1301                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1302
1303 #if VPU_SERVICE_SHOW_TIME
1304                 do_gettimeofday(&enc_start);
1305 #endif
1306
1307         } break;
1308         case VPU_DEC : {
1309                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1310
1311                 pservice->reg_codec = reg;
1312
1313                 if (data->hw_info->hw_id != HEVC_ID) {
1314                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1315                                 dst[i] = src[i];
1316                         VDPU_CLEAN_CACHE(dst);
1317                 } else {
1318                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1319                                 dst[i] = src[i];
1320                         HEVC_CLEAN_CACHE(dst);
1321                 }
1322
1323                 dsb(sy);
1324
1325                 if (data->hw_info->hw_id != HEVC_ID) {
1326                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1327                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1328                 } else {
1329                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1330                 }
1331                 dsb(sy);
1332                 dmb(sy);
1333 #if VPU_SERVICE_SHOW_TIME
1334                 do_gettimeofday(&dec_start);
1335 #endif
1336         } break;
1337         case VPU_PP : {
1338                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1339                 pservice->reg_pproc = reg;
1340
1341                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1342
1343                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1344                         dst[i] = src[i];
1345
1346                 dsb(sy);
1347
1348                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1349 #if VPU_SERVICE_SHOW_TIME
1350                 do_gettimeofday(&pp_start);
1351 #endif
1352
1353         } break;
1354         case VPU_DEC_PP : {
1355                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1356                 pservice->reg_codec = reg;
1357                 pservice->reg_pproc = reg;
1358
1359                 VDPU_SOFT_RESET(dst);
1360                 VDPU_CLEAN_CACHE(dst);
1361
1362                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1363                         dst[i] = src[i];
1364
1365                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1366                 dsb(sy);
1367
1368                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1369                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1370                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1371 #if VPU_SERVICE_SHOW_TIME
1372                 do_gettimeofday(&dec_start);
1373 #endif
1374         } break;
1375         default : {
1376                 vpu_err("error: unsupport session type %d", reg->type);
1377                 atomic_sub(1, &pservice->total_running);
1378                 atomic_sub(1, &reg->session->task_running);
1379                 break;
1380         }
1381         }
1382
1383         vcodec_exit_mode(pservice);
1384         vpu_debug_leave();
1385 }
1386
1387 static void try_set_reg(struct vpu_subdev_data *data)
1388 {
1389         struct vpu_service_info *pservice = data->pservice;
1390         vpu_debug_enter();
1391         if (!list_empty(&pservice->waiting)) {
1392                 int can_set = 0;
1393                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1394
1395                 vpu_service_power_on(pservice);
1396
1397                 switch (reg->type) {
1398                 case VPU_ENC : {
1399                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1400                                 can_set = 1;
1401                 } break;
1402                 case VPU_DEC : {
1403                         if (NULL == pservice->reg_codec)
1404                                 can_set = 1;
1405                         if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1406                                 can_set = 0;
1407                 } break;
1408                 case VPU_PP : {
1409                         if (NULL == pservice->reg_codec) {
1410                                 if (NULL == pservice->reg_pproc)
1411                                         can_set = 1;
1412                         } else {
1413                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1414                                         can_set = 1;
1415                                 /* can not charge frequency when vpu is working */
1416                                 if (pservice->auto_freq)
1417                                         can_set = 0;
1418                         }
1419                 } break;
1420                 case VPU_DEC_PP : {
1421                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1422                                 can_set = 1;
1423                         } break;
1424                 default : {
1425                         printk("undefined reg type %d\n", reg->type);
1426                 } break;
1427                 }
1428                 if (can_set) {
1429                         reg_from_wait_to_run(pservice, reg);
1430                         reg_copy_to_hw(data, reg);
1431                 }
1432         }
1433         vpu_debug_leave();
1434 }
1435
1436 static int return_reg(struct vpu_subdev_data *data,
1437         vpu_reg *reg, u32 __user *dst)
1438 {
1439         int ret = 0;
1440         vpu_debug_enter();
1441         switch (reg->type) {
1442         case VPU_ENC : {
1443                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1444                         ret = -EFAULT;
1445                 break;
1446         }
1447         case VPU_DEC : {
1448                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1449                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1450                         ret = -EFAULT;
1451                 break;
1452         }
1453         case VPU_PP : {
1454                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1455                         ret = -EFAULT;
1456                 break;
1457         }
1458         case VPU_DEC_PP : {
1459                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1460                         ret = -EFAULT;
1461                 break;
1462         }
1463         default : {
1464                 ret = -EFAULT;
1465                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1466                 break;
1467         }
1468         }
1469         reg_deinit(data, reg);
1470         vpu_debug_leave();
1471         return ret;
1472 }
1473
1474 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1475         unsigned long arg)
1476 {
1477         struct vpu_subdev_data *data =
1478                 container_of(filp->f_dentry->d_inode->i_cdev,
1479                         struct vpu_subdev_data, cdev);
1480         struct vpu_service_info *pservice = data->pservice;
1481         vpu_session *session = (vpu_session *)filp->private_data;
1482         vpu_debug_enter();
1483         vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, (u32)VPU_IOC_SET_CLIENT_TYPE);
1484         if (NULL == session)
1485                 return -EINVAL;
1486
1487         switch (cmd) {
1488         case VPU_IOC_SET_CLIENT_TYPE : {
1489                 session->type = (enum VPU_CLIENT_TYPE)arg;
1490                 break;
1491         }
1492         case VPU_IOC_GET_HW_FUSE_STATUS : {
1493                 vpu_request req;
1494                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1495                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1496                         return -EFAULT;
1497                 } else {
1498                         if (VPU_ENC != session->type) {
1499                                 if (copy_to_user((void __user *)req.req,
1500                                         &pservice->dec_config,
1501                                         sizeof(struct vpu_dec_config))) {
1502                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1503                                                 session->type);
1504                                         return -EFAULT;
1505                                 }
1506                         } else {
1507                                 if (copy_to_user((void __user *)req.req,
1508                                         &pservice->enc_config,
1509                                         sizeof(struct vpu_enc_config ))) {
1510                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1511                                                 session->type);
1512                                         return -EFAULT;
1513                                 }
1514                         }
1515                 }
1516
1517                 break;
1518         }
1519         case VPU_IOC_SET_REG : {
1520                 vpu_request req;
1521                 vpu_reg *reg;
1522                 if (copy_from_user(&req, (void __user *)arg,
1523                         sizeof(vpu_request))) {
1524                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1525                         return -EFAULT;
1526                 }
1527                 reg = reg_init(data, session,
1528                         (void __user *)req.req, req.size);
1529                 if (NULL == reg) {
1530                         return -EFAULT;
1531                 } else {
1532                         mutex_lock(&pservice->lock);
1533                         try_set_reg(data);
1534                         mutex_unlock(&pservice->lock);
1535                 }
1536
1537                 break;
1538         }
1539         case VPU_IOC_GET_REG : {
1540                 vpu_request req;
1541                 vpu_reg *reg;
1542                 if (copy_from_user(&req, (void __user *)arg,
1543                         sizeof(vpu_request))) {
1544                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1545                         return -EFAULT;
1546                 } else {
1547                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1548                         if (!list_empty(&session->done)) {
1549                                 if (ret < 0) {
1550                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1551                                 }
1552                                 ret = 0;
1553                         } else {
1554                                 if (unlikely(ret < 0)) {
1555                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1556                                 } else if (0 == ret) {
1557                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1558                                         ret = -ETIMEDOUT;
1559                                 }
1560                         }
1561                         if (ret < 0) {
1562                                 int task_running = atomic_read(&session->task_running);
1563                                 mutex_lock(&pservice->lock);
1564                                 vpu_service_dump(pservice);
1565                                 if (task_running) {
1566                                         atomic_set(&session->task_running, 0);
1567                                         atomic_sub(task_running, &pservice->total_running);
1568                                         printk("%d task is running but not return, reset hardware...", task_running);
1569                                         vpu_reset(data);
1570                                         printk("done\n");
1571                                 }
1572                                 vpu_service_session_clear(data, session);
1573                                 mutex_unlock(&pservice->lock);
1574                                 return ret;
1575                         }
1576                 }
1577                 mutex_lock(&pservice->lock);
1578                 reg = list_entry(session->done.next, vpu_reg, session_link);
1579                 return_reg(data, reg, (u32 __user *)req.req);
1580                 mutex_unlock(&pservice->lock);
1581                 break;
1582         }
1583         case VPU_IOC_PROBE_IOMMU_STATUS: {
1584                 int iommu_enable = 0;
1585
1586 #if defined(CONFIG_VCODEC_MMU)
1587                 iommu_enable = data->mmu_dev ? 1 : 0;
1588 #endif
1589
1590                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1591                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1592                         return -EFAULT;
1593                 }
1594                 break;
1595         }
1596         default : {
1597                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1598                 break;
1599         }
1600         }
1601         vpu_debug_leave();
1602         return 0;
1603 }
1604
1605 #ifdef CONFIG_COMPAT
1606 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1607         unsigned long arg)
1608 {
1609         struct vpu_subdev_data *data =
1610                 container_of(filp->f_dentry->d_inode->i_cdev,
1611                         struct vpu_subdev_data, cdev);
1612         struct vpu_service_info *pservice = data->pservice;
1613         vpu_session *session = (vpu_session *)filp->private_data;
1614         vpu_debug_enter();
1615         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1616                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1617         if (NULL == session)
1618                 return -EINVAL;
1619
1620         switch (cmd) {
1621         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1622                 session->type = (enum VPU_CLIENT_TYPE)arg;
1623                 break;
1624         }
1625         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1626                 vpu_request req;
1627                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1628                                    sizeof(vpu_request))) {
1629                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1630                                 " copy_from_user failed\n");
1631                         return -EFAULT;
1632                 } else {
1633                         if (VPU_ENC != session->type) {
1634                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1635                                                  &pservice->dec_config,
1636                                                  sizeof(struct vpu_dec_config))) {
1637                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1638                                                 "copy_to_user failed type %d\n",
1639                                                 session->type);
1640                                         return -EFAULT;
1641                                 }
1642                         } else {
1643                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1644                                                  &pservice->enc_config,
1645                                                  sizeof(struct vpu_enc_config ))) {
1646                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1647                                                 " copy_to_user failed type %d\n",
1648                                                 session->type);
1649                                         return -EFAULT;
1650                                 }
1651                         }
1652                 }
1653
1654                 break;
1655         }
1656         case COMPAT_VPU_IOC_SET_REG : {
1657                 vpu_request req;
1658                 vpu_reg *reg;
1659                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1660                                    sizeof(vpu_request))) {
1661                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1662                         return -EFAULT;
1663                 }
1664                 reg = reg_init(data, session,
1665                                compat_ptr((compat_uptr_t)req.req), req.size);
1666                 if (NULL == reg) {
1667                         return -EFAULT;
1668                 } else {
1669                         mutex_lock(&pservice->lock);
1670                         try_set_reg(data);
1671                         mutex_unlock(&pservice->lock);
1672                 }
1673
1674                 break;
1675         }
1676         case COMPAT_VPU_IOC_GET_REG : {
1677                 vpu_request req;
1678                 vpu_reg *reg;
1679                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1680                                    sizeof(vpu_request))) {
1681                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1682                         return -EFAULT;
1683                 } else {
1684                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1685                         if (!list_empty(&session->done)) {
1686                                 if (ret < 0) {
1687                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1688                                 }
1689                                 ret = 0;
1690                         } else {
1691                                 if (unlikely(ret < 0)) {
1692                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1693                                 } else if (0 == ret) {
1694                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1695                                         ret = -ETIMEDOUT;
1696                                 }
1697                         }
1698                         if (ret < 0) {
1699                                 int task_running = atomic_read(&session->task_running);
1700                                 mutex_lock(&pservice->lock);
1701                                 vpu_service_dump(pservice);
1702                                 if (task_running) {
1703                                         atomic_set(&session->task_running, 0);
1704                                         atomic_sub(task_running, &pservice->total_running);
1705                                         printk("%d task is running but not return, reset hardware...", task_running);
1706                                         vpu_reset(data);
1707                                         printk("done\n");
1708                                 }
1709                                 vpu_service_session_clear(data, session);
1710                                 mutex_unlock(&pservice->lock);
1711                                 return ret;
1712                         }
1713                 }
1714                 mutex_lock(&pservice->lock);
1715                 reg = list_entry(session->done.next, vpu_reg, session_link);
1716                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1717                 mutex_unlock(&pservice->lock);
1718                 break;
1719         }
1720         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1721                 int iommu_enable = 0;
1722
1723 #if defined(CONFIG_VCODEC_MMU)
1724                 iommu_enable = data->mmu_dev ? 1 : 0;
1725 #endif
1726
1727                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1728                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1729                         return -EFAULT;
1730                 }
1731                 break;
1732         }
1733         default : {
1734                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1735                 break;
1736         }
1737         }
1738         vpu_debug_leave();
1739         return 0;
1740 }
1741 #endif
1742
1743 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1744 {
1745         int ret = -EINVAL, i = 0;
1746         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1747         u32 enc_id = *tmp;
1748
1749         enc_id = (enc_id >> 16) & 0xFFFF;
1750         pr_info("checking hw id %x\n", enc_id);
1751         data->hw_info = NULL;
1752         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1753                 if (enc_id == vpu_hw_set[i].hw_id) {
1754                         data->hw_info = &vpu_hw_set[i];
1755                         ret = 0;
1756                         break;
1757                 }
1758         }
1759         iounmap((void *)tmp);
1760         return ret;
1761 }
1762
1763 static int vpu_service_open(struct inode *inode, struct file *filp)
1764 {
1765         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1766         struct vpu_service_info *pservice = data->pservice;
1767         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1768
1769         vpu_debug_enter();
1770
1771         if (NULL == session) {
1772                 vpu_err("error: unable to allocate memory for vpu_session.");
1773                 return -ENOMEM;
1774         }
1775
1776         session->type   = VPU_TYPE_BUTT;
1777         session->pid    = current->pid;
1778         INIT_LIST_HEAD(&session->waiting);
1779         INIT_LIST_HEAD(&session->running);
1780         INIT_LIST_HEAD(&session->done);
1781         INIT_LIST_HEAD(&session->list_session);
1782         init_waitqueue_head(&session->wait);
1783         atomic_set(&session->task_running, 0);
1784         mutex_lock(&pservice->lock);
1785         list_add_tail(&session->list_session, &pservice->session);
1786         filp->private_data = (void *)session;
1787         mutex_unlock(&pservice->lock);
1788
1789         pr_debug("dev opened\n");
1790         vpu_debug_leave();
1791         return nonseekable_open(inode, filp);
1792 }
1793
1794 static int vpu_service_release(struct inode *inode, struct file *filp)
1795 {
1796         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1797         struct vpu_service_info *pservice = data->pservice;
1798         int task_running;
1799         vpu_session *session = (vpu_session *)filp->private_data;
1800         vpu_debug_enter();
1801         if (NULL == session)
1802                 return -EINVAL;
1803
1804         task_running = atomic_read(&session->task_running);
1805         if (task_running) {
1806                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1807                 msleep(50);
1808         }
1809         wake_up(&session->wait);
1810
1811         mutex_lock(&pservice->lock);
1812         /* remove this filp from the asynchronusly notified filp's */
1813         list_del_init(&session->list_session);
1814         vpu_service_session_clear(data, session);
1815         kfree(session);
1816         filp->private_data = NULL;
1817         mutex_unlock(&pservice->lock);
1818
1819         pr_debug("dev closed\n");
1820         vpu_debug_leave();
1821         return 0;
1822 }
1823
1824 static const struct file_operations vpu_service_fops = {
1825         .unlocked_ioctl = vpu_service_ioctl,
1826         .open           = vpu_service_open,
1827         .release        = vpu_service_release,
1828 #ifdef CONFIG_COMPAT
1829         .compat_ioctl   = compat_vpu_service_ioctl,
1830 #endif
1831         //.fasync       = vpu_service_fasync,
1832 };
1833
1834 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1835 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1836 static irqreturn_t vepu_irq(int irq, void *dev_id);
1837 static irqreturn_t vepu_isr(int irq, void *dev_id);
1838 static void get_hw_info(struct vpu_subdev_data *data);
1839
1840 #ifdef CONFIG_VCODEC_MMU
1841 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1842 {
1843         struct device_node *dn = NULL;
1844         struct platform_device *pd = NULL;
1845         struct device *ret = NULL ;
1846
1847         dn = of_find_compatible_node(NULL,NULL,compt);
1848         if(!dn) {
1849                 printk("can't find device node %s \r\n",compt);
1850                 return NULL;
1851         }
1852
1853         pd = of_find_device_by_node(dn);
1854         if(!pd) {
1855                 printk("can't find platform device in device node %s\n",compt);
1856                 return  NULL;
1857         }
1858         ret = &pd->dev;
1859
1860         return ret;
1861
1862 }
1863 #ifdef CONFIG_IOMMU_API
1864 static inline void platform_set_sysmmu(struct device *iommu,
1865         struct device *dev)
1866 {
1867         dev->archdata.iommu = iommu;
1868 }
1869 #else
1870 static inline void platform_set_sysmmu(struct device *iommu,
1871         struct device *dev)
1872 {
1873 }
1874 #endif
1875
1876 int vcodec_sysmmu_fault_hdl(struct device *dev,
1877                                 enum rk_iommu_inttype itype,
1878                                 unsigned long pgtable_base,
1879                                 unsigned long fault_addr, unsigned int status)
1880 {
1881         struct platform_device *pdev;
1882         struct vpu_subdev_data *data;
1883         struct vpu_service_info *pservice;
1884
1885         vpu_debug_enter();
1886
1887         pdev = container_of(dev, struct platform_device, dev);
1888
1889         data = platform_get_drvdata(pdev);
1890         pservice = data->pservice;
1891
1892         if (pservice->reg_codec) {
1893                 struct vcodec_mem_region *mem, *n;
1894                 int i = 0;
1895                 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1896                 list_for_each_entry_safe(mem, n,
1897                                          &pservice->reg_codec->mem_region_list,
1898                                          reg_lnk) {
1899                         vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1900                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1901                         i++;
1902                 }
1903
1904                 pr_alert("vcodec, page fault occur, reset hw\n");
1905                 pservice->reg_codec->reg[101] = 1;
1906                 vpu_reset(data);
1907         }
1908
1909         return 0;
1910 }
1911 #endif
1912
1913 #if HEVC_TEST_ENABLE
1914 static int hevc_test_case0(vpu_service_info *pservice);
1915 #endif
1916 #if defined(CONFIG_ION_ROCKCHIP)
1917 extern struct ion_client *rockchip_ion_client_create(const char * name);
1918 #endif
1919
1920 static int vcodec_subdev_probe(struct platform_device *pdev,
1921         struct vpu_service_info *pservice)
1922 {
1923         int ret = 0;
1924         struct resource *res = NULL;
1925         u32 ioaddr = 0;
1926         struct device *dev = &pdev->dev;
1927         char *name = (char*)dev_name(dev);
1928         struct device_node *np = pdev->dev.of_node;
1929         struct vpu_subdev_data *data =
1930                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1931 #if defined(CONFIG_VCODEC_MMU)
1932         u32 iommu_en = 0;
1933         char mmu_dev_dts_name[40];
1934         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1935 #endif
1936         pr_info("probe device %s\n", dev_name(dev));
1937
1938         data->pservice = pservice;
1939         data->dev = dev;
1940
1941         of_property_read_string(np, "name", (const char**)&name);
1942         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
1943         dev_set_name(dev, name);
1944
1945         if (pservice->reg_base == 0) {
1946                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1947                 data->regs = devm_ioremap_resource(dev, res);
1948                 if (IS_ERR(data->regs)) {
1949                         ret = PTR_ERR(data->regs);
1950                         goto err;
1951                 }
1952                 ioaddr = res->start;
1953         } else {
1954                 data->regs = pservice->reg_base;
1955                 ioaddr = pservice->ioaddr;
1956         }
1957
1958         clear_bit(MMU_ACTIVATED, &data->state);
1959         vcodec_enter_mode(data);
1960         ret = vpu_service_check_hw(data, ioaddr);
1961         if (ret < 0) {
1962                 vpu_err("error: hw info check faild\n");
1963                 goto err;
1964         }
1965
1966         data->dec_dev.iosize = data->hw_info->dec_io_size;
1967         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1968         data->reg_size = data->dec_dev.iosize;
1969
1970         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1971                 data->enc_dev.iosize = data->hw_info->enc_io_size;
1972                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1973                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1974         }
1975
1976         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1977         if (data->irq_enc > 0) {
1978                 ret = devm_request_threaded_irq(dev,
1979                         data->irq_enc, vepu_irq, vepu_isr,
1980                         IRQF_SHARED, dev_name(dev),
1981                         (void *)data);
1982                 if (ret) {
1983                         dev_err(dev,
1984                                 "error: can't request vepu irq %d\n",
1985                                 data->irq_enc);
1986                         goto err;
1987                 }
1988         }
1989         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1990         if (data->irq_dec > 0) {
1991                 ret = devm_request_threaded_irq(dev,
1992                         data->irq_dec, vdpu_irq, vdpu_isr,
1993                         IRQF_SHARED, dev_name(dev),
1994                         (void *)data);
1995                 if (ret) {
1996                         dev_err(dev,
1997                                 "error: can't request vdpu irq %d\n",
1998                                 data->irq_dec);
1999                         goto err;
2000                 }
2001         }
2002         atomic_set(&data->dec_dev.irq_count_codec, 0);
2003         atomic_set(&data->dec_dev.irq_count_pp, 0);
2004         atomic_set(&data->enc_dev.irq_count_codec, 0);
2005         atomic_set(&data->enc_dev.irq_count_pp, 0);
2006 #if defined(CONFIG_VCODEC_MMU)
2007         if (iommu_en) {
2008                 vcodec_enter_mode(data);
2009                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2010                         sprintf(mmu_dev_dts_name,
2011                                 HEVC_IOMMU_COMPATIBLE_NAME);
2012                 else
2013                         sprintf(mmu_dev_dts_name,
2014                                 VPU_IOMMU_COMPATIBLE_NAME);
2015
2016                 data->mmu_dev =
2017                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2018
2019                 if (data->mmu_dev)
2020                         platform_set_sysmmu(data->mmu_dev, dev);
2021
2022                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2023         }
2024 #endif
2025         /* create device node */
2026         ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
2027         if (ret) {
2028                 dev_err(dev, "alloc dev_t failed\n");
2029                 goto err;
2030         }
2031
2032         cdev_init(&data->cdev, &vpu_service_fops);
2033
2034         data->cdev.owner = THIS_MODULE;
2035         data->cdev.ops = &vpu_service_fops;
2036
2037         ret = cdev_add(&data->cdev, data->dev_t, 1);
2038
2039         if (ret) {
2040                 dev_err(dev, "add dev_t failed\n");
2041                 goto err;
2042         }
2043
2044         data->cls = class_create(THIS_MODULE, dev_name(dev));
2045
2046         if (IS_ERR(data->cls)) {
2047                 ret = PTR_ERR(data->cls);
2048                 dev_err(dev, "class_create err:%d\n", ret);
2049                 goto err;
2050         }
2051
2052         data->child_dev = device_create(data->cls, dev,
2053                 data->dev_t, NULL, dev_name(dev));
2054
2055         get_hw_info(data);
2056
2057         platform_set_drvdata(pdev, data);
2058
2059         INIT_LIST_HEAD(&data->lnk_service);
2060         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2061
2062 #ifdef CONFIG_DEBUG_FS
2063         data->debugfs_dir =
2064                 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2065         if (data->debugfs_dir == NULL)
2066                 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2067
2068         data->debugfs_file_regs =
2069                 debugfs_create_file("regs", 0664,
2070                                     data->debugfs_dir, data,
2071                                     &debug_vcodec_fops);
2072 #endif
2073         return 0;
2074 err:
2075         if (data->irq_enc > 0)
2076                 free_irq(data->irq_enc, (void *)data);
2077         if (data->irq_dec > 0)
2078                 free_irq(data->irq_dec, (void *)data);
2079
2080         if (data->child_dev) {
2081                 device_destroy(data->cls, data->dev_t);
2082                 cdev_del(&data->cdev);
2083                 unregister_chrdev_region(data->dev_t, 1);
2084         }
2085
2086         if (data->cls)
2087                 class_destroy(data->cls);
2088         return -1;
2089 }
2090
2091 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2092 {
2093         device_destroy(data->cls, data->dev_t);
2094         class_destroy(data->cls);
2095         cdev_del(&data->cdev);
2096         unregister_chrdev_region(data->dev_t, 1);
2097
2098         free_irq(data->irq_enc, (void *)&data);
2099         free_irq(data->irq_dec, (void *)&data);
2100
2101 #ifdef CONFIG_DEBUG_FS
2102         debugfs_remove(data->debugfs_file_regs);
2103         debugfs_remove(data->debugfs_dir);
2104 #endif
2105 }
2106
2107 static void vcodec_read_property(struct device_node *np,
2108         struct vpu_service_info *pservice)
2109 {
2110         pservice->mode_bit = 0;
2111         pservice->mode_ctrl = 0;
2112         pservice->subcnt = 0;
2113
2114         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2115
2116         if (pservice->subcnt > 1) {
2117                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2118                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2119         }
2120 #ifdef CONFIG_MFD_SYSCON
2121         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2122 #else
2123         pservice->grf_base = (u32*)RK_GRF_VIRT;
2124 #endif
2125         if (IS_ERR(pservice->grf_base)) {
2126                 vpu_err("can't find vpu grf property\n");
2127                 return;
2128         }
2129         of_property_read_string(np, "name", (const char**)&pservice->name);
2130 }
2131
2132 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2133 {
2134         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2135         pservice->curr_mode = -1;
2136
2137         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2138         INIT_LIST_HEAD(&pservice->waiting);
2139         INIT_LIST_HEAD(&pservice->running);
2140         mutex_init(&pservice->lock);
2141
2142         INIT_LIST_HEAD(&pservice->done);
2143         INIT_LIST_HEAD(&pservice->session);
2144         INIT_LIST_HEAD(&pservice->subdev_list);
2145
2146         pservice->reg_pproc     = NULL;
2147         atomic_set(&pservice->total_running, 0);
2148         pservice->enabled = false;
2149
2150         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2151
2152         pservice->ion_client = rockchip_ion_client_create("vpu");
2153         if (IS_ERR(pservice->ion_client)) {
2154                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2155                         PTR_ERR(pservice->ion_client));
2156         } else {
2157                 vpu_debug(3, "vcodec ion client create success!\n");
2158         }
2159 }
2160
2161 static int vcodec_probe(struct platform_device *pdev)
2162 {
2163         int i;
2164         int ret = 0;
2165         struct resource *res = NULL;
2166         struct device *dev = &pdev->dev;
2167         struct device_node *np = pdev->dev.of_node;
2168         struct vpu_service_info *pservice =
2169                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2170
2171         pr_info("probe device %s\n", dev_name(dev));
2172
2173         vcodec_read_property(np, pservice);
2174         vcodec_init_drvdata(pservice);
2175
2176         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2177                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2178         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2179                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2180         else
2181                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2182
2183         pservice->dev = dev;
2184
2185         if (0 > vpu_get_clk(pservice))
2186                 goto err;
2187
2188         vpu_service_power_on(pservice);
2189
2190         if (of_property_read_bool(np, "reg")) {
2191                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2192
2193                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2194                 if (IS_ERR(pservice->reg_base)) {
2195                         vpu_err("ioremap registers base failed\n");
2196                         ret = PTR_ERR(pservice->reg_base);
2197                         goto err;
2198                 }
2199                 pservice->ioaddr = res->start;
2200         } else {
2201                 pservice->reg_base = 0;
2202         }
2203
2204         if (of_property_read_bool(np, "subcnt")) {
2205                 for (i = 0; i<pservice->subcnt; i++) {
2206                         struct device_node *sub_np;
2207                         struct platform_device *sub_pdev;
2208                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2209                         sub_pdev = of_find_device_by_node(sub_np);
2210
2211                         vcodec_subdev_probe(sub_pdev, pservice);
2212                 }
2213         } else {
2214                 vcodec_subdev_probe(pdev, pservice);
2215         }
2216         platform_set_drvdata(pdev, pservice);
2217
2218         vpu_service_power_off(pservice);
2219
2220         pr_info("init success\n");
2221
2222         return 0;
2223
2224 err:
2225         pr_info("init failed\n");
2226         vpu_service_power_off(pservice);
2227         vpu_put_clk(pservice);
2228         wake_lock_destroy(&pservice->wake_lock);
2229
2230         if (res)
2231                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2232
2233         return ret;
2234 }
2235
2236 static int vcodec_remove(struct platform_device *pdev)
2237 {
2238         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2239         struct resource *res;
2240         struct vpu_subdev_data *data, *n;
2241
2242         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2243                 vcodec_subdev_remove(data);
2244         }
2245
2246         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2247         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2248         vpu_put_clk(pservice);
2249         wake_lock_destroy(&pservice->wake_lock);
2250
2251         return 0;
2252 }
2253
2254 #if defined(CONFIG_OF)
2255 static const struct of_device_id vcodec_service_dt_ids[] = {
2256         {.compatible = "vpu_service",},
2257         {.compatible = "rockchip,hevc_service",},
2258         {.compatible = "rockchip,vpu_combo",},
2259         {},
2260 };
2261 #endif
2262
2263 static struct platform_driver vcodec_driver = {
2264         .probe = vcodec_probe,
2265         .remove = vcodec_remove,
2266         .driver = {
2267                 .name = "vcodec",
2268                 .owner = THIS_MODULE,
2269 #if defined(CONFIG_OF)
2270                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2271 #endif
2272         },
2273 };
2274
2275 static void get_hw_info(struct vpu_subdev_data *data)
2276 {
2277         struct vpu_service_info *pservice = data->pservice;
2278         struct vpu_dec_config *dec = &pservice->dec_config;
2279         struct vpu_enc_config *enc = &pservice->enc_config;
2280         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2281                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2282                 u32 asicID      = data->dec_dev.hwregs[0];
2283
2284                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2285                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2286                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2287                         dec->jpegSupport = JPEG_PROGRESSIVE;
2288                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2289                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2290                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2291                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2292                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2293                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2294
2295                 dec->maxDecPicWidth = 4096;
2296
2297                 /* 2nd Config register */
2298                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2299                 if (dec->refBufSupport) {
2300                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2301                                 dec->refBufSupport |= 2;
2302                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2303                                 dec->refBufSupport |= 4;
2304                 }
2305                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2306                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2307                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2308                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2309
2310                 /* JPEG xtensions */
2311                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2312                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2313                 else
2314                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2315
2316                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2317                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2318                 else
2319                         dec->rvSupport = RV_NOT_SUPPORTED;
2320                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2321
2322                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2323                         dec->refBufSupport |= 8; /* enable HW support for offset */
2324
2325                 if (!cpu_is_rk3036()) {
2326                         configReg = data->enc_dev.hwregs[63];
2327                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2328                         enc->h264Enabled = (configReg >> 27) & 1;
2329                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2330                         enc->jpegEnabled = (configReg >> 25) & 1;
2331                         enc->vsEnabled = (configReg >> 24) & 1;
2332                         enc->rgbEnabled = (configReg >> 28) & 1;
2333                         enc->reg_size = data->reg_size;
2334                         enc->reserv[0] = enc->reserv[1] = 0;
2335                 }
2336                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2337                 if (pservice->auto_freq) {
2338                         vpu_debug(3, "vpu_service set to auto frequency mode\n");
2339                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2340                 }
2341
2342                 pservice->bug_dec_addr = cpu_is_rk30xx();
2343         } else {
2344                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2345                         dec->maxDecPicWidth = 1920;
2346                 else
2347                         dec->maxDecPicWidth = 4096;
2348                 /* disable frequency switch in hevc.*/
2349                 pservice->auto_freq = false;
2350         }
2351 }
2352
2353 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2354 {
2355         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2356         struct vpu_service_info *pservice = data->pservice;
2357         vpu_device *dev = &data->dec_dev;
2358         u32 raw_status;
2359         u32 irq_status;
2360
2361         vcodec_enter_mode(data);
2362
2363         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2364
2365         vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2366
2367         if (irq_status & DEC_INTERRUPT_BIT) {
2368                 pr_debug("dec_isr dec %x\n", irq_status);
2369                 if ((irq_status & 0x40001) == 0x40001) {
2370                         do {
2371                                 irq_status =
2372                                         readl(dev->hwregs +
2373                                                 DEC_INTERRUPT_REGISTER);
2374                         } while ((irq_status & 0x40001) == 0x40001);
2375                 }
2376
2377                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2378                 atomic_add(1, &dev->irq_count_codec);
2379         }
2380
2381         if (data->hw_info->hw_id != HEVC_ID) {
2382                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2383                 if (irq_status & PP_INTERRUPT_BIT) {
2384                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2385                         /* clear pp IRQ */
2386                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2387                         atomic_add(1, &dev->irq_count_pp);
2388                 }
2389         }
2390
2391         pservice->irq_status = raw_status;
2392
2393         vcodec_exit_mode(pservice);
2394
2395         return IRQ_WAKE_THREAD;
2396 }
2397
2398 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2399 {
2400         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2401         struct vpu_service_info *pservice = data->pservice;
2402         vpu_device *dev = &data->dec_dev;
2403
2404         mutex_lock(&pservice->lock);
2405         if (atomic_read(&dev->irq_count_codec)) {
2406 #if VPU_SERVICE_SHOW_TIME
2407                 do_gettimeofday(&dec_end);
2408                 vpu_debug(3, "dec task: %ld ms\n",
2409                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2410                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2411 #endif
2412                 atomic_sub(1, &dev->irq_count_codec);
2413                 if (NULL == pservice->reg_codec) {
2414                         vpu_err("error: dec isr with no task waiting\n");
2415                 } else {
2416                         reg_from_run_to_done(data, pservice->reg_codec);
2417                 }
2418         }
2419
2420         if (atomic_read(&dev->irq_count_pp)) {
2421 #if VPU_SERVICE_SHOW_TIME
2422                 do_gettimeofday(&pp_end);
2423                 printk("pp  task: %ld ms\n",
2424                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2425                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2426 #endif
2427                 atomic_sub(1, &dev->irq_count_pp);
2428                 if (NULL == pservice->reg_pproc) {
2429                         vpu_err("error: pp isr with no task waiting\n");
2430                 } else {
2431                         reg_from_run_to_done(data, pservice->reg_pproc);
2432                 }
2433         }
2434         try_set_reg(data);
2435         mutex_unlock(&pservice->lock);
2436         return IRQ_HANDLED;
2437 }
2438
2439 static irqreturn_t vepu_irq(int irq, void *dev_id)
2440 {
2441         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2442         struct vpu_service_info *pservice = data->pservice;
2443         vpu_device *dev = &data->enc_dev;
2444         u32 irq_status;
2445
2446         vcodec_enter_mode(data);
2447         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2448
2449         pr_debug("vepu_irq irq status %x\n", irq_status);
2450
2451 #if VPU_SERVICE_SHOW_TIME
2452         do_gettimeofday(&enc_end);
2453         vpu_debug(3, "enc task: %ld ms\n",
2454                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2455                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2456 #endif
2457         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2458                 /* clear enc IRQ */
2459                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2460                 atomic_add(1, &dev->irq_count_codec);
2461         }
2462
2463         pservice->irq_status = irq_status;
2464
2465         vcodec_exit_mode(pservice);
2466
2467         return IRQ_WAKE_THREAD;
2468 }
2469
2470 static irqreturn_t vepu_isr(int irq, void *dev_id)
2471 {
2472         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2473         struct vpu_service_info *pservice = data->pservice;
2474         vpu_device *dev = &data->enc_dev;
2475
2476         mutex_lock(&pservice->lock);
2477         if (atomic_read(&dev->irq_count_codec)) {
2478                 atomic_sub(1, &dev->irq_count_codec);
2479                 if (NULL == pservice->reg_codec) {
2480                         vpu_err("error: enc isr with no task waiting\n");
2481                 } else {
2482                         reg_from_run_to_done(data, pservice->reg_codec);
2483                 }
2484         }
2485         try_set_reg(data);
2486         mutex_unlock(&pservice->lock);
2487         return IRQ_HANDLED;
2488 }
2489
2490 static int __init vcodec_service_init(void)
2491 {
2492         int ret;
2493
2494         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2495                 vpu_err("Platform device register failed (%d).\n", ret);
2496                 return ret;
2497         }
2498
2499 #ifdef CONFIG_DEBUG_FS
2500         vcodec_debugfs_init();
2501 #endif
2502
2503         return ret;
2504 }
2505
2506 static void __exit vcodec_service_exit(void)
2507 {
2508 #ifdef CONFIG_DEBUG_FS
2509         vcodec_debugfs_exit();
2510 #endif
2511
2512         platform_driver_unregister(&vcodec_driver);
2513 }
2514
2515 module_init(vcodec_service_init);
2516 module_exit(vcodec_service_exit);
2517
2518 #ifdef CONFIG_DEBUG_FS
2519 #include <linux/seq_file.h>
2520
2521 static int vcodec_debugfs_init()
2522 {
2523         parent = debugfs_create_dir("vcodec", NULL);
2524         if (!parent)
2525                 return -1;
2526
2527         return 0;
2528 }
2529
2530 static void vcodec_debugfs_exit()
2531 {
2532         debugfs_remove(parent);
2533 }
2534
2535 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2536 {
2537         return debugfs_create_dir(dirname, parent);
2538 }
2539
2540 static int debug_vcodec_show(struct seq_file *s, void *unused)
2541 {
2542         struct vpu_subdev_data *data = s->private;
2543         struct vpu_service_info *pservice = data->pservice;
2544         unsigned int i, n;
2545         vpu_reg *reg, *reg_tmp;
2546         vpu_session *session, *session_tmp;
2547
2548         mutex_lock(&pservice->lock);
2549         vpu_service_power_on(pservice);
2550         if (data->hw_info->hw_id != HEVC_ID) {
2551                 seq_printf(s, "\nENC Registers:\n");
2552                 n = data->enc_dev.iosize >> 2;
2553                 for (i = 0; i < n; i++)
2554                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2555         }
2556         seq_printf(s, "\nDEC Registers:\n");
2557         n = data->dec_dev.iosize >> 2;
2558         for (i = 0; i < n; i++)
2559                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2560
2561         seq_printf(s, "\nvpu service status:\n");
2562         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2563                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2564                 /*seq_printf(s, "waiting reg set %d\n");*/
2565                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2566                         seq_printf(s, "waiting register set\n");
2567                 }
2568                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2569                         seq_printf(s, "running register set\n");
2570                 }
2571                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2572                         seq_printf(s, "done    register set\n");
2573                 }
2574         }
2575         mutex_unlock(&pservice->lock);
2576
2577         return 0;
2578 }
2579
2580 static int debug_vcodec_open(struct inode *inode, struct file *file)
2581 {
2582         return single_open(file, debug_vcodec_show, inode->i_private);
2583 }
2584
2585 #endif
2586
2587 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2588 #include "hevc_test_inc/pps_00.h"
2589 #include "hevc_test_inc/register_00.h"
2590 #include "hevc_test_inc/rps_00.h"
2591 #include "hevc_test_inc/scaling_list_00.h"
2592 #include "hevc_test_inc/stream_00.h"
2593
2594 #include "hevc_test_inc/pps_01.h"
2595 #include "hevc_test_inc/register_01.h"
2596 #include "hevc_test_inc/rps_01.h"
2597 #include "hevc_test_inc/scaling_list_01.h"
2598 #include "hevc_test_inc/stream_01.h"
2599
2600 #include "hevc_test_inc/cabac.h"
2601
2602 extern struct ion_client *rockchip_ion_client_create(const char * name);
2603
2604 static struct ion_client *ion_client = NULL;
2605 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2606 {
2607         int size = (len+15) & (~15);
2608         struct ion_handle *handle;
2609         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2610
2611         if (ion_client == NULL)
2612                 ion_client = rockchip_ion_client_create("vcodec");
2613
2614         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2615
2616         ptr = ion_map_kernel(ion_client, handle);
2617
2618         ion_phys(ion_client, handle, phy, &size);
2619
2620         memcpy(ptr, tbl, len);
2621
2622         return ptr;
2623 }
2624
2625 u8* get_align_ptr_no_copy(int len, u32 *phy)
2626 {
2627         int size = (len+15) & (~15);
2628         struct ion_handle *handle;
2629         u8 *ptr;
2630
2631         if (ion_client == NULL)
2632                 ion_client = rockchip_ion_client_create("vcodec");
2633
2634         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2635
2636         ptr = ion_map_kernel(ion_client, handle);
2637
2638         ion_phys(ion_client, handle, phy, &size);
2639
2640         return ptr;
2641 }
2642
2643 #define TEST_CNT    2
2644 static int hevc_test_case0(vpu_service_info *pservice)
2645 {
2646         vpu_session session;
2647         vpu_reg *reg;
2648         unsigned long size = 272;//sizeof(register_00); // registers array length
2649         int testidx = 0;
2650         int ret = 0;
2651         u8 *pps_tbl[TEST_CNT];
2652         u8 *register_tbl[TEST_CNT];
2653         u8 *rps_tbl[TEST_CNT];
2654         u8 *scaling_list_tbl[TEST_CNT];
2655         u8 *stream_tbl[TEST_CNT];
2656
2657         int stream_size[2];
2658         int pps_size[2];
2659         int rps_size[2];
2660         int scl_size[2];
2661         int cabac_size[2];
2662
2663         u32 phy_pps;
2664         u32 phy_rps;
2665         u32 phy_scl;
2666         u32 phy_str;
2667         u32 phy_yuv;
2668         u32 phy_ref;
2669         u32 phy_cabac;
2670
2671         volatile u8 *stream_buf;
2672         volatile u8 *pps_buf;
2673         volatile u8 *rps_buf;
2674         volatile u8 *scl_buf;
2675         volatile u8 *yuv_buf;
2676         volatile u8 *cabac_buf;
2677         volatile u8 *ref_buf;
2678
2679         u8 *pps;
2680         u8 *yuv[2];
2681         int i;
2682
2683         pps_tbl[0] = pps_00;
2684         pps_tbl[1] = pps_01;
2685
2686         register_tbl[0] = register_00;
2687         register_tbl[1] = register_01;
2688
2689         rps_tbl[0] = rps_00;
2690         rps_tbl[1] = rps_01;
2691
2692         scaling_list_tbl[0] = scaling_list_00;
2693         scaling_list_tbl[1] = scaling_list_01;
2694
2695         stream_tbl[0] = stream_00;
2696         stream_tbl[1] = stream_01;
2697
2698         stream_size[0] = sizeof(stream_00);
2699         stream_size[1] = sizeof(stream_01);
2700
2701         pps_size[0] = sizeof(pps_00);
2702         pps_size[1] = sizeof(pps_01);
2703
2704         rps_size[0] = sizeof(rps_00);
2705         rps_size[1] = sizeof(rps_01);
2706
2707         scl_size[0] = sizeof(scaling_list_00);
2708         scl_size[1] = sizeof(scaling_list_01);
2709
2710         cabac_size[0] = sizeof(Cabac_table);
2711         cabac_size[1] = sizeof(Cabac_table);
2712
2713         /* create session */
2714         session.pid = current->pid;
2715         session.type = VPU_DEC;
2716         INIT_LIST_HEAD(&session.waiting);
2717         INIT_LIST_HEAD(&session.running);
2718         INIT_LIST_HEAD(&session.done);
2719         INIT_LIST_HEAD(&session.list_session);
2720         init_waitqueue_head(&session.wait);
2721         atomic_set(&session.task_running, 0);
2722         list_add_tail(&session.list_session, &pservice->session);
2723
2724         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2725         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2726
2727         while (testidx < TEST_CNT) {
2728                 /* create registers */
2729                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2730                 if (NULL == reg) {
2731                         vpu_err("error: kmalloc fail in reg_init\n");
2732                         return -1;
2733                 }
2734
2735                 if (size > pservice->reg_size) {
2736                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2737                         size = pservice->reg_size;
2738                 }
2739                 reg->session = &session;
2740                 reg->type = session.type;
2741                 reg->size = size;
2742                 reg->freq = VPU_FREQ_DEFAULT;
2743                 reg->reg = (unsigned long *)&reg[1];
2744                 INIT_LIST_HEAD(&reg->session_link);
2745                 INIT_LIST_HEAD(&reg->status_link);
2746
2747                 /* TODO: stuff registers */
2748                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2749
2750                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2751                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2752                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2753                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2754                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2755
2756                 pps = pps_buf;
2757
2758                 /* TODO: replace reigster address */
2759                 for (i=0; i<64; i++) {
2760                         u32 scaling_offset;
2761                         u32 tmp;
2762
2763                         scaling_offset = (u32)pps[i*80+74];
2764                         scaling_offset += (u32)pps[i*80+75] << 8;
2765                         scaling_offset += (u32)pps[i*80+76] << 16;
2766                         scaling_offset += (u32)pps[i*80+77] << 24;
2767
2768                         tmp = phy_scl + scaling_offset;
2769
2770                         pps[i*80+74] = tmp & 0xff;
2771                         pps[i*80+75] = (tmp >> 8) & 0xff;
2772                         pps[i*80+76] = (tmp >> 16) & 0xff;
2773                         pps[i*80+77] = (tmp >> 24) & 0xff;
2774                 }
2775
2776                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2777                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2778
2779                 reg->reg[1] = 0x21;
2780                 reg->reg[4] = phy_str;
2781                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2782                 reg->reg[6] = phy_cabac;
2783                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2784                 reg->reg[42] = phy_pps;
2785                 reg->reg[43] = phy_rps;
2786                 for (i = 10; i <= 24; i++)
2787                         reg->reg[i] = phy_yuv;
2788
2789                 mutex_lock(pservice->lock);
2790                 list_add_tail(&reg->status_link, &pservice->waiting);
2791                 list_add_tail(&reg->session_link, &session.waiting);
2792                 mutex_unlock(pservice->lock);
2793
2794                 /* stuff hardware */
2795                 try_set_reg(data);
2796
2797                 /* wait for result */
2798                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2799                 if (!list_empty(&session.done)) {
2800                         if (ret < 0)
2801                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2802                         ret = 0;
2803                 } else {
2804                         if (unlikely(ret < 0)) {
2805                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2806                         } else if (0 == ret) {
2807                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2808                                 ret = -ETIMEDOUT;
2809                         }
2810                 }
2811                 if (ret < 0) {
2812                         int task_running = atomic_read(&session.task_running);
2813                         int n;
2814                         mutex_lock(pservice->lock);
2815                         vpu_service_dump(pservice);
2816                         if (task_running) {
2817                                 atomic_set(&session.task_running, 0);
2818                                 atomic_sub(task_running, &pservice->total_running);
2819                                 printk("%d task is running but not return, reset hardware...", task_running);
2820                                 vpu_reset(data);
2821                                 printk("done\n");
2822                         }
2823                         vpu_service_session_clear(pservice, &session);
2824                         mutex_unlock(pservice->lock);
2825
2826                         printk("\nDEC Registers:\n");
2827                         n = data->dec_dev.iosize >> 2;
2828                         for (i=0; i<n; i++)
2829                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2830
2831                         vpu_err("test index %d failed\n", testidx);
2832                         break;
2833                 } else {
2834                         vpu_debug(3, "test index %d success\n", testidx);
2835
2836                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2837
2838                         for (i=0; i<68; i++) {
2839                                 if (i % 4 == 0)
2840                                         printk("%02d: ", i);
2841                                 printk("%08x ", reg->reg[i]);
2842                                 if ((i+1) % 4 == 0)
2843                                         printk("\n");
2844                         }
2845
2846                         testidx++;
2847                 }
2848
2849                 reg_deinit(data, reg);
2850         }
2851
2852         return 0;
2853 }
2854
2855 #endif
2856