arch/arm/mach-rockchip/vcodec_service.c

   1
   2 /* arch/arm/mach-rk29/vpu.c
   3  *
   4  * Copyright (C) 2010 ROCKCHIP, Inc.
   5  * author: chenhengming chm@rock-chips.com
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/fs.h>
  26 #include <linux/ioport.h>
  27 #include <linux/miscdevice.h>
  28 #include <linux/mm.h>
  29 #include <linux/poll.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/sched.h>
  32 #include <linux/slab.h>
  33 #include <linux/wakelock.h>
  34 #include <linux/cdev.h>
  35 #include <linux/of.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/rockchip/cpu.h>
  38 #include <linux/rockchip/cru.h>
  39
  40 #include <asm/cacheflush.h>
  41 #include <linux/uaccess.h>
  42 #include <linux/rockchip/grf.h>
  43
  44 #if defined(CONFIG_ION_ROCKCHIP)
  45 #include <linux/rockchip_ion.h>
  46 #endif
  47
  48 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  49 #define CONFIG_VCODEC_MMU
  50 #endif
  51
  52 #ifdef CONFIG_VCODEC_MMU
  53 #include <linux/rockchip-iovmm.h>
  54 #include <linux/dma-buf.h>
  55 #endif
  56
  57 #ifdef CONFIG_DEBUG_FS
  58 #include <linux/debugfs.h>
  59 #endif
  60
  61 #if defined(CONFIG_ARCH_RK319X)
  62 #include <mach/grf.h>
  63 #endif
  64
  65 #include "vcodec_service.h"
  66
  67 #define HEVC_TEST_ENABLE        0
  68 #define HEVC_SIM_ENABLE         0
  69 #define VCODEC_CLOCK_ENABLE     1
  70
  71 typedef enum {
  72         VPU_DEC_ID_9190         = 0x6731,
  73         VPU_ID_8270             = 0x8270,
  74         VPU_ID_4831             = 0x4831,
  75         HEVC_ID                 = 0x6867,
  76 } VPU_HW_ID;
  77
  78 typedef enum {
  79         VPU_DEC_TYPE_9190       = 0,
  80         VPU_ENC_TYPE_8270       = 0x100,
  81         VPU_ENC_TYPE_4831       ,
  82 } VPU_HW_TYPE_E;
  83
  84 typedef enum VPU_FREQ {
  85         VPU_FREQ_200M,
  86         VPU_FREQ_266M,
  87         VPU_FREQ_300M,
  88         VPU_FREQ_400M,
  89         VPU_FREQ_500M,
  90         VPU_FREQ_600M,
  91         VPU_FREQ_DEFAULT,
  92         VPU_FREQ_BUT,
  93 } VPU_FREQ;
  94
  95 typedef struct {
  96         VPU_HW_ID               hw_id;
  97         unsigned long           hw_addr;
  98         unsigned long           enc_offset;
  99         unsigned long           enc_reg_num;
 100         unsigned long           enc_io_size;
 101         unsigned long           dec_offset;
 102         unsigned long           dec_reg_num;
 103         unsigned long           dec_io_size;
 104 } VPU_HW_INFO_E;
 105
 106 struct extra_info_elem {
 107         u32 index;
 108         u32 offset;
 109 };
 110
 111 #define EXTRA_INFO_MAGIC        0x4C4A46
 112
 113 struct extra_info_for_iommu {
 114         u32 magic;
 115         u32 cnt;
 116         struct extra_info_elem elem[20];
 117 };
 118
 119 #define VPU_SERVICE_SHOW_TIME                   0
 120
 121 #if VPU_SERVICE_SHOW_TIME
 122 static struct timeval enc_start, enc_end;
 123 static struct timeval dec_start, dec_end;
 124 static struct timeval pp_start,  pp_end;
 125 #endif
 126
 127 #define MHZ                                     (1000*1000)
 128
 129 #define REG_NUM_9190_DEC                        (60)
 130 #define REG_NUM_9190_PP                         (41)
 131 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 132
 133 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 134
 135 #define REG_NUM_ENC_8270                        (96)
 136 #define REG_SIZE_ENC_8270                       (0x200)
 137 #define REG_NUM_ENC_4831                        (164)
 138 #define REG_SIZE_ENC_4831                       (0x400)
 139
 140 #define REG_NUM_HEVC_DEC                        (68)
 141
 142 #define SIZE_REG(reg)                           ((reg)*4)
 143
 144 static VPU_HW_INFO_E vpu_hw_set[] = {
 145         [0] = {
 146                 .hw_id          = VPU_ID_8270,
 147                 .hw_addr        = 0,
 148                 .enc_offset     = 0x0,
 149                 .enc_reg_num    = REG_NUM_ENC_8270,
 150                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 151                 .dec_offset     = REG_SIZE_ENC_8270,
 152                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 153                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 154         },
 155         [1] = {
 156                 .hw_id          = VPU_ID_4831,
 157                 .hw_addr        = 0,
 158                 .enc_offset     = 0x0,
 159                 .enc_reg_num    = REG_NUM_ENC_4831,
 160                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 161                 .dec_offset     = REG_SIZE_ENC_4831,
 162                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 163                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 164         },
 165         [2] = {
 166                 .hw_id          = HEVC_ID,
 167                 .hw_addr        = 0,
 168                 .dec_offset     = 0x0,
 169                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 170                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 171         },
 172         [3] = {
 173                 .hw_id          = VPU_DEC_ID_9190,
 174                 .hw_addr        = 0,
 175                 .enc_offset     = 0x0,
 176                 .enc_reg_num    = 0,
 177                 .enc_io_size    = 0,
 178                 .dec_offset     = REG_SIZE_ENC_4831,
 179                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 180                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 181         },
 182
 183 };
 184
 185
 186 #define DEC_INTERRUPT_REGISTER                  1
 187 #define PP_INTERRUPT_REGISTER                   60
 188 #define ENC_INTERRUPT_REGISTER                  1
 189
 190 #define DEC_INTERRUPT_BIT                       0x100
 191 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 192 #define PP_INTERRUPT_BIT                        0x100
 193 #define ENC_INTERRUPT_BIT                       0x1
 194
 195 #define HEVC_DEC_INT_RAW_BIT                    0x200
 196 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 197 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 198 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 199
 200 #define VPU_REG_EN_ENC                          14
 201 #define VPU_REG_ENC_GATE                        2
 202 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 203
 204 #define VPU_REG_EN_DEC                          1
 205 #define VPU_REG_DEC_GATE                        2
 206 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 207 #define VPU_REG_EN_PP                           0
 208 #define VPU_REG_PP_GATE                         1
 209 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 210 #define VPU_REG_EN_DEC_PP                       1
 211 #define VPU_REG_DEC_PP_GATE                     61
 212 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 213
 214 #if defined(CONFIG_VCODEC_MMU)
 215 static u8 addr_tbl_vpu_h264dec[] = {
 216         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 217         25, 26, 27, 28, 29, 40, 41
 218 };
 219
 220 static u8 addr_tbl_vpu_vp8dec[] = {
 221         10, 12, 13, 14, 18, 19, 27, 40
 222 };
 223
 224 static u8 addr_tbl_vpu_vp6dec[] = {
 225         12, 13, 14, 18, 27, 40
 226 };
 227
 228 static u8 addr_tbl_vpu_vc1dec[] = {
 229         12, 13, 14, 15, 16, 17, 27, 41
 230 };
 231
 232 static u8 addr_tbl_vpu_jpegdec[] = {
 233         12, 40, 66, 67
 234 };
 235
 236 static u8 addr_tbl_vpu_defaultdec[] = {
 237         12, 13, 14, 15, 16, 17, 40, 41
 238 };
 239
 240 static u8 addr_tbl_vpu_enc[] = {
 241         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 242 };
 243
 244 static u8 addr_tbl_hevc_dec[] = {
 245         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 246         21, 22, 23, 24, 42, 43
 247 };
 248 #endif
 249
 250 enum VPU_DEC_FMT {
 251         VPU_DEC_FMT_H264,
 252         VPU_DEC_FMT_MPEG4,
 253         VPU_DEC_FMT_H263,
 254         VPU_DEC_FMT_JPEG,
 255         VPU_DEC_FMT_VC1,
 256         VPU_DEC_FMT_MPEG2,
 257         VPU_DEC_FMT_MPEG1,
 258         VPU_DEC_FMT_VP6,
 259         VPU_DEC_FMT_RV,
 260         VPU_DEC_FMT_VP7,
 261         VPU_DEC_FMT_VP8,
 262         VPU_DEC_FMT_AVS,
 263         VPU_DEC_FMT_SVC,
 264         VPU_DEC_FMT_VC2,
 265         VPU_DEC_FMT_MVC,
 266         VPU_DEC_FMT_THEORA,
 267         VPU_DEC_FMT_RES
 268 };
 269
 270 /**
 271  * struct for process session which connect to vpu
 272  *
 273  * @author ChenHengming (2011-5-3)
 274  */
 275 typedef struct vpu_session {
 276         VPU_CLIENT_TYPE         type;
 277         /* a linked list of data so we can access them for debugging */
 278         struct list_head        list_session;
 279         /* a linked list of register data waiting for process */
 280         struct list_head        waiting;
 281         /* a linked list of register data in processing */
 282         struct list_head        running;
 283         /* a linked list of register data processed */
 284         struct list_head        done;
 285         wait_queue_head_t       wait;
 286         pid_t                   pid;
 287         atomic_t                task_running;
 288 } vpu_session;
 289
 290 /**
 291  * struct for process register set
 292  *
 293  * @author ChenHengming (2011-5-4)
 294  */
 295 typedef struct vpu_reg {
 296         VPU_CLIENT_TYPE         type;
 297         VPU_FREQ                freq;
 298         vpu_session             *session;
 299         struct list_head        session_link;           /* link to vpu service session */
 300         struct list_head        status_link;            /* link to register set list */
 301         unsigned long           size;
 302 #if defined(CONFIG_VCODEC_MMU)
 303         struct list_head        mem_region_list;
 304 #endif
 305         unsigned long           *reg;
 306 } vpu_reg;
 307
 308 typedef struct vpu_device {
 309         atomic_t                irq_count_codec;
 310         atomic_t                irq_count_pp;
 311         unsigned long           iobaseaddr;
 312         unsigned int            iosize;
 313         volatile u32            *hwregs;
 314 } vpu_device;
 315
 316 enum vcodec_device_id {
 317         VCODEC_DEVICE_ID_VPU,
 318         VCODEC_DEVICE_ID_HEVC
 319 };
 320
 321 struct vcodec_mem_region {
 322         struct list_head srv_lnk;
 323         struct list_head reg_lnk;
 324         struct list_head session_lnk;
 325         unsigned long iova;     /* virtual address for iommu */
 326         unsigned long len;
 327         struct ion_handle *hdl;
 328 };
 329
 330 typedef struct vpu_service_info {
 331         struct wake_lock        wake_lock;
 332         struct delayed_work     power_off_work;
 333         struct mutex            lock;
 334         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */
 335         struct list_head        running;                /* link to link_reg in struct vpu_reg */
 336         struct list_head        done;                   /* link to link_reg in struct vpu_reg */
 337         struct list_head        session;                /* link to list_session in struct vpu_session */
 338         atomic_t                total_running;
 339         bool                    enabled;
 340         vpu_reg                 *reg_codec;
 341         vpu_reg                 *reg_pproc;
 342         vpu_reg                 *reg_resev;
 343         VPUHwDecConfig_t        dec_config;
 344         VPUHwEncConfig_t        enc_config;
 345         VPU_HW_INFO_E           *hw_info;
 346         unsigned long           reg_size;
 347         bool                    auto_freq;
 348         bool                    bug_dec_addr;
 349         atomic_t                freq_status;
 350
 351         struct clk              *aclk_vcodec;
 352         struct clk              *hclk_vcodec;
 353         struct clk              *clk_core;
 354         struct clk              *clk_cabac;
 355         struct clk              *pd_video;
 356
 357         int                     irq_dec;
 358         int                     irq_enc;
 359
 360         vpu_device              enc_dev;
 361         vpu_device              dec_dev;
 362
 363         struct device           *dev;
 364
 365         struct cdev             cdev;
 366         dev_t                   dev_t;
 367         struct class            *cls;
 368         struct device           *child_dev;
 369
 370         struct dentry           *debugfs_dir;
 371         struct dentry           *debugfs_file_regs;
 372
 373         u32 irq_status;
 374 #if defined(CONFIG_VCODEC_MMU)
 375         struct ion_client       *ion_client;
 376         struct list_head        mem_region_list;
 377         struct device           *mmu_dev;
 378 #endif
 379
 380         enum vcodec_device_id   dev_id;
 381
 382         u32                     reserved_mode;
 383
 384         struct delayed_work     simulate_work;
 385 } vpu_service_info;
 386
 387 struct vcodec_combo {
 388         struct vpu_service_info *vpu_srv;
 389         struct vpu_service_info *hevc_srv;
 390 };
 391
 392 typedef struct vpu_request
 393 {
 394         unsigned long *req;
 395         unsigned long size;
 396 } vpu_request;
 397
 398 /// global variable
 399 //static struct clk *pd_video;
 400 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
 401 /* mutex for selecting operation registers of vpu or hevc */
 402 static struct mutex g_mode_mutex;
 403 static struct vcodec_combo g_combo;
 404
 405 #ifdef CONFIG_DEBUG_FS
 406 static int vcodec_debugfs_init(void);
 407 static void vcodec_debugfs_exit(void);
 408 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 409 static int debug_vcodec_open(struct inode *inode, struct file *file);
 410
 411 static const struct file_operations debug_vcodec_fops = {
 412         .open = debug_vcodec_open,
 413         .read = seq_read,
 414         .llseek = seq_lseek,
 415         .release = single_release,
 416 };
 417 #endif
 418
 419 #define VDPU_SOFT_RESET_REG     101
 420 #define VDPU_CLEAR_CACHE_REG    516
 421 #define VEPU_CLEAR_CACHE_REG    772
 422 #define HEVC_CLEAR_CACHE_REG    260
 423
 424 #define VPU_REG_ENABLE(base, reg)       do { \
 425                                                 base[reg] = 1; \
 426                                         } while (0)
 427
 428 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 429 #define VDPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAR_CACHE_REG)
 430 #define VEPU_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAR_CACHE_REG)
 431 #define HEVC_CLEAR_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAR_CACHE_REG)
 432
 433 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 434 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 435 #define VPU_SIMULATE_DELAY              msecs_to_jiffies(15)
 436
 437 #define BIT_VCODEC_SEL_RK3036           (1<<3)
 438 #define BIT_VCODEC_SEL_RK312X           (1<<15)
 439 static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)
 440 {
 441         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 442                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 443                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 444                 if (reserved_mode)
 445                         *reserved_mode = readl_relaxed(addr);
 446                 if (id == VCODEC_DEVICE_ID_HEVC)
 447                         writel_relaxed(readl_relaxed(addr) | (bits) | (bits << 16), addr);
 448                 else
 449                         writel_relaxed((readl_relaxed(addr) & (~bits)) | (bits << 16), addr);
 450         }
 451 }
 452
 453 static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)
 454 {
 455         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 456                 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
 457                 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 458                 writel_relaxed(reserved_mode | (bits << 16), addr);
 459         }
 460 }
 461
 462 static void vcodec_enter_mode(enum vcodec_device_id id)
 463 {
 464         if (cpu_is_rk3036() || cpu_is_rk312x())
 465                 mutex_lock(&g_mode_mutex);
 466         vcodec_enter_mode_nolock(id, NULL);
 467 }
 468
 469 static void vcodec_exit_mode(void)
 470 {
 471         if (cpu_is_rk3036() || cpu_is_rk312x())
 472                 mutex_unlock(&g_mode_mutex);
 473 }
 474
 475 static int vpu_get_clk(struct vpu_service_info *pservice)
 476 {
 477 #if VCODEC_CLOCK_ENABLE
 478         do {
 479                 pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");
 480                 if (IS_ERR(pservice->aclk_vcodec)) {
 481                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 482                         break;
 483                 }
 484
 485                 pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");
 486                 if (IS_ERR(pservice->hclk_vcodec)) {
 487                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 488                         break;
 489                 }
 490
 491                 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 492                         pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 493                         if (IS_ERR(pservice->clk_core)) {
 494                                 dev_err(pservice->dev, "failed on clk_get clk_core\n");
 495                                 break;
 496                         }
 497
 498                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 499                                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 500                                 if (IS_ERR(pservice->clk_cabac)) {
 501                                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 502                                         break;
 503                                 }
 504                         } else {
 505                                 pservice->clk_cabac = NULL;
 506                         }
 507
 508                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 509                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 510                                 if (IS_ERR(pservice->pd_video)) {
 511                                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 512                                         break;
 513                                 }
 514                         } else {
 515                                 pservice->pd_video = NULL;
 516                         }
 517                 } else {
 518                         if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
 519                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 520                                 if (IS_ERR(pservice->pd_video)) {
 521                                         dev_err(pservice->dev, "failed on clk_get pd_video\n");
 522                                         break;
 523                                 }
 524                         } else {
 525                                 pservice->pd_video = NULL;
 526                         }
 527                 }
 528
 529                 if (cpu_is_rk312x()) {
 530                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 531                         if (IS_ERR(pservice->pd_video)) {
 532                                 dev_err(pservice->dev, "failed on clk_get pd_video\n");
 533                                 break;
 534                         }
 535                 }
 536
 537                 return 0;
 538         } while (0);
 539
 540         return -1;
 541 #else
 542         return 0;
 543 #endif
 544 }
 545
 546 static void vpu_put_clk(struct vpu_service_info *pservice)
 547 {
 548 #if VCODEC_CLOCK_ENABLE
 549         if (pservice->pd_video) {
 550                 devm_clk_put(pservice->dev, pservice->pd_video);
 551         }
 552
 553         if (pservice->aclk_vcodec) {
 554                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 555         }
 556
 557         if (pservice->hclk_vcodec) {
 558                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 559         }
 560
 561         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 562                 if (pservice->clk_core) {
 563                         devm_clk_put(pservice->dev, pservice->clk_core);
 564                 }
 565
 566                 if (pservice->clk_cabac) {
 567                         devm_clk_put(pservice->dev, pservice->clk_cabac);
 568                 }
 569         }
 570 #endif
 571 }
 572
 573 static void vpu_reset(struct vpu_service_info *pservice)
 574 {
 575 #if defined(CONFIG_ARCH_RK29)
 576         clk_disable(aclk_ddr_vepu);
 577         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 578         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 579         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 580         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 581         mdelay(10);
 582         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 583         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 584         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 585         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 586         clk_enable(aclk_ddr_vepu);
 587 #elif defined(CONFIG_ARCH_RK30)
 588         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 589         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 590         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 591         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 592         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 593         mdelay(1);
 594         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 595         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 596         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 597         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 598         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 599 #endif
 600
 601         pservice->reg_codec = NULL;
 602         pservice->reg_pproc = NULL;
 603         pservice->reg_resev = NULL;
 604 }
 605
 606 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
 607 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
 608 {
 609         vpu_reg *reg, *n;
 610         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 611                 reg_deinit(pservice, reg);
 612         }
 613         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 614                 reg_deinit(pservice, reg);
 615         }
 616         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 617                 reg_deinit(pservice, reg);
 618         }
 619 }
 620
 621 static void vpu_service_dump(struct vpu_service_info *pservice)
 622 {
 623         int running;
 624         vpu_reg *reg, *reg_tmp;
 625         vpu_session *session, *session_tmp;
 626
 627         running = atomic_read(&pservice->total_running);
 628         printk("total_running %d\n", running);
 629
 630         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);
 631         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
 632         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
 633
 634         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
 635                 printk("session pid %d type %d:\n", session->pid, session->type);
 636                 running = atomic_read(&session->task_running);
 637                 printk("task_running %d\n", running);
 638                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
 639                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);
 640                 }
 641                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
 642                         printk("running register set 0x%.8x\n", (unsigned int)reg);
 643                 }
 644                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
 645                         printk("done    register set 0x%.8x\n", (unsigned int)reg);
 646                 }
 647         }
 648 }
 649
 650 static void vpu_service_power_off(struct vpu_service_info *pservice)
 651 {
 652         int total_running;
 653         if (!pservice->enabled)
 654                 return;
 655
 656         pservice->enabled = false;
 657         total_running = atomic_read(&pservice->total_running);
 658         if (total_running) {
 659                 pr_alert("alert: power off when %d task running!!\n", total_running);
 660                 mdelay(50);
 661                 pr_alert("alert: delay 50 ms for running task\n");
 662                 vpu_service_dump(pservice);
 663         }
 664
 665         pr_info("%s: power off...", dev_name(pservice->dev));
 666         udelay(10);
 667
 668 #if defined(CONFIG_VCODEC_MMU)
 669         if (pservice->mmu_dev) {
 670                 vcodec_enter_mode(pservice->dev_id);
 671                 rockchip_iovmm_deactivate(pservice->dev);
 672                 vcodec_exit_mode();
 673         }
 674 #endif
 675
 676 #if VCODEC_CLOCK_ENABLE
 677         if (pservice->pd_video)
 678                 clk_disable_unprepare(pservice->pd_video);
 679         if (pservice->hclk_vcodec)
 680                 clk_disable_unprepare(pservice->hclk_vcodec);
 681         if (pservice->aclk_vcodec)
 682                 clk_disable_unprepare(pservice->aclk_vcodec);
 683         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 684                 if (pservice->clk_core)
 685                         clk_disable_unprepare(pservice->clk_core);
 686                 if (pservice->clk_cabac)
 687                         clk_disable_unprepare(pservice->clk_cabac);
 688         }
 689 #endif
 690
 691         wake_unlock(&pservice->wake_lock);
 692         pr_info("done\n");
 693 }
 694
 695 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 696 {
 697         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 698 }
 699
 700 static void vpu_power_off_work(struct work_struct *work_s)
 701 {
 702         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 703         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 704
 705         if (mutex_trylock(&pservice->lock)) {
 706                 vpu_service_power_off(pservice);
 707                 mutex_unlock(&pservice->lock);
 708         } else {
 709                 /* Come back later if the device is busy... */
 710                 vpu_queue_power_off_work(pservice);
 711         }
 712 }
 713
 714 static void vpu_service_power_on(struct vpu_service_info *pservice)
 715 {
 716         static ktime_t last;
 717         ktime_t now = ktime_get();
 718         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 719                 cancel_delayed_work_sync(&pservice->power_off_work);
 720                 vpu_queue_power_off_work(pservice);
 721                 last = now;
 722         }
 723
 724         if (pservice->enabled)
 725                 return ;
 726
 727         pservice->enabled = true;
 728         printk("%s: power on\n", dev_name(pservice->dev));
 729
 730         if (cpu_is_rk3036() || cpu_is_rk312x()) {
 731                 if (pservice == g_combo.vpu_srv) {
 732                         if (g_combo.hevc_srv != NULL && g_combo.hevc_srv->mmu_dev) {
 733                                 u32 config;
 734                                 vcodec_enter_mode_nolock(g_combo.hevc_srv->dev_id, &config);
 735                                 rockchip_iovmm_deactivate(g_combo.hevc_srv->dev);
 736                                 vcodec_exit_mode_nolock(g_combo.hevc_srv->dev_id, config);
 737                         }
 738                 } else if (pservice == g_combo.hevc_srv) {
 739                         if (g_combo.vpu_srv != NULL && g_combo.vpu_srv->mmu_dev) {
 740                                 u32 config;
 741                                 vcodec_enter_mode_nolock(g_combo.vpu_srv->dev_id, &config);
 742                                 rockchip_iovmm_deactivate(g_combo.vpu_srv->dev);
 743                                 vcodec_exit_mode_nolock(g_combo.vpu_srv->dev_id, config);
 744                         }
 745                 }
 746         }
 747
 748 #if VCODEC_CLOCK_ENABLE
 749         if (pservice->aclk_vcodec)
 750                 clk_prepare_enable(pservice->aclk_vcodec);
 751
 752         if (pservice->hclk_vcodec)
 753                 clk_prepare_enable(pservice->hclk_vcodec);
 754
 755         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
 756                 if (pservice->clk_core)
 757                         clk_prepare_enable(pservice->clk_core);
 758         if (pservice->clk_cabac)
 759                 clk_prepare_enable(pservice->clk_cabac);
 760         }
 761
 762         if (pservice->pd_video)
 763                 clk_prepare_enable(pservice->pd_video);
 764 #endif
 765
 766 #if defined(CONFIG_ARCH_RK319X)
 767         /// select aclk_vepu as vcodec clock source.
 768 #define BIT_VCODEC_SEL  (1<<7)
 769         writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |
 770                 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
 771                 RK319X_GRF_BASE + GRF_SOC_CON1);
 772 #endif
 773 #define BIT_VCODEC_CLK_SEL      (1<<10)
 774         if (cpu_is_rk312x())
 775                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 776                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 777                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 778
 779         udelay(10);
 780         wake_lock(&pservice->wake_lock);
 781
 782 #if defined(CONFIG_VCODEC_MMU)
 783         if (pservice->mmu_dev) {
 784                 vcodec_enter_mode(pservice->dev_id);
 785                 rockchip_iovmm_activate(pservice->dev);
 786                 vcodec_exit_mode();
 787         }
 788 #endif
 789 }
 790
 791 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 792 {
 793         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
 794         return ((type == 8) || (type == 4));
 795 }
 796
 797 static inline bool reg_check_interlace(vpu_reg *reg)
 798 {
 799         unsigned long type = (reg->reg[3] & (1 << 23));
 800         return (type > 0);
 801 }
 802
 803 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 804 {
 805         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 806         return type;
 807 }
 808
 809 static inline int reg_probe_width(vpu_reg *reg)
 810 {
 811         int width_in_mb = reg->reg[4] >> 23;
 812         return width_in_mb * 16;
 813 }
 814
 815 #if defined(CONFIG_VCODEC_MMU)
 816 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl,
 817                                 int size, vpu_reg *reg,
 818                                 struct extra_info_for_iommu *ext_inf)
 819 {
 820         int i;
 821         int usr_fd = 0;
 822         int offset = 0;
 823
 824         if (tbl == NULL || size <= 0) {
 825                 dev_err(pservice->dev, "input arguments invalidate\n");
 826                 return -1;
 827         }
 828
 829         vpu_service_power_on(pservice);
 830
 831         for (i = 0; i < size; i++) {
 832                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 833
 834                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&
 835                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 836                         /* special for vpu dec num 41 regitster */
 837                         offset = reg->reg[tbl[i]] >> 10 << 4;
 838                 else
 839                         offset = reg->reg[tbl[i]] >> 10;
 840
 841                 if (usr_fd != 0) {
 842                         struct ion_handle *hdl;
 843                         int ret = 0;
 844                         struct vcodec_mem_region *mem_region;
 845
 846                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 847                         if (IS_ERR(hdl)) {
 848                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 849                                 return PTR_ERR(hdl);
 850                         }
 851
 852                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 853
 854                         if (mem_region == NULL) {
 855                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 856                                 ion_free(pservice->ion_client, hdl);
 857                                 return -1;
 858                         }
 859
 860                         mem_region->hdl = hdl;
 861                         vcodec_enter_mode(pservice->dev_id);
 862                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);
 863                         vcodec_exit_mode();
 864
 865                         if (ret < 0) {
 866                                 dev_err(pservice->dev, "ion map iommu failed\n");
 867                                 kfree(mem_region);
 868                                 ion_free(pservice->ion_client, hdl);
 869                                 return ret;
 870                         }
 871                         reg->reg[tbl[i]] = mem_region->iova + offset;
 872                         INIT_LIST_HEAD(&mem_region->reg_lnk);
 873                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 874                 }
 875         }
 876
 877         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
 878                 for (i=0; i<ext_inf->cnt; i++) {
 879                         pr_info("reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);
 880                         reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;
 881                 }
 882         }
 883
 884         return 0;
 885 }
 886
 887 static int vcodec_reg_address_translate(struct vpu_service_info *pservice,
 888                                         vpu_reg *reg,
 889                                         struct extra_info_for_iommu *ext_inf)
 890 {
 891         VPU_HW_ID hw_id;
 892         u8 *tbl;
 893         int size = 0;
 894
 895         hw_id = pservice->hw_info->hw_id;
 896
 897         if (hw_id == HEVC_ID) {
 898                 tbl = addr_tbl_hevc_dec;
 899                 size = sizeof(addr_tbl_hevc_dec);
 900         } else {
 901                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
 902                         switch (reg_check_fmt(reg)) {
 903                         case VPU_DEC_FMT_H264:
 904                                 {
 905                                         tbl = addr_tbl_vpu_h264dec;
 906                                         size = sizeof(addr_tbl_vpu_h264dec);
 907                                         break;
 908                                 }
 909                         case VPU_DEC_FMT_VP8:
 910                         case VPU_DEC_FMT_VP7:
 911                                 {
 912                                         tbl = addr_tbl_vpu_vp8dec;
 913                                         size = sizeof(addr_tbl_vpu_vp8dec);
 914                                         break;
 915                                 }
 916
 917                         case VPU_DEC_FMT_VP6:
 918                                 {
 919                                         tbl = addr_tbl_vpu_vp6dec;
 920                                         size = sizeof(addr_tbl_vpu_vp6dec);
 921                                         break;
 922                                 }
 923                         case VPU_DEC_FMT_VC1:
 924                                 {
 925                                         tbl = addr_tbl_vpu_vc1dec;
 926                                         size = sizeof(addr_tbl_vpu_vc1dec);
 927                                         break;
 928                                 }
 929
 930                         case VPU_DEC_FMT_JPEG:
 931                                 {
 932                                         tbl = addr_tbl_vpu_jpegdec;
 933                                         size = sizeof(addr_tbl_vpu_jpegdec);
 934                                         break;
 935                                 }
 936                         default:
 937                                 tbl = addr_tbl_vpu_defaultdec;
 938                                 size = sizeof(addr_tbl_vpu_defaultdec);
 939                                 break;
 940                         }
 941                 } else if (reg->type == VPU_ENC) {
 942                         tbl = addr_tbl_vpu_enc;
 943                         size = sizeof(addr_tbl_vpu_enc);
 944                 }
 945         }
 946
 947         if (size != 0) {
 948                 return vcodec_bufid_to_iova(pservice, tbl, size, reg, ext_inf);
 949         } else {
 950                 return -1;
 951         }
 952 }
 953 #endif
 954
 955 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
 956 {
 957         int extra_size = 0;
 958         struct extra_info_for_iommu extra_info;
 959         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
 960         if (NULL == reg) {
 961                 pr_err("error: kmalloc fail in reg_init\n");
 962                 return NULL;
 963         }
 964
 965         if (size > pservice->reg_size) {
 966                 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
 967                 size = pservice->reg_size;*/
 968                 extra_size = size - pservice->reg_size;
 969                 size = pservice->reg_size;
 970         }
 971         reg->session = session;
 972         reg->type = session->type;
 973         reg->size = size;
 974         reg->freq = VPU_FREQ_DEFAULT;
 975         reg->reg = (unsigned long *)&reg[1];
 976         INIT_LIST_HEAD(&reg->session_link);
 977         INIT_LIST_HEAD(&reg->status_link);
 978
 979 #if defined(CONFIG_VCODEC_MMU)
 980         if (pservice->mmu_dev)
 981                 INIT_LIST_HEAD(&reg->mem_region_list);
 982 #endif
 983
 984         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
 985                 pr_err("error: copy_from_user failed in reg_init\n");
 986                 kfree(reg);
 987                 return NULL;
 988         }
 989
 990         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
 991                 pr_err("error: copy_from_user failed in reg_init\n");
 992                 kfree(reg);
 993                 return NULL;
 994         }
 995
 996 #if defined(CONFIG_VCODEC_MMU)
 997         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg, &extra_info)) {
 998                 pr_err("error: translate reg address failed\n");
 999                 kfree(reg);
1000                 return NULL;
1001         }
1002 #endif
1003
1004         mutex_lock(&pservice->lock);
1005         list_add_tail(&reg->status_link, &pservice->waiting);
1006         list_add_tail(&reg->session_link, &session->waiting);
1007         mutex_unlock(&pservice->lock);
1008
1009         if (pservice->auto_freq) {
1010                 if (!soc_is_rk2928g()) {
1011                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1012                                 if (reg_check_rmvb_wmv(reg)) {
1013                                         reg->freq = VPU_FREQ_200M;
1014                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1015                                         if (reg_probe_width(reg) > 3200) {
1016                                                 // raise frequency for 4k avc.
1017                                                 reg->freq = VPU_FREQ_500M;
1018                                         }
1019                                 } else {
1020                                         if (reg_check_interlace(reg)) {
1021                                                 reg->freq = VPU_FREQ_400M;
1022                                         }
1023                                 }
1024                         }
1025                         if (reg->type == VPU_PP) {
1026                                 reg->freq = VPU_FREQ_400M;
1027                         }
1028                 }
1029         }
1030
1031         /*reg->reg[2] &= (~0x800000L);*/
1032
1033         return reg;
1034 }
1035
1036 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
1037 {
1038 #if defined(CONFIG_VCODEC_MMU)
1039         struct vcodec_mem_region *mem_region = NULL, *n;
1040 #endif
1041
1042         list_del_init(&reg->session_link);
1043         list_del_init(&reg->status_link);
1044         if (reg == pservice->reg_codec)
1045                 pservice->reg_codec = NULL;
1046         if (reg == pservice->reg_pproc)
1047                 pservice->reg_pproc = NULL;
1048
1049 #if defined(CONFIG_VCODEC_MMU)
1050         // release memory region attach to this registers table.
1051         if (pservice->mmu_dev) {
1052                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {
1053                         /* do not unmap iommu manually,
1054                            unmap will proccess when memory release */
1055                         vcodec_enter_mode(pservice->dev_id);
1056                         /*ion_unmap_iommu(pservice->dev,
1057                                         pservice->ion_client,
1058                                         mem_region->hdl);*/
1059                         vcodec_exit_mode();
1060                         ion_free(pservice->ion_client, mem_region->hdl);
1061                         list_del_init(&mem_region->reg_lnk);
1062                         kfree(mem_region);
1063                 }
1064         }
1065 #endif
1066
1067         kfree(reg);
1068 }
1069
1070 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1071 {
1072         list_del_init(&reg->status_link);
1073         list_add_tail(&reg->status_link, &pservice->running);
1074
1075         list_del_init(&reg->session_link);
1076         list_add_tail(&reg->session_link, &reg->session->running);
1077 }
1078
1079 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1080 {
1081         int i;
1082         u32 *dst = (u32 *)&reg->reg[0];
1083
1084         for (i = 0; i < count; i++)
1085                 *dst++ = *src++;
1086 }
1087
1088 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
1089 {
1090         int irq_reg = -1;
1091         list_del_init(&reg->status_link);
1092         list_add_tail(&reg->status_link, &pservice->done);
1093
1094         list_del_init(&reg->session_link);
1095         list_add_tail(&reg->session_link, &reg->session->done);
1096
1097         vcodec_enter_mode(pservice->dev_id);
1098         switch (reg->type) {
1099         case VPU_ENC : {
1100                 pservice->reg_codec = NULL;
1101                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
1102                 irq_reg = ENC_INTERRUPT_REGISTER;
1103                 break;
1104         }
1105         case VPU_DEC : {
1106                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1107                 pservice->reg_codec = NULL;
1108                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);
1109                 irq_reg = DEC_INTERRUPT_REGISTER;
1110                 break;
1111         }
1112         case VPU_PP : {
1113                 pservice->reg_pproc = NULL;
1114                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1115                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1116                 break;
1117         }
1118         case VPU_DEC_PP : {
1119                 pservice->reg_codec = NULL;
1120                 pservice->reg_pproc = NULL;
1121                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1122                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1123                 break;
1124         }
1125         default : {
1126                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
1127                 break;
1128         }
1129         }
1130         vcodec_exit_mode();
1131
1132         if (irq_reg != -1) {
1133                 reg->reg[irq_reg] = pservice->irq_status;
1134         }
1135
1136         atomic_sub(1, &reg->session->task_running);
1137         atomic_sub(1, &pservice->total_running);
1138         wake_up(&reg->session->wait);
1139 }
1140
1141 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1142 {
1143         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1144         if (curr == reg->freq) {
1145                 return ;
1146         }
1147         atomic_set(&pservice->freq_status, reg->freq);
1148         switch (reg->freq) {
1149         case VPU_FREQ_200M : {
1150                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1151                 //printk("default: 200M\n");
1152         } break;
1153         case VPU_FREQ_266M : {
1154                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1155                 //printk("default: 266M\n");
1156         } break;
1157         case VPU_FREQ_300M : {
1158                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1159                 //printk("default: 300M\n");
1160         } break;
1161         case VPU_FREQ_400M : {
1162                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1163                 //printk("default: 400M\n");
1164         } break;
1165         case VPU_FREQ_500M : {
1166                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1167         } break;
1168         case VPU_FREQ_600M : {
1169                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1170         } break;
1171         default : {
1172                 if (soc_is_rk2928g()) {
1173                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1174                 } else {
1175                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1176                 }
1177                 //printk("default: 300M\n");
1178         } break;
1179         }
1180 }
1181
1182 #if HEVC_SIM_ENABLE
1183 static void simulate_start(struct vpu_service_info *pservice);
1184 #endif
1185 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
1186 {
1187         int i;
1188         u32 *src = (u32 *)&reg->reg[0];
1189         atomic_add(1, &pservice->total_running);
1190         atomic_add(1, &reg->session->task_running);
1191         if (pservice->auto_freq) {
1192                 vpu_service_set_freq(pservice, reg);
1193         }
1194
1195         vcodec_enter_mode(pservice->dev_id);
1196
1197         switch (reg->type) {
1198         case VPU_ENC : {
1199                 int enc_count = pservice->hw_info->enc_reg_num;
1200                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
1201
1202                 pservice->reg_codec = reg;
1203
1204                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1205
1206                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1207                         dst[i] = src[i];
1208
1209                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1210                         dst[i] = src[i];
1211
1212                 VEPU_CLEAR_CACHE(dst);
1213
1214                 dsb();
1215
1216                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1217                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1218
1219 #if VPU_SERVICE_SHOW_TIME
1220                 do_gettimeofday(&enc_start);
1221 #endif
1222
1223         } break;
1224         case VPU_DEC : {
1225                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1226
1227                 pservice->reg_codec = reg;
1228
1229                 if (pservice->hw_info->hw_id != HEVC_ID) {
1230                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1231                                 dst[i] = src[i];
1232                         VDPU_CLEAR_CACHE(dst);
1233                 } else {
1234                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1235                                 dst[i] = src[i];
1236                         HEVC_CLEAR_CACHE(dst);
1237                 }
1238
1239                 dsb();
1240
1241                 if (pservice->hw_info->hw_id != HEVC_ID) {
1242                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1243                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];
1244                 } else {
1245                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1246                 }
1247
1248                 dsb();
1249                 dmb();
1250
1251 #if VPU_SERVICE_SHOW_TIME
1252                 do_gettimeofday(&dec_start);
1253 #endif
1254
1255         } break;
1256         case VPU_PP : {
1257                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1258                 pservice->reg_pproc = reg;
1259
1260                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1261
1262                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1263                         dst[i] = src[i];
1264
1265                 dsb();
1266
1267                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1268
1269 #if VPU_SERVICE_SHOW_TIME
1270                 do_gettimeofday(&pp_start);
1271 #endif
1272
1273         } break;
1274         case VPU_DEC_PP : {
1275                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1276                 pservice->reg_codec = reg;
1277                 pservice->reg_pproc = reg;
1278
1279                 VDPU_SOFT_RESET(dst);
1280                 VDPU_CLEAR_CACHE(dst);
1281
1282                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1283                         dst[i] = src[i];
1284
1285                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1286                 dsb();
1287
1288                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1289                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1290                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1291
1292 #if VPU_SERVICE_SHOW_TIME
1293                 do_gettimeofday(&dec_start);
1294 #endif
1295
1296         } break;
1297         default : {
1298                 pr_err("error: unsupport session type %d", reg->type);
1299                 atomic_sub(1, &pservice->total_running);
1300                 atomic_sub(1, &reg->session->task_running);
1301                 break;
1302         }
1303         }
1304
1305         vcodec_exit_mode();
1306
1307 #if HEVC_SIM_ENABLE
1308         if (pservice->hw_info->hw_id == HEVC_ID) {
1309                 simulate_start(pservice);
1310         }
1311 #endif
1312 }
1313
1314 static void try_set_reg(struct vpu_service_info *pservice)
1315 {
1316         // first get reg from reg list
1317         if (!list_empty(&pservice->waiting)) {
1318                 int can_set = 0;
1319                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1320
1321                 vpu_service_power_on(pservice);
1322
1323                 switch (reg->type) {
1324                 case VPU_ENC : {
1325                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1326                                 can_set = 1;
1327                 } break;
1328                 case VPU_DEC : {
1329                         if (NULL == pservice->reg_codec)
1330                                 can_set = 1;
1331                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
1332                                 can_set = 0;
1333                         }
1334                 } break;
1335                 case VPU_PP : {
1336                         if (NULL == pservice->reg_codec) {
1337                                 if (NULL == pservice->reg_pproc)
1338                                         can_set = 1;
1339                         } else {
1340                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1341                                         can_set = 1;
1342                                 // can not charge frequency when vpu is working
1343                                 if (pservice->auto_freq) {
1344                                         can_set = 0;
1345                                 }
1346                         }
1347                 } break;
1348                 case VPU_DEC_PP : {
1349                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1350                                 can_set = 1;
1351                         } break;
1352                 default : {
1353                         printk("undefined reg type %d\n", reg->type);
1354                 } break;
1355                 }
1356                 if (can_set) {
1357                         reg_from_wait_to_run(pservice, reg);
1358                         reg_copy_to_hw(pservice, reg);
1359                 }
1360         }
1361 }
1362
1363 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
1364 {
1365         int ret = 0;
1366         switch (reg->type) {
1367         case VPU_ENC : {
1368                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))
1369                         ret = -EFAULT;
1370                 break;
1371         }
1372         case VPU_DEC : {
1373                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1374                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1375                         ret = -EFAULT;
1376                 break;
1377         }
1378         case VPU_PP : {
1379                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1380                         ret = -EFAULT;
1381                 break;
1382         }
1383         case VPU_DEC_PP : {
1384                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1385                         ret = -EFAULT;
1386                 break;
1387         }
1388         default : {
1389                 ret = -EFAULT;
1390                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
1391                 break;
1392         }
1393         }
1394         reg_deinit(pservice, reg);
1395         return ret;
1396 }
1397
1398 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1399 {
1400     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
1401         vpu_session *session = (vpu_session *)filp->private_data;
1402         if (NULL == session) {
1403                 return -EINVAL;
1404         }
1405
1406         switch (cmd) {
1407         case VPU_IOC_SET_CLIENT_TYPE : {
1408                 session->type = (VPU_CLIENT_TYPE)arg;
1409                 break;
1410         }
1411         case VPU_IOC_GET_HW_FUSE_STATUS : {
1412                 vpu_request req;
1413                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1414                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1415                         return -EFAULT;
1416                 } else {
1417                         if (VPU_ENC != session->type) {
1418                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
1419                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1420                                         return -EFAULT;
1421                                 }
1422                         } else {
1423                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
1424                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1425                                         return -EFAULT;
1426                                 }
1427                         }
1428                 }
1429
1430                 break;
1431         }
1432         case VPU_IOC_SET_REG : {
1433                 vpu_request req;
1434                 vpu_reg *reg;
1435                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1436                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1437                         return -EFAULT;
1438                 }
1439                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
1440                 if (NULL == reg) {
1441                         return -EFAULT;
1442                 } else {
1443                         mutex_lock(&pservice->lock);
1444                         try_set_reg(pservice);
1445                         mutex_unlock(&pservice->lock);
1446                 }
1447
1448                 break;
1449         }
1450         case VPU_IOC_GET_REG : {
1451                 vpu_request req;
1452                 vpu_reg *reg;
1453                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1454                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1455                         return -EFAULT;
1456                 } else {
1457                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1458                         if (!list_empty(&session->done)) {
1459                                 if (ret < 0) {
1460                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1461                                 }
1462                                 ret = 0;
1463                         } else {
1464                                 if (unlikely(ret < 0)) {
1465                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
1466                                 } else if (0 == ret) {
1467                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1468                                         ret = -ETIMEDOUT;
1469                                 }
1470                         }
1471                         if (ret < 0) {
1472                                 int task_running = atomic_read(&session->task_running);
1473                                 mutex_lock(&pservice->lock);
1474                                 vpu_service_dump(pservice);
1475                                 if (task_running) {
1476                                         atomic_set(&session->task_running, 0);
1477                                         atomic_sub(task_running, &pservice->total_running);
1478                                         printk("%d task is running but not return, reset hardware...", task_running);
1479                                         vpu_reset(pservice);
1480                                         printk("done\n");
1481                                 }
1482                                 vpu_service_session_clear(pservice, session);
1483                                 mutex_unlock(&pservice->lock);
1484                                 return ret;
1485                         }
1486                 }
1487                 mutex_lock(&pservice->lock);
1488                 reg = list_entry(session->done.next, vpu_reg, session_link);
1489                 return_reg(pservice, reg, (u32 __user *)req.req);
1490                 mutex_unlock(&pservice->lock);
1491                 break;
1492         }
1493         case VPU_IOC_PROBE_IOMMU_STATUS: {
1494                 int iommu_enable = 0;
1495
1496 #if defined(CONFIG_VCODEC_MMU)
1497                 iommu_enable = pservice->mmu_dev ? 1 : 0;
1498 #endif
1499
1500                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1501                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1502                         return -EFAULT;
1503                 }
1504                 break;
1505         }
1506         default : {
1507                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1508                 break;
1509         }
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
1516 {
1517         int ret = -EINVAL, i = 0;
1518         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1519         u32 enc_id = *tmp;
1520
1521 #if HEVC_SIM_ENABLE
1522         /// temporary, hevc driver test.
1523         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
1524                 p->hw_info = &vpu_hw_set[2];
1525                 return 0;
1526         }
1527 #endif
1528         enc_id = (enc_id >> 16) & 0xFFFF;
1529         pr_info("checking hw id %x\n", enc_id);
1530         p->hw_info = NULL;
1531         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1532                 if (enc_id == vpu_hw_set[i].hw_id) {
1533                         p->hw_info = &vpu_hw_set[i];
1534                         ret = 0;
1535                         break;
1536                 }
1537         }
1538         iounmap((void *)tmp);
1539         return ret;
1540 }
1541
1542 static int vpu_service_open(struct inode *inode, struct file *filp)
1543 {
1544         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1545         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1546         if (NULL == session) {
1547                 pr_err("error: unable to allocate memory for vpu_session.");
1548                 return -ENOMEM;
1549         }
1550
1551         session->type   = VPU_TYPE_BUTT;
1552         session->pid    = current->pid;
1553         INIT_LIST_HEAD(&session->waiting);
1554         INIT_LIST_HEAD(&session->running);
1555         INIT_LIST_HEAD(&session->done);
1556         INIT_LIST_HEAD(&session->list_session);
1557         init_waitqueue_head(&session->wait);
1558         atomic_set(&session->task_running, 0);
1559         mutex_lock(&pservice->lock);
1560         list_add_tail(&session->list_session, &pservice->session);
1561         filp->private_data = (void *)session;
1562         mutex_unlock(&pservice->lock);
1563
1564         pr_debug("dev opened\n");
1565         return nonseekable_open(inode, filp);
1566 }
1567
1568 static int vpu_service_release(struct inode *inode, struct file *filp)
1569 {
1570         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1571         int task_running;
1572         vpu_session *session = (vpu_session *)filp->private_data;
1573         if (NULL == session)
1574                 return -EINVAL;
1575
1576         task_running = atomic_read(&session->task_running);
1577         if (task_running) {
1578                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1579                 msleep(50);
1580         }
1581         wake_up(&session->wait);
1582
1583         mutex_lock(&pservice->lock);
1584         /* remove this filp from the asynchronusly notified filp's */
1585         list_del_init(&session->list_session);
1586         vpu_service_session_clear(pservice, session);
1587         kfree(session);
1588         filp->private_data = NULL;
1589         mutex_unlock(&pservice->lock);
1590
1591         pr_debug("dev closed\n");
1592         return 0;
1593 }
1594
1595 static const struct file_operations vpu_service_fops = {
1596         .unlocked_ioctl = vpu_service_ioctl,
1597         .open           = vpu_service_open,
1598         .release        = vpu_service_release,
1599         //.fasync       = vpu_service_fasync,
1600 };
1601
1602 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1603 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1604 static irqreturn_t vepu_irq(int irq, void *dev_id);
1605 static irqreturn_t vepu_isr(int irq, void *dev_id);
1606 static void get_hw_info(struct vpu_service_info *pservice);
1607
1608 #if HEVC_SIM_ENABLE
1609 static void simulate_work(struct work_struct *work_s)
1610 {
1611         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
1612         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
1613         vpu_device *dev = &pservice->dec_dev;
1614
1615         if (!list_empty(&pservice->running)) {
1616                 atomic_add(1, &dev->irq_count_codec);
1617                 vdpu_isr(0, (void*)pservice);
1618         } else {
1619                 //simulate_start(pservice);
1620                 pr_err("empty running queue\n");
1621         }
1622 }
1623
1624 static void simulate_init(struct vpu_service_info *pservice)
1625 {
1626         INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
1627 }
1628
1629 static void simulate_start(struct vpu_service_info *pservice)
1630 {
1631         cancel_delayed_work_sync(&pservice->power_off_work);
1632         queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
1633 }
1634 #endif
1635
1636 #ifdef CONFIG_VCODEC_MMU
1637 static struct device *rockchip_get_sysmmu_device_by_compatible(const char *compt)
1638 {
1639         struct device_node *dn = NULL;
1640         struct platform_device *pd = NULL;
1641         struct device *ret = NULL ;
1642
1643         dn = of_find_compatible_node(NULL,NULL,compt);
1644         if(!dn) {
1645                 printk("can't find device node %s \r\n",compt);
1646                 return NULL;
1647         }
1648
1649         pd = of_find_device_by_node(dn);
1650         if(!pd) {
1651                 printk("can't find platform device in device node %s\n",compt);
1652                 return  NULL;
1653         }
1654         ret = &pd->dev;
1655
1656         return ret;
1657
1658 }
1659 #ifdef CONFIG_IOMMU_API
1660 static inline void platform_set_sysmmu(struct device *iommu,
1661         struct device *dev)
1662 {
1663         dev->archdata.iommu = iommu;
1664 }
1665 #else
1666 static inline void platform_set_sysmmu(struct device *iommu,
1667         struct device *dev)
1668 {
1669 }
1670 #endif
1671
1672 int vcodec_sysmmu_fault_handler(struct device *dev,
1673                                 enum rk_iommu_inttype itype,
1674                                 unsigned long pgtable_base,
1675                                 unsigned long fault_addr, unsigned int status)
1676 {
1677         struct platform_device *pdev;
1678         struct vpu_service_info *pservice;
1679
1680         pr_info("%s in\n", __func__);
1681
1682         pdev = container_of(dev, struct platform_device, dev);
1683
1684         pservice = platform_get_drvdata(pdev);
1685
1686         if (pservice->reg_codec) {
1687                 struct vcodec_mem_region *mem, *n;
1688                 int i = 0;
1689                 pr_info("vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1690                 list_for_each_entry_safe(mem, n,
1691                                          &pservice->reg_codec->mem_region_list,
1692                                          reg_lnk) {
1693                         pr_info("vcodec, mem region [%02d] 0x%08x %ld\n",
1694                                 i, (u32)mem->iova, mem->len);
1695                         i++;
1696                 }
1697
1698                 pr_alert("vcodec, page fault occur, reset hw\n");
1699                 pservice->reg_codec->reg[101] = 1;
1700                 vpu_reset(pservice);
1701         }
1702
1703         return 0;
1704 }
1705 #endif
1706
1707 #if HEVC_TEST_ENABLE
1708 static int hevc_test_case0(vpu_service_info *pservice);
1709 #endif
1710 #if defined(CONFIG_ION_ROCKCHIP)
1711 extern struct ion_client *rockchip_ion_client_create(const char * name);
1712 #endif
1713 static int vcodec_probe(struct platform_device *pdev)
1714 {
1715         int ret = 0;
1716         struct resource *res = NULL;
1717         struct device *dev = &pdev->dev;
1718         void __iomem *regs = NULL;
1719         struct device_node *np = pdev->dev.of_node;
1720         struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
1721         char *prop = (char*)dev_name(dev);
1722         u32 config;
1723 #if defined(CONFIG_VCODEC_MMU)
1724         u32 iommu_en = 0;
1725         char mmu_dev_dts_name[40];
1726         of_property_read_u32(np, "iommu_enabled", &iommu_en);
1727 #endif
1728
1729         pr_info("probe device %s\n", dev_name(dev));
1730
1731         of_property_read_string(np, "name", (const char**)&prop);
1732         dev_set_name(dev, prop);
1733
1734         if (strcmp(dev_name(dev), "hevc_service") == 0) {
1735                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
1736                 g_combo.hevc_srv = pservice;
1737         } else if (strcmp(dev_name(dev), "vpu_service") == 0) {
1738                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1739                 g_combo.vpu_srv = pservice;
1740         } else {
1741                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));
1742                 return -1;
1743         }
1744
1745         mutex_init(&g_mode_mutex);
1746         vcodec_enter_mode_nolock(pservice->dev_id, &config);
1747
1748         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1749         INIT_LIST_HEAD(&pservice->waiting);
1750         INIT_LIST_HEAD(&pservice->running);
1751         INIT_LIST_HEAD(&pservice->done);
1752         INIT_LIST_HEAD(&pservice->session);
1753         mutex_init(&pservice->lock);
1754         pservice->reg_codec     = NULL;
1755         pservice->reg_pproc     = NULL;
1756         atomic_set(&pservice->total_running, 0);
1757         pservice->enabled = false;
1758 #if defined(CONFIG_VCODEC_MMU)
1759         pservice->mmu_dev = NULL;
1760 #endif
1761         pservice->dev = dev;
1762
1763         if (0 > vpu_get_clk(pservice))
1764                 goto err;
1765
1766         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
1767
1768         vpu_service_power_on(pservice);
1769
1770         mdelay(1);
1771
1772         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1773
1774         res->flags &= ~IORESOURCE_CACHEABLE;
1775
1776         regs = devm_ioremap_resource(pservice->dev, res);
1777         if (IS_ERR(regs)) {
1778                 ret = PTR_ERR(regs);
1779                 goto err;
1780         }
1781
1782         {
1783                 u32 offset = res->start;
1784                 if (cpu_is_rk3036()) {
1785                         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)
1786                                 offset += 0x400;
1787                 }
1788                 ret = vpu_service_check_hw(pservice, offset);
1789                 if (ret < 0) {
1790                         pr_err("error: hw info check faild\n");
1791                         goto err;
1792                 }
1793         }
1794
1795         /// define regs address.
1796         pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
1797         pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;
1798
1799         pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
1800
1801         pservice->reg_size   = pservice->dec_dev.iosize;
1802
1803         if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {
1804                 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
1805                 pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;
1806
1807                 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
1808
1809                 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
1810
1811                 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1812                 if (pservice->irq_enc < 0) {
1813                         dev_err(pservice->dev, "cannot find IRQ encoder\n");
1814                         ret = -ENXIO;
1815                         goto err;
1816                 }
1817
1818                 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);
1819                 if (ret) {
1820                         dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
1821                         goto err;
1822                 }
1823         }
1824
1825         pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1826         if (pservice->irq_dec < 0) {
1827                 dev_err(pservice->dev, "cannot find IRQ decoder\n");
1828                 ret = -ENXIO;
1829                 goto err;
1830         }
1831
1832         /* get the IRQ line */
1833         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
1834         if (ret) {
1835                 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
1836                 goto err;
1837         }
1838
1839         atomic_set(&pservice->dec_dev.irq_count_codec, 0);
1840         atomic_set(&pservice->dec_dev.irq_count_pp, 0);
1841         atomic_set(&pservice->enc_dev.irq_count_codec, 0);
1842         atomic_set(&pservice->enc_dev.irq_count_pp, 0);
1843
1844         /// create device
1845         ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
1846         if (ret) {
1847                 dev_err(dev, "alloc dev_t failed\n");
1848                 goto err;
1849         }
1850
1851         cdev_init(&pservice->cdev, &vpu_service_fops);
1852
1853         pservice->cdev.owner = THIS_MODULE;
1854         pservice->cdev.ops = &vpu_service_fops;
1855
1856         ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
1857
1858         if (ret) {
1859                 dev_err(dev, "add dev_t failed\n");
1860                 goto err;
1861         }
1862
1863         pservice->cls = class_create(THIS_MODULE, dev_name(dev));
1864
1865         if (IS_ERR(pservice->cls)) {
1866                 ret = PTR_ERR(pservice->cls);
1867                 dev_err(dev, "class_create err:%d\n", ret);
1868                 goto err;
1869         }
1870
1871         pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
1872
1873         platform_set_drvdata(pdev, pservice);
1874
1875         get_hw_info(pservice);
1876
1877
1878 #ifdef CONFIG_DEBUG_FS
1879         pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
1880         if (pservice->debugfs_dir == NULL)
1881                 pr_err("create debugfs dir %s failed\n", dev_name(dev));
1882
1883         pservice->debugfs_file_regs =
1884                 debugfs_create_file("regs", 0664,
1885                                     pservice->debugfs_dir, pservice,
1886                                     &debug_vcodec_fops);
1887 #endif
1888
1889 #if defined(CONFIG_VCODEC_MMU)
1890         if (iommu_en) {
1891                 pservice->ion_client = rockchip_ion_client_create("vpu");
1892                 if (IS_ERR(pservice->ion_client)) {
1893                         dev_err(&pdev->dev, "failed to create ion client for vcodec");
1894                         return PTR_ERR(pservice->ion_client);
1895                 } else {
1896                         dev_info(&pdev->dev, "vcodec ion client create success!\n");
1897                 }
1898
1899                 if (pservice->hw_info->hw_id == HEVC_ID)
1900                         sprintf(mmu_dev_dts_name, HEVC_IOMMU_COMPATIBLE_NAME);
1901                 else
1902                         sprintf(mmu_dev_dts_name, VPU_IOMMU_COMPATIBLE_NAME);
1903
1904                 pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);
1905
1906                 if (pservice->mmu_dev) {
1907                         platform_set_sysmmu(pservice->mmu_dev, pservice->dev);
1908                         rockchip_iovmm_activate(pservice->dev);
1909                 }
1910
1911                 rockchip_iovmm_set_fault_handler(pservice->dev, vcodec_sysmmu_fault_handler);
1912         }
1913 #endif
1914         vcodec_exit_mode_nolock(pservice->dev_id, config);
1915         vpu_service_power_off(pservice);
1916
1917         pr_info("init success\n");
1918
1919 #if HEVC_SIM_ENABLE
1920         if (pservice->hw_info->hw_id == HEVC_ID)
1921                 simulate_init(pservice);
1922 #endif
1923
1924 #if HEVC_TEST_ENABLE
1925         hevc_test_case0(pservice);
1926 #endif
1927
1928         return 0;
1929
1930 err:
1931         pr_info("init failed\n");
1932         vcodec_exit_mode();
1933         vpu_service_power_off(pservice);
1934         vpu_put_clk(pservice);
1935         wake_lock_destroy(&pservice->wake_lock);
1936
1937         if (res)
1938                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1939         if (pservice->irq_enc > 0)
1940                 free_irq(pservice->irq_enc, (void *)pservice);
1941         if (pservice->irq_dec > 0)
1942                 free_irq(pservice->irq_dec, (void *)pservice);
1943
1944         if (pservice->child_dev) {
1945                 device_destroy(pservice->cls, pservice->dev_t);
1946                 cdev_del(&pservice->cdev);
1947                 unregister_chrdev_region(pservice->dev_t, 1);
1948         }
1949
1950         if (pservice->cls)
1951                 class_destroy(pservice->cls);
1952
1953         return ret;
1954 }
1955
1956 static int vcodec_remove(struct platform_device *pdev)
1957 {
1958         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
1959         struct resource *res;
1960
1961         device_destroy(pservice->cls, pservice->dev_t);
1962         class_destroy(pservice->cls);
1963         cdev_del(&pservice->cdev);
1964         unregister_chrdev_region(pservice->dev_t, 1);
1965
1966         free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
1967         free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
1968         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1969         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1970         vpu_put_clk(pservice);
1971         wake_lock_destroy(&pservice->wake_lock);
1972
1973 #ifdef CONFIG_DEBUG_FS
1974         debugfs_remove(pservice->debugfs_file_regs);
1975         debugfs_remove(pservice->debugfs_dir);
1976 #endif
1977
1978         return 0;
1979 }
1980
1981 #if defined(CONFIG_OF)
1982 static const struct of_device_id vcodec_service_dt_ids[] = {
1983         {.compatible = "vpu_service",},
1984         {.compatible = "rockchip,hevc_service",},
1985         {},
1986 };
1987 #endif
1988
1989 static struct platform_driver vcodec_driver = {
1990         .probe = vcodec_probe,
1991         .remove = vcodec_remove,
1992         .driver = {
1993                 .name = "vcodec",
1994                 .owner = THIS_MODULE,
1995 #if defined(CONFIG_OF)
1996                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
1997 #endif
1998         },
1999 };
2000
2001 static void get_hw_info(struct vpu_service_info *pservice)
2002 {
2003         VPUHwDecConfig_t *dec = &pservice->dec_config;
2004         VPUHwEncConfig_t *enc = &pservice->enc_config;
2005
2006         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {
2007                 u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
2008                 u32 asicID      = pservice->dec_dev.hwregs[0];
2009
2010                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;
2011                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2012                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2013                         dec->jpegSupport = JPEG_PROGRESSIVE;
2014                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2015                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2016                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2017                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2018                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2019                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2020
2021                 if (soc_is_rk3190() || soc_is_rk3288())
2022                         dec->maxDecPicWidth = 4096;
2023                 else if (cpu_is_rk3036() || cpu_is_rk312x())
2024                         dec->maxDecPicWidth = 1920;
2025                 else
2026                         dec->maxDecPicWidth = configReg & 0x07FFU;
2027
2028                 /* 2nd Config register */
2029                 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
2030                 if (dec->refBufSupport) {
2031                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2032                                 dec->refBufSupport |= 2;
2033                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2034                                 dec->refBufSupport |= 4;
2035                 }
2036                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2037                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2038                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2039                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2040
2041                 /* JPEG xtensions */
2042                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2043                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2044                 else
2045                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2046
2047                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2048                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2049                 else
2050                         dec->rvSupport = RV_NOT_SUPPORTED;
2051                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2052
2053                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2054                         dec->refBufSupport |= 8; /* enable HW support for offset */
2055
2056                 /// invalidate fuse register value in rk319x vpu and following.
2057                 if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {
2058                         VPUHwFuseStatus_t hwFuseSts;
2059                         /* Decoder fuse configuration */
2060                         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2061
2062                         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
2063                         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
2064                         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
2065                         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
2066                         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
2067                         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
2068                         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
2069                         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
2070                         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
2071                         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
2072                         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
2073                         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
2074                         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
2075                         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
2076
2077                         /* check max. decoder output width */
2078
2079                         if (fuseReg & 0x8000U)
2080                                 hwFuseSts.maxDecPicWidthFuse = 1920;
2081                         else if (fuseReg & 0x4000U)
2082                                 hwFuseSts.maxDecPicWidthFuse = 1280;
2083                         else if (fuseReg & 0x2000U)
2084                                 hwFuseSts.maxDecPicWidthFuse = 720;
2085                         else if (fuseReg & 0x1000U)
2086                                 hwFuseSts.maxDecPicWidthFuse = 352;
2087                         else    /* remove warning */
2088                                 hwFuseSts.maxDecPicWidthFuse = 352;
2089
2090                         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
2091
2092                         /* Pp configuration */
2093                         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
2094
2095                         if ((configReg >> DWL_PP_E) & 0x01U) {
2096                                 dec->ppSupport = 1;
2097                                 dec->maxPpOutPicWidth = configReg & 0x07FFU;
2098                                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
2099                                 dec->ppConfig = configReg;
2100                         } else {
2101                                 dec->ppSupport = 0;
2102                                 dec->maxPpOutPicWidth = 0;
2103                                 dec->ppConfig = 0;
2104                         }
2105
2106                         /* check the HW versio */
2107                         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
2108                                 /* Pp configuration */
2109                                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2110                                 if ((configReg >> DWL_PP_E) & 0x01U) {
2111                                         /* Pp fuse configuration */
2112                                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
2113
2114                                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
2115                                                 hwFuseSts.ppSupportFuse = 1;
2116                                                 /* check max. pp output width */
2117                                                 if (fuseRegPp & 0x8000U)
2118                                                         hwFuseSts.maxPpOutPicWidthFuse = 1920;
2119                                                 else if (fuseRegPp & 0x4000U)
2120                                                         hwFuseSts.maxPpOutPicWidthFuse = 1280;
2121                                                 else if (fuseRegPp & 0x2000U)
2122                                                         hwFuseSts.maxPpOutPicWidthFuse = 720;
2123                                                 else if (fuseRegPp & 0x1000U)
2124                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2125                                                 else
2126                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;
2127                                                 hwFuseSts.ppConfigFuse = fuseRegPp;
2128                                         } else {
2129                                                 hwFuseSts.ppSupportFuse = 0;
2130                                                 hwFuseSts.maxPpOutPicWidthFuse = 0;
2131                                                 hwFuseSts.ppConfigFuse = 0;
2132                                         }
2133                                 } else {
2134                                         hwFuseSts.ppSupportFuse = 0;
2135                                         hwFuseSts.maxPpOutPicWidthFuse = 0;
2136                                         hwFuseSts.ppConfigFuse = 0;
2137                                 }
2138
2139                                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
2140                                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
2141                                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
2142                                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
2143                                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
2144                                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
2145                                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
2146                                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
2147                                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
2148                                         dec->jpegSupport = JPEG_BASELINE;
2149                                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
2150                                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
2151                                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
2152                                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
2153                                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
2154                                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
2155
2156                                 /* check the pp config vs fuse status */
2157                                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
2158                                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
2159                                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
2160                                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
2161                                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
2162
2163                                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
2164                                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
2165                                 }
2166                                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
2167                                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
2168                                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;
2169                                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;
2170                                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;
2171                         }
2172                 }
2173
2174                 if (!cpu_is_rk3036()) {
2175                         configReg = pservice->enc_dev.hwregs[63];
2176                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2177                         enc->h264Enabled = (configReg >> 27) & 1;
2178                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2179                         enc->jpegEnabled = (configReg >> 25) & 1;
2180                         enc->vsEnabled = (configReg >> 24) & 1;
2181                         enc->rgbEnabled = (configReg >> 28) & 1;
2182                         /*enc->busType = (configReg >> 20) & 15;
2183                         enc->synthesisLanguage = (configReg >> 16) & 15;
2184                         enc->busWidth = (configReg >> 12) & 15;*/
2185                         enc->reg_size = pservice->reg_size;
2186                         enc->reserv[0] = enc->reserv[1] = 0;
2187                 }
2188
2189                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2190                 if (pservice->auto_freq) {
2191                         pr_info("vpu_service set to auto frequency mode\n");
2192                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2193                 }
2194
2195                 pservice->bug_dec_addr = cpu_is_rk30xx();
2196         } else {
2197                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2198                         dec->maxDecPicWidth = 1920;
2199                 else
2200                         dec->maxDecPicWidth = 4096;
2201                 /* disable frequency switch in hevc.*/
2202                 pservice->auto_freq = false;
2203         }
2204 }
2205
2206 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2207 {
2208         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2209         vpu_device *dev = &pservice->dec_dev;
2210         u32 raw_status;
2211         u32 irq_status;
2212
2213         vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);
2214
2215         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2216
2217         pr_debug("dec_irq\n");
2218
2219         if (irq_status & DEC_INTERRUPT_BIT) {
2220                 pr_debug("dec_isr dec %x\n", irq_status);
2221                 if ((irq_status & 0x40001) == 0x40001)
2222                 {
2223                         do {
2224                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2225                         } while ((irq_status & 0x40001) == 0x40001);
2226                 }
2227
2228                 /* clear dec IRQ */
2229                 if (pservice->hw_info->hw_id != HEVC_ID)
2230                         writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
2231                 else
2232                         writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2233                 atomic_add(1, &dev->irq_count_codec);
2234         }
2235
2236         if (pservice->hw_info->hw_id != HEVC_ID) {
2237                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2238                 if (irq_status & PP_INTERRUPT_BIT) {
2239                         pr_debug("vdpu_isr pp  %x\n", irq_status);
2240                         /* clear pp IRQ */
2241                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2242                         atomic_add(1, &dev->irq_count_pp);
2243                 }
2244         }
2245
2246         pservice->irq_status = raw_status;
2247
2248         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2249
2250         return IRQ_WAKE_THREAD;
2251 }
2252
2253 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2254 {
2255         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2256         vpu_device *dev = &pservice->dec_dev;
2257         mutex_lock(&pservice->lock);
2258         if (atomic_read(&dev->irq_count_codec)) {
2259 #if VPU_SERVICE_SHOW_TIME
2260                 do_gettimeofday(&dec_end);
2261                 pr_info("dec task: %ld ms\n",
2262                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2263                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2264 #endif
2265                 atomic_sub(1, &dev->irq_count_codec);
2266                 if (NULL == pservice->reg_codec) {
2267                         pr_err("error: dec isr with no task waiting\n");
2268                 } else {
2269                         reg_from_run_to_done(pservice, pservice->reg_codec);
2270                 }
2271         }
2272
2273         if (atomic_read(&dev->irq_count_pp)) {
2274
2275 #if VPU_SERVICE_SHOW_TIME
2276                 do_gettimeofday(&pp_end);
2277                 printk("pp  task: %ld ms\n",
2278                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2279                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2280 #endif
2281
2282                 atomic_sub(1, &dev->irq_count_pp);
2283                 if (NULL == pservice->reg_pproc) {
2284                         pr_err("error: pp isr with no task waiting\n");
2285                 } else {
2286                         reg_from_run_to_done(pservice, pservice->reg_pproc);
2287                 }
2288         }
2289         try_set_reg(pservice);
2290         mutex_unlock(&pservice->lock);
2291         return IRQ_HANDLED;
2292 }
2293
2294 static irqreturn_t vepu_irq(int irq, void *dev_id)
2295 {
2296         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2297         vpu_device *dev = &pservice->enc_dev;
2298         u32 irq_status;
2299
2300         vcodec_enter_mode_nolock(pservice->dev_id,  &pservice->reserved_mode);
2301         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2302
2303         pr_debug("vepu_irq irq status %x\n", irq_status);
2304
2305 #if VPU_SERVICE_SHOW_TIME
2306         do_gettimeofday(&enc_end);
2307         pr_info("enc task: %ld ms\n",
2308                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2309                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2310 #endif
2311         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2312                 /* clear enc IRQ */
2313                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2314                 atomic_add(1, &dev->irq_count_codec);
2315         }
2316
2317         pservice->irq_status = irq_status;
2318
2319         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2320
2321         return IRQ_WAKE_THREAD;
2322 }
2323
2324 static irqreturn_t vepu_isr(int irq, void *dev_id)
2325 {
2326         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2327         vpu_device *dev = &pservice->enc_dev;
2328
2329         mutex_lock(&pservice->lock);
2330         if (atomic_read(&dev->irq_count_codec)) {
2331                 atomic_sub(1, &dev->irq_count_codec);
2332                 if (NULL == pservice->reg_codec) {
2333                         pr_err("error: enc isr with no task waiting\n");
2334                 } else {
2335                         reg_from_run_to_done(pservice, pservice->reg_codec);
2336                 }
2337         }
2338         try_set_reg(pservice);
2339         mutex_unlock(&pservice->lock);
2340         return IRQ_HANDLED;
2341 }
2342
2343 static int __init vcodec_service_init(void)
2344 {
2345         int ret;
2346
2347         g_combo.hevc_srv = NULL;
2348         g_combo.vpu_srv = NULL;
2349
2350         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2351                 pr_err("Platform device register failed (%d).\n", ret);
2352                 return ret;
2353         }
2354
2355 #ifdef CONFIG_DEBUG_FS
2356         vcodec_debugfs_init();
2357 #endif
2358
2359         return ret;
2360 }
2361
2362 static void __exit vcodec_service_exit(void)
2363 {
2364 #ifdef CONFIG_DEBUG_FS
2365         vcodec_debugfs_exit();
2366 #endif
2367
2368         platform_driver_unregister(&vcodec_driver);
2369 }
2370
2371 module_init(vcodec_service_init);
2372 module_exit(vcodec_service_exit);
2373
2374 #ifdef CONFIG_DEBUG_FS
2375 #include <linux/seq_file.h>
2376
2377 static int vcodec_debugfs_init()
2378 {
2379         parent = debugfs_create_dir("vcodec", NULL);
2380         if (!parent)
2381                 return -1;
2382
2383         return 0;
2384 }
2385
2386 static void vcodec_debugfs_exit()
2387 {
2388         debugfs_remove(parent);
2389 }
2390
2391 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2392 {
2393         return debugfs_create_dir(dirname, parent);
2394 }
2395
2396 static int debug_vcodec_show(struct seq_file *s, void *unused)
2397 {
2398         struct vpu_service_info *pservice = s->private;
2399         unsigned int i, n;
2400         vpu_reg *reg, *reg_tmp;
2401         vpu_session *session, *session_tmp;
2402
2403         mutex_lock(&pservice->lock);
2404         vpu_service_power_on(pservice);
2405         if (pservice->hw_info->hw_id != HEVC_ID) {
2406                 seq_printf(s, "\nENC Registers:\n");
2407                 n = pservice->enc_dev.iosize >> 2;
2408                 for (i = 0; i < n; i++) {
2409                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
2410                 }
2411         }
2412         seq_printf(s, "\nDEC Registers:\n");
2413         n = pservice->dec_dev.iosize >> 2;
2414         for (i = 0; i < n; i++)
2415                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2416
2417         seq_printf(s, "\nvpu service status:\n");
2418         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2419                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2420                 /*seq_printf(s, "waiting reg set %d\n");*/
2421                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2422                         seq_printf(s, "waiting register set\n");
2423                 }
2424                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2425                         seq_printf(s, "running register set\n");
2426                 }
2427                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2428                         seq_printf(s, "done    register set\n");
2429                 }
2430         }
2431         mutex_unlock(&pservice->lock);
2432
2433         return 0;
2434 }
2435
2436 static int debug_vcodec_open(struct inode *inode, struct file *file)
2437 {
2438         return single_open(file, debug_vcodec_show, inode->i_private);
2439 }
2440
2441 #endif
2442
2443 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2444 #include "hevc_test_inc/pps_00.h"
2445 #include "hevc_test_inc/register_00.h"
2446 #include "hevc_test_inc/rps_00.h"
2447 #include "hevc_test_inc/scaling_list_00.h"
2448 #include "hevc_test_inc/stream_00.h"
2449
2450 #include "hevc_test_inc/pps_01.h"
2451 #include "hevc_test_inc/register_01.h"
2452 #include "hevc_test_inc/rps_01.h"
2453 #include "hevc_test_inc/scaling_list_01.h"
2454 #include "hevc_test_inc/stream_01.h"
2455
2456 #include "hevc_test_inc/cabac.h"
2457
2458 extern struct ion_client *rockchip_ion_client_create(const char * name);
2459
2460 static struct ion_client *ion_client = NULL;
2461 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2462 {
2463         int size = (len+15) & (~15);
2464         struct ion_handle *handle;
2465         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2466
2467         if (ion_client == NULL)
2468                 ion_client = rockchip_ion_client_create("vcodec");
2469
2470         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2471
2472         ptr = ion_map_kernel(ion_client, handle);
2473
2474         ion_phys(ion_client, handle, phy, &size);
2475
2476         memcpy(ptr, tbl, len);
2477
2478         return ptr;
2479 }
2480
2481 u8* get_align_ptr_no_copy(int len, u32 *phy)
2482 {
2483         int size = (len+15) & (~15);
2484         struct ion_handle *handle;
2485         u8 *ptr;
2486
2487         if (ion_client == NULL)
2488                 ion_client = rockchip_ion_client_create("vcodec");
2489
2490         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2491
2492         ptr = ion_map_kernel(ion_client, handle);
2493
2494         ion_phys(ion_client, handle, phy, &size);
2495
2496         return ptr;
2497 }
2498
2499 #define TEST_CNT    2
2500 static int hevc_test_case0(vpu_service_info *pservice)
2501 {
2502         vpu_session session;
2503         vpu_reg *reg;
2504         unsigned long size = 272;//sizeof(register_00); // registers array length
2505         int testidx = 0;
2506         int ret = 0;
2507
2508         u8 *pps_tbl[TEST_CNT];
2509         u8 *register_tbl[TEST_CNT];
2510         u8 *rps_tbl[TEST_CNT];
2511         u8 *scaling_list_tbl[TEST_CNT];
2512         u8 *stream_tbl[TEST_CNT];
2513
2514         int stream_size[2];
2515         int pps_size[2];
2516         int rps_size[2];
2517         int scl_size[2];
2518         int cabac_size[2];
2519
2520         u32 phy_pps;
2521         u32 phy_rps;
2522         u32 phy_scl;
2523         u32 phy_str;
2524         u32 phy_yuv;
2525         u32 phy_ref;
2526         u32 phy_cabac;
2527
2528         volatile u8 *stream_buf;
2529         volatile u8 *pps_buf;
2530         volatile u8 *rps_buf;
2531         volatile u8 *scl_buf;
2532         volatile u8 *yuv_buf;
2533         volatile u8 *cabac_buf;
2534         volatile u8 *ref_buf;
2535
2536         u8 *pps;
2537         u8 *yuv[2];
2538         int i;
2539
2540         pps_tbl[0] = pps_00;
2541         pps_tbl[1] = pps_01;
2542
2543         register_tbl[0] = register_00;
2544         register_tbl[1] = register_01;
2545
2546         rps_tbl[0] = rps_00;
2547         rps_tbl[1] = rps_01;
2548
2549         scaling_list_tbl[0] = scaling_list_00;
2550         scaling_list_tbl[1] = scaling_list_01;
2551
2552         stream_tbl[0] = stream_00;
2553         stream_tbl[1] = stream_01;
2554
2555         stream_size[0] = sizeof(stream_00);
2556         stream_size[1] = sizeof(stream_01);
2557
2558         pps_size[0] = sizeof(pps_00);
2559         pps_size[1] = sizeof(pps_01);
2560
2561         rps_size[0] = sizeof(rps_00);
2562         rps_size[1] = sizeof(rps_01);
2563
2564         scl_size[0] = sizeof(scaling_list_00);
2565         scl_size[1] = sizeof(scaling_list_01);
2566
2567         cabac_size[0] = sizeof(Cabac_table);
2568         cabac_size[1] = sizeof(Cabac_table);
2569
2570         /* create session */
2571         session.pid = current->pid;
2572         session.type = VPU_DEC;
2573         INIT_LIST_HEAD(&session.waiting);
2574         INIT_LIST_HEAD(&session.running);
2575         INIT_LIST_HEAD(&session.done);
2576         INIT_LIST_HEAD(&session.list_session);
2577         init_waitqueue_head(&session.wait);
2578         atomic_set(&session.task_running, 0);
2579         list_add_tail(&session.list_session, &pservice->session);
2580
2581         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2582         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2583
2584         while (testidx < TEST_CNT) {
2585                 /* create registers */
2586                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2587                 if (NULL == reg) {
2588                         pr_err("error: kmalloc fail in reg_init\n");
2589                         return -1;
2590                 }
2591
2592                 if (size > pservice->reg_size) {
2593                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2594                         size = pservice->reg_size;
2595                 }
2596                 reg->session = &session;
2597                 reg->type = session.type;
2598                 reg->size = size;
2599                 reg->freq = VPU_FREQ_DEFAULT;
2600                 reg->reg = (unsigned long *)&reg[1];
2601                 INIT_LIST_HEAD(&reg->session_link);
2602                 INIT_LIST_HEAD(&reg->status_link);
2603
2604                 /* TODO: stuff registers */
2605                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2606
2607                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2608                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2609                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2610                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2611                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2612
2613                 pps = pps_buf;
2614
2615                 /* TODO: replace reigster address */
2616                 for (i=0; i<64; i++) {
2617                         u32 scaling_offset;
2618                         u32 tmp;
2619
2620                         scaling_offset = (u32)pps[i*80+74];
2621                         scaling_offset += (u32)pps[i*80+75] << 8;
2622                         scaling_offset += (u32)pps[i*80+76] << 16;
2623                         scaling_offset += (u32)pps[i*80+77] << 24;
2624
2625                         tmp = phy_scl + scaling_offset;
2626
2627                         pps[i*80+74] = tmp & 0xff;
2628                         pps[i*80+75] = (tmp >> 8) & 0xff;
2629                         pps[i*80+76] = (tmp >> 16) & 0xff;
2630                         pps[i*80+77] = (tmp >> 24) & 0xff;
2631                 }
2632
2633                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2634                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2635
2636                 reg->reg[1] = 0x21;
2637                 reg->reg[4] = phy_str;
2638                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2639                 reg->reg[6] = phy_cabac;
2640                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2641                 reg->reg[42] = phy_pps;
2642                 reg->reg[43] = phy_rps;
2643                 for (i = 10; i <= 24; i++)
2644                         reg->reg[i] = phy_yuv;
2645
2646                 mutex_lock(&pservice->lock);
2647                 list_add_tail(&reg->status_link, &pservice->waiting);
2648                 list_add_tail(&reg->session_link, &session.waiting);
2649                 mutex_unlock(&pservice->lock);
2650
2651                 printk("%s %d %p\n", __func__, __LINE__, pservice);
2652
2653                 /* stuff hardware */
2654                 try_set_reg(pservice);
2655
2656                 /* wait for result */
2657                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2658                 if (!list_empty(&session.done)) {
2659                         if (ret < 0)
2660                                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2661                         ret = 0;
2662                 } else {
2663                         if (unlikely(ret < 0)) {
2664                                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
2665                         } else if (0 == ret) {
2666                                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2667                                 ret = -ETIMEDOUT;
2668                         }
2669                 }
2670                 if (ret < 0) {
2671                         int task_running = atomic_read(&session.task_running);
2672                         int n;
2673                         mutex_lock(&pservice->lock);
2674                         vpu_service_dump(pservice);
2675                         if (task_running) {
2676                                 atomic_set(&session.task_running, 0);
2677                                 atomic_sub(task_running, &pservice->total_running);
2678                                 printk("%d task is running but not return, reset hardware...", task_running);
2679                                 vpu_reset(pservice);
2680                                 printk("done\n");
2681                         }
2682                         vpu_service_session_clear(pservice, &session);
2683                         mutex_unlock(&pservice->lock);
2684
2685                         printk("\nDEC Registers:\n");
2686                         n = pservice->dec_dev.iosize >> 2;
2687                         for (i=0; i<n; i++)
2688                                 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2689
2690                         pr_err("test index %d failed\n", testidx);
2691                         break;
2692                 } else {
2693                         pr_info("test index %d success\n", testidx);
2694
2695                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2696
2697                         for (i=0; i<68; i++) {
2698                                 if (i % 4 == 0)
2699                                         printk("%02d: ", i);
2700                                 printk("%08x ", reg->reg[i]);
2701                                 if ((i+1) % 4 == 0)
2702                                         printk("\n");
2703                         }
2704
2705                         testidx++;
2706                 }
2707
2708                 reg_deinit(pservice, reg);
2709         }
2710
2711         return 0;
2712 }
2713
2714 #endif
2715