arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ROCKCHIP_IOMMU)\r
  47 //#define CONFIG_VCODEC_MMU\r
  48 #endif\r
  49 \r
  50 #ifdef CONFIG_VCODEC_MMU\r
  51 #include <linux/rockchip/iovmm.h>\r
  52 #include <linux/rockchip/sysmmu.h>\r
  53 #include <linux/dma-buf.h>\r
  54 #endif\r
  55 \r
  56 #ifdef CONFIG_DEBUG_FS\r
  57 #include <linux/debugfs.h>\r
  58 #endif\r
  59 \r
  60 #if defined(CONFIG_ARCH_RK319X)\r
  61 #include <mach/grf.h>\r
  62 #endif\r
  63 \r
  64 #include "vcodec_service.h"\r
  65 \r
  66 #define HEVC_TEST_ENABLE    0\r
  67 #define HEVC_SIM_ENABLE     0\r
  68 #define VCODEC_CLOCK_ENABLE 1\r
  69 \r
  70 typedef enum {\r
  71         VPU_DEC_ID_9190         = 0x6731,\r
  72         VPU_ID_8270             = 0x8270,\r
  73         VPU_ID_4831             = 0x4831,\r
  74     HEVC_ID         = 0x6867,\r
  75 } VPU_HW_ID;\r
  76 \r
  77 typedef enum {\r
  78         VPU_DEC_TYPE_9190       = 0,\r
  79         VPU_ENC_TYPE_8270       = 0x100,\r
  80         VPU_ENC_TYPE_4831       ,\r
  81 } VPU_HW_TYPE_E;\r
  82 \r
  83 typedef enum VPU_FREQ {\r
  84         VPU_FREQ_200M,\r
  85         VPU_FREQ_266M,\r
  86         VPU_FREQ_300M,\r
  87         VPU_FREQ_400M,\r
  88     VPU_FREQ_500M,\r
  89     VPU_FREQ_600M,\r
  90         VPU_FREQ_DEFAULT,\r
  91         VPU_FREQ_BUT,\r
  92 } VPU_FREQ;\r
  93 \r
  94 typedef struct {\r
  95         VPU_HW_ID               hw_id;\r
  96         unsigned long           hw_addr;\r
  97         unsigned long           enc_offset;\r
  98         unsigned long           enc_reg_num;\r
  99         unsigned long           enc_io_size;\r
 100         unsigned long           dec_offset;\r
 101         unsigned long           dec_reg_num;\r
 102         unsigned long           dec_io_size;\r
 103 } VPU_HW_INFO_E;\r
 104 \r
 105 #define VPU_SERVICE_SHOW_TIME                   0\r
 106 \r
 107 #if VPU_SERVICE_SHOW_TIME\r
 108 static struct timeval enc_start, enc_end;\r
 109 static struct timeval dec_start, dec_end;\r
 110 static struct timeval pp_start,  pp_end;\r
 111 #endif\r
 112 \r
 113 #define MHZ                                     (1000*1000)\r
 114 \r
 115 #define REG_NUM_9190_DEC                        (60)\r
 116 #define REG_NUM_9190_PP                         (41)\r
 117 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 120 \r
 121 #define REG_NUM_ENC_8270                        (96)\r
 122 #define REG_SIZE_ENC_8270                       (0x200)\r
 123 #define REG_NUM_ENC_4831                        (164)\r
 124 #define REG_SIZE_ENC_4831                       (0x400)\r
 125 \r
 126 #define REG_NUM_HEVC_DEC            (68)\r
 127 \r
 128 #define SIZE_REG(reg)                           ((reg)*4)\r
 129 \r
 130 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 131         [0] = {\r
 132                 .hw_id          = VPU_ID_8270,\r
 133                 .hw_addr        = 0,\r
 134                 .enc_offset     = 0x0,\r
 135                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 136                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 137                 .dec_offset     = REG_SIZE_ENC_8270,\r
 138                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 139                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 140         },\r
 141         [1] = {\r
 142                 .hw_id          = VPU_ID_4831,\r
 143                 .hw_addr        = 0,\r
 144                 .enc_offset     = 0x0,\r
 145                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 146                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 147                 .dec_offset     = REG_SIZE_ENC_4831,\r
 148                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 149                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 150         },\r
 151     [2] = {\r
 152         .hw_id      = HEVC_ID,\r
 153         .hw_addr    = 0,\r
 154         .dec_offset = 0x0,\r
 155         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 156         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 157     },\r
 158 };\r
 159 \r
 160 \r
 161 #define DEC_INTERRUPT_REGISTER                  1\r
 162 #define PP_INTERRUPT_REGISTER                   60\r
 163 #define ENC_INTERRUPT_REGISTER                  1\r
 164 \r
 165 #define DEC_INTERRUPT_BIT                       0x100\r
 166 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 167 #define PP_INTERRUPT_BIT                        0x100\r
 168 #define ENC_INTERRUPT_BIT                       0x1\r
 169 \r
 170 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 171 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 172 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 173 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 174 \r
 175 #define VPU_REG_EN_ENC                          14\r
 176 #define VPU_REG_ENC_GATE                        2\r
 177 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 178 \r
 179 #define VPU_REG_EN_DEC                          1\r
 180 #define VPU_REG_DEC_GATE                        2\r
 181 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 182 #define VPU_REG_EN_PP                           0\r
 183 #define VPU_REG_PP_GATE                         1\r
 184 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 185 #define VPU_REG_EN_DEC_PP                       1\r
 186 #define VPU_REG_DEC_PP_GATE                     61\r
 187 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 188 \r
 189 #if defined(CONFIG_VCODEC_MMU)\r
 190 static u8 addr_tbl_vpu_dec[] = {\r
 191     12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 192 };\r
 193 \r
 194 static u8 addr_tbl_vpu_enc[] = {\r
 195     5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 196 };\r
 197 \r
 198 static u8 addr_tbl_hevc_dec[] = {\r
 199     4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 200 };\r
 201 #endif\r
 202 \r
 203 /**\r
 204  * struct for process session which connect to vpu\r
 205  *\r
 206  * @author ChenHengming (2011-5-3)\r
 207  */\r
 208 typedef struct vpu_session {\r
 209         VPU_CLIENT_TYPE         type;\r
 210         /* a linked list of data so we can access them for debugging */\r
 211         struct list_head        list_session;\r
 212         /* a linked list of register data waiting for process */\r
 213         struct list_head        waiting;\r
 214         /* a linked list of register data in processing */\r
 215         struct list_head        running;\r
 216         /* a linked list of register data processed */\r
 217         struct list_head        done;\r
 218         wait_queue_head_t       wait;\r
 219         pid_t                   pid;\r
 220         atomic_t                task_running;\r
 221 } vpu_session;\r
 222 \r
 223 /**\r
 224  * struct for process register set\r
 225  *\r
 226  * @author ChenHengming (2011-5-4)\r
 227  */\r
 228 typedef struct vpu_reg {\r
 229         VPU_CLIENT_TYPE         type;\r
 230         VPU_FREQ                    freq;\r
 231         vpu_session             *session;\r
 232         struct list_head        session_link;           /* link to vpu service session */\r
 233         struct list_head        status_link;            /* link to register set list */\r
 234         unsigned long           size;\r
 235 #if defined(CONFIG_VCODEC_MMU)    \r
 236     struct list_head    mem_region_list;\r
 237 #endif    \r
 238         unsigned long           *reg;\r
 239 } vpu_reg;\r
 240 \r
 241 typedef struct vpu_device {\r
 242         atomic_t                irq_count_codec;\r
 243         atomic_t                irq_count_pp;\r
 244         unsigned long           iobaseaddr;\r
 245         unsigned int            iosize;\r
 246         volatile u32            *hwregs;\r
 247 } vpu_device;\r
 248 \r
 249 enum vcodec_device_id {\r
 250         VCODEC_DEVICE_ID_VPU,\r
 251         VCODEC_DEVICE_ID_HEVC\r
 252 };\r
 253 \r
 254 struct vcodec_mem_region {\r
 255     struct list_head srv_lnk;\r
 256     struct list_head reg_lnk;\r
 257     struct list_head session_lnk;\r
 258     unsigned long iova;              /* virtual address for iommu */\r
 259     unsigned long len;\r
 260     struct ion_handle *hdl;\r
 261 };\r
 262 \r
 263 typedef struct vpu_service_info {\r
 264         struct wake_lock        wake_lock;\r
 265         struct delayed_work     power_off_work;\r
 266         struct mutex            lock;\r
 267         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 268         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 269         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 270         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 271         atomic_t                total_running;\r
 272         bool                    enabled;\r
 273         vpu_reg                 *reg_codec;\r
 274         vpu_reg                 *reg_pproc;\r
 275         vpu_reg                 *reg_resev;\r
 276         VPUHwDecConfig_t        dec_config;\r
 277         VPUHwEncConfig_t        enc_config;\r
 278         VPU_HW_INFO_E           *hw_info;\r
 279         unsigned long           reg_size;\r
 280         bool                    auto_freq;\r
 281         bool                    bug_dec_addr;\r
 282         atomic_t                freq_status;\r
 283 \r
 284     struct clk *aclk_vcodec;\r
 285     struct clk *hclk_vcodec;\r
 286     struct clk *clk_core;\r
 287     struct clk *clk_cabac;\r
 288     struct clk *pd_video;\r
 289 \r
 290     int irq_dec;\r
 291     int irq_enc;\r
 292 \r
 293     vpu_device enc_dev;\r
 294     vpu_device dec_dev;\r
 295 \r
 296     struct device   *dev;\r
 297 \r
 298     struct cdev     cdev;\r
 299     dev_t           dev_t;\r
 300     struct class    *cls;\r
 301     struct device   *child_dev;\r
 302 \r
 303     struct dentry   *debugfs_dir;\r
 304     struct dentry   *debugfs_file_regs;\r
 305 \r
 306     u32 irq_status;\r
 307 #if defined(CONFIG_ION_ROCKCHIP)        \r
 308         struct ion_client * ion_client;\r
 309 #endif  \r
 310 \r
 311 #if defined(CONFIG_VCODEC_MMU)\r
 312     struct list_head mem_region_list;\r
 313 #endif\r
 314 \r
 315         enum vcodec_device_id dev_id;\r
 316 \r
 317     struct delayed_work simulate_work;\r
 318 } vpu_service_info;\r
 319 \r
 320 typedef struct vpu_request\r
 321 {\r
 322         unsigned long   *req;\r
 323         unsigned long   size;\r
 324 } vpu_request;\r
 325 \r
 326 /// global variable\r
 327 //static struct clk *pd_video;\r
 328 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 329 \r
 330 #ifdef CONFIG_DEBUG_FS\r
 331 static int vcodec_debugfs_init(void);\r
 332 static void vcodec_debugfs_exit(void);\r
 333 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 334 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 335 \r
 336 static const struct file_operations debug_vcodec_fops = {\r
 337     .open = debug_vcodec_open,\r
 338     .read = seq_read,\r
 339     .llseek = seq_lseek,\r
 340     .release = single_release,\r
 341 };\r
 342 #endif\r
 343 \r
 344 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 345 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 346 \r
 347 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 348 \r
 349 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 350 {\r
 351 #if VCODEC_CLOCK_ENABLE\r
 352     do {\r
 353         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 354         if (IS_ERR(pservice->aclk_vcodec)) {\r
 355             dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 356             break;\r
 357         }\r
 358     \r
 359         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 360         if (IS_ERR(pservice->hclk_vcodec)) {\r
 361             dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 362             break;\r
 363         }\r
 364     \r
 365         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 366             pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 367             if (IS_ERR(pservice->clk_core)) {\r
 368                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 369                 break;\r
 370             }\r
 371     \r
 372             pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 373             if (IS_ERR(pservice->clk_cabac)) {\r
 374                 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 375                 break;\r
 376             }\r
 377             \r
 378             pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 379             if (IS_ERR(pservice->pd_video)) {\r
 380                 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 381                 break;\r
 382             }\r
 383         } else {\r
 384             pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 385             if (IS_ERR(pservice->pd_video)) {\r
 386                 dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 387                 break;\r
 388             }\r
 389         }\r
 390         \r
 391         return 0;\r
 392     } while (0);\r
 393     \r
 394     return -1;\r
 395 #endif\r
 396 }\r
 397 \r
 398 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 399 {\r
 400 #if VCODEC_CLOCK_ENABLE\r
 401     if (pservice->pd_video) {\r
 402         devm_clk_put(pservice->dev, pservice->pd_video);\r
 403     }\r
 404 \r
 405     if (pservice->aclk_vcodec) {\r
 406         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 407     }\r
 408 \r
 409     if (pservice->hclk_vcodec) {\r
 410         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 411     }\r
 412 \r
 413     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 414         if (pservice->clk_core) {\r
 415             devm_clk_put(pservice->dev, pservice->clk_core);\r
 416         }\r
 417         \r
 418         if (pservice->clk_cabac) {\r
 419             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 420         }\r
 421     }\r
 422 #endif\r
 423 }\r
 424 \r
 425 static void vpu_reset(struct vpu_service_info *pservice)\r
 426 {\r
 427 #if defined(CONFIG_ARCH_RK29)\r
 428         clk_disable(aclk_ddr_vepu);\r
 429         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 430         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 431         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 432         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 433         mdelay(10);\r
 434         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 435         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 436         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 437         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 438         clk_enable(aclk_ddr_vepu);\r
 439 #elif defined(CONFIG_ARCH_RK30)\r
 440         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 441         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 442         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 443         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 444         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 445         mdelay(1);\r
 446         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 447         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 448         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 449         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 450         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 451 #endif\r
 452         pservice->reg_codec = NULL;\r
 453         pservice->reg_pproc = NULL;\r
 454         pservice->reg_resev = NULL;\r
 455 }\r
 456 \r
 457 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 458 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 459 {\r
 460         vpu_reg *reg, *n;\r
 461         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 462                 reg_deinit(pservice, reg);\r
 463         }\r
 464         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 465                 reg_deinit(pservice, reg);\r
 466         }\r
 467         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 468                 reg_deinit(pservice, reg);\r
 469         }\r
 470 }\r
 471 \r
 472 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 473 {\r
 474         int running;\r
 475         vpu_reg *reg, *reg_tmp;\r
 476         vpu_session *session, *session_tmp;\r
 477 \r
 478         running = atomic_read(&pservice->total_running);\r
 479         printk("total_running %d\n", running);\r
 480 \r
 481         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 482         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 483         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 484 \r
 485         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 486                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 487                 running = atomic_read(&session->task_running);\r
 488                 printk("task_running %d\n", running);\r
 489                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 490                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 491                 }\r
 492                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 493                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 494                 }\r
 495                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 496                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 497                 }\r
 498         }\r
 499 }\r
 500 \r
 501 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 502 {\r
 503     int total_running;\r
 504     if (!pservice->enabled) {\r
 505         return;\r
 506     }\r
 507 \r
 508     pservice->enabled = false;\r
 509     total_running = atomic_read(&pservice->total_running);\r
 510     if (total_running) {\r
 511         pr_alert("alert: power off when %d task running!!\n", total_running);\r
 512         mdelay(50);\r
 513         pr_alert("alert: delay 50 ms for running task\n");\r
 514         vpu_service_dump(pservice);\r
 515     }\r
 516 \r
 517     printk("%s: power off...", dev_name(pservice->dev));\r
 518     udelay(10);\r
 519 #if VCODEC_CLOCK_ENABLE\r
 520     clk_disable_unprepare(pservice->pd_video);\r
 521     clk_disable_unprepare(pservice->hclk_vcodec);\r
 522     clk_disable_unprepare(pservice->aclk_vcodec);\r
 523     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 524         clk_disable_unprepare(pservice->clk_core);\r
 525         clk_disable_unprepare(pservice->clk_cabac);\r
 526     }\r
 527 #endif\r
 528     wake_unlock(&pservice->wake_lock);\r
 529     printk("done\n");\r
 530 }\r
 531 \r
 532 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 533 {\r
 534         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 535 }\r
 536 \r
 537 static void vpu_power_off_work(struct work_struct *work_s)\r
 538 {\r
 539     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 540     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 541 \r
 542         if (mutex_trylock(&pservice->lock)) {\r
 543                 vpu_service_power_off(pservice);\r
 544                 mutex_unlock(&pservice->lock);\r
 545         } else {\r
 546                 /* Come back later if the device is busy... */\r
 547                 vpu_queue_power_off_work(pservice);\r
 548         }\r
 549 }\r
 550 \r
 551 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 552 {\r
 553     static ktime_t last;\r
 554     ktime_t now = ktime_get();\r
 555     if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 556         cancel_delayed_work_sync(&pservice->power_off_work);\r
 557         vpu_queue_power_off_work(pservice);\r
 558         last = now;\r
 559     }\r
 560     if (pservice->enabled)\r
 561         return ;\r
 562 \r
 563     pservice->enabled = true;\r
 564     printk("%s: power on\n", dev_name(pservice->dev));\r
 565 \r
 566 #if VCODEC_CLOCK_ENABLE\r
 567     clk_prepare_enable(pservice->aclk_vcodec);\r
 568     clk_prepare_enable(pservice->hclk_vcodec);\r
 569 \r
 570     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 571         clk_prepare_enable(pservice->clk_core);\r
 572         clk_prepare_enable(pservice->clk_cabac);\r
 573     }\r
 574     \r
 575     clk_prepare_enable(pservice->pd_video);\r
 576 #endif\r
 577 \r
 578 #if defined(CONFIG_ARCH_RK319X)\r
 579     /// select aclk_vepu as vcodec clock source. \r
 580     #define BIT_VCODEC_SEL  (1<<7)\r
 581     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 582 #endif\r
 583     \r
 584     udelay(10);\r
 585     wake_lock(&pservice->wake_lock);\r
 586 }\r
 587 \r
 588 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 589 {\r
 590         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 591         return ((type == 8) || (type == 4));\r
 592 }\r
 593 \r
 594 static inline bool reg_check_interlace(vpu_reg *reg)\r
 595 {\r
 596         unsigned long type = (reg->reg[3] & (1 << 23));\r
 597         return (type > 0);\r
 598 }\r
 599 \r
 600 static inline bool reg_check_avc(vpu_reg *reg)\r
 601 {\r
 602         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 603         return (type == 0);\r
 604 }\r
 605 \r
 606 static inline int reg_probe_width(vpu_reg *reg)\r
 607 {\r
 608     int width_in_mb = reg->reg[4] >> 23;\r
 609     \r
 610     return width_in_mb * 16;\r
 611 }\r
 612 \r
 613 #if defined(CONFIG_VCODEC_MMU)\r
 614 \r
 615 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 616 {\r
 617     int i;\r
 618     int usr_fd = 0;\r
 619     int offset = 0;\r
 620     \r
 621     if (tbl == NULL || size <= 0) {\r
 622         dev_err(pservice->dev, "input arguments invalidate\n");\r
 623         return -1;\r
 624     }\r
 625     \r
 626     for (i=0; i<size; i++) {\r
 627 #if 0\r
 628         if (copy_from_user(&usr_fd, &reg->reg[addr_tbl_vpu_dec[i]], sizeof(usr_fd)))\r
 629             return -EFAULT;\r
 630 #else\r
 631         usr_fd = reg->reg[tbl[i]] & 0xFF;\r
 632         offset = reg->reg[tbl[i]] >> 8;\r
 633         \r
 634 #endif\r
 635         if (usr_fd != 0) {\r
 636             struct ion_handle *hdl;\r
 637             \r
 638             hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 639             if (IS_ERR(hdl)) {\r
 640                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 641                 return PTR_ERR(hdl);\r
 642             }\r
 643 \r
 644 #if 0\r
 645             {\r
 646                 ion_phys_addr_t phy_addr;\r
 647                 size_t len;\r
 648                 ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 649     \r
 650                 reg->reg[tbl[i]] = phy_addr + offset;\r
 651                 \r
 652                 ion_free(pservice->ion_client, hdl);\r
 653             }\r
 654 #else \r
 655             {\r
 656                 int ret;\r
 657                 struct vcodec_mem_region *mem_region;\r
 658                 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 659      \r
 660                 if (mem_region == NULL) {\r
 661                     dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 662                     ion_free(pservice->ion_client, hdl);\r
 663                     return -1;\r
 664                 }\r
 665                 \r
 666                 ret = ion_map_iommu(pservice->dev, pservice->ion_client, hdl, &mem_region->iova, &mem_region->len);\r
 667                 if (ret < 0) {\r
 668                     dev_err(pservice->dev, "ion map iommu failed\n");\r
 669                     kfree(mem_region);\r
 670                     ion_free(pservice->ion_client, hdl);\r
 671                     return ret;\r
 672                 }\r
 673                 \r
 674                 reg->reg[tbl[i]] = mem_region->iova + offset;\r
 675                 INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 676                 list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 677             }\r
 678 #endif\r
 679         }\r
 680     }\r
 681     \r
 682     return 0;\r
 683 }\r
 684 \r
 685 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 686 {\r
 687     VPU_HW_ID hw_id;\r
 688     u8 *tbl;\r
 689     int size = 0;\r
 690     \r
 691     hw_id = pservice->hw_info->hw_id;\r
 692     \r
 693     if (hw_id == HEVC_ID) {\r
 694         tbl = addr_tbl_hevc_dec;\r
 695         size = sizeof(addr_tbl_hevc_dec);\r
 696     } else {\r
 697         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 698             tbl = addr_tbl_vpu_dec;\r
 699             size = sizeof(addr_tbl_vpu_dec);\r
 700         } else if (reg->type == VPU_ENC) {\r
 701             tbl = addr_tbl_vpu_enc;\r
 702             size = sizeof(addr_tbl_vpu_enc);\r
 703         }\r
 704     }\r
 705     \r
 706     if (size != 0) {\r
 707         return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 708     } else {\r
 709         return -1;\r
 710     }\r
 711 }\r
 712 #endif\r
 713 \r
 714 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 715 {\r
 716         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 717         if (NULL == reg) {\r
 718                 pr_err("error: kmalloc fail in reg_init\n");\r
 719                 return NULL;\r
 720         }\r
 721 \r
 722         if (size > pservice->reg_size) {\r
 723                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 724                 size = pservice->reg_size;\r
 725         }\r
 726         reg->session = session;\r
 727         reg->type = session->type;\r
 728         reg->size = size;\r
 729         reg->freq = VPU_FREQ_DEFAULT;\r
 730         reg->reg = (unsigned long *)&reg[1];\r
 731         INIT_LIST_HEAD(&reg->session_link);\r
 732         INIT_LIST_HEAD(&reg->status_link);\r
 733 \r
 734 #if defined(CONFIG_VCODEC_MMU)    \r
 735     INIT_LIST_HEAD(&reg->mem_region_list);\r
 736 #endif    \r
 737 \r
 738         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 739                 pr_err("error: copy_from_user failed in reg_init\n");\r
 740                 kfree(reg);\r
 741                 return NULL;\r
 742         }\r
 743 \r
 744 #if defined(CONFIG_VCODEC_MMU)\r
 745     if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
 746         pr_err("error: translate reg address failed\n");\r
 747         kfree(reg);\r
 748         return NULL;\r
 749     }\r
 750 #endif\r
 751 \r
 752         mutex_lock(&pservice->lock);\r
 753         list_add_tail(&reg->status_link, &pservice->waiting);\r
 754         list_add_tail(&reg->session_link, &session->waiting);\r
 755         mutex_unlock(&pservice->lock);\r
 756 \r
 757         if (pservice->auto_freq) {\r
 758                 if (!soc_is_rk2928g()) {\r
 759                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 760                                 if (reg_check_rmvb_wmv(reg)) {\r
 761                                         reg->freq = VPU_FREQ_200M;\r
 762                                 } else if (reg_check_avc(reg)) {\r
 763                     if (reg_probe_width(reg) > 3200) {\r
 764                         // raise frequency for 4k avc.\r
 765                         reg->freq = VPU_FREQ_500M;\r
 766                     }\r
 767                 } else {\r
 768                                         if (reg_check_interlace(reg)) {\r
 769                                                 reg->freq = VPU_FREQ_400M;\r
 770                                         }\r
 771                                 }\r
 772                         }\r
 773                         if (reg->type == VPU_PP) {\r
 774                                 reg->freq = VPU_FREQ_400M;\r
 775                         }\r
 776                 }\r
 777         }\r
 778 \r
 779         return reg;\r
 780 }\r
 781 \r
 782 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 783 {\r
 784 #if defined(CONFIG_VCODEC_MMU)    \r
 785     struct vcodec_mem_region *mem_region = NULL, *n;\r
 786 #endif\r
 787     \r
 788     list_del_init(&reg->session_link);\r
 789     list_del_init(&reg->status_link);\r
 790     if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 791     if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 792     \r
 793 #if defined(CONFIG_VCODEC_MMU)\r
 794     // release memory region attach to this registers table.\r
 795     list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 796         ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
 797         ion_free(pservice->ion_client, mem_region->hdl);\r
 798         list_del_init(&mem_region->reg_lnk);\r
 799         kfree(mem_region);\r
 800     }\r
 801 #endif    \r
 802     \r
 803     kfree(reg);\r
 804 }\r
 805 \r
 806 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 807 {\r
 808     list_del_init(&reg->status_link);\r
 809         list_add_tail(&reg->status_link, &pservice->running);\r
 810 \r
 811         list_del_init(&reg->session_link);\r
 812         list_add_tail(&reg->session_link, &reg->session->running);\r
 813 }\r
 814 \r
 815 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 816 {\r
 817         int i;\r
 818         u32 *dst = (u32 *)&reg->reg[0];\r
 819         for (i = 0; i < count; i++)\r
 820         *dst++ = *src++;\r
 821 }\r
 822 \r
 823 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 824 {\r
 825     int irq_reg = -1;\r
 826         list_del_init(&reg->status_link);\r
 827         list_add_tail(&reg->status_link, &pservice->done);\r
 828 \r
 829         list_del_init(&reg->session_link);\r
 830         list_add_tail(&reg->session_link, &reg->session->done);\r
 831 \r
 832         switch (reg->type) {\r
 833         case VPU_ENC : {\r
 834                 pservice->reg_codec = NULL;\r
 835                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 836                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 837                 break;\r
 838         }\r
 839         case VPU_DEC : {\r
 840         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 841                 pservice->reg_codec = NULL;\r
 842                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 843                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 844                 break;\r
 845         }\r
 846         case VPU_PP : {\r
 847                 pservice->reg_pproc = NULL;\r
 848                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 849                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 850                 break;\r
 851         }\r
 852         case VPU_DEC_PP : {\r
 853                 pservice->reg_codec = NULL;\r
 854                 pservice->reg_pproc = NULL;\r
 855                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 856                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 857                 break;\r
 858         }\r
 859         default : {\r
 860                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 861                 break;\r
 862         }\r
 863         }\r
 864 \r
 865     if (irq_reg != -1) {\r
 866         reg->reg[irq_reg] = pservice->irq_status;\r
 867     }\r
 868 \r
 869         atomic_sub(1, &reg->session->task_running);\r
 870         atomic_sub(1, &pservice->total_running);\r
 871         wake_up(&reg->session->wait);\r
 872 }\r
 873 \r
 874 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 875 {\r
 876         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 877         if (curr == reg->freq) {\r
 878                 return ;\r
 879         }\r
 880         atomic_set(&pservice->freq_status, reg->freq);\r
 881         switch (reg->freq) {\r
 882         case VPU_FREQ_200M : {\r
 883                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 884                 //printk("default: 200M\n");\r
 885         } break;\r
 886         case VPU_FREQ_266M : {\r
 887                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 888                 //printk("default: 266M\n");\r
 889         } break;\r
 890         case VPU_FREQ_300M : {\r
 891                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 892                 //printk("default: 300M\n");\r
 893         } break;\r
 894         case VPU_FREQ_400M : {\r
 895                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 896                 //printk("default: 400M\n");\r
 897         } break;\r
 898     case VPU_FREQ_500M : {\r
 899         clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 900     } break;\r
 901     case VPU_FREQ_600M : {\r
 902         clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 903     } break;\r
 904         default : {\r
 905                 if (soc_is_rk2928g()) {\r
 906                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 907                 } else {\r
 908                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 909                 }\r
 910                 //printk("default: 300M\n");\r
 911         } break;\r
 912         }\r
 913 }\r
 914 \r
 915 #if HEVC_SIM_ENABLE\r
 916 static void simulate_start(struct vpu_service_info *pservice);\r
 917 #endif\r
 918 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 919 {\r
 920         int i;\r
 921         u32 *src = (u32 *)&reg->reg[0];\r
 922         atomic_add(1, &pservice->total_running);\r
 923         atomic_add(1, &reg->session->task_running);\r
 924         if (pservice->auto_freq) {\r
 925                 vpu_service_set_freq(pservice, reg);\r
 926         }\r
 927         switch (reg->type) {\r
 928         case VPU_ENC : {\r
 929                 int enc_count = pservice->hw_info->enc_reg_num;\r
 930                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 931 #if 0\r
 932                 if (pservice->bug_dec_addr) {\r
 933 #if !defined(CONFIG_ARCH_RK319X)\r
 934                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 935 #endif\r
 936                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 937                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 938 #if !defined(CONFIG_ARCH_RK319X)\r
 939                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 940 #endif\r
 941                 }\r
 942 #endif\r
 943                 pservice->reg_codec = reg;\r
 944 \r
 945                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 946 \r
 947                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 948                         dst[i] = src[i];\r
 949 \r
 950                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 951                         dst[i] = src[i];\r
 952 \r
 953                 dsb();\r
 954 \r
 955                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 956                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 957 \r
 958 #if VPU_SERVICE_SHOW_TIME\r
 959                 do_gettimeofday(&enc_start);\r
 960 #endif\r
 961 \r
 962         } break;\r
 963         case VPU_DEC : {\r
 964                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 965 \r
 966                 pservice->reg_codec = reg;\r
 967 \r
 968         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 969                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 970                                 dst[i] = src[i];\r
 971         } else {\r
 972             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 973                                 dst[i] = src[i];\r
 974             }\r
 975                 }\r
 976 \r
 977                 dsb();\r
 978 \r
 979                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 980                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 981                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 982                 } else {\r
 983                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 984                 }\r
 985 \r
 986         dsb();\r
 987         dmb();\r
 988 \r
 989 #if VPU_SERVICE_SHOW_TIME\r
 990                 do_gettimeofday(&dec_start);\r
 991 #endif\r
 992 \r
 993         } break;\r
 994         case VPU_PP : {\r
 995                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 996                 pservice->reg_pproc = reg;\r
 997 \r
 998                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 999 \r
1000                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1001                         dst[i] = src[i];\r
1002 \r
1003                 dsb();\r
1004 \r
1005                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1006 \r
1007 #if VPU_SERVICE_SHOW_TIME\r
1008                 do_gettimeofday(&pp_start);\r
1009 #endif\r
1010 \r
1011         } break;\r
1012         case VPU_DEC_PP : {\r
1013                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1014                 pservice->reg_codec = reg;\r
1015                 pservice->reg_pproc = reg;\r
1016 \r
1017                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1018                         dst[i] = src[i];\r
1019 \r
1020                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1021                 dsb();\r
1022 \r
1023                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1024                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1025                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1026 \r
1027 #if VPU_SERVICE_SHOW_TIME\r
1028                 do_gettimeofday(&dec_start);\r
1029 #endif\r
1030 \r
1031         } break;\r
1032         default : {\r
1033                 pr_err("error: unsupport session type %d", reg->type);\r
1034                 atomic_sub(1, &pservice->total_running);\r
1035                 atomic_sub(1, &reg->session->task_running);\r
1036                 break;\r
1037         }\r
1038         }\r
1039 \r
1040 #if HEVC_SIM_ENABLE\r
1041     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1042         simulate_start(pservice);\r
1043     }\r
1044 #endif\r
1045 }\r
1046 \r
1047 static void try_set_reg(struct vpu_service_info *pservice)\r
1048 {\r
1049         // first get reg from reg list\r
1050         if (!list_empty(&pservice->waiting)) {\r
1051                 int can_set = 0;\r
1052                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1053 \r
1054                 vpu_service_power_on(pservice);\r
1055 \r
1056                 switch (reg->type) {\r
1057                 case VPU_ENC : {\r
1058                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1059                                 can_set = 1;\r
1060                 } break;\r
1061                 case VPU_DEC : {\r
1062                         if (NULL == pservice->reg_codec)\r
1063                                 can_set = 1;\r
1064                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1065                                 can_set = 0;\r
1066                         }\r
1067                 } break;\r
1068                 case VPU_PP : {\r
1069                         if (NULL == pservice->reg_codec) {\r
1070                                 if (NULL == pservice->reg_pproc)\r
1071                                         can_set = 1;\r
1072                         } else {\r
1073                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1074                                         can_set = 1;\r
1075                                 // can not charge frequency when vpu is working\r
1076                                 if (pservice->auto_freq) {\r
1077                                         can_set = 0;\r
1078                                 }\r
1079                         }\r
1080                 } break;\r
1081                 case VPU_DEC_PP : {\r
1082                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1083                                 can_set = 1;\r
1084                         } break;\r
1085                 default : {\r
1086                         printk("undefined reg type %d\n", reg->type);\r
1087                 } break;\r
1088                 }\r
1089                 if (can_set) {\r
1090                         reg_from_wait_to_run(pservice, reg);\r
1091                         reg_copy_to_hw(pservice, reg);\r
1092                 }\r
1093         }\r
1094 }\r
1095 \r
1096 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1097 {\r
1098         int ret = 0;\r
1099         switch (reg->type) {\r
1100         case VPU_ENC : {\r
1101                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1102                         ret = -EFAULT;\r
1103                 break;\r
1104         }\r
1105         case VPU_DEC : {\r
1106         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1107                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1108                         ret = -EFAULT;\r
1109                 break;\r
1110         }\r
1111         case VPU_PP : {\r
1112                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1113                         ret = -EFAULT;\r
1114                 break;\r
1115         }\r
1116         case VPU_DEC_PP : {\r
1117                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1118                         ret = -EFAULT;\r
1119                 break;\r
1120         }\r
1121         default : {\r
1122                 ret = -EFAULT;\r
1123                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1124                 break;\r
1125         }\r
1126         }\r
1127         reg_deinit(pservice, reg);\r
1128         return ret;\r
1129 }\r
1130 \r
1131 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1132 {\r
1133     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1134         vpu_session *session = (vpu_session *)filp->private_data;\r
1135         if (NULL == session) {\r
1136                 return -EINVAL;\r
1137         }\r
1138 \r
1139         switch (cmd) {\r
1140         case VPU_IOC_SET_CLIENT_TYPE : {\r
1141                 session->type = (VPU_CLIENT_TYPE)arg;\r
1142                 break;\r
1143         }\r
1144         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1145                 vpu_request req;\r
1146                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1147                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1148                         return -EFAULT;\r
1149                 } else {\r
1150                         if (VPU_ENC != session->type) {\r
1151                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1152                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1153                                         return -EFAULT;\r
1154                                 }\r
1155                         } else {\r
1156                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1157                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1158                                         return -EFAULT;\r
1159                                 }\r
1160                         }\r
1161                 }\r
1162 \r
1163                 break;\r
1164         }\r
1165         case VPU_IOC_SET_REG : {\r
1166                 vpu_request req;\r
1167                 vpu_reg *reg;\r
1168                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1169                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1170                         return -EFAULT;\r
1171                 }\r
1172                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1173                 if (NULL == reg) {\r
1174                         return -EFAULT;\r
1175                 } else {\r
1176                         mutex_lock(&pservice->lock);\r
1177                         try_set_reg(pservice);\r
1178                         mutex_unlock(&pservice->lock);\r
1179                 }\r
1180 \r
1181                 break;\r
1182         }\r
1183         case VPU_IOC_GET_REG : {\r
1184                 vpu_request req;\r
1185                 vpu_reg *reg;\r
1186                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1187                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1188                         return -EFAULT;\r
1189                 } else {\r
1190                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1191                         if (!list_empty(&session->done)) {\r
1192                                 if (ret < 0) {\r
1193                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1194                                 }\r
1195                                 ret = 0;\r
1196                         } else {\r
1197                                 if (unlikely(ret < 0)) {\r
1198                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1199                                 } else if (0 == ret) {\r
1200                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1201                                         ret = -ETIMEDOUT;\r
1202                                 }\r
1203                         }\r
1204                         if (ret < 0) {\r
1205                                 int task_running = atomic_read(&session->task_running);\r
1206                                 mutex_lock(&pservice->lock);\r
1207                                 vpu_service_dump(pservice);\r
1208                                 if (task_running) {\r
1209                                         atomic_set(&session->task_running, 0);\r
1210                                         atomic_sub(task_running, &pservice->total_running);\r
1211                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1212                                         vpu_reset(pservice);\r
1213                                         printk("done\n");\r
1214                                 }\r
1215                                 vpu_service_session_clear(pservice, session);\r
1216                                 mutex_unlock(&pservice->lock);\r
1217                                 return ret;\r
1218                         }\r
1219                 }\r
1220                 mutex_lock(&pservice->lock);\r
1221                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1222                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1223                 mutex_unlock(&pservice->lock);\r
1224                 break;\r
1225         }\r
1226         default : {\r
1227                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1228                 break;\r
1229         }\r
1230         }\r
1231 \r
1232         return 0;\r
1233 }\r
1234 \r
1235 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1236 {\r
1237         int ret = -EINVAL, i = 0;\r
1238         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1239         u32 enc_id = *tmp;\r
1240 \r
1241 #if HEVC_SIM_ENABLE\r
1242     /// temporary, hevc driver test.\r
1243     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1244         p->hw_info = &vpu_hw_set[2];\r
1245         return 0;\r
1246     }\r
1247 #endif\r
1248 \r
1249         enc_id = (enc_id >> 16) & 0xFFFF;\r
1250         pr_info("checking hw id %x\n", enc_id);\r
1251     p->hw_info = NULL;\r
1252         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1253                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1254                         p->hw_info = &vpu_hw_set[i];\r
1255                         ret = 0;\r
1256                         break;\r
1257                 }\r
1258         }\r
1259         iounmap((void *)tmp);\r
1260         return ret;\r
1261 }\r
1262 \r
1263 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1264 {\r
1265     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1266         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1267         if (NULL == session) {\r
1268                 pr_err("error: unable to allocate memory for vpu_session.");\r
1269                 return -ENOMEM;\r
1270         }\r
1271 \r
1272         session->type   = VPU_TYPE_BUTT;\r
1273         session->pid    = current->pid;\r
1274         INIT_LIST_HEAD(&session->waiting);\r
1275         INIT_LIST_HEAD(&session->running);\r
1276         INIT_LIST_HEAD(&session->done);\r
1277         INIT_LIST_HEAD(&session->list_session);\r
1278         init_waitqueue_head(&session->wait);\r
1279         atomic_set(&session->task_running, 0);\r
1280         mutex_lock(&pservice->lock);\r
1281         list_add_tail(&session->list_session, &pservice->session);\r
1282         filp->private_data = (void *)session;\r
1283         mutex_unlock(&pservice->lock);\r
1284 \r
1285         pr_debug("dev opened\n");\r
1286         return nonseekable_open(inode, filp);\r
1287 }\r
1288 \r
1289 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1290 {\r
1291     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1292         int task_running;\r
1293         vpu_session *session = (vpu_session *)filp->private_data;\r
1294         if (NULL == session)\r
1295                 return -EINVAL;\r
1296 \r
1297         task_running = atomic_read(&session->task_running);\r
1298         if (task_running) {\r
1299                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1300                 msleep(50);\r
1301         }\r
1302         wake_up(&session->wait);\r
1303 \r
1304         mutex_lock(&pservice->lock);\r
1305         /* remove this filp from the asynchronusly notified filp's */\r
1306         list_del_init(&session->list_session);\r
1307         vpu_service_session_clear(pservice, session);\r
1308         kfree(session);\r
1309         filp->private_data = NULL;\r
1310         mutex_unlock(&pservice->lock);\r
1311 \r
1312     pr_debug("dev closed\n");\r
1313         return 0;\r
1314 }\r
1315 \r
1316 static const struct file_operations vpu_service_fops = {\r
1317         .unlocked_ioctl = vpu_service_ioctl,\r
1318         .open           = vpu_service_open,\r
1319         .release        = vpu_service_release,\r
1320         //.fasync       = vpu_service_fasync,\r
1321 };\r
1322 \r
1323 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1324 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1325 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1326 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1327 static void get_hw_info(struct vpu_service_info *pservice);\r
1328 \r
1329 #if HEVC_SIM_ENABLE\r
1330 static void simulate_work(struct work_struct *work_s)\r
1331 {\r
1332     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1333     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1334     vpu_device *dev = &pservice->dec_dev;\r
1335 \r
1336     if (!list_empty(&pservice->running)) {\r
1337         atomic_add(1, &dev->irq_count_codec);\r
1338         vdpu_isr(0, (void*)pservice);\r
1339     } else {\r
1340         //simulate_start(pservice);\r
1341         pr_err("empty running queue\n");\r
1342     }\r
1343 }\r
1344 \r
1345 static void simulate_init(struct vpu_service_info *pservice)\r
1346 {\r
1347     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1348 }\r
1349 \r
1350 static void simulate_start(struct vpu_service_info *pservice)\r
1351 {\r
1352     cancel_delayed_work_sync(&pservice->power_off_work);\r
1353     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1354 }\r
1355 #endif\r
1356 \r
1357 #if HEVC_TEST_ENABLE\r
1358 static int hevc_test_case0(vpu_service_info *pservice);\r
1359 #endif\r
1360 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1361 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1362 #endif\r
1363 static int vcodec_probe(struct platform_device *pdev)\r
1364 {\r
1365     int ret = 0;\r
1366     struct resource *res = NULL;\r
1367     struct device *dev = &pdev->dev;\r
1368     void __iomem *regs = NULL;\r
1369     struct device_node *np = pdev->dev.of_node;\r
1370     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1371     char *prop = (char*)dev_name(dev);\r
1372 #if defined(CONFIG_VCODEC_MMU)\r
1373     struct device *mmu_dev = NULL;\r
1374     char mmu_dev_dts_name[40];\r
1375 #endif\r
1376 \r
1377     pr_info("probe device %s\n", dev_name(dev));\r
1378 \r
1379     of_property_read_string(np, "name", (const char**)&prop);\r
1380     dev_set_name(dev, prop);\r
1381 \r
1382     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1383         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1384     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1385         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1386     } else {\r
1387         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1388         return -1;\r
1389     }\r
1390 \r
1391     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1392     INIT_LIST_HEAD(&pservice->waiting);\r
1393     INIT_LIST_HEAD(&pservice->running);\r
1394     INIT_LIST_HEAD(&pservice->done);\r
1395     INIT_LIST_HEAD(&pservice->session);\r
1396     mutex_init(&pservice->lock);\r
1397     pservice->reg_codec = NULL;\r
1398     pservice->reg_pproc = NULL;\r
1399     atomic_set(&pservice->total_running, 0);\r
1400     pservice->enabled = false;\r
1401 \r
1402     pservice->dev = dev;\r
1403 \r
1404     if (0 > vpu_get_clk(pservice)) {\r
1405         goto err;\r
1406     }\r
1407 \r
1408     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1409 \r
1410     vpu_service_power_on(pservice);\r
1411 \r
1412     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1413 \r
1414     regs = devm_ioremap_resource(pservice->dev, res);\r
1415     if (IS_ERR(regs)) {\r
1416         ret = PTR_ERR(regs);\r
1417         goto err;\r
1418     }\r
1419 \r
1420     ret = vpu_service_check_hw(pservice, res->start);\r
1421     if (ret < 0) {\r
1422         pr_err("error: hw info check faild\n");\r
1423         goto err;\r
1424     }\r
1425 \r
1426     /// define regs address.\r
1427     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1428     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1429 \r
1430     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1431 \r
1432     pservice->reg_size   = pservice->dec_dev.iosize;\r
1433 \r
1434     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1435         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1436         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1437 \r
1438         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1439 \r
1440         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1441 \r
1442         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1443         if (pservice->irq_enc < 0) {\r
1444             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1445             ret = -ENXIO;\r
1446             goto err;\r
1447         }\r
1448 \r
1449         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1450         if (ret) {\r
1451             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1452             goto err;\r
1453         }\r
1454     }\r
1455 \r
1456     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1457     if (pservice->irq_dec < 0) {\r
1458         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1459         ret = -ENXIO;\r
1460         goto err;\r
1461     }\r
1462 \r
1463     /* get the IRQ line */\r
1464     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1465     if (ret) {\r
1466         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1467         goto err;\r
1468     }\r
1469 \r
1470     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1471     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1472     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1473     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1474 \r
1475     /// create device\r
1476     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1477     if (ret) {\r
1478         dev_err(dev, "alloc dev_t failed\n");\r
1479         goto err;\r
1480     }\r
1481 \r
1482     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1483 \r
1484     pservice->cdev.owner = THIS_MODULE;\r
1485     pservice->cdev.ops = &vpu_service_fops;\r
1486 \r
1487     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1488 \r
1489     if (ret) {\r
1490         dev_err(dev, "add dev_t failed\n");\r
1491         goto err;\r
1492     }\r
1493 \r
1494     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1495 \r
1496     if (IS_ERR(pservice->cls)) {\r
1497         ret = PTR_ERR(pservice->cls);\r
1498         dev_err(dev, "class_create err:%d\n", ret);\r
1499         goto err;\r
1500     }\r
1501 \r
1502     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1503 \r
1504     platform_set_drvdata(pdev, pservice);\r
1505 \r
1506     get_hw_info(pservice);\r
1507 \r
1508 \r
1509 #ifdef CONFIG_DEBUG_FS\r
1510     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1511     \r
1512     if (pservice->debugfs_dir == NULL) {\r
1513         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1514     }\r
1515 \r
1516     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1517                     pservice->debugfs_dir, pservice,\r
1518                     &debug_vcodec_fops);\r
1519 #endif\r
1520 \r
1521 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1522     pservice->ion_client = rockchip_ion_client_create("vpu");\r
1523     if (IS_ERR(pservice->ion_client)) {\r
1524         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1525         return PTR_ERR(pservice->ion_client);\r
1526     } else {\r
1527         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1528     }\r
1529     \r
1530     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1531         sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1532     } else {\r
1533         sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1534     }\r
1535     \r
1536     mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1537     \r
1538     if (mmu_dev) {\r
1539         platform_set_sysmmu(mmu_dev, pservice->dev);\r
1540         iovmm_activate(pservice->dev);\r
1541     }\r
1542 #endif\r
1543 \r
1544     vpu_service_power_off(pservice);\r
1545     pr_info("init success\n");\r
1546 \r
1547 #if HEVC_SIM_ENABLE\r
1548     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1549         simulate_init(pservice);\r
1550     }\r
1551 #endif\r
1552 \r
1553 #if HEVC_TEST_ENABLE\r
1554     hevc_test_case0(pservice);\r
1555 #endif\r
1556 \r
1557     return 0;\r
1558 \r
1559 err:\r
1560     pr_info("init failed\n");\r
1561     vpu_service_power_off(pservice);\r
1562     vpu_put_clk(pservice);\r
1563     wake_lock_destroy(&pservice->wake_lock);\r
1564 \r
1565     if (res) {\r
1566         if (regs) {\r
1567             devm_ioremap_release(&pdev->dev, res);\r
1568         }\r
1569         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1570     }\r
1571 \r
1572     if (pservice->irq_enc > 0) {\r
1573         free_irq(pservice->irq_enc, (void *)pservice);\r
1574     }\r
1575 \r
1576     if (pservice->irq_dec > 0) {\r
1577         free_irq(pservice->irq_dec, (void *)pservice);\r
1578     }\r
1579 \r
1580     if (pservice->child_dev) {\r
1581         device_destroy(pservice->cls, pservice->dev_t);\r
1582         cdev_del(&pservice->cdev);\r
1583         unregister_chrdev_region(pservice->dev_t, 1);\r
1584     }\r
1585 \r
1586     if (pservice->cls) {\r
1587         class_destroy(pservice->cls);\r
1588     }\r
1589 \r
1590     return ret;\r
1591 }\r
1592 \r
1593 static int vcodec_remove(struct platform_device *pdev)\r
1594 {\r
1595     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1596     struct resource *res;\r
1597 \r
1598     device_destroy(pservice->cls, pservice->dev_t);\r
1599     class_destroy(pservice->cls);\r
1600     cdev_del(&pservice->cdev);\r
1601     unregister_chrdev_region(pservice->dev_t, 1);\r
1602 \r
1603     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1604     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1605     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1606     devm_ioremap_release(&pdev->dev, res);\r
1607     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1608     vpu_put_clk(pservice);\r
1609     wake_lock_destroy(&pservice->wake_lock);\r
1610     \r
1611 #ifdef CONFIG_DEBUG_FS\r
1612     if (pservice->debugfs_file_regs) {\r
1613         debugfs_remove(pservice->debugfs_file_regs);\r
1614     }\r
1615 \r
1616     if (pservice->debugfs_dir) {\r
1617         debugfs_remove(pservice->debugfs_dir);\r
1618     }\r
1619 #endif\r
1620 \r
1621     return 0;\r
1622 }\r
1623 \r
1624 #if defined(CONFIG_OF)\r
1625 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1626     {.compatible = "vpu_service",},\r
1627     {.compatible = "rockchip,hevc_service",},\r
1628     {},\r
1629 };\r
1630 #endif\r
1631 \r
1632 static struct platform_driver vcodec_driver = {\r
1633     .probe     = vcodec_probe,\r
1634     .remove        = vcodec_remove,\r
1635     .driver = {\r
1636         .name = "vcodec",\r
1637         .owner = THIS_MODULE,\r
1638 #if defined(CONFIG_OF)\r
1639         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1640 #endif\r
1641     },\r
1642 };\r
1643 \r
1644 static void get_hw_info(struct vpu_service_info *pservice)\r
1645 {\r
1646     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1647     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1648 \r
1649     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1650         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1651         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1652     \r
1653         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1654         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1655         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1656             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1657         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1658         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1659         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1660         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1661         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1662         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1663     \r
1664         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1665             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1666         } else {\r
1667             dec->maxDecPicWidth = 4096;\r
1668         }\r
1669     \r
1670         /* 2nd Config register */\r
1671         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1672         if (dec->refBufSupport) {\r
1673             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1674                 dec->refBufSupport |= 2;\r
1675             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1676                 dec->refBufSupport |= 4;\r
1677         }\r
1678         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1679         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1680         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1681         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1682     \r
1683         /* JPEG xtensions */\r
1684         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1685             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1686         } else {\r
1687             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1688         }\r
1689     \r
1690         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1691             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1692         } else {\r
1693             dec->rvSupport = RV_NOT_SUPPORTED;\r
1694         }\r
1695     \r
1696         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1697     \r
1698         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1699             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1700         }\r
1701     \r
1702         /// invalidate fuse register value in rk319x vpu and following.\r
1703         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1704             VPUHwFuseStatus_t hwFuseSts;\r
1705             /* Decoder fuse configuration */\r
1706             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1707     \r
1708             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1709             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1710             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1711             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1712             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1713             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1714             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1715             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1716             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1717             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1718             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1719             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1720             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1721             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1722     \r
1723             /* check max. decoder output width */\r
1724     \r
1725             if (fuseReg & 0x8000U)\r
1726                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1727             else if (fuseReg & 0x4000U)\r
1728                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1729             else if (fuseReg & 0x2000U)\r
1730                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1731             else if (fuseReg & 0x1000U)\r
1732                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1733             else    /* remove warning */\r
1734                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1735     \r
1736             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1737     \r
1738             /* Pp configuration */\r
1739             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1740     \r
1741             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1742                 dec->ppSupport = 1;\r
1743                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1744                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1745                 dec->ppConfig = configReg;\r
1746             } else {\r
1747                 dec->ppSupport = 0;\r
1748                 dec->maxPpOutPicWidth = 0;\r
1749                 dec->ppConfig = 0;\r
1750             }\r
1751     \r
1752             /* check the HW versio */\r
1753             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1754                 /* Pp configuration */\r
1755                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1756     \r
1757                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1758                     /* Pp fuse configuration */\r
1759                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1760     \r
1761                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1762                         hwFuseSts.ppSupportFuse = 1;\r
1763                         /* check max. pp output width */\r
1764                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1765                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1766                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1767                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1768                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1769                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1770                     } else {\r
1771                         hwFuseSts.ppSupportFuse = 0;\r
1772                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1773                         hwFuseSts.ppConfigFuse = 0;\r
1774                     }\r
1775                 } else {\r
1776                     hwFuseSts.ppSupportFuse = 0;\r
1777                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1778                     hwFuseSts.ppConfigFuse = 0;\r
1779                 }\r
1780     \r
1781                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1782                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1783                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1784                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1785                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1786                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1787                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1788                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1789                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1790                     dec->jpegSupport = JPEG_BASELINE;\r
1791                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1792                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1793                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1794                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1795                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1796                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1797     \r
1798                 /* check the pp config vs fuse status */\r
1799                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1800                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1801                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1802                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1803                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1804     \r
1805                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1806                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1807                 }\r
1808                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1809                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1810                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1811                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1812                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1813             }\r
1814         }\r
1815     \r
1816         configReg = pservice->enc_dev.hwregs[63];\r
1817         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1818         enc->h264Enabled = (configReg >> 27) & 1;\r
1819         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1820         enc->jpegEnabled = (configReg >> 25) & 1;\r
1821         enc->vsEnabled = (configReg >> 24) & 1;\r
1822         enc->rgbEnabled = (configReg >> 28) & 1;\r
1823         //enc->busType = (configReg >> 20) & 15;\r
1824         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1825         //enc->busWidth = (configReg >> 12) & 15;\r
1826         enc->reg_size = pservice->reg_size;\r
1827         enc->reserv[0] = enc->reserv[1] = 0;\r
1828     \r
1829         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1830         if (pservice->auto_freq) {\r
1831             pr_info("vpu_service set to auto frequency mode\n");\r
1832             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1833         }\r
1834         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1835         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1836     } else {\r
1837         // disable frequency switch in hevc.\r
1838         pservice->auto_freq = false;\r
1839     }\r
1840 }\r
1841 \r
1842 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1843 {\r
1844     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1845     vpu_device *dev = &pservice->dec_dev;\r
1846     u32 raw_status;\r
1847     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1848 \r
1849         pr_debug("dec_irq\n");\r
1850 \r
1851         if (irq_status & DEC_INTERRUPT_BIT) {\r
1852                 pr_debug("dec_isr dec %x\n", irq_status);\r
1853                 if ((irq_status & 0x40001) == 0x40001)\r
1854                 {\r
1855                         do {\r
1856                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1857                         } while ((irq_status & 0x40001) == 0x40001);\r
1858                 }\r
1859 \r
1860                 /* clear dec IRQ */\r
1861         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1862             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1863         } else {\r
1864             /*writel(irq_status \r
1865               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1866                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1867 \r
1868             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1869         }\r
1870                 atomic_add(1, &dev->irq_count_codec);\r
1871         }\r
1872 \r
1873     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1874         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1875         if (irq_status & PP_INTERRUPT_BIT) {\r
1876             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1877             /* clear pp IRQ */\r
1878             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1879             atomic_add(1, &dev->irq_count_pp);\r
1880         }\r
1881     }\r
1882 \r
1883     pservice->irq_status = raw_status;\r
1884 \r
1885         return IRQ_WAKE_THREAD;\r
1886 }\r
1887 \r
1888 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1889 {\r
1890     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1891     vpu_device *dev = &pservice->dec_dev;\r
1892 \r
1893         mutex_lock(&pservice->lock);\r
1894         if (atomic_read(&dev->irq_count_codec)) {\r
1895 #if VPU_SERVICE_SHOW_TIME\r
1896                 do_gettimeofday(&dec_end);\r
1897                 pr_info("dec task: %ld ms\n",\r
1898                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1899                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1900 #endif\r
1901                 atomic_sub(1, &dev->irq_count_codec);\r
1902                 if (NULL == pservice->reg_codec) {\r
1903                         pr_err("error: dec isr with no task waiting\n");\r
1904                 } else {\r
1905                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1906                 }\r
1907         }\r
1908 \r
1909         if (atomic_read(&dev->irq_count_pp)) {\r
1910 \r
1911 #if VPU_SERVICE_SHOW_TIME\r
1912                 do_gettimeofday(&pp_end);\r
1913                 printk("pp  task: %ld ms\n",\r
1914                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1915                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1916 #endif\r
1917 \r
1918                 atomic_sub(1, &dev->irq_count_pp);\r
1919                 if (NULL == pservice->reg_pproc) {\r
1920                         pr_err("error: pp isr with no task waiting\n");\r
1921                 } else {\r
1922                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1923                 }\r
1924         }\r
1925         try_set_reg(pservice);\r
1926         mutex_unlock(&pservice->lock);\r
1927         return IRQ_HANDLED;\r
1928 }\r
1929 \r
1930 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1931 {\r
1932         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1933     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1934     vpu_device *dev = &pservice->enc_dev;\r
1935         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1936 \r
1937         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1938 \r
1939 #if VPU_SERVICE_SHOW_TIME\r
1940         do_gettimeofday(&enc_end);\r
1941         pr_info("enc task: %ld ms\n",\r
1942                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1943                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1944 #endif\r
1945     \r
1946         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1947                 /* clear enc IRQ */\r
1948                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1949                 atomic_add(1, &dev->irq_count_codec);\r
1950         }\r
1951     \r
1952     pservice->irq_status = irq_status;\r
1953 \r
1954         return IRQ_WAKE_THREAD;\r
1955 }\r
1956 \r
1957 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1958 {\r
1959         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1960     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1961     vpu_device *dev = &pservice->enc_dev;\r
1962 \r
1963         mutex_lock(&pservice->lock);\r
1964         if (atomic_read(&dev->irq_count_codec)) {\r
1965                 atomic_sub(1, &dev->irq_count_codec);\r
1966                 if (NULL == pservice->reg_codec) {\r
1967                         pr_err("error: enc isr with no task waiting\n");\r
1968                 } else {\r
1969                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1970                 }\r
1971         }\r
1972         try_set_reg(pservice);\r
1973         mutex_unlock(&pservice->lock);\r
1974         return IRQ_HANDLED;\r
1975 }\r
1976 \r
1977 static int __init vcodec_service_init(void)\r
1978 {\r
1979     int ret;\r
1980 \r
1981     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1982         pr_err("Platform device register failed (%d).\n", ret);\r
1983         return ret;\r
1984     }\r
1985 \r
1986 #ifdef CONFIG_DEBUG_FS\r
1987     vcodec_debugfs_init();\r
1988 #endif\r
1989 \r
1990     return ret;\r
1991 }\r
1992 \r
1993 static void __exit vcodec_service_exit(void)\r
1994 {\r
1995 #ifdef CONFIG_DEBUG_FS\r
1996     vcodec_debugfs_exit();\r
1997 #endif\r
1998 \r
1999         platform_driver_unregister(&vcodec_driver);\r
2000 }\r
2001 \r
2002 module_init(vcodec_service_init);\r
2003 module_exit(vcodec_service_exit);\r
2004 \r
2005 #ifdef CONFIG_DEBUG_FS\r
2006 #include <linux/seq_file.h>\r
2007 \r
2008 static int vcodec_debugfs_init()\r
2009 {\r
2010     parent = debugfs_create_dir("vcodec", NULL);\r
2011     if (!parent)\r
2012         return -1;\r
2013 \r
2014     return 0;\r
2015 }\r
2016 \r
2017 static void vcodec_debugfs_exit()\r
2018 {\r
2019     debugfs_remove(parent);\r
2020 }\r
2021 \r
2022 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2023 {\r
2024     return debugfs_create_dir(dirname, parent);\r
2025 }\r
2026 \r
2027 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2028 {\r
2029         struct vpu_service_info *pservice = s->private;\r
2030     unsigned int i, n;\r
2031         vpu_reg *reg, *reg_tmp;\r
2032         vpu_session *session, *session_tmp;\r
2033 \r
2034         mutex_lock(&pservice->lock);\r
2035         vpu_service_power_on(pservice);\r
2036     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2037         seq_printf(s, "\nENC Registers:\n");\r
2038         n = pservice->enc_dev.iosize >> 2;\r
2039         for (i = 0; i < n; i++) {\r
2040             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2041         }\r
2042     }\r
2043         seq_printf(s, "\nDEC Registers:\n");\r
2044         n = pservice->dec_dev.iosize >> 2;\r
2045         for (i = 0; i < n; i++) {\r
2046                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2047         }\r
2048 \r
2049         seq_printf(s, "\nvpu service status:\n");\r
2050         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2051                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2052                 //seq_printf(s, "waiting reg set %d\n");\r
2053                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2054                         seq_printf(s, "waiting register set\n");\r
2055                 }\r
2056                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2057                         seq_printf(s, "running register set\n");\r
2058                 }\r
2059                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2060                         seq_printf(s, "done    register set\n");\r
2061                 }\r
2062         }\r
2063         mutex_unlock(&pservice->lock);\r
2064 \r
2065     return 0;\r
2066 }\r
2067 \r
2068 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2069 {\r
2070         return single_open(file, debug_vcodec_show, inode->i_private);\r
2071 }\r
2072 \r
2073 #endif\r
2074 \r
2075 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2076 #include "hevc_test_inc/pps_00.h"\r
2077 #include "hevc_test_inc/register_00.h"\r
2078 #include "hevc_test_inc/rps_00.h"\r
2079 #include "hevc_test_inc/scaling_list_00.h"\r
2080 #include "hevc_test_inc/stream_00.h"\r
2081 \r
2082 #include "hevc_test_inc/pps_01.h"\r
2083 #include "hevc_test_inc/register_01.h"\r
2084 #include "hevc_test_inc/rps_01.h"\r
2085 #include "hevc_test_inc/scaling_list_01.h"\r
2086 #include "hevc_test_inc/stream_01.h"\r
2087 \r
2088 #include "hevc_test_inc/cabac.h"\r
2089 \r
2090 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2091 \r
2092 static struct ion_client *ion_client = NULL;\r
2093 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2094 {\r
2095         int size = (len+15) & (~15);\r
2096     struct ion_handle *handle;\r
2097         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2098 \r
2099     if (ion_client == NULL) {\r
2100         ion_client = rockchip_ion_client_create("vcodec");\r
2101     }\r
2102 \r
2103     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2104 \r
2105     ptr = ion_map_kernel(ion_client, handle);\r
2106 \r
2107     ion_phys(ion_client, handle, phy, &size);\r
2108 \r
2109         memcpy(ptr, tbl, len);\r
2110 \r
2111         return ptr;\r
2112 }\r
2113 \r
2114 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2115 {\r
2116         int size = (len+15) & (~15);\r
2117     struct ion_handle *handle;\r
2118         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2119 \r
2120     if (ion_client == NULL) {\r
2121         ion_client = rockchip_ion_client_create("vcodec");\r
2122     }\r
2123 \r
2124     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2125 \r
2126     ptr = ion_map_kernel(ion_client, handle);\r
2127 \r
2128     ion_phys(ion_client, handle, phy, &size);\r
2129 \r
2130         return ptr;\r
2131 }\r
2132 \r
2133 #define TEST_CNT    2\r
2134 static int hevc_test_case0(vpu_service_info *pservice)\r
2135 {\r
2136     vpu_session session;\r
2137     vpu_reg *reg; \r
2138     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2139     int testidx = 0;\r
2140     int ret = 0;\r
2141 \r
2142     u8 *pps_tbl[TEST_CNT];\r
2143     u8 *register_tbl[TEST_CNT];\r
2144     u8 *rps_tbl[TEST_CNT];\r
2145     u8 *scaling_list_tbl[TEST_CNT];\r
2146     u8 *stream_tbl[TEST_CNT];\r
2147 \r
2148         int stream_size[2];\r
2149         int pps_size[2];\r
2150         int rps_size[2];\r
2151         int scl_size[2];\r
2152         int cabac_size[2];\r
2153         \r
2154     u32 phy_pps;\r
2155     u32 phy_rps;\r
2156     u32 phy_scl;\r
2157     u32 phy_str;\r
2158     u32 phy_yuv;\r
2159     u32 phy_ref;\r
2160     u32 phy_cabac;\r
2161 \r
2162         volatile u8 *stream_buf;\r
2163         volatile u8 *pps_buf;\r
2164         volatile u8 *rps_buf;\r
2165         volatile u8 *scl_buf;\r
2166         volatile u8 *yuv_buf;\r
2167         volatile u8 *cabac_buf;\r
2168         volatile u8 *ref_buf;\r
2169 \r
2170     u8 *pps;\r
2171     u8 *yuv[2];\r
2172     int i;\r
2173     \r
2174     pps_tbl[0] = pps_00;\r
2175     pps_tbl[1] = pps_01;\r
2176 \r
2177     register_tbl[0] = register_00;\r
2178     register_tbl[1] = register_01;\r
2179     \r
2180     rps_tbl[0] = rps_00;\r
2181     rps_tbl[1] = rps_01;\r
2182     \r
2183     scaling_list_tbl[0] = scaling_list_00;\r
2184     scaling_list_tbl[1] = scaling_list_01;\r
2185 \r
2186     stream_tbl[0] = stream_00;\r
2187     stream_tbl[1] = stream_01;\r
2188 \r
2189     stream_size[0] = sizeof(stream_00);\r
2190     stream_size[1] = sizeof(stream_01);\r
2191 \r
2192         pps_size[0] = sizeof(pps_00);\r
2193         pps_size[1] = sizeof(pps_01);\r
2194 \r
2195         rps_size[0] = sizeof(rps_00);\r
2196         rps_size[1] = sizeof(rps_01);\r
2197 \r
2198         scl_size[0] = sizeof(scaling_list_00);\r
2199         scl_size[1] = sizeof(scaling_list_01);\r
2200         \r
2201         cabac_size[0] = sizeof(Cabac_table);\r
2202         cabac_size[1] = sizeof(Cabac_table);\r
2203 \r
2204     // create session\r
2205     session.pid = current->pid;\r
2206     session.type = VPU_DEC;\r
2207     INIT_LIST_HEAD(&session.waiting);\r
2208         INIT_LIST_HEAD(&session.running);\r
2209         INIT_LIST_HEAD(&session.done);\r
2210         INIT_LIST_HEAD(&session.list_session);\r
2211         init_waitqueue_head(&session.wait);\r
2212         atomic_set(&session.task_running, 0);\r
2213         list_add_tail(&session.list_session, &pservice->session);\r
2214 \r
2215     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2216     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2217 \r
2218         while (testidx < TEST_CNT) {\r
2219         \r
2220         // create registers\r
2221         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2222         if (NULL == reg) {\r
2223             pr_err("error: kmalloc fail in reg_init\n");\r
2224             return -1;\r
2225         }\r
2226 \r
2227 \r
2228         if (size > pservice->reg_size) {\r
2229             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2230             size = pservice->reg_size;\r
2231         }\r
2232         reg->session = &session;\r
2233         reg->type = session.type;\r
2234         reg->size = size;\r
2235         reg->freq = VPU_FREQ_DEFAULT;\r
2236         reg->reg = (unsigned long *)&reg[1];\r
2237         INIT_LIST_HEAD(&reg->session_link);\r
2238         INIT_LIST_HEAD(&reg->status_link);\r
2239 \r
2240         // TODO: stuff registers\r
2241         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2242 \r
2243                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2244                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2245                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2246                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2247                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2248 \r
2249                 pps = pps_buf;\r
2250 \r
2251         // TODO: replace reigster address\r
2252 \r
2253         for (i=0; i<64; i++) {\r
2254             u32 scaling_offset;\r
2255             u32 tmp;\r
2256 \r
2257             scaling_offset = (u32)pps[i*80+74];\r
2258             scaling_offset += (u32)pps[i*80+75] << 8;\r
2259             scaling_offset += (u32)pps[i*80+76] << 16;\r
2260             scaling_offset += (u32)pps[i*80+77] << 24;\r
2261 \r
2262             tmp = phy_scl + scaling_offset;\r
2263 \r
2264             pps[i*80+74] = tmp & 0xff;\r
2265             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2266             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2267             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2268         }\r
2269 \r
2270         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2271 \r
2272         reg->reg[1] = 0x21;\r
2273         reg->reg[4] = phy_str;\r
2274         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2275         reg->reg[6] = phy_cabac;\r
2276         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2277         reg->reg[42] = phy_pps;\r
2278         reg->reg[43] = phy_rps;\r
2279         for (i = 10; i <= 24; i++) {\r
2280             reg->reg[i] = phy_yuv;\r
2281         }\r
2282 \r
2283         mutex_lock(&pservice->lock);\r
2284         list_add_tail(&reg->status_link, &pservice->waiting);\r
2285         list_add_tail(&reg->session_link, &session.waiting);\r
2286         mutex_unlock(&pservice->lock);\r
2287 \r
2288         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2289 \r
2290         // stuff hardware\r
2291         try_set_reg(pservice);\r
2292 \r
2293         // wait for result\r
2294         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2295         if (!list_empty(&session.done)) {\r
2296             if (ret < 0) {\r
2297                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2298             }\r
2299             ret = 0;\r
2300         } else {\r
2301             if (unlikely(ret < 0)) {\r
2302                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2303             } else if (0 == ret) {\r
2304                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2305                 ret = -ETIMEDOUT;\r
2306             }\r
2307         }\r
2308         if (ret < 0) {\r
2309             int task_running = atomic_read(&session.task_running);\r
2310             int n;\r
2311             mutex_lock(&pservice->lock);\r
2312             vpu_service_dump(pservice);\r
2313             if (task_running) {\r
2314                 atomic_set(&session.task_running, 0);\r
2315                 atomic_sub(task_running, &pservice->total_running);\r
2316                 printk("%d task is running but not return, reset hardware...", task_running);\r
2317                 vpu_reset(pservice);\r
2318                 printk("done\n");\r
2319             }\r
2320             vpu_service_session_clear(pservice, &session);\r
2321             mutex_unlock(&pservice->lock);\r
2322 \r
2323             printk("\nDEC Registers:\n");\r
2324                 n = pservice->dec_dev.iosize >> 2;\r
2325                 for (i=0; i<n; i++) {\r
2326                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2327                 }\r
2328 \r
2329             pr_err("test index %d failed\n", testidx);\r
2330             break;\r
2331         } else {\r
2332             pr_info("test index %d success\n", testidx);\r
2333 \r
2334             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2335 \r
2336             for (i=0; i<68; i++) {\r
2337                 if (i % 4 == 0) {\r
2338                     printk("%02d: ", i);\r
2339                 }\r
2340                 printk("%08x ", reg->reg[i]);\r
2341                 if ((i+1) % 4 == 0) {\r
2342                     printk("\n");\r
2343                 }\r
2344             }\r
2345 \r
2346             testidx++;\r
2347         }\r
2348 \r
2349         reg_deinit(pservice, reg);\r
2350     }\r
2351 \r
2352     return 0;\r
2353 }\r
2354 \r
2355 #endif\r
2356 \r