arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <linux/uaccess.h>\r
  41 #include <linux/rockchip/grf.h>\r
  42 \r
  43 #if defined(CONFIG_ION_ROCKCHIP)\r
  44 #include <linux/rockchip_ion.h>\r
  45 #endif\r
  46 \r
  47 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
  48 #define CONFIG_VCODEC_MMU\r
  49 #endif\r
  50 \r
  51 #ifdef CONFIG_VCODEC_MMU\r
  52 #include <linux/rockchip/iovmm.h>\r
  53 #include <linux/rockchip/sysmmu.h>\r
  54 #include <linux/dma-buf.h>\r
  55 #endif\r
  56 \r
  57 #ifdef CONFIG_DEBUG_FS\r
  58 #include <linux/debugfs.h>\r
  59 #endif\r
  60 \r
  61 #if defined(CONFIG_ARCH_RK319X)\r
  62 #include <mach/grf.h>\r
  63 #endif\r
  64 \r
  65 #include "vcodec_service.h"\r
  66 \r
  67 #define HEVC_TEST_ENABLE        0\r
  68 #define HEVC_SIM_ENABLE         0\r
  69 #define VCODEC_CLOCK_ENABLE     1\r
  70 \r
  71 typedef enum {\r
  72         VPU_DEC_ID_9190         = 0x6731,\r
  73         VPU_ID_8270             = 0x8270,\r
  74         VPU_ID_4831             = 0x4831,\r
  75         HEVC_ID                 = 0x6867,\r
  76 } VPU_HW_ID;\r
  77 \r
  78 typedef enum {\r
  79         VPU_DEC_TYPE_9190       = 0,\r
  80         VPU_ENC_TYPE_8270       = 0x100,\r
  81         VPU_ENC_TYPE_4831       ,\r
  82 } VPU_HW_TYPE_E;\r
  83 \r
  84 typedef enum VPU_FREQ {\r
  85         VPU_FREQ_200M,\r
  86         VPU_FREQ_266M,\r
  87         VPU_FREQ_300M,\r
  88         VPU_FREQ_400M,\r
  89         VPU_FREQ_500M,\r
  90         VPU_FREQ_600M,\r
  91         VPU_FREQ_DEFAULT,\r
  92         VPU_FREQ_BUT,\r
  93 } VPU_FREQ;\r
  94 \r
  95 typedef struct {\r
  96         VPU_HW_ID               hw_id;\r
  97         unsigned long           hw_addr;\r
  98         unsigned long           enc_offset;\r
  99         unsigned long           enc_reg_num;\r
 100         unsigned long           enc_io_size;\r
 101         unsigned long           dec_offset;\r
 102         unsigned long           dec_reg_num;\r
 103         unsigned long           dec_io_size;\r
 104 } VPU_HW_INFO_E;\r
 105 \r
 106 #define VPU_SERVICE_SHOW_TIME                   0\r
 107 \r
 108 #if VPU_SERVICE_SHOW_TIME\r
 109 static struct timeval enc_start, enc_end;\r
 110 static struct timeval dec_start, dec_end;\r
 111 static struct timeval pp_start,  pp_end;\r
 112 #endif\r
 113 \r
 114 #define MHZ                                     (1000*1000)\r
 115 \r
 116 #define REG_NUM_9190_DEC                        (60)\r
 117 #define REG_NUM_9190_PP                         (41)\r
 118 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 119 \r
 120 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 121 \r
 122 #define REG_NUM_ENC_8270                        (96)\r
 123 #define REG_SIZE_ENC_8270                       (0x200)\r
 124 #define REG_NUM_ENC_4831                        (164)\r
 125 #define REG_SIZE_ENC_4831                       (0x400)\r
 126 \r
 127 #define REG_NUM_HEVC_DEC                        (68)\r
 128 \r
 129 #define SIZE_REG(reg)                           ((reg)*4)\r
 130 \r
 131 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 132         [0] = {\r
 133                 .hw_id          = VPU_ID_8270,\r
 134                 .hw_addr        = 0,\r
 135                 .enc_offset     = 0x0,\r
 136                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 137                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 138                 .dec_offset     = REG_SIZE_ENC_8270,\r
 139                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 140                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 141         },\r
 142         [1] = {\r
 143                 .hw_id          = VPU_ID_4831,\r
 144                 .hw_addr        = 0,\r
 145                 .enc_offset     = 0x0,\r
 146                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 147                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 148                 .dec_offset     = REG_SIZE_ENC_4831,\r
 149                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 150                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 151         },\r
 152         [2] = {\r
 153                 .hw_id          = HEVC_ID,\r
 154                 .hw_addr        = 0,\r
 155                 .dec_offset     = 0x0,\r
 156                 .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 157                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 158         },\r
 159         [3] = {\r
 160                 .hw_id          = VPU_DEC_ID_9190,\r
 161                 .hw_addr        = 0,\r
 162                 .enc_offset     = 0x0,\r
 163                 .enc_reg_num    = 0,\r
 164                 .enc_io_size    = 0,\r
 165                 .dec_offset     = REG_SIZE_ENC_4831,\r
 166                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 167                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 168         },\r
 169         \r
 170 };\r
 171 \r
 172 \r
 173 #define DEC_INTERRUPT_REGISTER                  1\r
 174 #define PP_INTERRUPT_REGISTER                   60\r
 175 #define ENC_INTERRUPT_REGISTER                  1\r
 176 \r
 177 #define DEC_INTERRUPT_BIT                       0x100\r
 178 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 179 #define PP_INTERRUPT_BIT                        0x100\r
 180 #define ENC_INTERRUPT_BIT                       0x1\r
 181 \r
 182 #define HEVC_DEC_INT_RAW_BIT                    0x200\r
 183 #define HEVC_DEC_STR_ERROR_BIT                  0x4000\r
 184 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000\r
 185 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000\r
 186 \r
 187 #define VPU_REG_EN_ENC                          14\r
 188 #define VPU_REG_ENC_GATE                        2\r
 189 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 190 \r
 191 #define VPU_REG_EN_DEC                          1\r
 192 #define VPU_REG_DEC_GATE                        2\r
 193 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 194 #define VPU_REG_EN_PP                           0\r
 195 #define VPU_REG_PP_GATE                         1\r
 196 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 197 #define VPU_REG_EN_DEC_PP                       1\r
 198 #define VPU_REG_DEC_PP_GATE                     61\r
 199 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 200 \r
 201 #if defined(CONFIG_VCODEC_MMU)\r
 202 static u8 addr_tbl_vpu_h264dec[] = {\r
 203         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\r
 204         25, 26, 27, 28, 29, 40, 41\r
 205 };\r
 206 \r
 207 static u8 addr_tbl_vpu_vp8dec[] = {\r
 208         10,12,13, 14, 18, 19, 27, 40\r
 209 };\r
 210 \r
 211 static u8 addr_tbl_vpu_vp6dec[] = {\r
 212         12, 13, 14, 18, 27, 40\r
 213 };\r
 214 \r
 215 static u8 addr_tbl_vpu_vc1dec[] = {\r
 216         12, 13, 14, 15, 16, 17, 27, 41\r
 217 };\r
 218 \r
 219 static u8 addr_tbl_vpu_jpegdec[] = {\r
 220         12, 40, 66, 67\r
 221 };\r
 222 \r
 223 static u8 addr_tbl_vpu_defaultdec[] = {\r
 224         12, 13, 14, 15, 16, 17, 40, 41\r
 225 };\r
 226 \r
 227 static u8 addr_tbl_vpu_enc[] = {\r
 228         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 229 };\r
 230 \r
 231 static u8 addr_tbl_hevc_dec[] = {\r
 232         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\r
 233         21, 22, 23, 24, 42, 43\r
 234 };\r
 235 #endif\r
 236 \r
 237 enum VPU_DEC_FMT {\r
 238         VPU_DEC_FMT_H264,\r
 239         VPU_DEC_FMT_MPEG4,\r
 240         VPU_DEC_FMT_H263,\r
 241         VPU_DEC_FMT_JPEG,\r
 242         VPU_DEC_FMT_VC1,\r
 243         VPU_DEC_FMT_MPEG2,\r
 244         VPU_DEC_FMT_MPEG1,\r
 245         VPU_DEC_FMT_VP6,\r
 246         VPU_DEC_FMT_RV,\r
 247         VPU_DEC_FMT_VP7,\r
 248         VPU_DEC_FMT_VP8,\r
 249         VPU_DEC_FMT_AVS,\r
 250         VPU_DEC_FMT_SVC,\r
 251         VPU_DEC_FMT_VC2,\r
 252         VPU_DEC_FMT_MVC,\r
 253         VPU_DEC_FMT_THEORA,\r
 254         VPU_DEC_FMT_RES\r
 255 };\r
 256 \r
 257 /**\r
 258  * struct for process session which connect to vpu\r
 259  *\r
 260  * @author ChenHengming (2011-5-3)\r
 261  */\r
 262 typedef struct vpu_session {\r
 263         VPU_CLIENT_TYPE         type;\r
 264         /* a linked list of data so we can access them for debugging */\r
 265         struct list_head        list_session;\r
 266         /* a linked list of register data waiting for process */\r
 267         struct list_head        waiting;\r
 268         /* a linked list of register data in processing */\r
 269         struct list_head        running;\r
 270         /* a linked list of register data processed */\r
 271         struct list_head        done;\r
 272         wait_queue_head_t       wait;\r
 273         pid_t                   pid;\r
 274         atomic_t                task_running;\r
 275 } vpu_session;\r
 276 \r
 277 /**\r
 278  * struct for process register set\r
 279  *\r
 280  * @author ChenHengming (2011-5-4)\r
 281  */\r
 282 typedef struct vpu_reg {\r
 283         VPU_CLIENT_TYPE         type;\r
 284         VPU_FREQ                freq;\r
 285         vpu_session             *session;\r
 286         struct list_head        session_link;           /* link to vpu service session */\r
 287         struct list_head        status_link;            /* link to register set list */\r
 288         unsigned long           size;\r
 289 #if defined(CONFIG_VCODEC_MMU)\r
 290         struct list_head        mem_region_list;\r
 291 #endif\r
 292         unsigned long           *reg;\r
 293 } vpu_reg;\r
 294 \r
 295 typedef struct vpu_device {\r
 296         atomic_t                irq_count_codec;\r
 297         atomic_t                irq_count_pp;\r
 298         unsigned long           iobaseaddr;\r
 299         unsigned int            iosize;\r
 300         volatile u32            *hwregs;\r
 301 } vpu_device;\r
 302 \r
 303 enum vcodec_device_id {\r
 304         VCODEC_DEVICE_ID_VPU,\r
 305         VCODEC_DEVICE_ID_HEVC\r
 306 };\r
 307 \r
 308 struct vcodec_mem_region {\r
 309         struct list_head srv_lnk;\r
 310         struct list_head reg_lnk;\r
 311         struct list_head session_lnk;\r
 312         unsigned long iova;     /* virtual address for iommu */\r
 313         unsigned long len;\r
 314         struct ion_handle *hdl;\r
 315 };\r
 316 \r
 317 typedef struct vpu_service_info {\r
 318         struct wake_lock        wake_lock;\r
 319         struct delayed_work     power_off_work;\r
 320         struct mutex            lock;\r
 321         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 322         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 323         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 324         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 325         atomic_t                total_running;\r
 326         bool                    enabled;\r
 327         vpu_reg                 *reg_codec;\r
 328         vpu_reg                 *reg_pproc;\r
 329         vpu_reg                 *reg_resev;\r
 330         VPUHwDecConfig_t        dec_config;\r
 331         VPUHwEncConfig_t        enc_config;\r
 332         VPU_HW_INFO_E           *hw_info;\r
 333         unsigned long           reg_size;\r
 334         bool                    auto_freq;\r
 335         bool                    bug_dec_addr;\r
 336         atomic_t                freq_status;\r
 337 \r
 338         struct clk              *aclk_vcodec;\r
 339         struct clk              *hclk_vcodec;\r
 340         struct clk              *clk_core;\r
 341         struct clk              *clk_cabac;\r
 342         struct clk              *pd_video;\r
 343 \r
 344         int                     irq_dec;\r
 345         int                     irq_enc;\r
 346 \r
 347         vpu_device              enc_dev;\r
 348         vpu_device              dec_dev;\r
 349 \r
 350         struct device           *dev;\r
 351 \r
 352         struct cdev             cdev;\r
 353         dev_t                   dev_t;\r
 354         struct class            *cls;\r
 355         struct device           *child_dev;\r
 356 \r
 357         struct dentry           *debugfs_dir;\r
 358         struct dentry           *debugfs_file_regs;\r
 359 \r
 360         u32 irq_status;\r
 361 #if defined(CONFIG_VCODEC_MMU)  \r
 362         struct ion_client       *ion_client;\r
 363         struct list_head        mem_region_list;\r
 364         struct device           *mmu_dev;\r
 365 #endif\r
 366 \r
 367         enum vcodec_device_id   dev_id;\r
 368 \r
 369         u32                     reserved_mode;\r
 370 \r
 371         struct delayed_work     simulate_work;\r
 372 } vpu_service_info;\r
 373 \r
 374 typedef struct vpu_request\r
 375 {\r
 376         unsigned long *req;\r
 377         unsigned long size;\r
 378 } vpu_request;\r
 379 \r
 380 /// global variable\r
 381 //static struct clk *pd_video;\r
 382 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 383 /* mutex for selecting operation registers of vpu or hevc */\r
 384 static struct mutex g_mode_mutex;\r
 385 \r
 386 #ifdef CONFIG_DEBUG_FS\r
 387 static int vcodec_debugfs_init(void);\r
 388 static void vcodec_debugfs_exit(void);\r
 389 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 390 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 391 \r
 392 static const struct file_operations debug_vcodec_fops = {\r
 393         .open = debug_vcodec_open,\r
 394         .read = seq_read,\r
 395         .llseek = seq_lseek,\r
 396         .release = single_release,\r
 397 };\r
 398 #endif\r
 399 \r
 400 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 401 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 402 #define VPU_SIMULATE_DELAY              msecs_to_jiffies(15)\r
 403 \r
 404 static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)\r
 405 {\r
 406         if (soc_is_rk3036()) {\r
 407                 if (reserved_mode)\r
 408                         *reserved_mode = readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 409 #define BIT_VCODEC_SEL          (1<<3)\r
 410                 if (id == VCODEC_DEVICE_ID_HEVC) {\r
 411                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 412                 } else {\r
 413                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) & (~BIT_VCODEC_SEL)) | (BIT_VCODEC_SEL << 16), RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 414                 }\r
 415         }\r
 416 }\r
 417 \r
 418 static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)\r
 419 {\r
 420         writel_relaxed(reserved_mode | (BIT_VCODEC_SEL << 16), RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 421 }\r
 422 \r
 423 static void vcodec_enter_mode(enum vcodec_device_id id)\r
 424 {\r
 425         if (soc_is_rk3036())\r
 426                 mutex_lock(&g_mode_mutex);\r
 427         vcodec_enter_mode_nolock(id, NULL);\r
 428 }\r
 429 \r
 430 static void vcodec_exit_mode(void)\r
 431 {\r
 432         if (soc_is_rk3036())\r
 433                 mutex_unlock(&g_mode_mutex);\r
 434 }\r
 435 \r
 436 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 437 {\r
 438 #if VCODEC_CLOCK_ENABLE\r
 439         do {\r
 440                 pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 441                 if (IS_ERR(pservice->aclk_vcodec)) {\r
 442                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 443                         break;\r
 444                 }\r
 445 \r
 446                 pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 447                 if (IS_ERR(pservice->hclk_vcodec)) {\r
 448                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 449                         break;\r
 450                 }\r
 451 \r
 452                 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 453                         pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 454                         if (IS_ERR(pservice->clk_core)) {\r
 455                                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 456                                 break;\r
 457                         }\r
 458 \r
 459                         if (!soc_is_rk3036()) {\r
 460                                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 461                                 if (IS_ERR(pservice->clk_cabac)) {\r
 462                                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 463                                         break;\r
 464                                 }\r
 465                         } else {\r
 466                                 pservice->clk_cabac = NULL;\r
 467                         }\r
 468 \r
 469                         if (!soc_is_rk3036()) {\r
 470                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 471                                 if (IS_ERR(pservice->pd_video)) {\r
 472                                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 473                                         break;\r
 474                                 }\r
 475                         } else {\r
 476                                 pservice->pd_video = NULL;\r
 477                         }\r
 478                 } else {\r
 479                         if (!soc_is_rk3036()) {\r
 480                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 481                                 if (IS_ERR(pservice->pd_video)) {\r
 482                                         dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 483                                         break;\r
 484                                 }\r
 485                         } else {\r
 486                                 pservice->pd_video = NULL;\r
 487                         }\r
 488                 }\r
 489 \r
 490                 return 0;\r
 491         } while (0);\r
 492 \r
 493         return -1;\r
 494 #else\r
 495         return 0;\r
 496 #endif\r
 497 }\r
 498 \r
 499 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 500 {\r
 501 #if VCODEC_CLOCK_ENABLE\r
 502         if (pservice->pd_video) {\r
 503                 devm_clk_put(pservice->dev, pservice->pd_video);\r
 504         }\r
 505 \r
 506         if (pservice->aclk_vcodec) {\r
 507                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 508         }\r
 509 \r
 510         if (pservice->hclk_vcodec) {\r
 511                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 512         }\r
 513 \r
 514         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 515                 if (pservice->clk_core) {\r
 516                         devm_clk_put(pservice->dev, pservice->clk_core);\r
 517                 }\r
 518 \r
 519                 if (pservice->clk_cabac) {\r
 520                         devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 521                 }\r
 522         }\r
 523 #endif\r
 524 }\r
 525 \r
 526 static void vpu_reset(struct vpu_service_info *pservice)\r
 527 {\r
 528 #if defined(CONFIG_ARCH_RK29)\r
 529         clk_disable(aclk_ddr_vepu);\r
 530         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 531         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 532         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 533         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 534         mdelay(10);\r
 535         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 536         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 537         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 538         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 539         clk_enable(aclk_ddr_vepu);\r
 540 #elif defined(CONFIG_ARCH_RK30)\r
 541         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 542         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 543         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 544         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 545         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 546         mdelay(1);\r
 547         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 548         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 549         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 550         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 551         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 552 #endif\r
 553         pservice->reg_codec = NULL;\r
 554         pservice->reg_pproc = NULL;\r
 555         pservice->reg_resev = NULL;\r
 556 }\r
 557 \r
 558 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 559 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 560 {\r
 561         vpu_reg *reg, *n;\r
 562         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 563                 reg_deinit(pservice, reg);\r
 564         }\r
 565         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 566                 reg_deinit(pservice, reg);\r
 567         }\r
 568         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 569                 reg_deinit(pservice, reg);\r
 570         }\r
 571 }\r
 572 \r
 573 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 574 {\r
 575         int running;\r
 576         vpu_reg *reg, *reg_tmp;\r
 577         vpu_session *session, *session_tmp;\r
 578 \r
 579         running = atomic_read(&pservice->total_running);\r
 580         printk("total_running %d\n", running);\r
 581 \r
 582         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 583         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 584         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 585 \r
 586         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 587                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 588                 running = atomic_read(&session->task_running);\r
 589                 printk("task_running %d\n", running);\r
 590                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 591                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 592                 }\r
 593                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 594                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 595                 }\r
 596                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 597                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 598                 }\r
 599         }\r
 600 }\r
 601 \r
 602 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 603 {\r
 604         int total_running;\r
 605         if (!pservice->enabled)\r
 606                 return;\r
 607 \r
 608         pservice->enabled = false;\r
 609         total_running = atomic_read(&pservice->total_running);\r
 610         if (total_running) {\r
 611                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 612                 mdelay(50);\r
 613                 pr_alert("alert: delay 50 ms for running task\n");\r
 614                 vpu_service_dump(pservice);\r
 615         }\r
 616 \r
 617 #if defined(CONFIG_VCODEC_MMU)\r
 618         if (pservice->mmu_dev)\r
 619                 iovmm_deactivate(pservice->dev);\r
 620 #endif\r
 621 \r
 622         pr_info("%s: power off...", dev_name(pservice->dev));\r
 623         udelay(10);\r
 624 #if VCODEC_CLOCK_ENABLE\r
 625         if (pservice->pd_video)\r
 626                 clk_disable_unprepare(pservice->pd_video);\r
 627         if (pservice->hclk_vcodec)\r
 628                 clk_disable_unprepare(pservice->hclk_vcodec);\r
 629         if (pservice->aclk_vcodec)\r
 630                 clk_disable_unprepare(pservice->aclk_vcodec);\r
 631         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 632                 if (pservice->clk_core)\r
 633                         clk_disable_unprepare(pservice->clk_core);\r
 634                 if (pservice->clk_cabac)\r
 635                         clk_disable_unprepare(pservice->clk_cabac);\r
 636         }\r
 637 #endif\r
 638         wake_unlock(&pservice->wake_lock);\r
 639         pr_info("done\n");\r
 640 }\r
 641 \r
 642 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 643 {\r
 644         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 645 }\r
 646 \r
 647 static void vpu_power_off_work(struct work_struct *work_s)\r
 648 {\r
 649         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 650         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 651 \r
 652         if (mutex_trylock(&pservice->lock)) {\r
 653                 vpu_service_power_off(pservice);\r
 654                 mutex_unlock(&pservice->lock);\r
 655         } else {\r
 656                 /* Come back later if the device is busy... */\r
 657                 vpu_queue_power_off_work(pservice);\r
 658         }\r
 659 }\r
 660 \r
 661 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 662 {\r
 663         static ktime_t last;\r
 664         ktime_t now = ktime_get();\r
 665         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 666                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 667                 vpu_queue_power_off_work(pservice);\r
 668                 last = now;\r
 669         }\r
 670         if (pservice->enabled)\r
 671                 return ;\r
 672 \r
 673         pservice->enabled = true;\r
 674         printk("%s: power on\n", dev_name(pservice->dev));\r
 675 \r
 676 #if VCODEC_CLOCK_ENABLE\r
 677         if (pservice->aclk_vcodec)\r
 678                 clk_prepare_enable(pservice->aclk_vcodec);\r
 679 \r
 680         if (pservice->hclk_vcodec)\r
 681                 clk_prepare_enable(pservice->hclk_vcodec);\r
 682 \r
 683         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 684                 if (pservice->clk_core)\r
 685                         clk_prepare_enable(pservice->clk_core);\r
 686         if (pservice->clk_cabac)\r
 687                 clk_prepare_enable(pservice->clk_cabac);\r
 688         }\r
 689 \r
 690         if (pservice->pd_video)\r
 691                 clk_prepare_enable(pservice->pd_video);\r
 692 #endif\r
 693 \r
 694 #if defined(CONFIG_ARCH_RK319X)\r
 695         /// select aclk_vepu as vcodec clock source. \r
 696 #define BIT_VCODEC_SEL  (1<<7)\r
 697         writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |\r
 698                 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),\r
 699                 RK319X_GRF_BASE + GRF_SOC_CON1);\r
 700 #endif\r
 701 \r
 702         udelay(10);\r
 703         wake_lock(&pservice->wake_lock);\r
 704 \r
 705 #if defined(CONFIG_VCODEC_MMU)\r
 706         if (pservice->mmu_dev)\r
 707                 iovmm_activate(pservice->dev);\r
 708 #endif\r
 709 }\r
 710 \r
 711 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 712 {\r
 713         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 714         return ((type == 8) || (type == 4));\r
 715 }\r
 716 \r
 717 static inline bool reg_check_interlace(vpu_reg *reg)\r
 718 {\r
 719         unsigned long type = (reg->reg[3] & (1 << 23));\r
 720         return (type > 0);\r
 721 }\r
 722 \r
 723 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
 724 {\r
 725         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
 726         return type;\r
 727 }\r
 728 \r
 729 static inline int reg_probe_width(vpu_reg *reg)\r
 730 {\r
 731         int width_in_mb = reg->reg[4] >> 23;\r
 732         return width_in_mb * 16;\r
 733 }\r
 734 \r
 735 #if defined(CONFIG_VCODEC_MMU)\r
 736 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 737 {\r
 738         int i;\r
 739         int usr_fd = 0;\r
 740         int offset = 0;\r
 741 \r
 742         if (tbl == NULL || size <= 0) {\r
 743                 dev_err(pservice->dev, "input arguments invalidate\n");\r
 744                 return -1;\r
 745         }\r
 746 \r
 747         vpu_service_power_on(pservice);\r
 748 \r
 749         for (i = 0; i < size; i++) {\r
 750                 usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 751 \r
 752                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&\r
 753                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))\r
 754                         /* special for vpu dec num 41 regitster */\r
 755                         offset = reg->reg[tbl[i]] >> 10 << 4;\r
 756                 else\r
 757                         offset = reg->reg[tbl[i]] >> 10;\r
 758 \r
 759                 if (usr_fd != 0) {\r
 760                         struct ion_handle *hdl;\r
 761                         int ret;\r
 762                         struct vcodec_mem_region *mem_region;\r
 763 \r
 764                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 765                         if (IS_ERR(hdl)) {\r
 766                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 767                                 return PTR_ERR(hdl);\r
 768                         }\r
 769 \r
 770                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 771 \r
 772                         if (mem_region == NULL) {\r
 773                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 774                                 ion_free(pservice->ion_client, hdl);\r
 775                                 return -1;\r
 776                         }\r
 777 \r
 778                         mem_region->hdl = hdl;\r
 779 \r
 780                         vcodec_enter_mode(pservice->dev_id);\r
 781                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 782                         vcodec_exit_mode();\r
 783                         if (ret < 0) {\r
 784                                 dev_err(pservice->dev, "ion map iommu failed\n");\r
 785                                 kfree(mem_region);\r
 786                                 ion_free(pservice->ion_client, hdl);\r
 787                                 return ret;\r
 788                         }\r
 789                         reg->reg[tbl[i]] = mem_region->iova + offset;\r
 790                         INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 791                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 792                 }\r
 793         }\r
 794         return 0;\r
 795 }\r
 796 \r
 797 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 798 {\r
 799         VPU_HW_ID hw_id;\r
 800         u8 *tbl;\r
 801         int size = 0;\r
 802 \r
 803         hw_id = pservice->hw_info->hw_id;\r
 804 \r
 805         if (hw_id == HEVC_ID) {\r
 806                 tbl = addr_tbl_hevc_dec;\r
 807                 size = sizeof(addr_tbl_hevc_dec);\r
 808         } else {\r
 809                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 810                         switch (reg_check_fmt(reg)) {\r
 811                         case VPU_DEC_FMT_H264:\r
 812                                 {\r
 813                                         tbl = addr_tbl_vpu_h264dec;\r
 814                                         size = sizeof(addr_tbl_vpu_h264dec);\r
 815                                         break;\r
 816                                 }\r
 817                         case VPU_DEC_FMT_VP8:\r
 818                         case VPU_DEC_FMT_VP7:\r
 819                                 {\r
 820                                         tbl = addr_tbl_vpu_vp8dec;\r
 821                                         size = sizeof(addr_tbl_vpu_vp8dec);\r
 822                                         break;\r
 823                                 }\r
 824 \r
 825                         case VPU_DEC_FMT_VP6:\r
 826                                 {\r
 827                                         tbl = addr_tbl_vpu_vp6dec;\r
 828                                         size = sizeof(addr_tbl_vpu_vp6dec);\r
 829                                         break;\r
 830                                 }\r
 831                         case VPU_DEC_FMT_VC1:\r
 832                                 {\r
 833                                         tbl = addr_tbl_vpu_vc1dec;\r
 834                                         size = sizeof(addr_tbl_vpu_vc1dec);\r
 835                                         break;\r
 836                                 }\r
 837 \r
 838                         case VPU_DEC_FMT_JPEG:\r
 839                                 {\r
 840                                         tbl = addr_tbl_vpu_jpegdec;\r
 841                                         size = sizeof(addr_tbl_vpu_jpegdec);\r
 842                                         break;\r
 843                                 }\r
 844                         default:\r
 845                                 tbl = addr_tbl_vpu_defaultdec;\r
 846                                 size = sizeof(addr_tbl_vpu_defaultdec);\r
 847                                 break;\r
 848                         }\r
 849                 } else if (reg->type == VPU_ENC) {\r
 850                         tbl = addr_tbl_vpu_enc;\r
 851                         size = sizeof(addr_tbl_vpu_enc);\r
 852                 }\r
 853         }\r
 854 \r
 855         if (size != 0) {\r
 856                 return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 857         } else {\r
 858                 return -1;\r
 859         }\r
 860 }\r
 861 #endif\r
 862 \r
 863 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 864 {\r
 865         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 866         if (NULL == reg) {\r
 867                 pr_err("error: kmalloc fail in reg_init\n");\r
 868                 return NULL;\r
 869         }\r
 870 \r
 871         if (size > pservice->reg_size) {\r
 872                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 873                 size = pservice->reg_size;\r
 874         }\r
 875         reg->session = session;\r
 876         reg->type = session->type;\r
 877         reg->size = size;\r
 878         reg->freq = VPU_FREQ_DEFAULT;\r
 879         reg->reg = (unsigned long *)&reg[1];\r
 880         INIT_LIST_HEAD(&reg->session_link);\r
 881         INIT_LIST_HEAD(&reg->status_link);\r
 882 \r
 883 #if defined(CONFIG_VCODEC_MMU)  \r
 884         if (pservice->mmu_dev)\r
 885                 INIT_LIST_HEAD(&reg->mem_region_list);\r
 886 #endif\r
 887 \r
 888         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 889                 pr_err("error: copy_from_user failed in reg_init\n");\r
 890                 kfree(reg);\r
 891                 return NULL;\r
 892         }\r
 893 \r
 894 #if defined(CONFIG_VCODEC_MMU)\r
 895         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg)) {\r
 896                 pr_err("error: translate reg address failed\n");\r
 897                 kfree(reg);\r
 898                 return NULL;\r
 899         }\r
 900 #endif\r
 901 \r
 902         mutex_lock(&pservice->lock);\r
 903         list_add_tail(&reg->status_link, &pservice->waiting);\r
 904         list_add_tail(&reg->session_link, &session->waiting);\r
 905         mutex_unlock(&pservice->lock);\r
 906 \r
 907         if (pservice->auto_freq) {\r
 908                 if (!soc_is_rk2928g()) {\r
 909                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 910                                 if (reg_check_rmvb_wmv(reg)) {\r
 911                                         reg->freq = VPU_FREQ_200M;\r
 912                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
 913                                         if (reg_probe_width(reg) > 3200) {\r
 914                                                 // raise frequency for 4k avc.\r
 915                                                 reg->freq = VPU_FREQ_500M;\r
 916                                         }\r
 917                                 } else {\r
 918                                         if (reg_check_interlace(reg)) {\r
 919                                                 reg->freq = VPU_FREQ_400M;\r
 920                                         }\r
 921                                 }\r
 922                         }\r
 923                         if (reg->type == VPU_PP) {\r
 924                                 reg->freq = VPU_FREQ_400M;\r
 925                         }\r
 926                 }\r
 927         }\r
 928 \r
 929         return reg;\r
 930 }\r
 931 \r
 932 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 933 {\r
 934 #if defined(CONFIG_VCODEC_MMU)\r
 935         struct vcodec_mem_region *mem_region = NULL, *n;\r
 936 #endif\r
 937 \r
 938         list_del_init(&reg->session_link);\r
 939         list_del_init(&reg->status_link);\r
 940         if (reg == pservice->reg_codec)\r
 941                 pservice->reg_codec = NULL;\r
 942         if (reg == pservice->reg_pproc)\r
 943                 pservice->reg_pproc = NULL;\r
 944 \r
 945 #if defined(CONFIG_VCODEC_MMU)\r
 946         // release memory region attach to this registers table.\r
 947         if (pservice->mmu_dev) {\r
 948                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 949                         /* do not unmap iommu manually,\r
 950                            unmap will proccess when memory release */\r
 951                         /*vcodec_enter_mode(pservice->dev_id);\r
 952                         ion_unmap_iommu(pservice->dev,\r
 953                                         pservice->ion_client,\r
 954                                         mem_region->hdl);\r
 955                         vcodec_exit_mode();*/\r
 956                         ion_free(pservice->ion_client, mem_region->hdl);\r
 957                         list_del_init(&mem_region->reg_lnk);\r
 958                         kfree(mem_region);\r
 959                 }\r
 960         }\r
 961 #endif\r
 962 \r
 963         kfree(reg);\r
 964 }\r
 965 \r
 966 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 967 {\r
 968         list_del_init(&reg->status_link);\r
 969         list_add_tail(&reg->status_link, &pservice->running);\r
 970 \r
 971         list_del_init(&reg->session_link);\r
 972         list_add_tail(&reg->session_link, &reg->session->running);\r
 973 }\r
 974 \r
 975 static void reg_copy_from_hw(struct vpu_service_info *pservice, vpu_reg *reg, volatile u32 *src, u32 count)\r
 976 {\r
 977         int i;\r
 978         u32 *dst = (u32 *)&reg->reg[0];\r
 979 \r
 980         for (i = 0; i < count; i++)\r
 981                 *dst++ = *src++;\r
 982 }\r
 983 \r
 984 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 985 {\r
 986         int irq_reg = -1;\r
 987         list_del_init(&reg->status_link);\r
 988         list_add_tail(&reg->status_link, &pservice->done);\r
 989 \r
 990         list_del_init(&reg->session_link);\r
 991         list_add_tail(&reg->session_link, &reg->session->done);\r
 992 \r
 993         vcodec_enter_mode(pservice->dev_id);\r
 994         switch (reg->type) {\r
 995         case VPU_ENC : {\r
 996                 pservice->reg_codec = NULL;\r
 997                 reg_copy_from_hw(pservice, reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 998                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 999                 break;\r
1000         }\r
1001         case VPU_DEC : {\r
1002                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1003                 pservice->reg_codec = NULL;\r
1004                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs, reg_len);\r
1005                 irq_reg = DEC_INTERRUPT_REGISTER;\r
1006                 break;\r
1007         }\r
1008         case VPU_PP : {\r
1009                 pservice->reg_pproc = NULL;\r
1010                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
1011                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
1012                 break;\r
1013         }\r
1014         case VPU_DEC_PP : {\r
1015                 pservice->reg_codec = NULL;\r
1016                 pservice->reg_pproc = NULL;\r
1017                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
1018                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
1019                 break;\r
1020         }\r
1021         default : {\r
1022                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
1023                 break;\r
1024         }\r
1025         }\r
1026         vcodec_exit_mode();\r
1027 \r
1028         if (irq_reg != -1) {\r
1029                 reg->reg[irq_reg] = pservice->irq_status;\r
1030         }\r
1031 \r
1032         atomic_sub(1, &reg->session->task_running);\r
1033         atomic_sub(1, &pservice->total_running);\r
1034         wake_up(&reg->session->wait);\r
1035 }\r
1036 \r
1037 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
1038 {\r
1039         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
1040         if (curr == reg->freq) {\r
1041                 return ;\r
1042         }\r
1043         atomic_set(&pservice->freq_status, reg->freq);\r
1044         switch (reg->freq) {\r
1045         case VPU_FREQ_200M : {\r
1046                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
1047                 //printk("default: 200M\n");\r
1048         } break;\r
1049         case VPU_FREQ_266M : {\r
1050                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
1051                 //printk("default: 266M\n");\r
1052         } break;\r
1053         case VPU_FREQ_300M : {\r
1054                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
1055                 //printk("default: 300M\n");\r
1056         } break;\r
1057         case VPU_FREQ_400M : {\r
1058                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
1059                 //printk("default: 400M\n");\r
1060         } break;\r
1061         case VPU_FREQ_500M : {\r
1062                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
1063         } break;\r
1064         case VPU_FREQ_600M : {\r
1065                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
1066         } break;\r
1067         default : {\r
1068                 if (soc_is_rk2928g()) {\r
1069                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
1070                 } else {\r
1071                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
1072                 }\r
1073                 //printk("default: 300M\n");\r
1074         } break;\r
1075         }\r
1076 }\r
1077 \r
1078 #if HEVC_SIM_ENABLE\r
1079 static void simulate_start(struct vpu_service_info *pservice);\r
1080 #endif\r
1081 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
1082 {\r
1083         int i;\r
1084         u32 *src = (u32 *)&reg->reg[0];\r
1085         atomic_add(1, &pservice->total_running);\r
1086         atomic_add(1, &reg->session->task_running);\r
1087         if (pservice->auto_freq) {\r
1088                 vpu_service_set_freq(pservice, reg);\r
1089         }\r
1090 \r
1091         vcodec_enter_mode(pservice->dev_id);\r
1092 \r
1093         switch (reg->type) {\r
1094         case VPU_ENC : {\r
1095                 int enc_count = pservice->hw_info->enc_reg_num;\r
1096                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
1097 \r
1098                 pservice->reg_codec = reg;\r
1099 \r
1100                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
1101 \r
1102                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
1103                         dst[i] = src[i];\r
1104 \r
1105                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
1106                         dst[i] = src[i];\r
1107 \r
1108                 dsb();\r
1109 \r
1110                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
1111                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
1112 \r
1113 #if VPU_SERVICE_SHOW_TIME\r
1114                 do_gettimeofday(&enc_start);\r
1115 #endif\r
1116 \r
1117         } break;\r
1118         case VPU_DEC : {\r
1119                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1120 \r
1121                 pservice->reg_codec = reg;\r
1122 \r
1123                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1124                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
1125                                 dst[i] = src[i];\r
1126                 } else {\r
1127                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
1128                                 dst[i] = src[i];\r
1129                         }\r
1130                 }\r
1131 \r
1132                 dsb();\r
1133 \r
1134                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1135                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
1136                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
1137                 } else {\r
1138                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
1139                 }\r
1140 \r
1141                 dsb();\r
1142                 dmb();\r
1143 \r
1144 #if VPU_SERVICE_SHOW_TIME\r
1145                 do_gettimeofday(&dec_start);\r
1146 #endif\r
1147 \r
1148         } break;\r
1149         case VPU_PP : {\r
1150                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1151                 pservice->reg_pproc = reg;\r
1152 \r
1153                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1154 \r
1155                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1156                         dst[i] = src[i];\r
1157 \r
1158                 dsb();\r
1159 \r
1160                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1161 \r
1162 #if VPU_SERVICE_SHOW_TIME\r
1163                 do_gettimeofday(&pp_start);\r
1164 #endif\r
1165 \r
1166         } break;\r
1167         case VPU_DEC_PP : {\r
1168                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1169                 pservice->reg_codec = reg;\r
1170                 pservice->reg_pproc = reg;\r
1171 \r
1172                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1173                         dst[i] = src[i];\r
1174 \r
1175                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1176                 dsb();\r
1177 \r
1178                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1179                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1180                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1181 \r
1182 #if VPU_SERVICE_SHOW_TIME\r
1183                 do_gettimeofday(&dec_start);\r
1184 #endif\r
1185 \r
1186         } break;\r
1187         default : {\r
1188                 pr_err("error: unsupport session type %d", reg->type);\r
1189                 atomic_sub(1, &pservice->total_running);\r
1190                 atomic_sub(1, &reg->session->task_running);\r
1191                 break;\r
1192         }\r
1193         }\r
1194 \r
1195         vcodec_exit_mode();\r
1196 \r
1197 #if HEVC_SIM_ENABLE\r
1198         if (pservice->hw_info->hw_id == HEVC_ID) {\r
1199                 simulate_start(pservice);\r
1200         }\r
1201 #endif\r
1202 }\r
1203 \r
1204 static void try_set_reg(struct vpu_service_info *pservice)\r
1205 {\r
1206         // first get reg from reg list\r
1207         if (!list_empty(&pservice->waiting)) {\r
1208                 int can_set = 0;\r
1209                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1210 \r
1211                 vpu_service_power_on(pservice);\r
1212 \r
1213                 switch (reg->type) {\r
1214                 case VPU_ENC : {\r
1215                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1216                                 can_set = 1;\r
1217                 } break;\r
1218                 case VPU_DEC : {\r
1219                         if (NULL == pservice->reg_codec)\r
1220                                 can_set = 1;\r
1221                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1222                                 can_set = 0;\r
1223                         }\r
1224                 } break;\r
1225                 case VPU_PP : {\r
1226                         if (NULL == pservice->reg_codec) {\r
1227                                 if (NULL == pservice->reg_pproc)\r
1228                                         can_set = 1;\r
1229                         } else {\r
1230                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1231                                         can_set = 1;\r
1232                                 // can not charge frequency when vpu is working\r
1233                                 if (pservice->auto_freq) {\r
1234                                         can_set = 0;\r
1235                                 }\r
1236                         }\r
1237                 } break;\r
1238                 case VPU_DEC_PP : {\r
1239                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1240                                 can_set = 1;\r
1241                         } break;\r
1242                 default : {\r
1243                         printk("undefined reg type %d\n", reg->type);\r
1244                 } break;\r
1245                 }\r
1246                 if (can_set) {\r
1247                         reg_from_wait_to_run(pservice, reg);\r
1248                         reg_copy_to_hw(pservice, reg);\r
1249                 }\r
1250         }\r
1251 }\r
1252 \r
1253 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1254 {\r
1255         int ret = 0;\r
1256         switch (reg->type) {\r
1257         case VPU_ENC : {\r
1258                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1259                         ret = -EFAULT;\r
1260                 break;\r
1261         }\r
1262         case VPU_DEC : {\r
1263                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1264                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1265                         ret = -EFAULT;\r
1266                 break;\r
1267         }\r
1268         case VPU_PP : {\r
1269                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1270                         ret = -EFAULT;\r
1271                 break;\r
1272         }\r
1273         case VPU_DEC_PP : {\r
1274                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1275                         ret = -EFAULT;\r
1276                 break;\r
1277         }\r
1278         default : {\r
1279                 ret = -EFAULT;\r
1280                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1281                 break;\r
1282         }\r
1283         }\r
1284         reg_deinit(pservice, reg);\r
1285         return ret;\r
1286 }\r
1287 \r
1288 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1289 {\r
1290     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1291         vpu_session *session = (vpu_session *)filp->private_data;\r
1292         if (NULL == session) {\r
1293                 return -EINVAL;\r
1294         }\r
1295 \r
1296         switch (cmd) {\r
1297         case VPU_IOC_SET_CLIENT_TYPE : {\r
1298                 session->type = (VPU_CLIENT_TYPE)arg;\r
1299                 break;\r
1300         }\r
1301         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1302                 vpu_request req;\r
1303                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1304                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1305                         return -EFAULT;\r
1306                 } else {\r
1307                         if (VPU_ENC != session->type) {\r
1308                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1309                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1310                                         return -EFAULT;\r
1311                                 }\r
1312                         } else {\r
1313                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1314                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1315                                         return -EFAULT;\r
1316                                 }\r
1317                         }\r
1318                 }\r
1319 \r
1320                 break;\r
1321         }\r
1322         case VPU_IOC_SET_REG : {\r
1323                 vpu_request req;\r
1324                 vpu_reg *reg;\r
1325                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1326                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1327                         return -EFAULT;\r
1328                 }\r
1329                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1330                 if (NULL == reg) {\r
1331                         return -EFAULT;\r
1332                 } else {\r
1333                         mutex_lock(&pservice->lock);\r
1334                         try_set_reg(pservice);\r
1335                         mutex_unlock(&pservice->lock);\r
1336                 }\r
1337 \r
1338                 break;\r
1339         }\r
1340         case VPU_IOC_GET_REG : {\r
1341                 vpu_request req;\r
1342                 vpu_reg *reg;\r
1343                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1344                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1345                         return -EFAULT;\r
1346                 } else {\r
1347                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1348                         if (!list_empty(&session->done)) {\r
1349                                 if (ret < 0) {\r
1350                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1351                                 }\r
1352                                 ret = 0;\r
1353                         } else {\r
1354                                 if (unlikely(ret < 0)) {\r
1355                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1356                                 } else if (0 == ret) {\r
1357                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1358                                         ret = -ETIMEDOUT;\r
1359                                 }\r
1360                         }\r
1361                         if (ret < 0) {\r
1362                                 int task_running = atomic_read(&session->task_running);\r
1363                                 mutex_lock(&pservice->lock);\r
1364                                 vpu_service_dump(pservice);\r
1365                                 if (task_running) {\r
1366                                         atomic_set(&session->task_running, 0);\r
1367                                         atomic_sub(task_running, &pservice->total_running);\r
1368                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1369                                         vpu_reset(pservice);\r
1370                                         printk("done\n");\r
1371                                 }\r
1372                                 vpu_service_session_clear(pservice, session);\r
1373                                 mutex_unlock(&pservice->lock);\r
1374                                 return ret;\r
1375                         }\r
1376                 }\r
1377                 mutex_lock(&pservice->lock);\r
1378                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1379                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1380                 mutex_unlock(&pservice->lock);\r
1381                 break;\r
1382         }\r
1383         case VPU_IOC_PROBE_IOMMU_STATUS: {\r
1384                 int iommu_enable = 0;\r
1385 \r
1386 #if defined(CONFIG_VCODEC_MMU)\r
1387                 iommu_enable = pservice->mmu_dev ? 1 : 0; \r
1388 #endif\r
1389 \r
1390                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
1391                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
1392                         return -EFAULT;\r
1393                 }\r
1394                 break;\r
1395         }\r
1396         default : {\r
1397                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1398                 break;\r
1399         }\r
1400         }\r
1401 \r
1402         return 0;\r
1403 }\r
1404 #if 1\r
1405 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1406 {\r
1407         int ret = -EINVAL, i = 0;\r
1408         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1409         u32 enc_id = *tmp;\r
1410 \r
1411 #if HEVC_SIM_ENABLE\r
1412         /// temporary, hevc driver test.\r
1413         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1414                 p->hw_info = &vpu_hw_set[2];\r
1415                 return 0;\r
1416         }\r
1417 #endif\r
1418         enc_id = (enc_id >> 16) & 0xFFFF;\r
1419         pr_info("checking hw id %x\n", enc_id);\r
1420         p->hw_info = NULL;\r
1421         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1422                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1423                         p->hw_info = &vpu_hw_set[i];\r
1424                         ret = 0;\r
1425                         break;\r
1426                 }\r
1427         }\r
1428         iounmap((void *)tmp);\r
1429         return ret;\r
1430 }\r
1431 #endif\r
1432 \r
1433 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1434 {\r
1435         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1436         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1437         if (NULL == session) {\r
1438                 pr_err("error: unable to allocate memory for vpu_session.");\r
1439                 return -ENOMEM;\r
1440         }\r
1441 \r
1442         session->type   = VPU_TYPE_BUTT;\r
1443         session->pid    = current->pid;\r
1444         INIT_LIST_HEAD(&session->waiting);\r
1445         INIT_LIST_HEAD(&session->running);\r
1446         INIT_LIST_HEAD(&session->done);\r
1447         INIT_LIST_HEAD(&session->list_session);\r
1448         init_waitqueue_head(&session->wait);\r
1449         atomic_set(&session->task_running, 0);\r
1450         mutex_lock(&pservice->lock);\r
1451         list_add_tail(&session->list_session, &pservice->session);\r
1452         filp->private_data = (void *)session;\r
1453         mutex_unlock(&pservice->lock);\r
1454 \r
1455         pr_debug("dev opened\n");\r
1456         return nonseekable_open(inode, filp);\r
1457 }\r
1458 \r
1459 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1460 {\r
1461         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1462         int task_running;\r
1463         vpu_session *session = (vpu_session *)filp->private_data;\r
1464         if (NULL == session)\r
1465                 return -EINVAL;\r
1466 \r
1467         task_running = atomic_read(&session->task_running);\r
1468         if (task_running) {\r
1469                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1470                 msleep(50);\r
1471         }\r
1472         wake_up(&session->wait);\r
1473 \r
1474         mutex_lock(&pservice->lock);\r
1475         /* remove this filp from the asynchronusly notified filp's */\r
1476         list_del_init(&session->list_session);\r
1477         vpu_service_session_clear(pservice, session);\r
1478         kfree(session);\r
1479         filp->private_data = NULL;\r
1480         mutex_unlock(&pservice->lock);\r
1481 \r
1482         pr_debug("dev closed\n");\r
1483         return 0;\r
1484 }\r
1485 \r
1486 static const struct file_operations vpu_service_fops = {\r
1487         .unlocked_ioctl = vpu_service_ioctl,\r
1488         .open           = vpu_service_open,\r
1489         .release        = vpu_service_release,\r
1490         //.fasync       = vpu_service_fasync,\r
1491 };\r
1492 \r
1493 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1494 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1495 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1496 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1497 static void get_hw_info(struct vpu_service_info *pservice);\r
1498 \r
1499 #if HEVC_SIM_ENABLE\r
1500 static void simulate_work(struct work_struct *work_s)\r
1501 {\r
1502         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1503         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1504         vpu_device *dev = &pservice->dec_dev;\r
1505 \r
1506         if (!list_empty(&pservice->running)) {\r
1507                 atomic_add(1, &dev->irq_count_codec);\r
1508                 vdpu_isr(0, (void*)pservice);\r
1509         } else {\r
1510                 //simulate_start(pservice);\r
1511                 pr_err("empty running queue\n");\r
1512         }\r
1513 }\r
1514 \r
1515 static void simulate_init(struct vpu_service_info *pservice)\r
1516 {\r
1517         INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1518 }\r
1519 \r
1520 static void simulate_start(struct vpu_service_info *pservice)\r
1521 {\r
1522         cancel_delayed_work_sync(&pservice->power_off_work);\r
1523         queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1524 }\r
1525 #endif\r
1526 \r
1527 #if HEVC_TEST_ENABLE\r
1528 static int hevc_test_case0(vpu_service_info *pservice);\r
1529 #endif\r
1530 #if defined(CONFIG_ION_ROCKCHIP)\r
1531 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1532 #endif\r
1533 static int vcodec_probe(struct platform_device *pdev)\r
1534 {\r
1535         int ret = 0;\r
1536         struct resource *res = NULL;\r
1537         struct device *dev = &pdev->dev;\r
1538         void __iomem *regs = NULL;\r
1539         struct device_node *np = pdev->dev.of_node;\r
1540         struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1541         char *prop = (char*)dev_name(dev);\r
1542 #if defined(CONFIG_VCODEC_MMU)\r
1543         char mmu_dev_dts_name[40];\r
1544 #endif\r
1545 \r
1546         pr_info("probe device %s\n", dev_name(dev));\r
1547 \r
1548         of_property_read_string(np, "name", (const char**)&prop);\r
1549         dev_set_name(dev, prop);\r
1550 \r
1551         if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1552                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1553         } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1554                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1555         } else {\r
1556                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1557                 return -1;\r
1558         }\r
1559 \r
1560         mutex_init(&g_mode_mutex);\r
1561         vcodec_enter_mode(pservice->dev_id);\r
1562 \r
1563         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1564         INIT_LIST_HEAD(&pservice->waiting);\r
1565         INIT_LIST_HEAD(&pservice->running);\r
1566         INIT_LIST_HEAD(&pservice->done);\r
1567         INIT_LIST_HEAD(&pservice->session);\r
1568         mutex_init(&pservice->lock);\r
1569         pservice->reg_codec     = NULL;\r
1570         pservice->reg_pproc     = NULL;\r
1571         atomic_set(&pservice->total_running, 0);\r
1572         pservice->enabled = false;\r
1573 #if defined(CONFIG_VCODEC_MMU)    \r
1574         pservice->mmu_dev = NULL;\r
1575 #endif\r
1576         pservice->dev = dev;\r
1577 \r
1578         if (0 > vpu_get_clk(pservice))\r
1579                 goto err;\r
1580 \r
1581         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1582 \r
1583         vpu_service_power_on(pservice);\r
1584 \r
1585         mdelay(1);\r
1586 \r
1587         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1588 \r
1589         res->flags &= ~IORESOURCE_CACHEABLE;\r
1590 \r
1591         regs = devm_ioremap_resource(pservice->dev, res);\r
1592         if (IS_ERR(regs)) {\r
1593                 ret = PTR_ERR(regs);\r
1594                 goto err;\r
1595         }\r
1596 \r
1597         {\r
1598                 u32 offset = res->start;\r
1599                 if (soc_is_rk3036()) {\r
1600                         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)\r
1601                                 offset += 0x400;\r
1602                 }\r
1603                 ret = vpu_service_check_hw(pservice, offset);\r
1604                 if (ret < 0) {\r
1605                         pr_err("error: hw info check faild\n");\r
1606                         goto err;\r
1607                 }\r
1608         }\r
1609 \r
1610         /// define regs address.\r
1611         pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1612         pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1613 \r
1614         pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1615 \r
1616         pservice->reg_size   = pservice->dec_dev.iosize;\r
1617 \r
1618         if (pservice->hw_info->hw_id != HEVC_ID && !soc_is_rk3036()) {\r
1619                 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1620                 pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1621 \r
1622                 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1623 \r
1624                 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1625 \r
1626                 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1627                 if (pservice->irq_enc < 0) {\r
1628                         dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1629                         ret = -ENXIO;\r
1630                         goto err;\r
1631                 }\r
1632 \r
1633                 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1634                 if (ret) {\r
1635                         dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1636                         goto err;\r
1637                 }\r
1638         }\r
1639 \r
1640         pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1641         if (pservice->irq_dec < 0) {\r
1642                 dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1643                 ret = -ENXIO;\r
1644                 goto err;\r
1645         }\r
1646 \r
1647         /* get the IRQ line */\r
1648         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1649         if (ret) {\r
1650                 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1651                 goto err;\r
1652         }\r
1653 \r
1654         atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1655         atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1656         atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1657         atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1658 \r
1659         /// create device\r
1660         ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1661         if (ret) {\r
1662                 dev_err(dev, "alloc dev_t failed\n");\r
1663                 goto err;\r
1664         }\r
1665 \r
1666         cdev_init(&pservice->cdev, &vpu_service_fops);\r
1667 \r
1668         pservice->cdev.owner = THIS_MODULE;\r
1669         pservice->cdev.ops = &vpu_service_fops;\r
1670 \r
1671         ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1672 \r
1673         if (ret) {\r
1674                 dev_err(dev, "add dev_t failed\n");\r
1675                 goto err;\r
1676         }\r
1677 \r
1678         pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1679 \r
1680         if (IS_ERR(pservice->cls)) {\r
1681                 ret = PTR_ERR(pservice->cls);\r
1682                 dev_err(dev, "class_create err:%d\n", ret);\r
1683                 goto err;\r
1684         }\r
1685 \r
1686         pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1687 \r
1688         platform_set_drvdata(pdev, pservice);\r
1689 \r
1690         get_hw_info(pservice);\r
1691 \r
1692 \r
1693 #ifdef CONFIG_DEBUG_FS\r
1694         pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1695         if (pservice->debugfs_dir == NULL)\r
1696                 pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1697 \r
1698         pservice->debugfs_file_regs = \r
1699                 debugfs_create_file("regs", 0664,\r
1700                                     pservice->debugfs_dir, pservice,\r
1701                                     &debug_vcodec_fops);\r
1702 #endif\r
1703 \r
1704 #if defined(CONFIG_VCODEC_MMU)\r
1705         pservice->ion_client = rockchip_ion_client_create("vpu");\r
1706         if (IS_ERR(pservice->ion_client)) {\r
1707                 dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1708                 return PTR_ERR(pservice->ion_client);\r
1709         } else {\r
1710                 dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1711         }\r
1712 \r
1713         if (pservice->hw_info->hw_id == HEVC_ID)\r
1714                 sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1715         else\r
1716                 sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1717         pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1718 \r
1719         if (pservice->mmu_dev) {\r
1720                 platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
1721                 iovmm_activate(pservice->dev);\r
1722         }\r
1723 #endif\r
1724 \r
1725         vpu_service_power_off(pservice);\r
1726         vcodec_exit_mode();\r
1727 \r
1728         pr_info("init success\n");\r
1729 \r
1730 #if HEVC_SIM_ENABLE\r
1731         if (pservice->hw_info->hw_id == HEVC_ID)\r
1732                 simulate_init(pservice);\r
1733 #endif\r
1734 \r
1735 #if HEVC_TEST_ENABLE\r
1736         hevc_test_case0(pservice);\r
1737 #endif\r
1738 \r
1739         return 0;\r
1740 \r
1741 err:\r
1742         pr_info("init failed\n");\r
1743         vpu_service_power_off(pservice);\r
1744         vpu_put_clk(pservice);\r
1745         wake_lock_destroy(&pservice->wake_lock);\r
1746 \r
1747         if (res)\r
1748                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1749         if (pservice->irq_enc > 0)\r
1750                 free_irq(pservice->irq_enc, (void *)pservice);\r
1751         if (pservice->irq_dec > 0)\r
1752                 free_irq(pservice->irq_dec, (void *)pservice);\r
1753 \r
1754         if (pservice->child_dev) {\r
1755                 device_destroy(pservice->cls, pservice->dev_t);\r
1756                 cdev_del(&pservice->cdev);\r
1757                 unregister_chrdev_region(pservice->dev_t, 1);\r
1758         }\r
1759 \r
1760         if (pservice->cls)\r
1761                 class_destroy(pservice->cls);\r
1762 \r
1763         return ret;\r
1764 }\r
1765 \r
1766 static int vcodec_remove(struct platform_device *pdev)\r
1767 {\r
1768         struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1769         struct resource *res;\r
1770 \r
1771         device_destroy(pservice->cls, pservice->dev_t);\r
1772         class_destroy(pservice->cls);\r
1773         cdev_del(&pservice->cdev);\r
1774         unregister_chrdev_region(pservice->dev_t, 1);\r
1775 \r
1776         free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1777         free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1778         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1779         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1780         vpu_put_clk(pservice);\r
1781         wake_lock_destroy(&pservice->wake_lock);\r
1782 \r
1783 #ifdef CONFIG_DEBUG_FS\r
1784         debugfs_remove(pservice->debugfs_file_regs);\r
1785         debugfs_remove(pservice->debugfs_dir);\r
1786 #endif\r
1787 \r
1788         return 0;\r
1789 }\r
1790 \r
1791 #if defined(CONFIG_OF)\r
1792 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1793         {.compatible = "vpu_service",},\r
1794         {.compatible = "rockchip,hevc_service",},\r
1795         {},\r
1796 };\r
1797 #endif\r
1798 \r
1799 static struct platform_driver vcodec_driver = {\r
1800         .probe = vcodec_probe,\r
1801         .remove = vcodec_remove,\r
1802         .driver = {\r
1803                 .name = "vcodec",\r
1804                 .owner = THIS_MODULE,\r
1805 #if defined(CONFIG_OF)\r
1806                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1807 #endif\r
1808         },\r
1809 };\r
1810 \r
1811 static void get_hw_info(struct vpu_service_info *pservice)\r
1812 {\r
1813         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1814         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1815 \r
1816         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {\r
1817                 u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1818                 u32 asicID      = pservice->dec_dev.hwregs[0];\r
1819         \r
1820                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1821                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1822                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1823                         dec->jpegSupport = JPEG_PROGRESSIVE;\r
1824                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1825                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1826                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1827                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1828                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1829                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1830 \r
1831                 if (soc_is_rk3190() || soc_is_rk3288())\r
1832                         dec->maxDecPicWidth = 4096;\r
1833                 else if (soc_is_rk3036())\r
1834                         dec->maxDecPicWidth = 1920;\r
1835                 else\r
1836                         dec->maxDecPicWidth = configReg & 0x07FFU;\r
1837         \r
1838                 /* 2nd Config register */\r
1839                 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1840                 if (dec->refBufSupport) {\r
1841                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1842                                 dec->refBufSupport |= 2;\r
1843                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1844                                 dec->refBufSupport |= 4;\r
1845                 }\r
1846                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1847                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1848                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1849                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1850 \r
1851                 /* JPEG xtensions */\r
1852                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))\r
1853                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1854                 else\r
1855                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1856 \r
1857                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )\r
1858                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1859                 else\r
1860                         dec->rvSupport = RV_NOT_SUPPORTED;\r
1861                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1862 \r
1863                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )\r
1864                         dec->refBufSupport |= 8; /* enable HW support for offset */\r
1865         \r
1866                 /// invalidate fuse register value in rk319x vpu and following.\r
1867                 if (!soc_is_rk3190() && !soc_is_rk3288() && !soc_is_rk3036()) {\r
1868                         VPUHwFuseStatus_t hwFuseSts;\r
1869                         /* Decoder fuse configuration */\r
1870                         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1871 \r
1872                         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1873                         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1874                         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1875                         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1876                         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1877                         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1878                         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1879                         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1880                         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1881                         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1882                         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1883                         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1884                         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1885                         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1886 \r
1887                         /* check max. decoder output width */\r
1888 \r
1889                         if (fuseReg & 0x8000U)\r
1890                                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1891                         else if (fuseReg & 0x4000U)\r
1892                                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1893                         else if (fuseReg & 0x2000U)\r
1894                                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1895                         else if (fuseReg & 0x1000U)\r
1896                                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1897                         else    /* remove warning */\r
1898                                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1899 \r
1900                         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1901 \r
1902                         /* Pp configuration */\r
1903                         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1904 \r
1905                         if ((configReg >> DWL_PP_E) & 0x01U) {\r
1906                                 dec->ppSupport = 1;\r
1907                                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1908                                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1909                                 dec->ppConfig = configReg;\r
1910                         } else {\r
1911                                 dec->ppSupport = 0;\r
1912                                 dec->maxPpOutPicWidth = 0;\r
1913                                 dec->ppConfig = 0;\r
1914                         }\r
1915 \r
1916                         /* check the HW versio */\r
1917                         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1918                                 /* Pp configuration */\r
1919                                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1920                                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1921                                         /* Pp fuse configuration */\r
1922                                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1923 \r
1924                                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1925                                                 hwFuseSts.ppSupportFuse = 1;\r
1926                                                 /* check max. pp output width */\r
1927                                                 if (fuseRegPp & 0x8000U)\r
1928                                                         hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1929                                                 else if (fuseRegPp & 0x4000U)\r
1930                                                         hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1931                                                 else if (fuseRegPp & 0x2000U)\r
1932                                                         hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1933                                                 else if (fuseRegPp & 0x1000U)\r
1934                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1935                                                 else\r
1936                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1937                                                 hwFuseSts.ppConfigFuse = fuseRegPp;\r
1938                                         } else {\r
1939                                                 hwFuseSts.ppSupportFuse = 0;\r
1940                                                 hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1941                                                 hwFuseSts.ppConfigFuse = 0;\r
1942                                         }\r
1943                                 } else {\r
1944                                         hwFuseSts.ppSupportFuse = 0;\r
1945                                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1946                                         hwFuseSts.ppConfigFuse = 0;\r
1947                                 }\r
1948 \r
1949                                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1950                                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1951                                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1952                                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1953                                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1954                                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1955                                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1956                                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1957                                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1958                                         dec->jpegSupport = JPEG_BASELINE;\r
1959                                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1960                                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1961                                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1962                                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1963                                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1964                                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1965 \r
1966                                 /* check the pp config vs fuse status */\r
1967                                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1968                                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1969                                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1970                                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1971                                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1972 \r
1973                                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1974                                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1975                                 }\r
1976                                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1977                                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1978                                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1979                                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1980                                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1981                         }\r
1982                 }\r
1983 \r
1984                 if (!soc_is_rk3036()) {\r
1985                         configReg = pservice->enc_dev.hwregs[63];\r
1986                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1987                         enc->h264Enabled = (configReg >> 27) & 1;\r
1988                         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1989                         enc->jpegEnabled = (configReg >> 25) & 1;\r
1990                         enc->vsEnabled = (configReg >> 24) & 1;\r
1991                         enc->rgbEnabled = (configReg >> 28) & 1;\r
1992                         /*enc->busType = (configReg >> 20) & 15;\r
1993                         enc->synthesisLanguage = (configReg >> 16) & 15;\r
1994                         enc->busWidth = (configReg >> 12) & 15;*/\r
1995                         enc->reg_size = pservice->reg_size;\r
1996                         enc->reserv[0] = enc->reserv[1] = 0;\r
1997                 }\r
1998 \r
1999                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
2000                 if (pservice->auto_freq) {\r
2001                         pr_info("vpu_service set to auto frequency mode\n");\r
2002                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
2003                 }\r
2004 \r
2005                 pservice->bug_dec_addr = cpu_is_rk30xx();\r
2006         } else {\r
2007                 if (soc_is_rk3036())\r
2008                         dec->maxDecPicWidth = 1920;\r
2009                 else\r
2010                         dec->maxDecPicWidth = 4096;\r
2011                 /* disable frequency switch in hevc.*/\r
2012                 pservice->auto_freq = false;\r
2013         }\r
2014 }\r
2015 \r
2016 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
2017 {\r
2018         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2019         vpu_device *dev = &pservice->dec_dev;\r
2020         u32 raw_status;\r
2021         u32 irq_status;\r
2022 \r
2023         vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);\r
2024 \r
2025         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2026 \r
2027         pr_debug("dec_irq\n");\r
2028 \r
2029         if (irq_status & DEC_INTERRUPT_BIT) {\r
2030                 pr_debug("dec_isr dec %x\n", irq_status);\r
2031                 if ((irq_status & 0x40001) == 0x40001)\r
2032                 {\r
2033                         do {\r
2034                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2035                         } while ((irq_status & 0x40001) == 0x40001);\r
2036                 }\r
2037 \r
2038                 /* clear dec IRQ */\r
2039                 if (pservice->hw_info->hw_id != HEVC_ID)\r
2040                         writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2041                 else\r
2042                         writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2043                 atomic_add(1, &dev->irq_count_codec);\r
2044         }\r
2045 \r
2046         if (pservice->hw_info->hw_id != HEVC_ID) {\r
2047                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
2048                 if (irq_status & PP_INTERRUPT_BIT) {\r
2049                         pr_debug("vdpu_isr pp  %x\n", irq_status);\r
2050                         /* clear pp IRQ */\r
2051                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
2052                         atomic_add(1, &dev->irq_count_pp);\r
2053                 }\r
2054         }\r
2055 \r
2056         pservice->irq_status = raw_status;\r
2057 \r
2058         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);\r
2059 \r
2060         return IRQ_WAKE_THREAD;\r
2061 }\r
2062 \r
2063 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
2064 {\r
2065         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2066         vpu_device *dev = &pservice->dec_dev;\r
2067 \r
2068         mutex_lock(&pservice->lock);\r
2069         if (atomic_read(&dev->irq_count_codec)) {\r
2070 #if VPU_SERVICE_SHOW_TIME\r
2071                 do_gettimeofday(&dec_end);\r
2072                 pr_info("dec task: %ld ms\n",\r
2073                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
2074                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
2075 #endif\r
2076                 atomic_sub(1, &dev->irq_count_codec);\r
2077                 if (NULL == pservice->reg_codec) {\r
2078                         pr_err("error: dec isr with no task waiting\n");\r
2079                 } else {\r
2080                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2081                 }\r
2082         }\r
2083 \r
2084         if (atomic_read(&dev->irq_count_pp)) {\r
2085 \r
2086 #if VPU_SERVICE_SHOW_TIME\r
2087                 do_gettimeofday(&pp_end);\r
2088                 printk("pp  task: %ld ms\n",\r
2089                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
2090                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
2091 #endif\r
2092 \r
2093                 atomic_sub(1, &dev->irq_count_pp);\r
2094                 if (NULL == pservice->reg_pproc) {\r
2095                         pr_err("error: pp isr with no task waiting\n");\r
2096                 } else {\r
2097                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
2098                 }\r
2099         }\r
2100         try_set_reg(pservice);\r
2101         mutex_unlock(&pservice->lock);\r
2102         return IRQ_HANDLED;\r
2103 }\r
2104 \r
2105 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
2106 {\r
2107         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2108         vpu_device *dev = &pservice->enc_dev;\r
2109         u32 irq_status;\r
2110 \r
2111         vcodec_enter_mode_nolock(pservice->dev_id,  &pservice->reserved_mode);\r
2112         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2113 \r
2114         pr_debug("vepu_irq irq status %x\n", irq_status);\r
2115 \r
2116 #if VPU_SERVICE_SHOW_TIME\r
2117         do_gettimeofday(&enc_end);\r
2118         pr_info("enc task: %ld ms\n",\r
2119                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
2120                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
2121 #endif\r
2122         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
2123                 /* clear enc IRQ */\r
2124                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2125                 atomic_add(1, &dev->irq_count_codec);\r
2126         }\r
2127 \r
2128         pservice->irq_status = irq_status;\r
2129 \r
2130         vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);\r
2131 \r
2132         return IRQ_WAKE_THREAD;\r
2133 }\r
2134 \r
2135 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
2136 {\r
2137         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2138         vpu_device *dev = &pservice->enc_dev;\r
2139 \r
2140         mutex_lock(&pservice->lock);\r
2141         if (atomic_read(&dev->irq_count_codec)) {\r
2142                 atomic_sub(1, &dev->irq_count_codec);\r
2143                 if (NULL == pservice->reg_codec) {\r
2144                         pr_err("error: enc isr with no task waiting\n");\r
2145                 } else {\r
2146                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2147                 }\r
2148         }\r
2149         try_set_reg(pservice);\r
2150         mutex_unlock(&pservice->lock);\r
2151         return IRQ_HANDLED;\r
2152 }\r
2153 \r
2154 static int __init vcodec_service_init(void)\r
2155 {\r
2156         int ret;\r
2157 \r
2158         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
2159                 pr_err("Platform device register failed (%d).\n", ret);\r
2160                 return ret;\r
2161         }\r
2162 \r
2163 #ifdef CONFIG_DEBUG_FS\r
2164         vcodec_debugfs_init();\r
2165 #endif\r
2166 \r
2167         return ret;\r
2168 }\r
2169 \r
2170 static void __exit vcodec_service_exit(void)\r
2171 {\r
2172 #ifdef CONFIG_DEBUG_FS\r
2173         vcodec_debugfs_exit();\r
2174 #endif\r
2175 \r
2176         platform_driver_unregister(&vcodec_driver);\r
2177 }\r
2178 \r
2179 module_init(vcodec_service_init);\r
2180 module_exit(vcodec_service_exit);\r
2181 \r
2182 #ifdef CONFIG_DEBUG_FS\r
2183 #include <linux/seq_file.h>\r
2184 \r
2185 static int vcodec_debugfs_init()\r
2186 {\r
2187         parent = debugfs_create_dir("vcodec", NULL);\r
2188         if (!parent)\r
2189                 return -1;\r
2190 \r
2191         return 0;\r
2192 }\r
2193 \r
2194 static void vcodec_debugfs_exit()\r
2195 {\r
2196         debugfs_remove(parent);\r
2197 }\r
2198 \r
2199 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2200 {\r
2201         return debugfs_create_dir(dirname, parent);\r
2202 }\r
2203 \r
2204 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2205 {\r
2206         struct vpu_service_info *pservice = s->private;\r
2207         unsigned int i, n;\r
2208         vpu_reg *reg, *reg_tmp;\r
2209         vpu_session *session, *session_tmp;\r
2210 \r
2211         mutex_lock(&pservice->lock);\r
2212         vpu_service_power_on(pservice);\r
2213         if (pservice->hw_info->hw_id != HEVC_ID) {\r
2214                 seq_printf(s, "\nENC Registers:\n");\r
2215                 n = pservice->enc_dev.iosize >> 2;\r
2216                 for (i = 0; i < n; i++) {\r
2217                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2218                 }\r
2219         }\r
2220         seq_printf(s, "\nDEC Registers:\n");\r
2221         n = pservice->dec_dev.iosize >> 2;\r
2222         for (i = 0; i < n; i++)\r
2223                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2224 \r
2225         seq_printf(s, "\nvpu service status:\n");\r
2226         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2227                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2228                 /*seq_printf(s, "waiting reg set %d\n");*/\r
2229                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2230                         seq_printf(s, "waiting register set\n");\r
2231                 }\r
2232                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2233                         seq_printf(s, "running register set\n");\r
2234                 }\r
2235                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2236                         seq_printf(s, "done    register set\n");\r
2237                 }\r
2238         }\r
2239         mutex_unlock(&pservice->lock);\r
2240 \r
2241         return 0;\r
2242 }\r
2243 \r
2244 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2245 {\r
2246         return single_open(file, debug_vcodec_show, inode->i_private);\r
2247 }\r
2248 \r
2249 #endif\r
2250 \r
2251 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2252 #include "hevc_test_inc/pps_00.h"\r
2253 #include "hevc_test_inc/register_00.h"\r
2254 #include "hevc_test_inc/rps_00.h"\r
2255 #include "hevc_test_inc/scaling_list_00.h"\r
2256 #include "hevc_test_inc/stream_00.h"\r
2257 \r
2258 #include "hevc_test_inc/pps_01.h"\r
2259 #include "hevc_test_inc/register_01.h"\r
2260 #include "hevc_test_inc/rps_01.h"\r
2261 #include "hevc_test_inc/scaling_list_01.h"\r
2262 #include "hevc_test_inc/stream_01.h"\r
2263 \r
2264 #include "hevc_test_inc/cabac.h"\r
2265 \r
2266 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2267 \r
2268 static struct ion_client *ion_client = NULL;\r
2269 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2270 {\r
2271         int size = (len+15) & (~15);\r
2272         struct ion_handle *handle;\r
2273         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2274 \r
2275         if (ion_client == NULL)\r
2276                 ion_client = rockchip_ion_client_create("vcodec");\r
2277 \r
2278         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2279 \r
2280         ptr = ion_map_kernel(ion_client, handle);\r
2281 \r
2282         ion_phys(ion_client, handle, phy, &size);\r
2283 \r
2284         memcpy(ptr, tbl, len);\r
2285 \r
2286         return ptr;\r
2287 }\r
2288 \r
2289 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2290 {\r
2291         int size = (len+15) & (~15);\r
2292         struct ion_handle *handle;\r
2293         u8 *ptr;\r
2294 \r
2295         if (ion_client == NULL)\r
2296                 ion_client = rockchip_ion_client_create("vcodec");\r
2297 \r
2298         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2299 \r
2300         ptr = ion_map_kernel(ion_client, handle);\r
2301 \r
2302         ion_phys(ion_client, handle, phy, &size);\r
2303 \r
2304         return ptr;\r
2305 }\r
2306 \r
2307 #define TEST_CNT    2\r
2308 static int hevc_test_case0(vpu_service_info *pservice)\r
2309 {\r
2310         vpu_session session;\r
2311         vpu_reg *reg; \r
2312         unsigned long size = 272;//sizeof(register_00); // registers array length\r
2313         int testidx = 0;\r
2314         int ret = 0;\r
2315 \r
2316         u8 *pps_tbl[TEST_CNT];\r
2317         u8 *register_tbl[TEST_CNT];\r
2318         u8 *rps_tbl[TEST_CNT];\r
2319         u8 *scaling_list_tbl[TEST_CNT];\r
2320         u8 *stream_tbl[TEST_CNT];\r
2321 \r
2322         int stream_size[2];\r
2323         int pps_size[2];\r
2324         int rps_size[2];\r
2325         int scl_size[2];\r
2326         int cabac_size[2];\r
2327         \r
2328         u32 phy_pps;\r
2329         u32 phy_rps;\r
2330         u32 phy_scl;\r
2331         u32 phy_str;\r
2332         u32 phy_yuv;\r
2333         u32 phy_ref;\r
2334         u32 phy_cabac;\r
2335 \r
2336         volatile u8 *stream_buf;\r
2337         volatile u8 *pps_buf;\r
2338         volatile u8 *rps_buf;\r
2339         volatile u8 *scl_buf;\r
2340         volatile u8 *yuv_buf;\r
2341         volatile u8 *cabac_buf;\r
2342         volatile u8 *ref_buf;\r
2343 \r
2344         u8 *pps;\r
2345         u8 *yuv[2];\r
2346         int i;\r
2347 \r
2348         pps_tbl[0] = pps_00;\r
2349         pps_tbl[1] = pps_01;\r
2350 \r
2351         register_tbl[0] = register_00;\r
2352         register_tbl[1] = register_01;\r
2353 \r
2354         rps_tbl[0] = rps_00;\r
2355         rps_tbl[1] = rps_01;\r
2356 \r
2357         scaling_list_tbl[0] = scaling_list_00;\r
2358         scaling_list_tbl[1] = scaling_list_01;\r
2359 \r
2360         stream_tbl[0] = stream_00;\r
2361         stream_tbl[1] = stream_01;\r
2362 \r
2363         stream_size[0] = sizeof(stream_00);\r
2364         stream_size[1] = sizeof(stream_01);\r
2365 \r
2366         pps_size[0] = sizeof(pps_00);\r
2367         pps_size[1] = sizeof(pps_01);\r
2368 \r
2369         rps_size[0] = sizeof(rps_00);\r
2370         rps_size[1] = sizeof(rps_01);\r
2371 \r
2372         scl_size[0] = sizeof(scaling_list_00);\r
2373         scl_size[1] = sizeof(scaling_list_01);\r
2374         \r
2375         cabac_size[0] = sizeof(Cabac_table);\r
2376         cabac_size[1] = sizeof(Cabac_table);\r
2377 \r
2378         /* create session */\r
2379         session.pid = current->pid;\r
2380         session.type = VPU_DEC;\r
2381         INIT_LIST_HEAD(&session.waiting);\r
2382         INIT_LIST_HEAD(&session.running);\r
2383         INIT_LIST_HEAD(&session.done);\r
2384         INIT_LIST_HEAD(&session.list_session);\r
2385         init_waitqueue_head(&session.wait);\r
2386         atomic_set(&session.task_running, 0);\r
2387         list_add_tail(&session.list_session, &pservice->session);\r
2388 \r
2389         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2390         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2391 \r
2392         while (testidx < TEST_CNT) {\r
2393                 /* create registers */\r
2394                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2395                 if (NULL == reg) {\r
2396                         pr_err("error: kmalloc fail in reg_init\n");\r
2397                         return -1;\r
2398                 }\r
2399 \r
2400                 if (size > pservice->reg_size) {\r
2401                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2402                         size = pservice->reg_size;\r
2403                 }\r
2404                 reg->session = &session;\r
2405                 reg->type = session.type;\r
2406                 reg->size = size;\r
2407                 reg->freq = VPU_FREQ_DEFAULT;\r
2408                 reg->reg = (unsigned long *)&reg[1];\r
2409                 INIT_LIST_HEAD(&reg->session_link);\r
2410                 INIT_LIST_HEAD(&reg->status_link);\r
2411 \r
2412                 /* TODO: stuff registers */\r
2413                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2414 \r
2415                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2416                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2417                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2418                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2419                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2420 \r
2421                 pps = pps_buf;\r
2422 \r
2423                 /* TODO: replace reigster address */\r
2424                 for (i=0; i<64; i++) {\r
2425                         u32 scaling_offset;\r
2426                         u32 tmp;\r
2427 \r
2428                         scaling_offset = (u32)pps[i*80+74];\r
2429                         scaling_offset += (u32)pps[i*80+75] << 8;\r
2430                         scaling_offset += (u32)pps[i*80+76] << 16;\r
2431                         scaling_offset += (u32)pps[i*80+77] << 24;\r
2432 \r
2433                         tmp = phy_scl + scaling_offset;\r
2434 \r
2435                         pps[i*80+74] = tmp & 0xff;\r
2436                         pps[i*80+75] = (tmp >> 8) & 0xff;\r
2437                         pps[i*80+76] = (tmp >> 16) & 0xff;\r
2438                         pps[i*80+77] = (tmp >> 24) & 0xff;\r
2439                 }\r
2440 \r
2441                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",\r
2442                         __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2443 \r
2444                 reg->reg[1] = 0x21;\r
2445                 reg->reg[4] = phy_str;\r
2446                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2447                 reg->reg[6] = phy_cabac;\r
2448                 reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2449                 reg->reg[42] = phy_pps;\r
2450                 reg->reg[43] = phy_rps;\r
2451                 for (i = 10; i <= 24; i++)\r
2452                         reg->reg[i] = phy_yuv;\r
2453 \r
2454                 mutex_lock(&pservice->lock);\r
2455                 list_add_tail(&reg->status_link, &pservice->waiting);\r
2456                 list_add_tail(&reg->session_link, &session.waiting);\r
2457                 mutex_unlock(&pservice->lock);\r
2458 \r
2459                 printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2460 \r
2461                 /* stuff hardware */\r
2462                 try_set_reg(pservice);\r
2463 \r
2464                 /* wait for result */\r
2465                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2466                 if (!list_empty(&session.done)) {\r
2467                         if (ret < 0)\r
2468                                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2469                         ret = 0;\r
2470                 } else {\r
2471                         if (unlikely(ret < 0)) {\r
2472                                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2473                         } else if (0 == ret) {\r
2474                                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2475                                 ret = -ETIMEDOUT;\r
2476                         }\r
2477                 }\r
2478                 if (ret < 0) {\r
2479                         int task_running = atomic_read(&session.task_running);\r
2480                         int n;\r
2481                         mutex_lock(&pservice->lock);\r
2482                         vpu_service_dump(pservice);\r
2483                         if (task_running) {\r
2484                                 atomic_set(&session.task_running, 0);\r
2485                                 atomic_sub(task_running, &pservice->total_running);\r
2486                                 printk("%d task is running but not return, reset hardware...", task_running);\r
2487                                 vpu_reset(pservice);\r
2488                                 printk("done\n");\r
2489                         }\r
2490                         vpu_service_session_clear(pservice, &session);\r
2491                         mutex_unlock(&pservice->lock);\r
2492 \r
2493                         printk("\nDEC Registers:\n");\r
2494                         n = pservice->dec_dev.iosize >> 2;\r
2495                         for (i=0; i<n; i++)\r
2496                                 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2497 \r
2498                         pr_err("test index %d failed\n", testidx);\r
2499                         break;\r
2500                 } else {\r
2501                         pr_info("test index %d success\n", testidx);\r
2502 \r
2503                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2504 \r
2505                         for (i=0; i<68; i++) {\r
2506                                 if (i % 4 == 0)\r
2507                                         printk("%02d: ", i);\r
2508                                 printk("%08x ", reg->reg[i]);\r
2509                                 if ((i+1) % 4 == 0)\r
2510                                         printk("\n");\r
2511                         }\r
2512 \r
2513                         testidx++;\r
2514                 }\r
2515 \r
2516                 reg_deinit(pservice, reg);\r
2517         }\r
2518 \r
2519         return 0;\r
2520 }\r
2521 \r
2522 #endif\r
2523 \r