2 /* arch/arm/mach-rk29/vpu.c
4 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * author: chenhengming chm@rock-chips.com
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/miscdevice.h>
29 #include <linux/poll.h>
30 #include <linux/platform_device.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/wakelock.h>
34 #include <linux/cdev.h>
36 #include <linux/of_platform.h>
37 #include <linux/rockchip/cpu.h>
38 #include <linux/rockchip/cru.h>
40 #include <asm/cacheflush.h>
41 #include <linux/uaccess.h>
42 #include <linux/rockchip/grf.h>
44 #if defined(CONFIG_ION_ROCKCHIP)
45 #include <linux/rockchip_ion.h>
48 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
49 #define CONFIG_VCODEC_MMU
52 #ifdef CONFIG_VCODEC_MMU
53 #include <linux/rockchip-iovmm.h>
54 #include <linux/dma-buf.h>
57 #ifdef CONFIG_DEBUG_FS
58 #include <linux/debugfs.h>
61 #if defined(CONFIG_ARCH_RK319X)
65 #include "vcodec_service.h"
67 #define HEVC_TEST_ENABLE 0
68 #define HEVC_SIM_ENABLE 0
69 #define VCODEC_CLOCK_ENABLE 1
72 VPU_DEC_ID_9190 = 0x6731,
79 VPU_DEC_TYPE_9190 = 0,
80 VPU_ENC_TYPE_8270 = 0x100,
84 typedef enum VPU_FREQ {
97 unsigned long hw_addr;
98 unsigned long enc_offset;
99 unsigned long enc_reg_num;
100 unsigned long enc_io_size;
101 unsigned long dec_offset;
102 unsigned long dec_reg_num;
103 unsigned long dec_io_size;
106 struct extra_info_elem {
111 #define EXTRA_INFO_MAGIC 0x4C4A46
113 struct extra_info_for_iommu {
116 struct extra_info_elem elem[20];
119 #define VPU_SERVICE_SHOW_TIME 0
121 #if VPU_SERVICE_SHOW_TIME
122 static struct timeval enc_start, enc_end;
123 static struct timeval dec_start, dec_end;
124 static struct timeval pp_start, pp_end;
127 #define MHZ (1000*1000)
129 #define REG_NUM_9190_DEC (60)
130 #define REG_NUM_9190_PP (41)
131 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
133 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
135 #define REG_NUM_ENC_8270 (96)
136 #define REG_SIZE_ENC_8270 (0x200)
137 #define REG_NUM_ENC_4831 (164)
138 #define REG_SIZE_ENC_4831 (0x400)
140 #define REG_NUM_HEVC_DEC (68)
142 #define SIZE_REG(reg) ((reg)*4)
144 static VPU_HW_INFO_E vpu_hw_set[] = {
146 .hw_id = VPU_ID_8270,
149 .enc_reg_num = REG_NUM_ENC_8270,
150 .enc_io_size = REG_NUM_ENC_8270 * 4,
151 .dec_offset = REG_SIZE_ENC_8270,
152 .dec_reg_num = REG_NUM_9190_DEC_PP,
153 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
156 .hw_id = VPU_ID_4831,
159 .enc_reg_num = REG_NUM_ENC_4831,
160 .enc_io_size = REG_NUM_ENC_4831 * 4,
161 .dec_offset = REG_SIZE_ENC_4831,
162 .dec_reg_num = REG_NUM_9190_DEC_PP,
163 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
169 .dec_reg_num = REG_NUM_HEVC_DEC,
170 .dec_io_size = REG_NUM_HEVC_DEC * 4,
173 .hw_id = VPU_DEC_ID_9190,
178 .dec_offset = REG_SIZE_ENC_4831,
179 .dec_reg_num = REG_NUM_9190_DEC_PP,
180 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
186 #define DEC_INTERRUPT_REGISTER 1
187 #define PP_INTERRUPT_REGISTER 60
188 #define ENC_INTERRUPT_REGISTER 1
190 #define DEC_INTERRUPT_BIT 0x100
191 #define DEC_BUFFER_EMPTY_BIT 0x4000
192 #define PP_INTERRUPT_BIT 0x100
193 #define ENC_INTERRUPT_BIT 0x1
195 #define HEVC_DEC_INT_RAW_BIT 0x200
196 #define HEVC_DEC_STR_ERROR_BIT 0x4000
197 #define HEVC_DEC_BUS_ERROR_BIT 0x2000
198 #define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000
200 #define VPU_REG_EN_ENC 14
201 #define VPU_REG_ENC_GATE 2
202 #define VPU_REG_ENC_GATE_BIT (1<<4)
204 #define VPU_REG_EN_DEC 1
205 #define VPU_REG_DEC_GATE 2
206 #define VPU_REG_DEC_GATE_BIT (1<<10)
207 #define VPU_REG_EN_PP 0
208 #define VPU_REG_PP_GATE 1
209 #define VPU_REG_PP_GATE_BIT (1<<8)
210 #define VPU_REG_EN_DEC_PP 1
211 #define VPU_REG_DEC_PP_GATE 61
212 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
214 #if defined(CONFIG_VCODEC_MMU)
215 static u8 addr_tbl_vpu_h264dec[] = {
216 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
217 25, 26, 27, 28, 29, 40, 41
220 static u8 addr_tbl_vpu_vp8dec[] = {
221 10, 12, 13, 14, 18, 19, 27, 40
224 static u8 addr_tbl_vpu_vp6dec[] = {
225 12, 13, 14, 18, 27, 40
228 static u8 addr_tbl_vpu_vc1dec[] = {
229 12, 13, 14, 15, 16, 17, 27, 41
232 static u8 addr_tbl_vpu_jpegdec[] = {
236 static u8 addr_tbl_vpu_defaultdec[] = {
237 12, 13, 14, 15, 16, 17, 40, 41
240 static u8 addr_tbl_vpu_enc[] = {
241 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
244 static u8 addr_tbl_hevc_dec[] = {
245 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
246 21, 22, 23, 24, 42, 43
271 * struct for process session which connect to vpu
273 * @author ChenHengming (2011-5-3)
275 typedef struct vpu_session {
276 VPU_CLIENT_TYPE type;
277 /* a linked list of data so we can access them for debugging */
278 struct list_head list_session;
279 /* a linked list of register data waiting for process */
280 struct list_head waiting;
281 /* a linked list of register data in processing */
282 struct list_head running;
283 /* a linked list of register data processed */
284 struct list_head done;
285 wait_queue_head_t wait;
287 atomic_t task_running;
291 * struct for process register set
293 * @author ChenHengming (2011-5-4)
295 typedef struct vpu_reg {
296 VPU_CLIENT_TYPE type;
298 vpu_session *session;
299 struct list_head session_link; /* link to vpu service session */
300 struct list_head status_link; /* link to register set list */
302 #if defined(CONFIG_VCODEC_MMU)
303 struct list_head mem_region_list;
308 typedef struct vpu_device {
309 atomic_t irq_count_codec;
310 atomic_t irq_count_pp;
311 unsigned long iobaseaddr;
313 volatile u32 *hwregs;
316 enum vcodec_device_id {
317 VCODEC_DEVICE_ID_VPU,
318 VCODEC_DEVICE_ID_HEVC
321 struct vcodec_mem_region {
322 struct list_head srv_lnk;
323 struct list_head reg_lnk;
324 struct list_head session_lnk;
325 unsigned long iova; /* virtual address for iommu */
327 struct ion_handle *hdl;
330 typedef struct vpu_service_info {
331 struct wake_lock wake_lock;
332 struct delayed_work power_off_work;
334 struct list_head *waiting; /* link to link_reg in struct vpu_reg */
335 struct list_head *running; /* link to link_reg in struct vpu_reg */
336 struct list_head done; /* link to link_reg in struct vpu_reg */
337 struct list_head session; /* link to list_session in struct vpu_session */
338 atomic_t total_running;
343 VPUHwDecConfig_t dec_config;
344 VPUHwEncConfig_t enc_config;
345 VPU_HW_INFO_E *hw_info;
346 unsigned long reg_size;
349 atomic_t freq_status;
351 struct clk *aclk_vcodec;
352 struct clk *hclk_vcodec;
353 struct clk *clk_core;
354 struct clk *clk_cabac;
355 struct clk *pd_video;
368 struct device *child_dev;
370 struct dentry *debugfs_dir;
371 struct dentry *debugfs_file_regs;
374 #if defined(CONFIG_VCODEC_MMU)
375 struct ion_client *ion_client;
376 struct list_head mem_region_list;
377 struct device *mmu_dev;
380 enum vcodec_device_id dev_id;
384 struct delayed_work simulate_work;
387 struct vcodec_combo {
388 struct vpu_service_info *vpu_srv;
389 struct vpu_service_info *hevc_srv;
390 struct list_head waiting;
391 struct list_head running;
392 struct mutex run_lock;
394 enum vcodec_device_id current_hw_mode;
397 typedef struct vpu_request
404 //static struct clk *pd_video;
405 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
406 /* mutex for selecting operation registers of vpu or hevc */
407 static struct mutex g_mode_mutex;
408 static struct vcodec_combo g_combo;
410 #ifdef CONFIG_DEBUG_FS
411 static int vcodec_debugfs_init(void);
412 static void vcodec_debugfs_exit(void);
413 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
414 static int debug_vcodec_open(struct inode *inode, struct file *file);
416 static const struct file_operations debug_vcodec_fops = {
417 .open = debug_vcodec_open,
420 .release = single_release,
424 #define VDPU_SOFT_RESET_REG 101
425 #define VDPU_CLEAR_CACHE_REG 516
426 #define VEPU_CLEAR_CACHE_REG 772
427 #define HEVC_CLEAR_CACHE_REG 260
429 #define VPU_REG_ENABLE(base, reg) do { \
433 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
434 #define VDPU_CLEAR_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAR_CACHE_REG)
435 #define VEPU_CLEAR_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAR_CACHE_REG)
436 #define HEVC_CLEAR_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAR_CACHE_REG)
438 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
439 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
440 #define VPU_SIMULATE_DELAY msecs_to_jiffies(15)
442 #define BIT_VCODEC_SEL_RK3036 (1<<3)
443 #define BIT_VCODEC_SEL_RK312X (1<<15)
444 static void vcodec_enter_mode_nolock(enum vcodec_device_id id, u32 *reserved_mode)
446 if (cpu_is_rk3036() || cpu_is_rk312x()) {
447 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
448 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
450 *reserved_mode = readl_relaxed(addr);
451 if (id == VCODEC_DEVICE_ID_HEVC)
452 writel_relaxed(readl_relaxed(addr) | (bits) | (bits << 16), addr);
454 writel_relaxed((readl_relaxed(addr) & (~bits)) | (bits << 16), addr);
458 static void vcodec_exit_mode_nolock(enum vcodec_device_id id, u32 reserved_mode)
460 if (cpu_is_rk3036() || cpu_is_rk312x()) {
461 int bits = cpu_is_rk3036() ? BIT_VCODEC_SEL_RK3036 : BIT_VCODEC_SEL_RK312X;
462 void __iomem *addr = cpu_is_rk3036() ? (RK_GRF_VIRT + RK3036_GRF_SOC_CON1) : (RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
463 writel_relaxed(reserved_mode | (bits << 16), addr);
467 static void vcodec_enter_mode(enum vcodec_device_id id)
469 if (cpu_is_rk3036() || cpu_is_rk312x())
470 mutex_lock(&g_mode_mutex);
471 vcodec_enter_mode_nolock(id, NULL);
474 static void vcodec_exit_mode(void)
476 if (cpu_is_rk3036() || cpu_is_rk312x())
477 mutex_unlock(&g_mode_mutex);
480 static int vpu_get_clk(struct vpu_service_info *pservice)
482 #if VCODEC_CLOCK_ENABLE
484 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
485 if (IS_ERR(pservice->aclk_vcodec)) {
486 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
490 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
491 if (IS_ERR(pservice->hclk_vcodec)) {
492 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
496 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
497 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
498 if (IS_ERR(pservice->clk_core)) {
499 dev_err(pservice->dev, "failed on clk_get clk_core\n");
503 if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
504 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
505 if (IS_ERR(pservice->clk_cabac)) {
506 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
510 pservice->clk_cabac = NULL;
513 if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
514 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
515 if (IS_ERR(pservice->pd_video)) {
516 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
520 pservice->pd_video = NULL;
523 if (!cpu_is_rk3036() && !cpu_is_rk312x()) {
524 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
525 if (IS_ERR(pservice->pd_video)) {
526 dev_err(pservice->dev, "failed on clk_get pd_video\n");
530 pservice->pd_video = NULL;
534 if (cpu_is_rk312x()) {
535 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
536 if (IS_ERR(pservice->pd_video)) {
537 dev_err(pservice->dev, "failed on clk_get pd_video\n");
551 static void vpu_put_clk(struct vpu_service_info *pservice)
553 #if VCODEC_CLOCK_ENABLE
554 if (pservice->pd_video) {
555 devm_clk_put(pservice->dev, pservice->pd_video);
558 if (pservice->aclk_vcodec) {
559 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
562 if (pservice->hclk_vcodec) {
563 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
566 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
567 if (pservice->clk_core) {
568 devm_clk_put(pservice->dev, pservice->clk_core);
571 if (pservice->clk_cabac) {
572 devm_clk_put(pservice->dev, pservice->clk_cabac);
578 static void vpu_reset(struct vpu_service_info *pservice)
580 #if defined(CONFIG_ARCH_RK29)
581 clk_disable(aclk_ddr_vepu);
582 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
583 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
584 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
585 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
587 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
588 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
589 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
590 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
591 clk_enable(aclk_ddr_vepu);
592 #elif defined(CONFIG_ARCH_RK30)
593 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
594 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
595 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
596 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
597 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
599 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
600 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
601 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
602 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
603 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
605 *pservice->reg_codec = NULL;
606 pservice->reg_pproc = NULL;
607 pservice->reg_resev = NULL;
610 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
611 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
614 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
615 reg_deinit(pservice, reg);
617 list_for_each_entry_safe(reg, n, &session->running, session_link) {
618 reg_deinit(pservice, reg);
620 list_for_each_entry_safe(reg, n, &session->done, session_link) {
621 reg_deinit(pservice, reg);
625 static void vpu_service_dump(struct vpu_service_info *pservice)
628 vpu_reg *reg, *reg_tmp;
629 vpu_session *session, *session_tmp;
631 running = atomic_read(&pservice->total_running);
632 printk("total_running %d\n", running);
634 printk("reg_codec 0x%.8x\n", (unsigned int)(*pservice->reg_codec));
635 printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
636 printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
638 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
639 printk("session pid %d type %d:\n", session->pid, session->type);
640 running = atomic_read(&session->task_running);
641 printk("task_running %d\n", running);
642 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
643 printk("waiting register set 0x%.8x\n", (unsigned int)reg);
645 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
646 printk("running register set 0x%.8x\n", (unsigned int)reg);
648 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
649 printk("done register set 0x%.8x\n", (unsigned int)reg);
654 static void vpu_service_power_off(struct vpu_service_info *pservice)
657 if (!pservice->enabled)
660 pservice->enabled = false;
661 total_running = atomic_read(&pservice->total_running);
663 pr_alert("alert: power off when %d task running!!\n", total_running);
665 pr_alert("alert: delay 50 ms for running task\n");
666 vpu_service_dump(pservice);
669 pr_info("%s: power off...", dev_name(pservice->dev));
672 #if defined(CONFIG_VCODEC_MMU)
673 if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
674 vcodec_enter_mode(pservice->dev_id);
675 rockchip_iovmm_deactivate(pservice->dev);
680 #if VCODEC_CLOCK_ENABLE
681 if (pservice->pd_video)
682 clk_disable_unprepare(pservice->pd_video);
683 if (pservice->hclk_vcodec)
684 clk_disable_unprepare(pservice->hclk_vcodec);
685 if (pservice->aclk_vcodec)
686 clk_disable_unprepare(pservice->aclk_vcodec);
687 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
688 if (pservice->clk_core)
689 clk_disable_unprepare(pservice->clk_core);
690 if (pservice->clk_cabac)
691 clk_disable_unprepare(pservice->clk_cabac);
695 wake_unlock(&pservice->wake_lock);
699 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
701 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
704 static void vpu_power_off_work(struct work_struct *work_s)
706 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
707 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
709 if (mutex_trylock(pservice->lock)) {
710 vpu_service_power_off(pservice);
711 mutex_unlock(pservice->lock);
713 /* Come back later if the device is busy... */
714 vpu_queue_power_off_work(pservice);
718 static void vpu_service_power_on(struct vpu_service_info *pservice)
721 ktime_t now = ktime_get();
722 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
723 cancel_delayed_work_sync(&pservice->power_off_work);
724 vpu_queue_power_off_work(pservice);
727 if (pservice->enabled)
730 pservice->enabled = true;
731 printk("%s: power on\n", dev_name(pservice->dev));
733 #if VCODEC_CLOCK_ENABLE
734 if (pservice->aclk_vcodec)
735 clk_prepare_enable(pservice->aclk_vcodec);
737 if (pservice->hclk_vcodec)
738 clk_prepare_enable(pservice->hclk_vcodec);
740 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {
741 if (pservice->clk_core)
742 clk_prepare_enable(pservice->clk_core);
743 if (pservice->clk_cabac)
744 clk_prepare_enable(pservice->clk_cabac);
747 if (pservice->pd_video)
748 clk_prepare_enable(pservice->pd_video);
751 #if defined(CONFIG_ARCH_RK319X)
752 /// select aclk_vepu as vcodec clock source.
753 #define BIT_VCODEC_SEL (1<<7)
754 writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |
755 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),
756 RK319X_GRF_BASE + GRF_SOC_CON1);
758 #define BIT_VCODEC_CLK_SEL (1<<10)
760 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
761 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
762 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
765 wake_lock(&pservice->wake_lock);
767 #if defined(CONFIG_VCODEC_MMU)
768 if (pservice->mmu_dev && !(cpu_is_rk3036() || cpu_is_rk312x())) {
769 vcodec_enter_mode(pservice->dev_id);
770 rockchip_iovmm_activate(pservice->dev);
776 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
778 unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
779 return ((type == 8) || (type == 4));
782 static inline bool reg_check_interlace(vpu_reg *reg)
784 unsigned long type = (reg->reg[3] & (1 << 23));
788 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
790 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
794 static inline int reg_probe_width(vpu_reg *reg)
796 int width_in_mb = reg->reg[4] >> 23;
797 return width_in_mb * 16;
800 #if defined(CONFIG_VCODEC_MMU)
801 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl,
802 int size, vpu_reg *reg,
803 struct extra_info_for_iommu *ext_inf)
809 if (tbl == NULL || size <= 0) {
810 dev_err(pservice->dev, "input arguments invalidate\n");
814 vpu_service_power_on(pservice);
816 for (i = 0; i < size; i++) {
817 usr_fd = reg->reg[tbl[i]] & 0x3FF;
819 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&
820 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
821 /* special for vpu dec num 41 regitster */
822 offset = reg->reg[tbl[i]] >> 10 << 4;
824 offset = reg->reg[tbl[i]] >> 10;
827 struct ion_handle *hdl;
829 struct vcodec_mem_region *mem_region;
831 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
833 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
837 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
839 if (mem_region == NULL) {
840 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
841 ion_free(pservice->ion_client, hdl);
845 mem_region->hdl = hdl;
846 vcodec_enter_mode(pservice->dev_id);
847 ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);
851 dev_err(pservice->dev, "ion map iommu failed\n");
853 ion_free(pservice->ion_client, hdl);
856 reg->reg[tbl[i]] = mem_region->iova + offset;
857 INIT_LIST_HEAD(&mem_region->reg_lnk);
858 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
862 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
863 for (i=0; i<ext_inf->cnt; i++) {
864 pr_info("reg[%d] + offset %d\n", ext_inf->elem[i].index, ext_inf->elem[i].offset);
865 reg->reg[ext_inf->elem[i].index] += ext_inf->elem[i].offset;
872 static int vcodec_reg_address_translate(struct vpu_service_info *pservice,
874 struct extra_info_for_iommu *ext_inf)
880 hw_id = pservice->hw_info->hw_id;
882 if (hw_id == HEVC_ID) {
883 tbl = addr_tbl_hevc_dec;
884 size = sizeof(addr_tbl_hevc_dec);
886 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
887 switch (reg_check_fmt(reg)) {
888 case VPU_DEC_FMT_H264:
890 tbl = addr_tbl_vpu_h264dec;
891 size = sizeof(addr_tbl_vpu_h264dec);
894 case VPU_DEC_FMT_VP8:
895 case VPU_DEC_FMT_VP7:
897 tbl = addr_tbl_vpu_vp8dec;
898 size = sizeof(addr_tbl_vpu_vp8dec);
902 case VPU_DEC_FMT_VP6:
904 tbl = addr_tbl_vpu_vp6dec;
905 size = sizeof(addr_tbl_vpu_vp6dec);
908 case VPU_DEC_FMT_VC1:
910 tbl = addr_tbl_vpu_vc1dec;
911 size = sizeof(addr_tbl_vpu_vc1dec);
915 case VPU_DEC_FMT_JPEG:
917 tbl = addr_tbl_vpu_jpegdec;
918 size = sizeof(addr_tbl_vpu_jpegdec);
922 tbl = addr_tbl_vpu_defaultdec;
923 size = sizeof(addr_tbl_vpu_defaultdec);
926 } else if (reg->type == VPU_ENC) {
927 tbl = addr_tbl_vpu_enc;
928 size = sizeof(addr_tbl_vpu_enc);
933 return vcodec_bufid_to_iova(pservice, tbl, size, reg, ext_inf);
940 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
943 struct extra_info_for_iommu extra_info;
944 vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
946 pr_err("error: kmalloc fail in reg_init\n");
950 if (size > pservice->reg_size) {
951 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
952 size = pservice->reg_size;*/
953 extra_size = size - pservice->reg_size;
954 size = pservice->reg_size;
956 reg->session = session;
957 reg->type = session->type;
959 reg->freq = VPU_FREQ_DEFAULT;
960 reg->reg = (unsigned long *)®[1];
961 INIT_LIST_HEAD(®->session_link);
962 INIT_LIST_HEAD(®->status_link);
964 #if defined(CONFIG_VCODEC_MMU)
965 if (pservice->mmu_dev)
966 INIT_LIST_HEAD(®->mem_region_list);
969 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
970 pr_err("error: copy_from_user failed in reg_init\n");
975 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
976 pr_err("error: copy_from_user failed in reg_init\n");
981 #if defined(CONFIG_VCODEC_MMU)
982 if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg, &extra_info)) {
983 pr_err("error: translate reg address failed\n");
989 mutex_lock(pservice->lock);
990 list_add_tail(®->status_link, pservice->waiting);
991 list_add_tail(®->session_link, &session->waiting);
992 mutex_unlock(pservice->lock);
994 if (pservice->auto_freq) {
995 if (!soc_is_rk2928g()) {
996 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
997 if (reg_check_rmvb_wmv(reg)) {
998 reg->freq = VPU_FREQ_200M;
999 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1000 if (reg_probe_width(reg) > 3200) {
1001 // raise frequency for 4k avc.
1002 reg->freq = VPU_FREQ_500M;
1005 if (reg_check_interlace(reg)) {
1006 reg->freq = VPU_FREQ_400M;
1010 if (reg->type == VPU_PP) {
1011 reg->freq = VPU_FREQ_400M;
1016 /*reg->reg[2] &= (~0x800000L);*/
1021 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
1023 #if defined(CONFIG_VCODEC_MMU)
1024 struct vcodec_mem_region *mem_region = NULL, *n;
1027 list_del_init(®->session_link);
1028 list_del_init(®->status_link);
1029 if (reg == (*pservice->reg_codec))
1030 *pservice->reg_codec = NULL;
1031 if (reg == pservice->reg_pproc)
1032 pservice->reg_pproc = NULL;
1034 #if defined(CONFIG_VCODEC_MMU)
1035 // release memory region attach to this registers table.
1036 if (pservice->mmu_dev) {
1037 list_for_each_entry_safe(mem_region, n, ®->mem_region_list, reg_lnk) {
1038 /* do not unmap iommu manually,
1039 unmap will proccess when memory release */
1040 /*vcodec_enter_mode(pservice->dev_id);
1041 ion_unmap_iommu(pservice->dev,
1042 pservice->ion_client,
1044 vcodec_exit_mode();*/
1045 ion_free(pservice->ion_client, mem_region->hdl);
1046 list_del_init(&mem_region->reg_lnk);
1055 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1057 list_del_init(®->status_link);
1058 list_add_tail(®->status_link, pservice->running);
1060 list_del_init(®->session_link);
1061 list_add_tail(®->session_link, ®->session->running);
1064 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1067 u32 *dst = (u32 *)®->reg[0];
1069 for (i = 0; i < count; i++)
1073 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
1076 list_del_init(®->status_link);
1077 list_add_tail(®->status_link, &pservice->done);
1079 list_del_init(®->session_link);
1080 list_add_tail(®->session_link, ®->session->done);
1082 vcodec_enter_mode(pservice->dev_id);
1083 switch (reg->type) {
1085 *pservice->reg_codec = NULL;
1086 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
1087 irq_reg = ENC_INTERRUPT_REGISTER;
1091 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1092 *pservice->reg_codec = NULL;
1093 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);
1094 irq_reg = DEC_INTERRUPT_REGISTER;
1098 pservice->reg_pproc = NULL;
1099 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1100 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1104 *pservice->reg_codec = NULL;
1105 pservice->reg_pproc = NULL;
1106 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1107 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1111 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
1115 if (cpu_is_rk3036() || cpu_is_rk312x())
1116 rockchip_iovmm_deactivate(pservice->dev);
1119 if (irq_reg != -1) {
1120 reg->reg[irq_reg] = pservice->irq_status;
1123 atomic_sub(1, ®->session->task_running);
1124 atomic_sub(1, &pservice->total_running);
1125 wake_up(®->session->wait);
1128 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1130 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1131 if (curr == reg->freq) {
1134 atomic_set(&pservice->freq_status, reg->freq);
1135 switch (reg->freq) {
1136 case VPU_FREQ_200M : {
1137 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1138 //printk("default: 200M\n");
1140 case VPU_FREQ_266M : {
1141 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1142 //printk("default: 266M\n");
1144 case VPU_FREQ_300M : {
1145 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1146 //printk("default: 300M\n");
1148 case VPU_FREQ_400M : {
1149 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1150 //printk("default: 400M\n");
1152 case VPU_FREQ_500M : {
1153 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1155 case VPU_FREQ_600M : {
1156 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1159 if (soc_is_rk2928g()) {
1160 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1162 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1164 //printk("default: 300M\n");
1170 static void simulate_start(struct vpu_service_info *pservice);
1172 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
1175 u32 *src = (u32 *)®->reg[0];
1176 atomic_add(1, &pservice->total_running);
1177 atomic_add(1, ®->session->task_running);
1178 if (pservice->auto_freq) {
1179 vpu_service_set_freq(pservice, reg);
1182 vcodec_enter_mode(pservice->dev_id);
1184 if (cpu_is_rk3036() || cpu_is_rk312x())
1185 rockchip_iovmm_activate(pservice->dev);
1187 switch (reg->type) {
1189 int enc_count = pservice->hw_info->enc_reg_num;
1190 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
1192 *pservice->reg_codec = reg;
1194 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1196 for (i = 0; i < VPU_REG_EN_ENC; i++)
1199 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1202 VEPU_CLEAR_CACHE(dst);
1206 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1207 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1209 #if VPU_SERVICE_SHOW_TIME
1210 do_gettimeofday(&enc_start);
1215 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1217 *pservice->reg_codec = reg;
1219 if (pservice->hw_info->hw_id != HEVC_ID) {
1220 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1222 VDPU_CLEAR_CACHE(dst);
1224 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1226 HEVC_CLEAR_CACHE(dst);
1231 if (pservice->hw_info->hw_id != HEVC_ID) {
1232 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1233 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1235 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1241 #if VPU_SERVICE_SHOW_TIME
1242 do_gettimeofday(&dec_start);
1247 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1248 pservice->reg_pproc = reg;
1250 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1252 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1257 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1259 #if VPU_SERVICE_SHOW_TIME
1260 do_gettimeofday(&pp_start);
1265 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
1266 *pservice->reg_codec = reg;
1267 pservice->reg_pproc = reg;
1269 VDPU_SOFT_RESET(dst);
1270 VDPU_CLEAR_CACHE(dst);
1272 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1275 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1278 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1279 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1280 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1282 #if VPU_SERVICE_SHOW_TIME
1283 do_gettimeofday(&dec_start);
1288 pr_err("error: unsupport session type %d", reg->type);
1289 atomic_sub(1, &pservice->total_running);
1290 atomic_sub(1, ®->session->task_running);
1298 if (pservice->hw_info->hw_id == HEVC_ID) {
1299 simulate_start(pservice);
1304 static void try_set_reg(struct vpu_service_info *pservice)
1306 // first get reg from reg list
1307 if (!list_empty(pservice->waiting)) {
1309 vpu_reg *reg = list_entry(pservice->waiting->next, vpu_reg, status_link);
1311 vpu_service_power_on(pservice);
1313 switch (reg->type) {
1315 if ((NULL == *pservice->reg_codec) && (NULL == pservice->reg_pproc))
1319 if (NULL == *pservice->reg_codec)
1321 if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
1326 if (NULL == *pservice->reg_codec) {
1327 if (NULL == pservice->reg_pproc)
1330 if ((VPU_DEC == (*pservice->reg_codec)->type) && (NULL == pservice->reg_pproc))
1332 // can not charge frequency when vpu is working
1333 if (pservice->auto_freq) {
1339 if ((NULL == *pservice->reg_codec) && (NULL == pservice->reg_pproc))
1343 printk("undefined reg type %d\n", reg->type);
1347 reg_from_wait_to_run(pservice, reg);
1348 reg_copy_to_hw(pservice, reg);
1353 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
1356 switch (reg->type) {
1358 if (copy_to_user(dst, ®->reg[0], pservice->hw_info->enc_io_size))
1363 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1364 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1369 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1374 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1380 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
1384 reg_deinit(pservice, reg);
1388 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1390 struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
1391 vpu_session *session = (vpu_session *)filp->private_data;
1392 if (NULL == session) {
1397 case VPU_IOC_SET_CLIENT_TYPE : {
1398 session->type = (VPU_CLIENT_TYPE)arg;
1401 case VPU_IOC_GET_HW_FUSE_STATUS : {
1403 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1404 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1407 if (VPU_ENC != session->type) {
1408 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
1409 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1413 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
1414 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
1422 case VPU_IOC_SET_REG : {
1425 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1426 pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1429 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
1433 mutex_lock(pservice->lock);
1434 try_set_reg(pservice);
1435 mutex_unlock(pservice->lock);
1440 case VPU_IOC_GET_REG : {
1443 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1444 pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1447 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1448 if (!list_empty(&session->done)) {
1450 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1454 if (unlikely(ret < 0)) {
1455 pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
1456 } else if (0 == ret) {
1457 pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1462 int task_running = atomic_read(&session->task_running);
1463 mutex_lock(pservice->lock);
1464 vpu_service_dump(pservice);
1466 atomic_set(&session->task_running, 0);
1467 atomic_sub(task_running, &pservice->total_running);
1468 printk("%d task is running but not return, reset hardware...", task_running);
1469 vpu_reset(pservice);
1472 vpu_service_session_clear(pservice, session);
1473 mutex_unlock(pservice->lock);
1477 mutex_lock(pservice->lock);
1478 reg = list_entry(session->done.next, vpu_reg, session_link);
1479 return_reg(pservice, reg, (u32 __user *)req.req);
1480 mutex_unlock(pservice->lock);
1483 case VPU_IOC_PROBE_IOMMU_STATUS: {
1484 int iommu_enable = 0;
1486 #if defined(CONFIG_VCODEC_MMU)
1487 iommu_enable = pservice->mmu_dev ? 1 : 0;
1490 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1491 pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1497 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1505 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
1507 int ret = -EINVAL, i = 0;
1508 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1512 /// temporary, hevc driver test.
1513 if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
1514 p->hw_info = &vpu_hw_set[2];
1518 enc_id = (enc_id >> 16) & 0xFFFF;
1519 pr_info("checking hw id %x\n", enc_id);
1521 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1522 if (enc_id == vpu_hw_set[i].hw_id) {
1523 p->hw_info = &vpu_hw_set[i];
1528 iounmap((void *)tmp);
1532 static int vpu_service_open(struct inode *inode, struct file *filp)
1534 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1535 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1536 if (NULL == session) {
1537 pr_err("error: unable to allocate memory for vpu_session.");
1541 session->type = VPU_TYPE_BUTT;
1542 session->pid = current->pid;
1543 INIT_LIST_HEAD(&session->waiting);
1544 INIT_LIST_HEAD(&session->running);
1545 INIT_LIST_HEAD(&session->done);
1546 INIT_LIST_HEAD(&session->list_session);
1547 init_waitqueue_head(&session->wait);
1548 atomic_set(&session->task_running, 0);
1549 mutex_lock(pservice->lock);
1550 list_add_tail(&session->list_session, &pservice->session);
1551 filp->private_data = (void *)session;
1552 mutex_unlock(pservice->lock);
1554 pr_debug("dev opened\n");
1555 return nonseekable_open(inode, filp);
1558 static int vpu_service_release(struct inode *inode, struct file *filp)
1560 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
1562 vpu_session *session = (vpu_session *)filp->private_data;
1563 if (NULL == session)
1566 task_running = atomic_read(&session->task_running);
1568 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1571 wake_up(&session->wait);
1573 mutex_lock(pservice->lock);
1574 /* remove this filp from the asynchronusly notified filp's */
1575 list_del_init(&session->list_session);
1576 vpu_service_session_clear(pservice, session);
1578 filp->private_data = NULL;
1579 mutex_unlock(pservice->lock);
1581 pr_debug("dev closed\n");
1585 static const struct file_operations vpu_service_fops = {
1586 .unlocked_ioctl = vpu_service_ioctl,
1587 .open = vpu_service_open,
1588 .release = vpu_service_release,
1589 //.fasync = vpu_service_fasync,
1592 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1593 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1594 static irqreturn_t vepu_irq(int irq, void *dev_id);
1595 static irqreturn_t vepu_isr(int irq, void *dev_id);
1596 static void get_hw_info(struct vpu_service_info *pservice);
1599 static void simulate_work(struct work_struct *work_s)
1601 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
1602 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
1603 vpu_device *dev = &pservice->dec_dev;
1605 if (!list_empty(&pservice->running)) {
1606 atomic_add(1, &dev->irq_count_codec);
1607 vdpu_isr(0, (void*)pservice);
1609 //simulate_start(pservice);
1610 pr_err("empty running queue\n");
1614 static void simulate_init(struct vpu_service_info *pservice)
1616 INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
1619 static void simulate_start(struct vpu_service_info *pservice)
1621 cancel_delayed_work_sync(&pservice->power_off_work);
1622 queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
1626 #ifdef CONFIG_VCODEC_MMU
1627 static struct device *rockchip_get_sysmmu_device_by_compatible(const char *compt)
1629 struct device_node *dn = NULL;
1630 struct platform_device *pd = NULL;
1631 struct device *ret = NULL ;
1633 dn = of_find_compatible_node(NULL,NULL,compt);
1635 printk("can't find device node %s \r\n",compt);
1639 pd = of_find_device_by_node(dn);
1641 printk("can't find platform device in device node %s\n",compt);
1649 #ifdef CONFIG_IOMMU_API
1650 static inline void platform_set_sysmmu(struct device *iommu,
1653 dev->archdata.iommu = iommu;
1656 static inline void platform_set_sysmmu(struct device *iommu,
1662 int vcodec_sysmmu_fault_handler(struct device *dev,
1663 enum rk_iommu_inttype itype,
1664 unsigned long pgtable_base,
1665 unsigned long fault_addr, unsigned int status)
1667 struct platform_device *pdev;
1668 struct vpu_service_info *pservice;
1670 pr_info("%s in\n", __func__);
1672 pdev = container_of(dev, struct platform_device, dev);
1674 pservice = platform_get_drvdata(pdev);
1676 if (pservice->reg_codec) {
1677 struct vcodec_mem_region *mem, *n;
1679 pr_info("vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1680 list_for_each_entry_safe(mem, n,
1681 &(*pservice->reg_codec)->mem_region_list,
1683 pr_info("vcodec, mem region [%02d] 0x%08x %ld\n",
1684 i, (u32)mem->iova, mem->len);
1688 pr_alert("vcodec, page fault occur, reset hw\n");
1689 (*pservice->reg_codec)->reg[101] = 1;
1690 vpu_reset(pservice);
1697 #if HEVC_TEST_ENABLE
1698 static int hevc_test_case0(vpu_service_info *pservice);
1700 #if defined(CONFIG_ION_ROCKCHIP)
1701 extern struct ion_client *rockchip_ion_client_create(const char * name);
1703 static int vcodec_probe(struct platform_device *pdev)
1706 struct resource *res = NULL;
1707 struct device *dev = &pdev->dev;
1708 void __iomem *regs = NULL;
1709 struct device_node *np = pdev->dev.of_node;
1710 struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
1711 char *prop = (char*)dev_name(dev);
1713 #if defined(CONFIG_VCODEC_MMU)
1715 char mmu_dev_dts_name[40];
1716 of_property_read_u32(np, "iommu_enabled", &iommu_en);
1719 pr_info("probe device %s\n", dev_name(dev));
1721 of_property_read_string(np, "name", (const char**)&prop);
1722 dev_set_name(dev, prop);
1724 if (strcmp(dev_name(dev), "hevc_service") == 0) {
1725 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
1726 g_combo.hevc_srv = pservice;
1727 } else if (strcmp(dev_name(dev), "vpu_service") == 0) {
1728 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
1729 g_combo.vpu_srv = pservice;
1731 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));
1735 mutex_init(&g_mode_mutex);
1736 vcodec_enter_mode_nolock(pservice->dev_id, &config);
1738 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
1739 if (cpu_is_rk3036() || cpu_is_rk312x()) {
1740 pservice->waiting = &g_combo.waiting;
1741 pservice->running = &g_combo.running;
1742 pservice->lock = &g_combo.run_lock;
1743 pservice->reg_codec = &g_combo.reg_codec;
1745 pservice->waiting = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1746 pservice->running = kzalloc(sizeof(struct list_head), GFP_KERNEL);
1747 pservice->lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
1748 pservice->reg_codec = kzalloc(sizeof(vpu_reg*), GFP_KERNEL);
1749 INIT_LIST_HEAD(pservice->waiting);
1750 INIT_LIST_HEAD(pservice->running);
1751 mutex_init(pservice->lock);
1753 INIT_LIST_HEAD(&pservice->done);
1754 INIT_LIST_HEAD(&pservice->session);
1756 pservice->reg_pproc = NULL;
1757 atomic_set(&pservice->total_running, 0);
1758 pservice->enabled = false;
1759 #if defined(CONFIG_VCODEC_MMU)
1760 pservice->mmu_dev = NULL;
1762 pservice->dev = dev;
1764 if (0 > vpu_get_clk(pservice))
1767 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
1769 vpu_service_power_on(pservice);
1773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1775 res->flags &= ~IORESOURCE_CACHEABLE;
1777 regs = devm_ioremap_resource(pservice->dev, res);
1779 ret = PTR_ERR(regs);
1784 u32 offset = res->start;
1785 if (cpu_is_rk3036()) {
1786 if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)
1789 ret = vpu_service_check_hw(pservice, offset);
1791 pr_err("error: hw info check faild\n");
1796 /// define regs address.
1797 pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
1798 pservice->dec_dev.iosize = pservice->hw_info->dec_io_size;
1800 pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
1802 pservice->reg_size = pservice->dec_dev.iosize;
1804 if (pservice->hw_info->hw_id != HEVC_ID && !cpu_is_rk3036()) {
1805 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
1806 pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;
1808 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
1810 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
1812 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1813 if (pservice->irq_enc < 0) {
1814 dev_err(pservice->dev, "cannot find IRQ encoder\n");
1819 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, IRQF_DISABLED, dev_name(pservice->dev), (void *)pservice);
1821 dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
1826 pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1827 if (pservice->irq_dec < 0) {
1828 dev_err(pservice->dev, "cannot find IRQ decoder\n");
1833 /* get the IRQ line */
1834 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
1836 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
1840 atomic_set(&pservice->dec_dev.irq_count_codec, 0);
1841 atomic_set(&pservice->dec_dev.irq_count_pp, 0);
1842 atomic_set(&pservice->enc_dev.irq_count_codec, 0);
1843 atomic_set(&pservice->enc_dev.irq_count_pp, 0);
1846 ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
1848 dev_err(dev, "alloc dev_t failed\n");
1852 cdev_init(&pservice->cdev, &vpu_service_fops);
1854 pservice->cdev.owner = THIS_MODULE;
1855 pservice->cdev.ops = &vpu_service_fops;
1857 ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
1860 dev_err(dev, "add dev_t failed\n");
1864 pservice->cls = class_create(THIS_MODULE, dev_name(dev));
1866 if (IS_ERR(pservice->cls)) {
1867 ret = PTR_ERR(pservice->cls);
1868 dev_err(dev, "class_create err:%d\n", ret);
1872 pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
1874 platform_set_drvdata(pdev, pservice);
1876 get_hw_info(pservice);
1879 #ifdef CONFIG_DEBUG_FS
1880 pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
1881 if (pservice->debugfs_dir == NULL)
1882 pr_err("create debugfs dir %s failed\n", dev_name(dev));
1884 pservice->debugfs_file_regs =
1885 debugfs_create_file("regs", 0664,
1886 pservice->debugfs_dir, pservice,
1887 &debug_vcodec_fops);
1890 #if defined(CONFIG_VCODEC_MMU)
1892 pservice->ion_client = rockchip_ion_client_create("vpu");
1893 if (IS_ERR(pservice->ion_client)) {
1894 dev_err(&pdev->dev, "failed to create ion client for vcodec");
1895 return PTR_ERR(pservice->ion_client);
1897 dev_info(&pdev->dev, "vcodec ion client create success!\n");
1900 if (pservice->hw_info->hw_id == HEVC_ID)
1901 sprintf(mmu_dev_dts_name, HEVC_IOMMU_COMPATIBLE_NAME);
1903 sprintf(mmu_dev_dts_name, VPU_IOMMU_COMPATIBLE_NAME);
1905 pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);
1907 if (pservice->mmu_dev) {
1908 platform_set_sysmmu(pservice->mmu_dev, pservice->dev);
1909 /*rockchip_iovmm_activate(pservice->dev);*/
1912 rockchip_iovmm_set_fault_handler(pservice->dev, vcodec_sysmmu_fault_handler);
1915 vcodec_exit_mode_nolock(pservice->dev_id, config);
1916 vpu_service_power_off(pservice);
1918 pr_info("init success\n");
1921 if (pservice->hw_info->hw_id == HEVC_ID)
1922 simulate_init(pservice);
1925 #if HEVC_TEST_ENABLE
1926 hevc_test_case0(pservice);
1932 pr_info("init failed\n");
1933 vcodec_exit_mode_nolock(pservice->dev_id, config);
1934 vpu_service_power_off(pservice);
1935 vpu_put_clk(pservice);
1936 wake_lock_destroy(&pservice->wake_lock);
1939 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1940 if (pservice->irq_enc > 0)
1941 free_irq(pservice->irq_enc, (void *)pservice);
1942 if (pservice->irq_dec > 0)
1943 free_irq(pservice->irq_dec, (void *)pservice);
1945 if (pservice->child_dev) {
1946 device_destroy(pservice->cls, pservice->dev_t);
1947 cdev_del(&pservice->cdev);
1948 unregister_chrdev_region(pservice->dev_t, 1);
1952 class_destroy(pservice->cls);
1957 static int vcodec_remove(struct platform_device *pdev)
1959 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
1960 struct resource *res;
1962 device_destroy(pservice->cls, pservice->dev_t);
1963 class_destroy(pservice->cls);
1964 cdev_del(&pservice->cdev);
1965 unregister_chrdev_region(pservice->dev_t, 1);
1967 free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
1968 free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
1969 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1970 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
1971 vpu_put_clk(pservice);
1972 wake_lock_destroy(&pservice->wake_lock);
1974 #ifdef CONFIG_DEBUG_FS
1975 debugfs_remove(pservice->debugfs_file_regs);
1976 debugfs_remove(pservice->debugfs_dir);
1982 #if defined(CONFIG_OF)
1983 static const struct of_device_id vcodec_service_dt_ids[] = {
1984 {.compatible = "vpu_service",},
1985 {.compatible = "rockchip,hevc_service",},
1990 static struct platform_driver vcodec_driver = {
1991 .probe = vcodec_probe,
1992 .remove = vcodec_remove,
1995 .owner = THIS_MODULE,
1996 #if defined(CONFIG_OF)
1997 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2002 static void get_hw_info(struct vpu_service_info *pservice)
2004 VPUHwDecConfig_t *dec = &pservice->dec_config;
2005 VPUHwEncConfig_t *enc = &pservice->enc_config;
2007 if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {
2008 u32 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
2009 u32 asicID = pservice->dec_dev.hwregs[0];
2011 dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;
2012 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2013 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2014 dec->jpegSupport = JPEG_PROGRESSIVE;
2015 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2016 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2017 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2018 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2019 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2020 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2022 if (soc_is_rk3190() || soc_is_rk3288())
2023 dec->maxDecPicWidth = 4096;
2024 else if (cpu_is_rk3036() || cpu_is_rk312x())
2025 dec->maxDecPicWidth = 1920;
2027 dec->maxDecPicWidth = configReg & 0x07FFU;
2029 /* 2nd Config register */
2030 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
2031 if (dec->refBufSupport) {
2032 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2033 dec->refBufSupport |= 2;
2034 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2035 dec->refBufSupport |= 4;
2037 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2038 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2039 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2040 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2042 /* JPEG xtensions */
2043 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2044 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2046 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2048 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2049 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2051 dec->rvSupport = RV_NOT_SUPPORTED;
2052 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2054 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2055 dec->refBufSupport |= 8; /* enable HW support for offset */
2057 /// invalidate fuse register value in rk319x vpu and following.
2058 if (!soc_is_rk3190() && !soc_is_rk3288() && !cpu_is_rk3036() && !cpu_is_rk312x()) {
2059 VPUHwFuseStatus_t hwFuseSts;
2060 /* Decoder fuse configuration */
2061 u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2063 hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
2064 hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
2065 hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
2066 hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
2067 hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
2068 hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
2069 hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
2070 hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
2071 hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
2072 hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
2073 hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
2074 hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
2075 hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
2076 hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
2078 /* check max. decoder output width */
2080 if (fuseReg & 0x8000U)
2081 hwFuseSts.maxDecPicWidthFuse = 1920;
2082 else if (fuseReg & 0x4000U)
2083 hwFuseSts.maxDecPicWidthFuse = 1280;
2084 else if (fuseReg & 0x2000U)
2085 hwFuseSts.maxDecPicWidthFuse = 720;
2086 else if (fuseReg & 0x1000U)
2087 hwFuseSts.maxDecPicWidthFuse = 352;
2088 else /* remove warning */
2089 hwFuseSts.maxDecPicWidthFuse = 352;
2091 hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
2093 /* Pp configuration */
2094 configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
2096 if ((configReg >> DWL_PP_E) & 0x01U) {
2098 dec->maxPpOutPicWidth = configReg & 0x07FFU;
2099 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
2100 dec->ppConfig = configReg;
2103 dec->maxPpOutPicWidth = 0;
2107 /* check the HW versio */
2108 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
2109 /* Pp configuration */
2110 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
2111 if ((configReg >> DWL_PP_E) & 0x01U) {
2112 /* Pp fuse configuration */
2113 u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
2115 if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
2116 hwFuseSts.ppSupportFuse = 1;
2117 /* check max. pp output width */
2118 if (fuseRegPp & 0x8000U)
2119 hwFuseSts.maxPpOutPicWidthFuse = 1920;
2120 else if (fuseRegPp & 0x4000U)
2121 hwFuseSts.maxPpOutPicWidthFuse = 1280;
2122 else if (fuseRegPp & 0x2000U)
2123 hwFuseSts.maxPpOutPicWidthFuse = 720;
2124 else if (fuseRegPp & 0x1000U)
2125 hwFuseSts.maxPpOutPicWidthFuse = 352;
2127 hwFuseSts.maxPpOutPicWidthFuse = 352;
2128 hwFuseSts.ppConfigFuse = fuseRegPp;
2130 hwFuseSts.ppSupportFuse = 0;
2131 hwFuseSts.maxPpOutPicWidthFuse = 0;
2132 hwFuseSts.ppConfigFuse = 0;
2135 hwFuseSts.ppSupportFuse = 0;
2136 hwFuseSts.maxPpOutPicWidthFuse = 0;
2137 hwFuseSts.ppConfigFuse = 0;
2140 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
2141 dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
2142 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
2143 dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
2144 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
2145 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
2146 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
2147 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
2148 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
2149 dec->jpegSupport = JPEG_BASELINE;
2150 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
2151 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
2152 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
2153 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
2154 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
2155 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
2157 /* check the pp config vs fuse status */
2158 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
2159 u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
2160 u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
2161 u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
2162 u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
2164 if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
2165 if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
2167 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
2168 if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
2169 if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;
2170 if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;
2171 if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;
2175 if (!cpu_is_rk3036()) {
2176 configReg = pservice->enc_dev.hwregs[63];
2177 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2178 enc->h264Enabled = (configReg >> 27) & 1;
2179 enc->mpeg4Enabled = (configReg >> 26) & 1;
2180 enc->jpegEnabled = (configReg >> 25) & 1;
2181 enc->vsEnabled = (configReg >> 24) & 1;
2182 enc->rgbEnabled = (configReg >> 28) & 1;
2183 /*enc->busType = (configReg >> 20) & 15;
2184 enc->synthesisLanguage = (configReg >> 16) & 15;
2185 enc->busWidth = (configReg >> 12) & 15;*/
2186 enc->reg_size = pservice->reg_size;
2187 enc->reserv[0] = enc->reserv[1] = 0;
2190 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2191 if (pservice->auto_freq) {
2192 pr_info("vpu_service set to auto frequency mode\n");
2193 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2196 pservice->bug_dec_addr = cpu_is_rk30xx();
2198 if (cpu_is_rk3036() || cpu_is_rk312x())
2199 dec->maxDecPicWidth = 1920;
2201 dec->maxDecPicWidth = 4096;
2202 /* disable frequency switch in hevc.*/
2203 pservice->auto_freq = false;
2207 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2209 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2210 vpu_device *dev = &pservice->dec_dev;
2214 vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);
2216 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2218 pr_debug("dec_irq\n");
2220 if (irq_status & DEC_INTERRUPT_BIT) {
2221 pr_debug("dec_isr dec %x\n", irq_status);
2222 if ((irq_status & 0x40001) == 0x40001)
2225 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2226 } while ((irq_status & 0x40001) == 0x40001);
2230 if (pservice->hw_info->hw_id != HEVC_ID)
2231 writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
2233 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2234 atomic_add(1, &dev->irq_count_codec);
2237 if (pservice->hw_info->hw_id != HEVC_ID) {
2238 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2239 if (irq_status & PP_INTERRUPT_BIT) {
2240 pr_debug("vdpu_isr pp %x\n", irq_status);
2242 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2243 atomic_add(1, &dev->irq_count_pp);
2247 pservice->irq_status = raw_status;
2249 vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2251 return IRQ_WAKE_THREAD;
2254 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2256 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2257 vpu_device *dev = &pservice->dec_dev;
2259 mutex_lock(pservice->lock);
2260 if (atomic_read(&dev->irq_count_codec)) {
2261 #if VPU_SERVICE_SHOW_TIME
2262 do_gettimeofday(&dec_end);
2263 pr_info("dec task: %ld ms\n",
2264 (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
2265 (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2267 atomic_sub(1, &dev->irq_count_codec);
2268 if (NULL == pservice->reg_codec) {
2269 pr_err("error: dec isr with no task waiting\n");
2271 reg_from_run_to_done(pservice, *pservice->reg_codec);
2275 if (atomic_read(&dev->irq_count_pp)) {
2277 #if VPU_SERVICE_SHOW_TIME
2278 do_gettimeofday(&pp_end);
2279 printk("pp task: %ld ms\n",
2280 (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
2281 (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2284 atomic_sub(1, &dev->irq_count_pp);
2285 if (NULL == pservice->reg_pproc) {
2286 pr_err("error: pp isr with no task waiting\n");
2288 reg_from_run_to_done(pservice, pservice->reg_pproc);
2291 try_set_reg(pservice);
2292 mutex_unlock(pservice->lock);
2296 static irqreturn_t vepu_irq(int irq, void *dev_id)
2298 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2299 vpu_device *dev = &pservice->enc_dev;
2302 vcodec_enter_mode_nolock(pservice->dev_id, &pservice->reserved_mode);
2303 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2305 pr_debug("vepu_irq irq status %x\n", irq_status);
2307 #if VPU_SERVICE_SHOW_TIME
2308 do_gettimeofday(&enc_end);
2309 pr_info("enc task: %ld ms\n",
2310 (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
2311 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2313 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2315 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2316 atomic_add(1, &dev->irq_count_codec);
2319 pservice->irq_status = irq_status;
2321 vcodec_exit_mode_nolock(pservice->dev_id, pservice->reserved_mode);
2323 return IRQ_WAKE_THREAD;
2326 static irqreturn_t vepu_isr(int irq, void *dev_id)
2328 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
2329 vpu_device *dev = &pservice->enc_dev;
2331 mutex_lock(pservice->lock);
2332 if (atomic_read(&dev->irq_count_codec)) {
2333 atomic_sub(1, &dev->irq_count_codec);
2334 if (NULL == pservice->reg_codec) {
2335 pr_err("error: enc isr with no task waiting\n");
2337 reg_from_run_to_done(pservice, *pservice->reg_codec);
2340 try_set_reg(pservice);
2341 mutex_unlock(pservice->lock);
2345 static int __init vcodec_service_init(void)
2349 g_combo.hevc_srv = NULL;
2350 g_combo.vpu_srv = NULL;
2351 INIT_LIST_HEAD(&g_combo.waiting);
2352 INIT_LIST_HEAD(&g_combo.running);
2353 mutex_init(&g_combo.run_lock);
2354 g_combo.reg_codec = NULL;
2355 g_combo.current_hw_mode = VCODEC_DEVICE_ID_VPU;
2357 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2358 pr_err("Platform device register failed (%d).\n", ret);
2362 #ifdef CONFIG_DEBUG_FS
2363 vcodec_debugfs_init();
2369 static void __exit vcodec_service_exit(void)
2371 #ifdef CONFIG_DEBUG_FS
2372 vcodec_debugfs_exit();
2375 platform_driver_unregister(&vcodec_driver);
2378 module_init(vcodec_service_init);
2379 module_exit(vcodec_service_exit);
2381 #ifdef CONFIG_DEBUG_FS
2382 #include <linux/seq_file.h>
2384 static int vcodec_debugfs_init()
2386 parent = debugfs_create_dir("vcodec", NULL);
2393 static void vcodec_debugfs_exit()
2395 debugfs_remove(parent);
2398 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2400 return debugfs_create_dir(dirname, parent);
2403 static int debug_vcodec_show(struct seq_file *s, void *unused)
2405 struct vpu_service_info *pservice = s->private;
2407 vpu_reg *reg, *reg_tmp;
2408 vpu_session *session, *session_tmp;
2410 mutex_lock(pservice->lock);
2411 vpu_service_power_on(pservice);
2412 if (pservice->hw_info->hw_id != HEVC_ID) {
2413 seq_printf(s, "\nENC Registers:\n");
2414 n = pservice->enc_dev.iosize >> 2;
2415 for (i = 0; i < n; i++) {
2416 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
2419 seq_printf(s, "\nDEC Registers:\n");
2420 n = pservice->dec_dev.iosize >> 2;
2421 for (i = 0; i < n; i++)
2422 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2424 seq_printf(s, "\nvpu service status:\n");
2425 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2426 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2427 /*seq_printf(s, "waiting reg set %d\n");*/
2428 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2429 seq_printf(s, "waiting register set\n");
2431 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2432 seq_printf(s, "running register set\n");
2434 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2435 seq_printf(s, "done register set\n");
2438 mutex_unlock(pservice->lock);
2443 static int debug_vcodec_open(struct inode *inode, struct file *file)
2445 return single_open(file, debug_vcodec_show, inode->i_private);
2450 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2451 #include "hevc_test_inc/pps_00.h"
2452 #include "hevc_test_inc/register_00.h"
2453 #include "hevc_test_inc/rps_00.h"
2454 #include "hevc_test_inc/scaling_list_00.h"
2455 #include "hevc_test_inc/stream_00.h"
2457 #include "hevc_test_inc/pps_01.h"
2458 #include "hevc_test_inc/register_01.h"
2459 #include "hevc_test_inc/rps_01.h"
2460 #include "hevc_test_inc/scaling_list_01.h"
2461 #include "hevc_test_inc/stream_01.h"
2463 #include "hevc_test_inc/cabac.h"
2465 extern struct ion_client *rockchip_ion_client_create(const char * name);
2467 static struct ion_client *ion_client = NULL;
2468 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2470 int size = (len+15) & (~15);
2471 struct ion_handle *handle;
2472 u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2474 if (ion_client == NULL)
2475 ion_client = rockchip_ion_client_create("vcodec");
2477 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2479 ptr = ion_map_kernel(ion_client, handle);
2481 ion_phys(ion_client, handle, phy, &size);
2483 memcpy(ptr, tbl, len);
2488 u8* get_align_ptr_no_copy(int len, u32 *phy)
2490 int size = (len+15) & (~15);
2491 struct ion_handle *handle;
2494 if (ion_client == NULL)
2495 ion_client = rockchip_ion_client_create("vcodec");
2497 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2499 ptr = ion_map_kernel(ion_client, handle);
2501 ion_phys(ion_client, handle, phy, &size);
2507 static int hevc_test_case0(vpu_service_info *pservice)
2509 vpu_session session;
2511 unsigned long size = 272;//sizeof(register_00); // registers array length
2515 u8 *pps_tbl[TEST_CNT];
2516 u8 *register_tbl[TEST_CNT];
2517 u8 *rps_tbl[TEST_CNT];
2518 u8 *scaling_list_tbl[TEST_CNT];
2519 u8 *stream_tbl[TEST_CNT];
2535 volatile u8 *stream_buf;
2536 volatile u8 *pps_buf;
2537 volatile u8 *rps_buf;
2538 volatile u8 *scl_buf;
2539 volatile u8 *yuv_buf;
2540 volatile u8 *cabac_buf;
2541 volatile u8 *ref_buf;
2547 pps_tbl[0] = pps_00;
2548 pps_tbl[1] = pps_01;
2550 register_tbl[0] = register_00;
2551 register_tbl[1] = register_01;
2553 rps_tbl[0] = rps_00;
2554 rps_tbl[1] = rps_01;
2556 scaling_list_tbl[0] = scaling_list_00;
2557 scaling_list_tbl[1] = scaling_list_01;
2559 stream_tbl[0] = stream_00;
2560 stream_tbl[1] = stream_01;
2562 stream_size[0] = sizeof(stream_00);
2563 stream_size[1] = sizeof(stream_01);
2565 pps_size[0] = sizeof(pps_00);
2566 pps_size[1] = sizeof(pps_01);
2568 rps_size[0] = sizeof(rps_00);
2569 rps_size[1] = sizeof(rps_01);
2571 scl_size[0] = sizeof(scaling_list_00);
2572 scl_size[1] = sizeof(scaling_list_01);
2574 cabac_size[0] = sizeof(Cabac_table);
2575 cabac_size[1] = sizeof(Cabac_table);
2577 /* create session */
2578 session.pid = current->pid;
2579 session.type = VPU_DEC;
2580 INIT_LIST_HEAD(&session.waiting);
2581 INIT_LIST_HEAD(&session.running);
2582 INIT_LIST_HEAD(&session.done);
2583 INIT_LIST_HEAD(&session.list_session);
2584 init_waitqueue_head(&session.wait);
2585 atomic_set(&session.task_running, 0);
2586 list_add_tail(&session.list_session, &pservice->session);
2588 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2589 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2591 while (testidx < TEST_CNT) {
2592 /* create registers */
2593 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2595 pr_err("error: kmalloc fail in reg_init\n");
2599 if (size > pservice->reg_size) {
2600 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2601 size = pservice->reg_size;
2603 reg->session = &session;
2604 reg->type = session.type;
2606 reg->freq = VPU_FREQ_DEFAULT;
2607 reg->reg = (unsigned long *)®[1];
2608 INIT_LIST_HEAD(®->session_link);
2609 INIT_LIST_HEAD(®->status_link);
2611 /* TODO: stuff registers */
2612 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2614 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2615 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2616 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2617 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2618 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2622 /* TODO: replace reigster address */
2623 for (i=0; i<64; i++) {
2627 scaling_offset = (u32)pps[i*80+74];
2628 scaling_offset += (u32)pps[i*80+75] << 8;
2629 scaling_offset += (u32)pps[i*80+76] << 16;
2630 scaling_offset += (u32)pps[i*80+77] << 24;
2632 tmp = phy_scl + scaling_offset;
2634 pps[i*80+74] = tmp & 0xff;
2635 pps[i*80+75] = (tmp >> 8) & 0xff;
2636 pps[i*80+76] = (tmp >> 16) & 0xff;
2637 pps[i*80+77] = (tmp >> 24) & 0xff;
2640 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2641 __func__, __LINE__, phy_str, phy_pps, phy_rps);
2644 reg->reg[4] = phy_str;
2645 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2646 reg->reg[6] = phy_cabac;
2647 reg->reg[7] = testidx?phy_ref:phy_yuv;
2648 reg->reg[42] = phy_pps;
2649 reg->reg[43] = phy_rps;
2650 for (i = 10; i <= 24; i++)
2651 reg->reg[i] = phy_yuv;
2653 mutex_lock(pservice->lock);
2654 list_add_tail(®->status_link, pservice->waiting);
2655 list_add_tail(®->session_link, &session.waiting);
2656 mutex_unlock(pservice->lock);
2658 printk("%s %d %p\n", __func__, __LINE__, pservice);
2660 /* stuff hardware */
2661 try_set_reg(pservice);
2663 /* wait for result */
2664 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2665 if (!list_empty(&session.done)) {
2667 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2670 if (unlikely(ret < 0)) {
2671 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
2672 } else if (0 == ret) {
2673 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2678 int task_running = atomic_read(&session.task_running);
2680 mutex_lock(pservice->lock);
2681 vpu_service_dump(pservice);
2683 atomic_set(&session.task_running, 0);
2684 atomic_sub(task_running, &pservice->total_running);
2685 printk("%d task is running but not return, reset hardware...", task_running);
2686 vpu_reset(pservice);
2689 vpu_service_session_clear(pservice, &session);
2690 mutex_unlock(pservice->lock);
2692 printk("\nDEC Registers:\n");
2693 n = pservice->dec_dev.iosize >> 2;
2695 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
2697 pr_err("test index %d failed\n", testidx);
2700 pr_info("test index %d success\n", testidx);
2702 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2704 for (i=0; i<68; i++) {
2706 printk("%02d: ", i);
2707 printk("%08x ", reg->reg[i]);
2715 reg_deinit(pservice, reg);