arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <linux/uaccess.h>\r
  41 #include <linux/rockchip/grf.h>\r
  42 \r
  43 #if defined(CONFIG_ION_ROCKCHIP)\r
  44 #include <linux/rockchip_ion.h>\r
  45 #endif\r
  46 \r
  47 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
  48 #define CONFIG_VCODEC_MMU\r
  49 #endif\r
  50 \r
  51 #ifdef CONFIG_VCODEC_MMU\r
  52 #include <linux/rockchip/iovmm.h>\r
  53 #include <linux/rockchip/sysmmu.h>\r
  54 #include <linux/dma-buf.h>\r
  55 #endif\r
  56 \r
  57 #ifdef CONFIG_DEBUG_FS\r
  58 #include <linux/debugfs.h>\r
  59 #endif\r
  60 \r
  61 #if defined(CONFIG_ARCH_RK319X)\r
  62 #include <mach/grf.h>\r
  63 #endif\r
  64 \r
  65 #include "vcodec_service.h"\r
  66 \r
  67 #define HEVC_TEST_ENABLE        0\r
  68 #define HEVC_SIM_ENABLE         0\r
  69 #define VCODEC_CLOCK_ENABLE     1\r
  70 \r
  71 typedef enum {\r
  72         VPU_DEC_ID_9190         = 0x6731,\r
  73         VPU_ID_8270             = 0x8270,\r
  74         VPU_ID_4831             = 0x4831,\r
  75         HEVC_ID                 = 0x6867,\r
  76 } VPU_HW_ID;\r
  77 \r
  78 typedef enum {\r
  79         VPU_DEC_TYPE_9190       = 0,\r
  80         VPU_ENC_TYPE_8270       = 0x100,\r
  81         VPU_ENC_TYPE_4831       ,\r
  82 } VPU_HW_TYPE_E;\r
  83 \r
  84 typedef enum VPU_FREQ {\r
  85         VPU_FREQ_200M,\r
  86         VPU_FREQ_266M,\r
  87         VPU_FREQ_300M,\r
  88         VPU_FREQ_400M,\r
  89         VPU_FREQ_500M,\r
  90         VPU_FREQ_600M,\r
  91         VPU_FREQ_DEFAULT,\r
  92         VPU_FREQ_BUT,\r
  93 } VPU_FREQ;\r
  94 \r
  95 typedef struct {\r
  96         VPU_HW_ID               hw_id;\r
  97         unsigned long           hw_addr;\r
  98         unsigned long           enc_offset;\r
  99         unsigned long           enc_reg_num;\r
 100         unsigned long           enc_io_size;\r
 101         unsigned long           dec_offset;\r
 102         unsigned long           dec_reg_num;\r
 103         unsigned long           dec_io_size;\r
 104 } VPU_HW_INFO_E;\r
 105 \r
 106 #define VPU_SERVICE_SHOW_TIME                   0\r
 107 \r
 108 #if VPU_SERVICE_SHOW_TIME\r
 109 static struct timeval enc_start, enc_end;\r
 110 static struct timeval dec_start, dec_end;\r
 111 static struct timeval pp_start,  pp_end;\r
 112 #endif\r
 113 \r
 114 #define MHZ                                     (1000*1000)\r
 115 \r
 116 #define REG_NUM_9190_DEC                        (60)\r
 117 #define REG_NUM_9190_PP                         (41)\r
 118 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 119 \r
 120 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 121 \r
 122 #define REG_NUM_ENC_8270                        (96)\r
 123 #define REG_SIZE_ENC_8270                       (0x200)\r
 124 #define REG_NUM_ENC_4831                        (164)\r
 125 #define REG_SIZE_ENC_4831                       (0x400)\r
 126 \r
 127 #define REG_NUM_HEVC_DEC                        (68)\r
 128 \r
 129 #define SIZE_REG(reg)                           ((reg)*4)\r
 130 \r
 131 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 132         [0] = {\r
 133                 .hw_id          = VPU_ID_8270,\r
 134                 .hw_addr        = 0,\r
 135                 .enc_offset     = 0x0,\r
 136                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 137                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 138                 .dec_offset     = REG_SIZE_ENC_8270,\r
 139                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 140                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 141         },\r
 142         [1] = {\r
 143                 .hw_id          = VPU_ID_4831,\r
 144                 .hw_addr        = 0,\r
 145                 .enc_offset     = 0x0,\r
 146                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 147                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 148                 .dec_offset     = REG_SIZE_ENC_4831,\r
 149                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 150                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 151         },\r
 152         [2] = {\r
 153                 .hw_id          = HEVC_ID,\r
 154                 .hw_addr        = 0,\r
 155                 .dec_offset     = 0x0,\r
 156                 .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 157                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 158         },\r
 159         [3] = {\r
 160                 .hw_id          = VPU_DEC_ID_9190,\r
 161                 .hw_addr        = 0,\r
 162                 .enc_offset     = 0x0,\r
 163                 .enc_reg_num    = 0,\r
 164                 .enc_io_size    = 0,\r
 165                 .dec_offset     = REG_SIZE_ENC_4831,\r
 166                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 167                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 168         },\r
 169         \r
 170 };\r
 171 \r
 172 \r
 173 #define DEC_INTERRUPT_REGISTER                  1\r
 174 #define PP_INTERRUPT_REGISTER                   60\r
 175 #define ENC_INTERRUPT_REGISTER                  1\r
 176 \r
 177 #define DEC_INTERRUPT_BIT                       0x100\r
 178 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 179 #define PP_INTERRUPT_BIT                        0x100\r
 180 #define ENC_INTERRUPT_BIT                       0x1\r
 181 \r
 182 #define HEVC_DEC_INT_RAW_BIT                    0x200\r
 183 #define HEVC_DEC_STR_ERROR_BIT                  0x4000\r
 184 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000\r
 185 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000\r
 186 \r
 187 #define VPU_REG_EN_ENC                          14\r
 188 #define VPU_REG_ENC_GATE                        2\r
 189 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 190 \r
 191 #define VPU_REG_EN_DEC                          1\r
 192 #define VPU_REG_DEC_GATE                        2\r
 193 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 194 #define VPU_REG_EN_PP                           0\r
 195 #define VPU_REG_PP_GATE                         1\r
 196 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 197 #define VPU_REG_EN_DEC_PP                       1\r
 198 #define VPU_REG_DEC_PP_GATE                     61\r
 199 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 200 \r
 201 #if defined(CONFIG_VCODEC_MMU)\r
 202 static u8 addr_tbl_vpu_h264dec[] = {\r
 203         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,\r
 204         25, 26, 27, 28, 29, 40, 41\r
 205 };\r
 206 \r
 207 static u8 addr_tbl_vpu_vp8dec[] = {\r
 208         10,12,13, 14, 18, 19, 27, 40\r
 209 };\r
 210 \r
 211 static u8 addr_tbl_vpu_vp6dec[] = {\r
 212         12, 13, 14, 18, 27, 40\r
 213 };\r
 214 \r
 215 static u8 addr_tbl_vpu_vc1dec[] = {\r
 216         12, 13, 14, 15, 16, 17, 27, 41\r
 217 };\r
 218 \r
 219 static u8 addr_tbl_vpu_jpegdec[] = {\r
 220         12, 40, 66, 67\r
 221 };\r
 222 \r
 223 static u8 addr_tbl_vpu_defaultdec[] = {\r
 224         12, 13, 14, 15, 16, 17, 40, 41\r
 225 };\r
 226 \r
 227 static u8 addr_tbl_vpu_enc[] = {\r
 228         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 229 };\r
 230 \r
 231 static u8 addr_tbl_hevc_dec[] = {\r
 232         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,\r
 233         21, 22, 23, 24, 42, 43\r
 234 };\r
 235 #endif\r
 236 \r
 237 enum VPU_DEC_FMT {\r
 238         VPU_DEC_FMT_H264,\r
 239         VPU_DEC_FMT_MPEG4,\r
 240         VPU_DEC_FMT_H263,\r
 241         VPU_DEC_FMT_JPEG,\r
 242         VPU_DEC_FMT_VC1,\r
 243         VPU_DEC_FMT_MPEG2,\r
 244         VPU_DEC_FMT_MPEG1,\r
 245         VPU_DEC_FMT_VP6,\r
 246         VPU_DEC_FMT_RV,\r
 247         VPU_DEC_FMT_VP7,\r
 248         VPU_DEC_FMT_VP8,\r
 249         VPU_DEC_FMT_AVS,\r
 250         VPU_DEC_FMT_SVC,\r
 251         VPU_DEC_FMT_VC2,\r
 252         VPU_DEC_FMT_MVC,\r
 253         VPU_DEC_FMT_THEORA,\r
 254         VPU_DEC_FMT_RES\r
 255 };\r
 256 \r
 257 /**\r
 258  * struct for process session which connect to vpu\r
 259  *\r
 260  * @author ChenHengming (2011-5-3)\r
 261  */\r
 262 typedef struct vpu_session {\r
 263         VPU_CLIENT_TYPE         type;\r
 264         /* a linked list of data so we can access them for debugging */\r
 265         struct list_head        list_session;\r
 266         /* a linked list of register data waiting for process */\r
 267         struct list_head        waiting;\r
 268         /* a linked list of register data in processing */\r
 269         struct list_head        running;\r
 270         /* a linked list of register data processed */\r
 271         struct list_head        done;\r
 272         wait_queue_head_t       wait;\r
 273         pid_t                   pid;\r
 274         atomic_t                task_running;\r
 275 } vpu_session;\r
 276 \r
 277 /**\r
 278  * struct for process register set\r
 279  *\r
 280  * @author ChenHengming (2011-5-4)\r
 281  */\r
 282 typedef struct vpu_reg {\r
 283         VPU_CLIENT_TYPE         type;\r
 284         VPU_FREQ                    freq;\r
 285         vpu_session             *session;\r
 286         struct list_head        session_link;           /* link to vpu service session */\r
 287         struct list_head        status_link;            /* link to register set list */\r
 288         unsigned long           size;\r
 289 #if defined(CONFIG_VCODEC_MMU)\r
 290         struct list_head        mem_region_list;\r
 291 #endif\r
 292         unsigned long           *reg;\r
 293 } vpu_reg;\r
 294 \r
 295 typedef struct vpu_device {\r
 296         atomic_t                irq_count_codec;\r
 297         atomic_t                irq_count_pp;\r
 298         unsigned long           iobaseaddr;\r
 299         unsigned int            iosize;\r
 300         volatile u32            *hwregs;\r
 301 } vpu_device;\r
 302 \r
 303 enum vcodec_device_id {\r
 304         VCODEC_DEVICE_ID_VPU,\r
 305         VCODEC_DEVICE_ID_HEVC\r
 306 };\r
 307 \r
 308 struct vcodec_mem_region {\r
 309         struct list_head srv_lnk;\r
 310         struct list_head reg_lnk;\r
 311         struct list_head session_lnk;\r
 312         unsigned long iova;     /* virtual address for iommu */\r
 313         unsigned long len;\r
 314         struct ion_handle *hdl;\r
 315 };\r
 316 \r
 317 typedef struct vpu_service_info {\r
 318         struct wake_lock        wake_lock;\r
 319         struct delayed_work     power_off_work;\r
 320         struct mutex            lock;\r
 321         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 322         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 323         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 324         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 325         atomic_t                total_running;\r
 326         bool                    enabled;\r
 327         vpu_reg                 *reg_codec;\r
 328         vpu_reg                 *reg_pproc;\r
 329         vpu_reg                 *reg_resev;\r
 330         VPUHwDecConfig_t        dec_config;\r
 331         VPUHwEncConfig_t        enc_config;\r
 332         VPU_HW_INFO_E           *hw_info;\r
 333         unsigned long           reg_size;\r
 334         bool                    auto_freq;\r
 335         bool                    bug_dec_addr;\r
 336         atomic_t                freq_status;\r
 337 \r
 338         struct clk              *aclk_vcodec;\r
 339         struct clk              *hclk_vcodec;\r
 340         struct clk              *clk_core;\r
 341         struct clk              *clk_cabac;\r
 342         struct clk              *pd_video;\r
 343 \r
 344         int                     irq_dec;\r
 345         int                     irq_enc;\r
 346 \r
 347         vpu_device              enc_dev;\r
 348         vpu_device              dec_dev;\r
 349 \r
 350         struct device           *dev;\r
 351 \r
 352         struct cdev             cdev;\r
 353         dev_t                   dev_t;\r
 354         struct class            *cls;\r
 355         struct device           *child_dev;\r
 356 \r
 357         struct dentry           *debugfs_dir;\r
 358         struct dentry           *debugfs_file_regs;\r
 359 \r
 360         u32 irq_status;\r
 361 #if defined(CONFIG_VCODEC_MMU)  \r
 362         struct ion_client       *ion_client;\r
 363         struct list_head        mem_region_list;\r
 364         struct device           *mmu_dev;\r
 365 #endif\r
 366 \r
 367         enum vcodec_device_id   dev_id;\r
 368 \r
 369         struct delayed_work     simulate_work;\r
 370 } vpu_service_info;\r
 371 \r
 372 typedef struct vpu_request\r
 373 {\r
 374         unsigned long *req;\r
 375         unsigned long size;\r
 376 } vpu_request;\r
 377 \r
 378 /// global variable\r
 379 //static struct clk *pd_video;\r
 380 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 381 \r
 382 #ifdef CONFIG_DEBUG_FS\r
 383 static int vcodec_debugfs_init(void);\r
 384 static void vcodec_debugfs_exit(void);\r
 385 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 386 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 387 \r
 388 static const struct file_operations debug_vcodec_fops = {\r
 389         .open = debug_vcodec_open,\r
 390         .read = seq_read,\r
 391         .llseek = seq_lseek,\r
 392         .release = single_release,\r
 393 };\r
 394 #endif\r
 395 \r
 396 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 397 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 398 #define VPU_SIMULATE_DELAY              msecs_to_jiffies(15)\r
 399 \r
 400 static void vcodec_select_mode(enum vcodec_device_id id)\r
 401 {\r
 402         if (soc_is_rk3036()) {\r
 403 #define BIT_VCODEC_SEL          (1<<3)\r
 404                 if (id == VCODEC_DEVICE_ID_HEVC) {\r
 405                         writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 406                 } else {\r
 407                         writel_relaxed((readl_relaxed(RK_GRF_VIRT + RK3036_GRF_SOC_CON1) & (~BIT_VCODEC_SEL)) | (BIT_VCODEC_SEL << 16), RK_GRF_VIRT + RK3036_GRF_SOC_CON1);\r
 408                 }\r
 409         }\r
 410 }\r
 411 \r
 412 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 413 {\r
 414 #if VCODEC_CLOCK_ENABLE\r
 415         do {\r
 416                 pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 417                 if (IS_ERR(pservice->aclk_vcodec)) {\r
 418                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 419                         break;\r
 420                 }\r
 421 \r
 422                 pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 423                 if (IS_ERR(pservice->hclk_vcodec)) {\r
 424                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 425                         break;\r
 426                 }\r
 427 \r
 428                 if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 429                         pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 430                         if (IS_ERR(pservice->clk_core)) {\r
 431                                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 432                                 break;\r
 433                         }\r
 434 \r
 435                         if (!soc_is_rk3036()) {\r
 436                                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 437                                 if (IS_ERR(pservice->clk_cabac)) {\r
 438                                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 439                                         break;\r
 440                                 }\r
 441                         } else {\r
 442                                 pservice->clk_cabac = NULL;\r
 443                         }\r
 444 \r
 445                         if (!soc_is_rk3036()) {\r
 446                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 447                                 if (IS_ERR(pservice->pd_video)) {\r
 448                                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 449                                         break;\r
 450                                 }\r
 451                         } else {\r
 452                                 pservice->pd_video = NULL;\r
 453                         }\r
 454                 } else {\r
 455                         if (!soc_is_rk3036()) {\r
 456                                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 457                                 if (IS_ERR(pservice->pd_video)) {\r
 458                                         dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 459                                         break;\r
 460                                 }\r
 461                         } else {\r
 462                                 pservice->pd_video = NULL;\r
 463                         }\r
 464                 }\r
 465 \r
 466                 return 0;\r
 467         } while (0);\r
 468 \r
 469         return -1;\r
 470 #else\r
 471         return 0;\r
 472 #endif\r
 473 }\r
 474 \r
 475 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 476 {\r
 477 #if VCODEC_CLOCK_ENABLE\r
 478         if (pservice->pd_video) {\r
 479                 devm_clk_put(pservice->dev, pservice->pd_video);\r
 480         }\r
 481 \r
 482         if (pservice->aclk_vcodec) {\r
 483                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 484         }\r
 485 \r
 486         if (pservice->hclk_vcodec) {\r
 487                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 488         }\r
 489 \r
 490         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 491                 if (pservice->clk_core) {\r
 492                         devm_clk_put(pservice->dev, pservice->clk_core);\r
 493                 }\r
 494 \r
 495                 if (pservice->clk_cabac) {\r
 496                         devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 497                 }\r
 498         }\r
 499 #endif\r
 500 }\r
 501 \r
 502 static void vpu_reset(struct vpu_service_info *pservice)\r
 503 {\r
 504 #if defined(CONFIG_ARCH_RK29)\r
 505         clk_disable(aclk_ddr_vepu);\r
 506         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 507         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 508         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 509         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 510         mdelay(10);\r
 511         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 512         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 513         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 514         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 515         clk_enable(aclk_ddr_vepu);\r
 516 #elif defined(CONFIG_ARCH_RK30)\r
 517         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 518         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 519         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 520         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 521         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 522         mdelay(1);\r
 523         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 524         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 525         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 526         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 527         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 528 #endif\r
 529         pservice->reg_codec = NULL;\r
 530         pservice->reg_pproc = NULL;\r
 531         pservice->reg_resev = NULL;\r
 532 }\r
 533 \r
 534 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 535 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 536 {\r
 537         vpu_reg *reg, *n;\r
 538         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 539                 reg_deinit(pservice, reg);\r
 540         }\r
 541         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 542                 reg_deinit(pservice, reg);\r
 543         }\r
 544         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 545                 reg_deinit(pservice, reg);\r
 546         }\r
 547 }\r
 548 \r
 549 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 550 {\r
 551         int running;\r
 552         vpu_reg *reg, *reg_tmp;\r
 553         vpu_session *session, *session_tmp;\r
 554 \r
 555         running = atomic_read(&pservice->total_running);\r
 556         printk("total_running %d\n", running);\r
 557 \r
 558         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 559         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 560         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 561 \r
 562         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 563                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 564                 running = atomic_read(&session->task_running);\r
 565                 printk("task_running %d\n", running);\r
 566                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 567                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 568                 }\r
 569                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 570                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 571                 }\r
 572                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 573                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 574                 }\r
 575         }\r
 576 }\r
 577 \r
 578 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 579 {\r
 580         int total_running;\r
 581         if (!pservice->enabled)\r
 582                 return;\r
 583 \r
 584         pservice->enabled = false;\r
 585         total_running = atomic_read(&pservice->total_running);\r
 586         if (total_running) {\r
 587                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 588                 mdelay(50);\r
 589                 pr_alert("alert: delay 50 ms for running task\n");\r
 590                 vpu_service_dump(pservice);\r
 591         }\r
 592 \r
 593 #if defined(CONFIG_VCODEC_MMU)\r
 594         if (pservice->mmu_dev)\r
 595                 iovmm_deactivate(pservice->dev);\r
 596 #endif\r
 597 \r
 598         pr_info("%s: power off...", dev_name(pservice->dev));\r
 599         udelay(10);\r
 600 #if VCODEC_CLOCK_ENABLE\r
 601         if (pservice->pd_video)\r
 602                 clk_disable_unprepare(pservice->pd_video);\r
 603         if (pservice->hclk_vcodec)\r
 604                 clk_disable_unprepare(pservice->hclk_vcodec);\r
 605         if (pservice->aclk_vcodec)\r
 606                 clk_disable_unprepare(pservice->aclk_vcodec);\r
 607         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 608                 if (pservice->clk_core)\r
 609                         clk_disable_unprepare(pservice->clk_core);\r
 610                 if (pservice->clk_cabac)\r
 611                         clk_disable_unprepare(pservice->clk_cabac);\r
 612         }\r
 613 #endif\r
 614         wake_unlock(&pservice->wake_lock);\r
 615         pr_info("done\n");\r
 616 }\r
 617 \r
 618 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 619 {\r
 620         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 621 }\r
 622 \r
 623 static void vpu_power_off_work(struct work_struct *work_s)\r
 624 {\r
 625         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 626         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 627 \r
 628         if (mutex_trylock(&pservice->lock)) {\r
 629                 vpu_service_power_off(pservice);\r
 630                 mutex_unlock(&pservice->lock);\r
 631         } else {\r
 632                 /* Come back later if the device is busy... */\r
 633                 vpu_queue_power_off_work(pservice);\r
 634         }\r
 635 }\r
 636 \r
 637 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 638 {\r
 639         static ktime_t last;\r
 640         ktime_t now = ktime_get();\r
 641         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 642                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 643                 vpu_queue_power_off_work(pservice);\r
 644                 last = now;\r
 645         }\r
 646         if (pservice->enabled)\r
 647                 return ;\r
 648 \r
 649         pservice->enabled = true;\r
 650         printk("%s: power on\n", dev_name(pservice->dev));\r
 651 \r
 652 #if VCODEC_CLOCK_ENABLE\r
 653         if (pservice->aclk_vcodec)\r
 654                 clk_prepare_enable(pservice->aclk_vcodec);\r
 655 \r
 656         if (pservice->hclk_vcodec)\r
 657                 clk_prepare_enable(pservice->hclk_vcodec);\r
 658 \r
 659         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 660                 if (pservice->clk_core)\r
 661                         clk_prepare_enable(pservice->clk_core);\r
 662         if (pservice->clk_cabac)\r
 663                 clk_prepare_enable(pservice->clk_cabac);\r
 664         }\r
 665 \r
 666         if (pservice->pd_video)\r
 667                 clk_prepare_enable(pservice->pd_video);\r
 668 #endif\r
 669 \r
 670 #if defined(CONFIG_ARCH_RK319X)\r
 671         /// select aclk_vepu as vcodec clock source. \r
 672 #define BIT_VCODEC_SEL  (1<<7)\r
 673         writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) |\r
 674                 (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16),\r
 675                 RK319X_GRF_BASE + GRF_SOC_CON1);\r
 676 #endif\r
 677 \r
 678         udelay(10);\r
 679         wake_lock(&pservice->wake_lock);\r
 680 \r
 681 #if defined(CONFIG_VCODEC_MMU)\r
 682         if (pservice->mmu_dev)\r
 683                 iovmm_activate(pservice->dev);\r
 684 #endif\r
 685 }\r
 686 \r
 687 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 688 {\r
 689         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 690         return ((type == 8) || (type == 4));\r
 691 }\r
 692 \r
 693 static inline bool reg_check_interlace(vpu_reg *reg)\r
 694 {\r
 695         unsigned long type = (reg->reg[3] & (1 << 23));\r
 696         return (type > 0);\r
 697 }\r
 698 \r
 699 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
 700 {\r
 701         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
 702         return type;\r
 703 }\r
 704 \r
 705 static inline int reg_probe_width(vpu_reg *reg)\r
 706 {\r
 707         int width_in_mb = reg->reg[4] >> 23;\r
 708         return width_in_mb * 16;\r
 709 }\r
 710 \r
 711 #if defined(CONFIG_VCODEC_MMU)\r
 712 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 713 {\r
 714         int i;\r
 715         int usr_fd = 0;\r
 716         int offset = 0;\r
 717 \r
 718         if (tbl == NULL || size <= 0) {\r
 719                 dev_err(pservice->dev, "input arguments invalidate\n");\r
 720                 return -1;\r
 721         }\r
 722 \r
 723         vpu_service_power_on(pservice);\r
 724 \r
 725         for (i = 0; i < size; i++) {\r
 726                 usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 727 \r
 728                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID &&\r
 729                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))\r
 730                         /* special for vpu dec num 41 regitster */\r
 731                         offset = reg->reg[tbl[i]] >> 10 << 4;\r
 732                 else\r
 733                         offset = reg->reg[tbl[i]] >> 10;\r
 734 \r
 735                 if (usr_fd != 0) {\r
 736                         struct ion_handle *hdl;\r
 737                         int ret;\r
 738                         struct vcodec_mem_region *mem_region;\r
 739 \r
 740                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 741                         if (IS_ERR(hdl)) {\r
 742                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 743                                 return PTR_ERR(hdl);\r
 744                         }\r
 745 \r
 746                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 747 \r
 748                         if (mem_region == NULL) {\r
 749                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 750                                 ion_free(pservice->ion_client, hdl);\r
 751                                 return -1;\r
 752                         }\r
 753 \r
 754                         mem_region->hdl = hdl;\r
 755 \r
 756                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 757                         if (ret < 0) {\r
 758                                 dev_err(pservice->dev, "ion map iommu failed\n");\r
 759                                 kfree(mem_region);\r
 760                                 ion_free(pservice->ion_client, hdl);\r
 761                                 return ret;\r
 762                         }\r
 763                         reg->reg[tbl[i]] = mem_region->iova + offset;\r
 764                         INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 765                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 766                 }\r
 767         }\r
 768         return 0;\r
 769 }\r
 770 \r
 771 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 772 {\r
 773         VPU_HW_ID hw_id;\r
 774         u8 *tbl;\r
 775         int size = 0;\r
 776 \r
 777         hw_id = pservice->hw_info->hw_id;\r
 778 \r
 779         if (hw_id == HEVC_ID) {\r
 780                 tbl = addr_tbl_hevc_dec;\r
 781                 size = sizeof(addr_tbl_hevc_dec);\r
 782         } else {\r
 783                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 784                         switch (reg_check_fmt(reg)) {\r
 785                         case VPU_DEC_FMT_H264:\r
 786                                 {\r
 787                                         tbl = addr_tbl_vpu_h264dec;\r
 788                                         size = sizeof(addr_tbl_vpu_h264dec);\r
 789                                         break;\r
 790                                 }\r
 791                         case VPU_DEC_FMT_VP8:\r
 792                         case VPU_DEC_FMT_VP7:\r
 793                                 {\r
 794                                         tbl = addr_tbl_vpu_vp8dec;\r
 795                                         size = sizeof(addr_tbl_vpu_vp8dec);\r
 796                                         break;\r
 797                                 }\r
 798 \r
 799                         case VPU_DEC_FMT_VP6:\r
 800                                 {\r
 801                                         tbl = addr_tbl_vpu_vp6dec;\r
 802                                         size = sizeof(addr_tbl_vpu_vp6dec);\r
 803                                         break;\r
 804                                 }\r
 805                         case VPU_DEC_FMT_VC1:\r
 806                                 {\r
 807                                         tbl = addr_tbl_vpu_vc1dec;\r
 808                                         size = sizeof(addr_tbl_vpu_vc1dec);\r
 809                                         break;\r
 810                                 }\r
 811 \r
 812                         case VPU_DEC_FMT_JPEG:\r
 813                                 {\r
 814                                         tbl = addr_tbl_vpu_jpegdec;\r
 815                                         size = sizeof(addr_tbl_vpu_jpegdec);\r
 816                                         break;\r
 817                                 }\r
 818                         default:\r
 819                                 tbl = addr_tbl_vpu_defaultdec;\r
 820                                 size = sizeof(addr_tbl_vpu_defaultdec);\r
 821                                 break;\r
 822                         }\r
 823                 } else if (reg->type == VPU_ENC) {\r
 824                         tbl = addr_tbl_vpu_enc;\r
 825                         size = sizeof(addr_tbl_vpu_enc);\r
 826                 }\r
 827         }\r
 828 \r
 829         if (size != 0) {\r
 830                 return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 831         } else {\r
 832                 return -1;\r
 833         }\r
 834 }\r
 835 #endif\r
 836 \r
 837 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 838 {\r
 839         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 840         if (NULL == reg) {\r
 841                 pr_err("error: kmalloc fail in reg_init\n");\r
 842                 return NULL;\r
 843         }\r
 844 \r
 845         if (size > pservice->reg_size) {\r
 846                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 847                 size = pservice->reg_size;\r
 848         }\r
 849         reg->session = session;\r
 850         reg->type = session->type;\r
 851         reg->size = size;\r
 852         reg->freq = VPU_FREQ_DEFAULT;\r
 853         reg->reg = (unsigned long *)&reg[1];\r
 854         INIT_LIST_HEAD(&reg->session_link);\r
 855         INIT_LIST_HEAD(&reg->status_link);\r
 856 \r
 857 #if defined(CONFIG_VCODEC_MMU)  \r
 858         if (pservice->mmu_dev)\r
 859                 INIT_LIST_HEAD(&reg->mem_region_list);\r
 860 #endif\r
 861 \r
 862         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 863                 pr_err("error: copy_from_user failed in reg_init\n");\r
 864                 kfree(reg);\r
 865                 return NULL;\r
 866         }\r
 867 \r
 868 #if defined(CONFIG_VCODEC_MMU)\r
 869         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg)) {\r
 870                 pr_err("error: translate reg address failed\n");\r
 871                 kfree(reg);\r
 872                 return NULL;\r
 873         }\r
 874 #endif\r
 875 \r
 876         mutex_lock(&pservice->lock);\r
 877         list_add_tail(&reg->status_link, &pservice->waiting);\r
 878         list_add_tail(&reg->session_link, &session->waiting);\r
 879         mutex_unlock(&pservice->lock);\r
 880 \r
 881         if (pservice->auto_freq) {\r
 882                 if (!soc_is_rk2928g()) {\r
 883                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 884                                 if (reg_check_rmvb_wmv(reg)) {\r
 885                                         reg->freq = VPU_FREQ_200M;\r
 886                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
 887                                         if (reg_probe_width(reg) > 3200) {\r
 888                                                 // raise frequency for 4k avc.\r
 889                                                 reg->freq = VPU_FREQ_500M;\r
 890                                         }\r
 891                                 } else {\r
 892                                         if (reg_check_interlace(reg)) {\r
 893                                                 reg->freq = VPU_FREQ_400M;\r
 894                                         }\r
 895                                 }\r
 896                         }\r
 897                         if (reg->type == VPU_PP) {\r
 898                                 reg->freq = VPU_FREQ_400M;\r
 899                         }\r
 900                 }\r
 901         }\r
 902 \r
 903         return reg;\r
 904 }\r
 905 \r
 906 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 907 {\r
 908 #if defined(CONFIG_VCODEC_MMU)\r
 909         struct vcodec_mem_region *mem_region = NULL, *n;\r
 910 #endif\r
 911 \r
 912         list_del_init(&reg->session_link);\r
 913         list_del_init(&reg->status_link);\r
 914         if (reg == pservice->reg_codec)\r
 915                 pservice->reg_codec = NULL;\r
 916         if (reg == pservice->reg_pproc)\r
 917                 pservice->reg_pproc = NULL;\r
 918 \r
 919 #if defined(CONFIG_VCODEC_MMU)\r
 920         // release memory region attach to this registers table.\r
 921         if (pservice->mmu_dev) {\r
 922                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 923                         ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
 924                         ion_free(pservice->ion_client, mem_region->hdl);\r
 925                         list_del_init(&mem_region->reg_lnk);\r
 926                         kfree(mem_region);\r
 927                 }\r
 928         }\r
 929 #endif\r
 930 \r
 931         kfree(reg);\r
 932 }\r
 933 \r
 934 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 935 {\r
 936         list_del_init(&reg->status_link);\r
 937         list_add_tail(&reg->status_link, &pservice->running);\r
 938 \r
 939         list_del_init(&reg->session_link);\r
 940         list_add_tail(&reg->session_link, &reg->session->running);\r
 941 }\r
 942 \r
 943 static void reg_copy_from_hw(struct vpu_service_info *pservice, vpu_reg *reg, volatile u32 *src, u32 count)\r
 944 {\r
 945         int i;\r
 946         u32 *dst = (u32 *)&reg->reg[0];\r
 947 \r
 948         vcodec_select_mode(pservice->dev_id);\r
 949         for (i = 0; i < count; i++)\r
 950                 *dst++ = *src++;\r
 951 }\r
 952 \r
 953 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 954 {\r
 955         int irq_reg = -1;\r
 956         list_del_init(&reg->status_link);\r
 957         list_add_tail(&reg->status_link, &pservice->done);\r
 958 \r
 959         list_del_init(&reg->session_link);\r
 960         list_add_tail(&reg->session_link, &reg->session->done);\r
 961 \r
 962         switch (reg->type) {\r
 963         case VPU_ENC : {\r
 964                 pservice->reg_codec = NULL;\r
 965                 reg_copy_from_hw(pservice, reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 966                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 967                 break;\r
 968         }\r
 969         case VPU_DEC : {\r
 970                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 971                 pservice->reg_codec = NULL;\r
 972                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs, reg_len);\r
 973                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 974                 break;\r
 975         }\r
 976         case VPU_PP : {\r
 977                 pservice->reg_pproc = NULL;\r
 978                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 979                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 980                 break;\r
 981         }\r
 982         case VPU_DEC_PP : {\r
 983                 pservice->reg_codec = NULL;\r
 984                 pservice->reg_pproc = NULL;\r
 985                 reg_copy_from_hw(pservice, reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 986                 vcodec_select_mode(pservice->dev_id);\r
 987                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 988                 break;\r
 989         }\r
 990         default : {\r
 991                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 992                 break;\r
 993         }\r
 994         }\r
 995 \r
 996         if (irq_reg != -1) {\r
 997                 reg->reg[irq_reg] = pservice->irq_status;\r
 998         }\r
 999 \r
1000         atomic_sub(1, &reg->session->task_running);\r
1001         atomic_sub(1, &pservice->total_running);\r
1002         wake_up(&reg->session->wait);\r
1003 }\r
1004 \r
1005 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
1006 {\r
1007         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
1008         if (curr == reg->freq) {\r
1009                 return ;\r
1010         }\r
1011         atomic_set(&pservice->freq_status, reg->freq);\r
1012         switch (reg->freq) {\r
1013         case VPU_FREQ_200M : {\r
1014                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
1015                 //printk("default: 200M\n");\r
1016         } break;\r
1017         case VPU_FREQ_266M : {\r
1018                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
1019                 //printk("default: 266M\n");\r
1020         } break;\r
1021         case VPU_FREQ_300M : {\r
1022                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
1023                 //printk("default: 300M\n");\r
1024         } break;\r
1025         case VPU_FREQ_400M : {\r
1026                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
1027                 //printk("default: 400M\n");\r
1028         } break;\r
1029         case VPU_FREQ_500M : {\r
1030                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
1031         } break;\r
1032         case VPU_FREQ_600M : {\r
1033                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
1034         } break;\r
1035         default : {\r
1036                 if (soc_is_rk2928g()) {\r
1037                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
1038                 } else {\r
1039                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
1040                 }\r
1041                 //printk("default: 300M\n");\r
1042         } break;\r
1043         }\r
1044 }\r
1045 \r
1046 #if HEVC_SIM_ENABLE\r
1047 static void simulate_start(struct vpu_service_info *pservice);\r
1048 #endif\r
1049 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
1050 {\r
1051         int i;\r
1052         u32 *src = (u32 *)&reg->reg[0];\r
1053         atomic_add(1, &pservice->total_running);\r
1054         atomic_add(1, &reg->session->task_running);\r
1055         if (pservice->auto_freq) {\r
1056                 vpu_service_set_freq(pservice, reg);\r
1057         }\r
1058         \r
1059         vcodec_select_mode(pservice->dev_id);\r
1060         \r
1061         switch (reg->type) {\r
1062         case VPU_ENC : {\r
1063                 int enc_count = pservice->hw_info->enc_reg_num;\r
1064                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
1065 \r
1066                 pservice->reg_codec = reg;\r
1067 \r
1068                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
1069 \r
1070                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
1071                         dst[i] = src[i];\r
1072 \r
1073                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
1074                         dst[i] = src[i];\r
1075 \r
1076                 dsb();\r
1077 \r
1078                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
1079                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
1080 \r
1081 #if VPU_SERVICE_SHOW_TIME\r
1082                 do_gettimeofday(&enc_start);\r
1083 #endif\r
1084 \r
1085         } break;\r
1086         case VPU_DEC : {\r
1087                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1088 \r
1089                 pservice->reg_codec = reg;\r
1090 \r
1091                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1092                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
1093                                 dst[i] = src[i];\r
1094                 } else {\r
1095                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
1096                                 dst[i] = src[i];\r
1097                         }\r
1098                 }\r
1099 \r
1100                 dsb();\r
1101 \r
1102                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1103                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
1104                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
1105                 } else {\r
1106                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
1107                 }\r
1108 \r
1109                 dsb();\r
1110                 dmb();\r
1111 \r
1112 #if VPU_SERVICE_SHOW_TIME\r
1113                 do_gettimeofday(&dec_start);\r
1114 #endif\r
1115 \r
1116         } break;\r
1117         case VPU_PP : {\r
1118                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1119                 pservice->reg_pproc = reg;\r
1120 \r
1121                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1122 \r
1123                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1124                         dst[i] = src[i];\r
1125 \r
1126                 dsb();\r
1127 \r
1128                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1129 \r
1130 #if VPU_SERVICE_SHOW_TIME\r
1131                 do_gettimeofday(&pp_start);\r
1132 #endif\r
1133 \r
1134         } break;\r
1135         case VPU_DEC_PP : {\r
1136                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1137                 pservice->reg_codec = reg;\r
1138                 pservice->reg_pproc = reg;\r
1139 \r
1140                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1141                         dst[i] = src[i];\r
1142 \r
1143                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1144                 dsb();\r
1145 \r
1146                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1147                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1148                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1149 \r
1150 #if VPU_SERVICE_SHOW_TIME\r
1151                 do_gettimeofday(&dec_start);\r
1152 #endif\r
1153 \r
1154         } break;\r
1155         default : {\r
1156                 pr_err("error: unsupport session type %d", reg->type);\r
1157                 atomic_sub(1, &pservice->total_running);\r
1158                 atomic_sub(1, &reg->session->task_running);\r
1159                 break;\r
1160         }\r
1161         }\r
1162 \r
1163 #if HEVC_SIM_ENABLE\r
1164         if (pservice->hw_info->hw_id == HEVC_ID) {\r
1165                 simulate_start(pservice);\r
1166         }\r
1167 #endif\r
1168 }\r
1169 \r
1170 static void try_set_reg(struct vpu_service_info *pservice)\r
1171 {\r
1172         // first get reg from reg list\r
1173         if (!list_empty(&pservice->waiting)) {\r
1174                 int can_set = 0;\r
1175                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1176 \r
1177                 vpu_service_power_on(pservice);\r
1178 \r
1179                 switch (reg->type) {\r
1180                 case VPU_ENC : {\r
1181                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1182                                 can_set = 1;\r
1183                 } break;\r
1184                 case VPU_DEC : {\r
1185                         if (NULL == pservice->reg_codec)\r
1186                                 can_set = 1;\r
1187                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1188                                 can_set = 0;\r
1189                         }\r
1190                 } break;\r
1191                 case VPU_PP : {\r
1192                         if (NULL == pservice->reg_codec) {\r
1193                                 if (NULL == pservice->reg_pproc)\r
1194                                         can_set = 1;\r
1195                         } else {\r
1196                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1197                                         can_set = 1;\r
1198                                 // can not charge frequency when vpu is working\r
1199                                 if (pservice->auto_freq) {\r
1200                                         can_set = 0;\r
1201                                 }\r
1202                         }\r
1203                 } break;\r
1204                 case VPU_DEC_PP : {\r
1205                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1206                                 can_set = 1;\r
1207                         } break;\r
1208                 default : {\r
1209                         printk("undefined reg type %d\n", reg->type);\r
1210                 } break;\r
1211                 }\r
1212                 if (can_set) {\r
1213                         reg_from_wait_to_run(pservice, reg);\r
1214                         reg_copy_to_hw(pservice, reg);\r
1215                 }\r
1216         }\r
1217 }\r
1218 \r
1219 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1220 {\r
1221         int ret = 0;\r
1222         switch (reg->type) {\r
1223         case VPU_ENC : {\r
1224                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1225                         ret = -EFAULT;\r
1226                 break;\r
1227         }\r
1228         case VPU_DEC : {\r
1229                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1230                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1231                         ret = -EFAULT;\r
1232                 break;\r
1233         }\r
1234         case VPU_PP : {\r
1235                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1236                         ret = -EFAULT;\r
1237                 break;\r
1238         }\r
1239         case VPU_DEC_PP : {\r
1240                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1241                         ret = -EFAULT;\r
1242                 break;\r
1243         }\r
1244         default : {\r
1245                 ret = -EFAULT;\r
1246                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1247                 break;\r
1248         }\r
1249         }\r
1250         reg_deinit(pservice, reg);\r
1251         return ret;\r
1252 }\r
1253 \r
1254 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1255 {\r
1256     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1257         vpu_session *session = (vpu_session *)filp->private_data;\r
1258         if (NULL == session) {\r
1259                 return -EINVAL;\r
1260         }\r
1261 \r
1262         switch (cmd) {\r
1263         case VPU_IOC_SET_CLIENT_TYPE : {\r
1264                 session->type = (VPU_CLIENT_TYPE)arg;\r
1265                 break;\r
1266         }\r
1267         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1268                 vpu_request req;\r
1269                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1270                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1271                         return -EFAULT;\r
1272                 } else {\r
1273                         if (VPU_ENC != session->type) {\r
1274                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1275                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1276                                         return -EFAULT;\r
1277                                 }\r
1278                         } else {\r
1279                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1280                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1281                                         return -EFAULT;\r
1282                                 }\r
1283                         }\r
1284                 }\r
1285 \r
1286                 break;\r
1287         }\r
1288         case VPU_IOC_SET_REG : {\r
1289                 vpu_request req;\r
1290                 vpu_reg *reg;\r
1291                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1292                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1293                         return -EFAULT;\r
1294                 }\r
1295                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1296                 if (NULL == reg) {\r
1297                         return -EFAULT;\r
1298                 } else {\r
1299                         mutex_lock(&pservice->lock);\r
1300                         try_set_reg(pservice);\r
1301                         mutex_unlock(&pservice->lock);\r
1302                 }\r
1303 \r
1304                 break;\r
1305         }\r
1306         case VPU_IOC_GET_REG : {\r
1307                 vpu_request req;\r
1308                 vpu_reg *reg;\r
1309                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1310                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1311                         return -EFAULT;\r
1312                 } else {\r
1313                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1314                         if (!list_empty(&session->done)) {\r
1315                                 if (ret < 0) {\r
1316                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1317                                 }\r
1318                                 ret = 0;\r
1319                         } else {\r
1320                                 if (unlikely(ret < 0)) {\r
1321                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1322                                 } else if (0 == ret) {\r
1323                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1324                                         ret = -ETIMEDOUT;\r
1325                                 }\r
1326                         }\r
1327                         if (ret < 0) {\r
1328                                 int task_running = atomic_read(&session->task_running);\r
1329                                 mutex_lock(&pservice->lock);\r
1330                                 vpu_service_dump(pservice);\r
1331                                 if (task_running) {\r
1332                                         atomic_set(&session->task_running, 0);\r
1333                                         atomic_sub(task_running, &pservice->total_running);\r
1334                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1335                                         vpu_reset(pservice);\r
1336                                         printk("done\n");\r
1337                                 }\r
1338                                 vpu_service_session_clear(pservice, session);\r
1339                                 mutex_unlock(&pservice->lock);\r
1340                                 return ret;\r
1341                         }\r
1342                 }\r
1343                 mutex_lock(&pservice->lock);\r
1344                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1345                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1346                 mutex_unlock(&pservice->lock);\r
1347                 break;\r
1348         }\r
1349         case VPU_IOC_PROBE_IOMMU_STATUS: {\r
1350                 int iommu_enable = 0;\r
1351 \r
1352 #if defined(CONFIG_VCODEC_MMU)\r
1353                 iommu_enable = pservice->mmu_dev ? 1 : 0; \r
1354 #endif\r
1355 \r
1356                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
1357                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
1358                         return -EFAULT;\r
1359                 }\r
1360                 break;\r
1361         }\r
1362         default : {\r
1363                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1364                 break;\r
1365         }\r
1366         }\r
1367 \r
1368         return 0;\r
1369 }\r
1370 #if 1\r
1371 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1372 {\r
1373         int ret = -EINVAL, i = 0;\r
1374         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1375         u32 enc_id = *tmp;\r
1376 \r
1377 #if HEVC_SIM_ENABLE\r
1378         /// temporary, hevc driver test.\r
1379         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1380                 p->hw_info = &vpu_hw_set[2];\r
1381                 return 0;\r
1382         }\r
1383 #endif\r
1384         enc_id = (enc_id >> 16) & 0xFFFF;\r
1385         pr_info("checking hw id %x\n", enc_id);\r
1386         p->hw_info = NULL;\r
1387         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1388                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1389                         p->hw_info = &vpu_hw_set[i];\r
1390                         ret = 0;\r
1391                         break;\r
1392                 }\r
1393         }\r
1394         iounmap((void *)tmp);\r
1395         return ret;\r
1396 }\r
1397 #endif\r
1398 \r
1399 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1400 {\r
1401         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1402         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1403         if (NULL == session) {\r
1404                 pr_err("error: unable to allocate memory for vpu_session.");\r
1405                 return -ENOMEM;\r
1406         }\r
1407 \r
1408         session->type   = VPU_TYPE_BUTT;\r
1409         session->pid    = current->pid;\r
1410         INIT_LIST_HEAD(&session->waiting);\r
1411         INIT_LIST_HEAD(&session->running);\r
1412         INIT_LIST_HEAD(&session->done);\r
1413         INIT_LIST_HEAD(&session->list_session);\r
1414         init_waitqueue_head(&session->wait);\r
1415         atomic_set(&session->task_running, 0);\r
1416         mutex_lock(&pservice->lock);\r
1417         list_add_tail(&session->list_session, &pservice->session);\r
1418         filp->private_data = (void *)session;\r
1419         mutex_unlock(&pservice->lock);\r
1420 \r
1421         pr_debug("dev opened\n");\r
1422         return nonseekable_open(inode, filp);\r
1423 }\r
1424 \r
1425 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1426 {\r
1427         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1428         int task_running;\r
1429         vpu_session *session = (vpu_session *)filp->private_data;\r
1430         if (NULL == session)\r
1431                 return -EINVAL;\r
1432 \r
1433         task_running = atomic_read(&session->task_running);\r
1434         if (task_running) {\r
1435                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1436                 msleep(50);\r
1437         }\r
1438         wake_up(&session->wait);\r
1439 \r
1440         mutex_lock(&pservice->lock);\r
1441         /* remove this filp from the asynchronusly notified filp's */\r
1442         list_del_init(&session->list_session);\r
1443         vpu_service_session_clear(pservice, session);\r
1444         kfree(session);\r
1445         filp->private_data = NULL;\r
1446         mutex_unlock(&pservice->lock);\r
1447 \r
1448         pr_debug("dev closed\n");\r
1449         return 0;\r
1450 }\r
1451 \r
1452 static const struct file_operations vpu_service_fops = {\r
1453         .unlocked_ioctl = vpu_service_ioctl,\r
1454         .open           = vpu_service_open,\r
1455         .release        = vpu_service_release,\r
1456         //.fasync       = vpu_service_fasync,\r
1457 };\r
1458 \r
1459 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1460 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1461 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1462 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1463 static void get_hw_info(struct vpu_service_info *pservice);\r
1464 \r
1465 #if HEVC_SIM_ENABLE\r
1466 static void simulate_work(struct work_struct *work_s)\r
1467 {\r
1468         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1469         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1470         vpu_device *dev = &pservice->dec_dev;\r
1471 \r
1472         if (!list_empty(&pservice->running)) {\r
1473                 atomic_add(1, &dev->irq_count_codec);\r
1474                 vdpu_isr(0, (void*)pservice);\r
1475         } else {\r
1476                 //simulate_start(pservice);\r
1477                 pr_err("empty running queue\n");\r
1478         }\r
1479 }\r
1480 \r
1481 static void simulate_init(struct vpu_service_info *pservice)\r
1482 {\r
1483         INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1484 }\r
1485 \r
1486 static void simulate_start(struct vpu_service_info *pservice)\r
1487 {\r
1488         cancel_delayed_work_sync(&pservice->power_off_work);\r
1489         queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1490 }\r
1491 #endif\r
1492 \r
1493 #if HEVC_TEST_ENABLE\r
1494 static int hevc_test_case0(vpu_service_info *pservice);\r
1495 #endif\r
1496 #if defined(CONFIG_ION_ROCKCHIP)\r
1497 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1498 #endif\r
1499 static int vcodec_probe(struct platform_device *pdev)\r
1500 {\r
1501         int ret = 0;\r
1502         struct resource *res = NULL;\r
1503         struct device *dev = &pdev->dev;\r
1504         void __iomem *regs = NULL;\r
1505         struct device_node *np = pdev->dev.of_node;\r
1506         struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1507         char *prop = (char*)dev_name(dev);\r
1508 #if defined(CONFIG_VCODEC_MMU)\r
1509         char mmu_dev_dts_name[40];\r
1510 #endif\r
1511 \r
1512         pr_info("probe device %s\n", dev_name(dev));\r
1513 \r
1514         of_property_read_string(np, "name", (const char**)&prop);\r
1515         dev_set_name(dev, prop);\r
1516 \r
1517         if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1518                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1519                 vcodec_select_mode(VCODEC_DEVICE_ID_HEVC);\r
1520         } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1521                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1522         } else {\r
1523                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1524                 return -1;\r
1525         }\r
1526 \r
1527         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1528         INIT_LIST_HEAD(&pservice->waiting);\r
1529         INIT_LIST_HEAD(&pservice->running);\r
1530         INIT_LIST_HEAD(&pservice->done);\r
1531         INIT_LIST_HEAD(&pservice->session);\r
1532         mutex_init(&pservice->lock);\r
1533         pservice->reg_codec     = NULL;\r
1534         pservice->reg_pproc     = NULL;\r
1535         atomic_set(&pservice->total_running, 0);\r
1536         pservice->enabled = false;\r
1537 #if defined(CONFIG_VCODEC_MMU)    \r
1538         pservice->mmu_dev = NULL;\r
1539 #endif\r
1540         pservice->dev = dev;\r
1541 \r
1542         if (0 > vpu_get_clk(pservice))\r
1543                 goto err;\r
1544 \r
1545         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1546 \r
1547         vpu_service_power_on(pservice);\r
1548 \r
1549         mdelay(1);\r
1550 \r
1551         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1552 \r
1553         res->flags &= ~IORESOURCE_CACHEABLE;\r
1554 \r
1555         regs = devm_ioremap_resource(pservice->dev, res);\r
1556         if (IS_ERR(regs)) {\r
1557                 ret = PTR_ERR(regs);\r
1558                 goto err;\r
1559         }\r
1560 \r
1561         {\r
1562                 u32 offset = res->start;\r
1563                 if (soc_is_rk3036()) {\r
1564                         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU)\r
1565                                 offset += 0x400;\r
1566                         vcodec_select_mode(pservice->dev_id);\r
1567                 }\r
1568                 ret = vpu_service_check_hw(pservice, offset);\r
1569                 if (ret < 0) {\r
1570                         pr_err("error: hw info check faild\n");\r
1571                         goto err;\r
1572                 }\r
1573         }\r
1574 \r
1575         /// define regs address.\r
1576         pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1577         pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1578 \r
1579         printk("%s %d\n", __func__, __LINE__);\r
1580 \r
1581         pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1582 \r
1583         pservice->reg_size   = pservice->dec_dev.iosize;\r
1584 \r
1585         printk("%s %d\n", __func__, __LINE__);\r
1586 \r
1587         if (pservice->hw_info->hw_id != HEVC_ID && !soc_is_rk3036()) {\r
1588                 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1589                 pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1590 \r
1591                 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1592 \r
1593                 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1594 \r
1595                 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1596                 if (pservice->irq_enc < 0) {\r
1597                         dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1598                         ret = -ENXIO;\r
1599                         goto err;\r
1600                 }\r
1601 \r
1602                 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1603                 if (ret) {\r
1604                         dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1605                         goto err;\r
1606                 }\r
1607         }\r
1608 \r
1609         pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1610         if (pservice->irq_dec < 0) {\r
1611                 dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1612                 ret = -ENXIO;\r
1613                 goto err;\r
1614         }\r
1615 \r
1616         /* get the IRQ line */\r
1617         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1618         if (ret) {\r
1619                 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1620                 goto err;\r
1621         }\r
1622 \r
1623         atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1624         atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1625         atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1626         atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1627 \r
1628         /// create device\r
1629         ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1630         if (ret) {\r
1631                 dev_err(dev, "alloc dev_t failed\n");\r
1632                 goto err;\r
1633         }\r
1634 \r
1635         cdev_init(&pservice->cdev, &vpu_service_fops);\r
1636 \r
1637         pservice->cdev.owner = THIS_MODULE;\r
1638         pservice->cdev.ops = &vpu_service_fops;\r
1639 \r
1640         ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1641 \r
1642         if (ret) {\r
1643                 dev_err(dev, "add dev_t failed\n");\r
1644                 goto err;\r
1645         }\r
1646 \r
1647         pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1648 \r
1649         if (IS_ERR(pservice->cls)) {\r
1650                 ret = PTR_ERR(pservice->cls);\r
1651                 dev_err(dev, "class_create err:%d\n", ret);\r
1652                 goto err;\r
1653         }\r
1654 \r
1655         pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1656 \r
1657         platform_set_drvdata(pdev, pservice);\r
1658 \r
1659         get_hw_info(pservice);\r
1660 \r
1661 \r
1662 #ifdef CONFIG_DEBUG_FS\r
1663         pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1664         if (pservice->debugfs_dir == NULL)\r
1665                 pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1666 \r
1667         pservice->debugfs_file_regs = \r
1668                 debugfs_create_file("regs", 0664,\r
1669                                     pservice->debugfs_dir, pservice,\r
1670                                     &debug_vcodec_fops);\r
1671 #endif\r
1672 \r
1673 #if defined(CONFIG_VCODEC_MMU)\r
1674         pservice->ion_client = rockchip_ion_client_create("vpu");\r
1675         if (IS_ERR(pservice->ion_client)) {\r
1676                 dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1677                 return PTR_ERR(pservice->ion_client);\r
1678         } else {\r
1679                 dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1680         }\r
1681 \r
1682         if (pservice->hw_info->hw_id == HEVC_ID)\r
1683                 sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1684         else\r
1685                 sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1686         pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1687 \r
1688         if (pservice->mmu_dev) {\r
1689                 platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
1690                 iovmm_activate(pservice->dev);\r
1691         }\r
1692 #endif\r
1693 \r
1694         vpu_service_power_off(pservice);\r
1695         pr_info("init success\n");\r
1696 \r
1697 #if HEVC_SIM_ENABLE\r
1698         if (pservice->hw_info->hw_id == HEVC_ID)\r
1699                 simulate_init(pservice);\r
1700 #endif\r
1701 \r
1702 #if HEVC_TEST_ENABLE\r
1703         hevc_test_case0(pservice);\r
1704 #endif\r
1705 \r
1706         return 0;\r
1707 \r
1708 err:\r
1709         pr_info("init failed\n");\r
1710         vpu_service_power_off(pservice);\r
1711         vpu_put_clk(pservice);\r
1712         wake_lock_destroy(&pservice->wake_lock);\r
1713 \r
1714         if (res)\r
1715                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1716         if (pservice->irq_enc > 0)\r
1717                 free_irq(pservice->irq_enc, (void *)pservice);\r
1718         if (pservice->irq_dec > 0)\r
1719                 free_irq(pservice->irq_dec, (void *)pservice);\r
1720 \r
1721         if (pservice->child_dev) {\r
1722                 device_destroy(pservice->cls, pservice->dev_t);\r
1723                 cdev_del(&pservice->cdev);\r
1724                 unregister_chrdev_region(pservice->dev_t, 1);\r
1725         }\r
1726 \r
1727         if (pservice->cls)\r
1728                 class_destroy(pservice->cls);\r
1729 \r
1730         return ret;\r
1731 }\r
1732 \r
1733 static int vcodec_remove(struct platform_device *pdev)\r
1734 {\r
1735         struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1736         struct resource *res;\r
1737 \r
1738         device_destroy(pservice->cls, pservice->dev_t);\r
1739         class_destroy(pservice->cls);\r
1740         cdev_del(&pservice->cdev);\r
1741         unregister_chrdev_region(pservice->dev_t, 1);\r
1742 \r
1743         free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1744         free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1745         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1746         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1747         vpu_put_clk(pservice);\r
1748         wake_lock_destroy(&pservice->wake_lock);\r
1749 \r
1750 #ifdef CONFIG_DEBUG_FS\r
1751         debugfs_remove(pservice->debugfs_file_regs);\r
1752         debugfs_remove(pservice->debugfs_dir);\r
1753 #endif\r
1754 \r
1755         return 0;\r
1756 }\r
1757 \r
1758 #if defined(CONFIG_OF)\r
1759 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1760         {.compatible = "vpu_service",},\r
1761         {.compatible = "rockchip,hevc_service",},\r
1762         {},\r
1763 };\r
1764 #endif\r
1765 \r
1766 static struct platform_driver vcodec_driver = {\r
1767         .probe = vcodec_probe,\r
1768         .remove = vcodec_remove,\r
1769         .driver = {\r
1770                 .name = "vcodec",\r
1771                 .owner = THIS_MODULE,\r
1772 #if defined(CONFIG_OF)\r
1773                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1774 #endif\r
1775         },\r
1776 };\r
1777 \r
1778 static void get_hw_info(struct vpu_service_info *pservice)\r
1779 {\r
1780         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1781         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1782 \r
1783         if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {\r
1784                 u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1785                 u32 asicID      = pservice->dec_dev.hwregs[0];\r
1786         \r
1787                 dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1788                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1789                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1790                         dec->jpegSupport = JPEG_PROGRESSIVE;\r
1791                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1792                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1793                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1794                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1795                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1796                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1797 \r
1798                 if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1799                         dec->maxDecPicWidth = configReg & 0x07FFU;\r
1800                 } else {\r
1801                         dec->maxDecPicWidth = 4096;\r
1802                 }\r
1803         \r
1804                 /* 2nd Config register */\r
1805                 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1806                 if (dec->refBufSupport) {\r
1807                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1808                                 dec->refBufSupport |= 2;\r
1809                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1810                                 dec->refBufSupport |= 4;\r
1811                 }\r
1812                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1813                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1814                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1815                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1816 \r
1817                 /* JPEG xtensions */\r
1818                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))\r
1819                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1820                 else\r
1821                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1822 \r
1823                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )\r
1824                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1825                 else\r
1826                         dec->rvSupport = RV_NOT_SUPPORTED;\r
1827                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1828 \r
1829                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )\r
1830                         dec->refBufSupport |= 8; /* enable HW support for offset */\r
1831         \r
1832                 /// invalidate fuse register value in rk319x vpu and following.\r
1833                 if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1834                         VPUHwFuseStatus_t hwFuseSts;\r
1835                         /* Decoder fuse configuration */\r
1836                         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1837 \r
1838                         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1839                         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1840                         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1841                         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1842                         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1843                         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1844                         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1845                         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1846                         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1847                         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1848                         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1849                         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1850                         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1851                         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1852 \r
1853                         /* check max. decoder output width */\r
1854 \r
1855                         if (fuseReg & 0x8000U)\r
1856                                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1857                         else if (fuseReg & 0x4000U)\r
1858                                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1859                         else if (fuseReg & 0x2000U)\r
1860                                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1861                         else if (fuseReg & 0x1000U)\r
1862                                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1863                         else    /* remove warning */\r
1864                                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1865 \r
1866                         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1867 \r
1868                         /* Pp configuration */\r
1869                         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1870 \r
1871                         if ((configReg >> DWL_PP_E) & 0x01U) {\r
1872                                 dec->ppSupport = 1;\r
1873                                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1874                                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1875                                 dec->ppConfig = configReg;\r
1876                         } else {\r
1877                                 dec->ppSupport = 0;\r
1878                                 dec->maxPpOutPicWidth = 0;\r
1879                                 dec->ppConfig = 0;\r
1880                         }\r
1881 \r
1882                         /* check the HW versio */\r
1883                         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1884                                 /* Pp configuration */\r
1885                                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1886                                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1887                                         /* Pp fuse configuration */\r
1888                                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1889 \r
1890                                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1891                                                 hwFuseSts.ppSupportFuse = 1;\r
1892                                                 /* check max. pp output width */\r
1893                                                 if (fuseRegPp & 0x8000U)\r
1894                                                         hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1895                                                 else if (fuseRegPp & 0x4000U)\r
1896                                                         hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1897                                                 else if (fuseRegPp & 0x2000U)\r
1898                                                         hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1899                                                 else if (fuseRegPp & 0x1000U)\r
1900                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1901                                                 else\r
1902                                                         hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1903                                                 hwFuseSts.ppConfigFuse = fuseRegPp;\r
1904                                         } else {\r
1905                                                 hwFuseSts.ppSupportFuse = 0;\r
1906                                                 hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1907                                                 hwFuseSts.ppConfigFuse = 0;\r
1908                                         }\r
1909                                 } else {\r
1910                                         hwFuseSts.ppSupportFuse = 0;\r
1911                                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1912                                         hwFuseSts.ppConfigFuse = 0;\r
1913                                 }\r
1914 \r
1915                                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1916                                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1917                                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1918                                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1919                                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1920                                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1921                                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1922                                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1923                                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1924                                         dec->jpegSupport = JPEG_BASELINE;\r
1925                                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1926                                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1927                                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1928                                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1929                                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1930                                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1931 \r
1932                                 /* check the pp config vs fuse status */\r
1933                                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1934                                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1935                                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1936                                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1937                                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1938 \r
1939                                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1940                                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1941                                 }\r
1942                                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1943                                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1944                                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1945                                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1946                                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1947                         }\r
1948                 }\r
1949 \r
1950                 if (!soc_is_rk3036()) {\r
1951                         configReg = pservice->enc_dev.hwregs[63];\r
1952                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1953                         enc->h264Enabled = (configReg >> 27) & 1;\r
1954                         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1955                         enc->jpegEnabled = (configReg >> 25) & 1;\r
1956                         enc->vsEnabled = (configReg >> 24) & 1;\r
1957                         enc->rgbEnabled = (configReg >> 28) & 1;\r
1958                         /*enc->busType = (configReg >> 20) & 15;\r
1959                         enc->synthesisLanguage = (configReg >> 16) & 15;\r
1960                         enc->busWidth = (configReg >> 12) & 15;*/\r
1961                         enc->reg_size = pservice->reg_size;\r
1962                         enc->reserv[0] = enc->reserv[1] = 0;\r
1963                 }\r
1964 \r
1965                 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1966                 if (pservice->auto_freq) {\r
1967                         pr_info("vpu_service set to auto frequency mode\n");\r
1968                         atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1969                 }\r
1970 \r
1971                 pservice->bug_dec_addr = cpu_is_rk30xx();\r
1972         } else {\r
1973                 /* disable frequency switch in hevc.*/\r
1974                 pservice->auto_freq = false;\r
1975         }\r
1976 }\r
1977 \r
1978 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1979 {\r
1980         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1981         vpu_device *dev = &pservice->dec_dev;\r
1982         u32 raw_status;\r
1983         u32 irq_status;\r
1984 \r
1985         vcodec_select_mode(pservice->dev_id);\r
1986 \r
1987         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1988 \r
1989         pr_debug("dec_irq\n");\r
1990 \r
1991         if (irq_status & DEC_INTERRUPT_BIT) {\r
1992                 pr_debug("dec_isr dec %x\n", irq_status);\r
1993                 if ((irq_status & 0x40001) == 0x40001)\r
1994                 {\r
1995                         do {\r
1996                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1997                         } while ((irq_status & 0x40001) == 0x40001);\r
1998                 }\r
1999 \r
2000                 /* clear dec IRQ */\r
2001                 if (pservice->hw_info->hw_id != HEVC_ID)\r
2002                         writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2003                 else\r
2004                         writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
2005                 atomic_add(1, &dev->irq_count_codec);\r
2006         }\r
2007 \r
2008         if (pservice->hw_info->hw_id != HEVC_ID) {\r
2009                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
2010                 if (irq_status & PP_INTERRUPT_BIT) {\r
2011                         pr_debug("vdpu_isr pp  %x\n", irq_status);\r
2012                         /* clear pp IRQ */\r
2013                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
2014                         atomic_add(1, &dev->irq_count_pp);\r
2015                 }\r
2016         }\r
2017 \r
2018         pservice->irq_status = raw_status;\r
2019 \r
2020         return IRQ_WAKE_THREAD;\r
2021 }\r
2022 \r
2023 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
2024 {\r
2025         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2026         vpu_device *dev = &pservice->dec_dev;\r
2027 \r
2028         mutex_lock(&pservice->lock);\r
2029         if (atomic_read(&dev->irq_count_codec)) {\r
2030 #if VPU_SERVICE_SHOW_TIME\r
2031                 do_gettimeofday(&dec_end);\r
2032                 pr_info("dec task: %ld ms\n",\r
2033                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
2034                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
2035 #endif\r
2036                 atomic_sub(1, &dev->irq_count_codec);\r
2037                 if (NULL == pservice->reg_codec) {\r
2038                         pr_err("error: dec isr with no task waiting\n");\r
2039                 } else {\r
2040                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2041                 }\r
2042         }\r
2043 \r
2044         if (atomic_read(&dev->irq_count_pp)) {\r
2045 \r
2046 #if VPU_SERVICE_SHOW_TIME\r
2047                 do_gettimeofday(&pp_end);\r
2048                 printk("pp  task: %ld ms\n",\r
2049                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
2050                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
2051 #endif\r
2052 \r
2053                 atomic_sub(1, &dev->irq_count_pp);\r
2054                 if (NULL == pservice->reg_pproc) {\r
2055                         pr_err("error: pp isr with no task waiting\n");\r
2056                 } else {\r
2057                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
2058                 }\r
2059         }\r
2060         try_set_reg(pservice);\r
2061         mutex_unlock(&pservice->lock);\r
2062         return IRQ_HANDLED;\r
2063 }\r
2064 \r
2065 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
2066 {\r
2067         struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2068         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2069         vpu_device *dev = &pservice->enc_dev;\r
2070         u32 irq_status;\r
2071 \r
2072         vcodec_select_mode(pservice->dev_id);\r
2073         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2074 \r
2075         pr_debug("vepu_irq irq status %x\n", irq_status);\r
2076 \r
2077 #if VPU_SERVICE_SHOW_TIME\r
2078         do_gettimeofday(&enc_end);\r
2079         pr_info("enc task: %ld ms\n",\r
2080                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
2081                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
2082 #endif\r
2083         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
2084                 /* clear enc IRQ */\r
2085                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2086                 atomic_add(1, &dev->irq_count_codec);\r
2087         }\r
2088 \r
2089         pservice->irq_status = irq_status;\r
2090 \r
2091         return IRQ_WAKE_THREAD;\r
2092 }\r
2093 \r
2094 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
2095 {\r
2096         struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2097         vpu_device *dev = &pservice->enc_dev;\r
2098 \r
2099         mutex_lock(&pservice->lock);\r
2100         if (atomic_read(&dev->irq_count_codec)) {\r
2101                 atomic_sub(1, &dev->irq_count_codec);\r
2102                 if (NULL == pservice->reg_codec) {\r
2103                         pr_err("error: enc isr with no task waiting\n");\r
2104                 } else {\r
2105                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2106                 }\r
2107         }\r
2108         try_set_reg(pservice);\r
2109         mutex_unlock(&pservice->lock);\r
2110         return IRQ_HANDLED;\r
2111 }\r
2112 \r
2113 static int __init vcodec_service_init(void)\r
2114 {\r
2115         int ret;\r
2116 \r
2117         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
2118                 pr_err("Platform device register failed (%d).\n", ret);\r
2119                 return ret;\r
2120         }\r
2121 \r
2122 #ifdef CONFIG_DEBUG_FS\r
2123         vcodec_debugfs_init();\r
2124 #endif\r
2125 \r
2126         return ret;\r
2127 }\r
2128 \r
2129 static void __exit vcodec_service_exit(void)\r
2130 {\r
2131 #ifdef CONFIG_DEBUG_FS\r
2132         vcodec_debugfs_exit();\r
2133 #endif\r
2134 \r
2135         platform_driver_unregister(&vcodec_driver);\r
2136 }\r
2137 \r
2138 module_init(vcodec_service_init);\r
2139 module_exit(vcodec_service_exit);\r
2140 \r
2141 #ifdef CONFIG_DEBUG_FS\r
2142 #include <linux/seq_file.h>\r
2143 \r
2144 static int vcodec_debugfs_init()\r
2145 {\r
2146         parent = debugfs_create_dir("vcodec", NULL);\r
2147         if (!parent)\r
2148                 return -1;\r
2149 \r
2150         return 0;\r
2151 }\r
2152 \r
2153 static void vcodec_debugfs_exit()\r
2154 {\r
2155         debugfs_remove(parent);\r
2156 }\r
2157 \r
2158 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2159 {\r
2160         return debugfs_create_dir(dirname, parent);\r
2161 }\r
2162 \r
2163 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2164 {\r
2165         struct vpu_service_info *pservice = s->private;\r
2166         unsigned int i, n;\r
2167         vpu_reg *reg, *reg_tmp;\r
2168         vpu_session *session, *session_tmp;\r
2169 \r
2170         mutex_lock(&pservice->lock);\r
2171         vpu_service_power_on(pservice);\r
2172         if (pservice->hw_info->hw_id != HEVC_ID) {\r
2173                 seq_printf(s, "\nENC Registers:\n");\r
2174                 n = pservice->enc_dev.iosize >> 2;\r
2175                 for (i = 0; i < n; i++) {\r
2176                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2177                 }\r
2178         }\r
2179         seq_printf(s, "\nDEC Registers:\n");\r
2180         n = pservice->dec_dev.iosize >> 2;\r
2181         for (i = 0; i < n; i++)\r
2182                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2183 \r
2184         seq_printf(s, "\nvpu service status:\n");\r
2185         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2186                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2187                 /*seq_printf(s, "waiting reg set %d\n");*/\r
2188                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2189                         seq_printf(s, "waiting register set\n");\r
2190                 }\r
2191                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2192                         seq_printf(s, "running register set\n");\r
2193                 }\r
2194                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2195                         seq_printf(s, "done    register set\n");\r
2196                 }\r
2197         }\r
2198         mutex_unlock(&pservice->lock);\r
2199 \r
2200         return 0;\r
2201 }\r
2202 \r
2203 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2204 {\r
2205         return single_open(file, debug_vcodec_show, inode->i_private);\r
2206 }\r
2207 \r
2208 #endif\r
2209 \r
2210 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2211 #include "hevc_test_inc/pps_00.h"\r
2212 #include "hevc_test_inc/register_00.h"\r
2213 #include "hevc_test_inc/rps_00.h"\r
2214 #include "hevc_test_inc/scaling_list_00.h"\r
2215 #include "hevc_test_inc/stream_00.h"\r
2216 \r
2217 #include "hevc_test_inc/pps_01.h"\r
2218 #include "hevc_test_inc/register_01.h"\r
2219 #include "hevc_test_inc/rps_01.h"\r
2220 #include "hevc_test_inc/scaling_list_01.h"\r
2221 #include "hevc_test_inc/stream_01.h"\r
2222 \r
2223 #include "hevc_test_inc/cabac.h"\r
2224 \r
2225 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2226 \r
2227 static struct ion_client *ion_client = NULL;\r
2228 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2229 {\r
2230         int size = (len+15) & (~15);\r
2231         struct ion_handle *handle;\r
2232         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2233 \r
2234         if (ion_client == NULL)\r
2235                 ion_client = rockchip_ion_client_create("vcodec");\r
2236 \r
2237         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2238 \r
2239         ptr = ion_map_kernel(ion_client, handle);\r
2240 \r
2241         ion_phys(ion_client, handle, phy, &size);\r
2242 \r
2243         memcpy(ptr, tbl, len);\r
2244 \r
2245         return ptr;\r
2246 }\r
2247 \r
2248 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2249 {\r
2250         int size = (len+15) & (~15);\r
2251         struct ion_handle *handle;\r
2252         u8 *ptr;\r
2253 \r
2254         if (ion_client == NULL)\r
2255                 ion_client = rockchip_ion_client_create("vcodec");\r
2256 \r
2257         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2258 \r
2259         ptr = ion_map_kernel(ion_client, handle);\r
2260 \r
2261         ion_phys(ion_client, handle, phy, &size);\r
2262 \r
2263         return ptr;\r
2264 }\r
2265 \r
2266 #define TEST_CNT    2\r
2267 static int hevc_test_case0(vpu_service_info *pservice)\r
2268 {\r
2269         vpu_session session;\r
2270         vpu_reg *reg; \r
2271         unsigned long size = 272;//sizeof(register_00); // registers array length\r
2272         int testidx = 0;\r
2273         int ret = 0;\r
2274 \r
2275         u8 *pps_tbl[TEST_CNT];\r
2276         u8 *register_tbl[TEST_CNT];\r
2277         u8 *rps_tbl[TEST_CNT];\r
2278         u8 *scaling_list_tbl[TEST_CNT];\r
2279         u8 *stream_tbl[TEST_CNT];\r
2280 \r
2281         int stream_size[2];\r
2282         int pps_size[2];\r
2283         int rps_size[2];\r
2284         int scl_size[2];\r
2285         int cabac_size[2];\r
2286         \r
2287         u32 phy_pps;\r
2288         u32 phy_rps;\r
2289         u32 phy_scl;\r
2290         u32 phy_str;\r
2291         u32 phy_yuv;\r
2292         u32 phy_ref;\r
2293         u32 phy_cabac;\r
2294 \r
2295         volatile u8 *stream_buf;\r
2296         volatile u8 *pps_buf;\r
2297         volatile u8 *rps_buf;\r
2298         volatile u8 *scl_buf;\r
2299         volatile u8 *yuv_buf;\r
2300         volatile u8 *cabac_buf;\r
2301         volatile u8 *ref_buf;\r
2302 \r
2303         u8 *pps;\r
2304         u8 *yuv[2];\r
2305         int i;\r
2306 \r
2307         pps_tbl[0] = pps_00;\r
2308         pps_tbl[1] = pps_01;\r
2309 \r
2310         register_tbl[0] = register_00;\r
2311         register_tbl[1] = register_01;\r
2312 \r
2313         rps_tbl[0] = rps_00;\r
2314         rps_tbl[1] = rps_01;\r
2315 \r
2316         scaling_list_tbl[0] = scaling_list_00;\r
2317         scaling_list_tbl[1] = scaling_list_01;\r
2318 \r
2319         stream_tbl[0] = stream_00;\r
2320         stream_tbl[1] = stream_01;\r
2321 \r
2322         stream_size[0] = sizeof(stream_00);\r
2323         stream_size[1] = sizeof(stream_01);\r
2324 \r
2325         pps_size[0] = sizeof(pps_00);\r
2326         pps_size[1] = sizeof(pps_01);\r
2327 \r
2328         rps_size[0] = sizeof(rps_00);\r
2329         rps_size[1] = sizeof(rps_01);\r
2330 \r
2331         scl_size[0] = sizeof(scaling_list_00);\r
2332         scl_size[1] = sizeof(scaling_list_01);\r
2333         \r
2334         cabac_size[0] = sizeof(Cabac_table);\r
2335         cabac_size[1] = sizeof(Cabac_table);\r
2336 \r
2337         /* create session */\r
2338         session.pid = current->pid;\r
2339         session.type = VPU_DEC;\r
2340         INIT_LIST_HEAD(&session.waiting);\r
2341         INIT_LIST_HEAD(&session.running);\r
2342         INIT_LIST_HEAD(&session.done);\r
2343         INIT_LIST_HEAD(&session.list_session);\r
2344         init_waitqueue_head(&session.wait);\r
2345         atomic_set(&session.task_running, 0);\r
2346         list_add_tail(&session.list_session, &pservice->session);\r
2347 \r
2348         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2349         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2350 \r
2351         while (testidx < TEST_CNT) {\r
2352                 /* create registers */\r
2353                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2354                 if (NULL == reg) {\r
2355                         pr_err("error: kmalloc fail in reg_init\n");\r
2356                         return -1;\r
2357                 }\r
2358 \r
2359                 if (size > pservice->reg_size) {\r
2360                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2361                         size = pservice->reg_size;\r
2362                 }\r
2363                 reg->session = &session;\r
2364                 reg->type = session.type;\r
2365                 reg->size = size;\r
2366                 reg->freq = VPU_FREQ_DEFAULT;\r
2367                 reg->reg = (unsigned long *)&reg[1];\r
2368                 INIT_LIST_HEAD(&reg->session_link);\r
2369                 INIT_LIST_HEAD(&reg->status_link);\r
2370 \r
2371                 /* TODO: stuff registers */\r
2372                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2373 \r
2374                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2375                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2376                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2377                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2378                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2379 \r
2380                 pps = pps_buf;\r
2381 \r
2382                 /* TODO: replace reigster address */\r
2383                 for (i=0; i<64; i++) {\r
2384                         u32 scaling_offset;\r
2385                         u32 tmp;\r
2386 \r
2387                         scaling_offset = (u32)pps[i*80+74];\r
2388                         scaling_offset += (u32)pps[i*80+75] << 8;\r
2389                         scaling_offset += (u32)pps[i*80+76] << 16;\r
2390                         scaling_offset += (u32)pps[i*80+77] << 24;\r
2391 \r
2392                         tmp = phy_scl + scaling_offset;\r
2393 \r
2394                         pps[i*80+74] = tmp & 0xff;\r
2395                         pps[i*80+75] = (tmp >> 8) & 0xff;\r
2396                         pps[i*80+76] = (tmp >> 16) & 0xff;\r
2397                         pps[i*80+77] = (tmp >> 24) & 0xff;\r
2398                 }\r
2399 \r
2400                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",\r
2401                         __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2402 \r
2403                 reg->reg[1] = 0x21;\r
2404                 reg->reg[4] = phy_str;\r
2405                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2406                 reg->reg[6] = phy_cabac;\r
2407                 reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2408                 reg->reg[42] = phy_pps;\r
2409                 reg->reg[43] = phy_rps;\r
2410                 for (i = 10; i <= 24; i++)\r
2411                         reg->reg[i] = phy_yuv;\r
2412 \r
2413                 mutex_lock(&pservice->lock);\r
2414                 list_add_tail(&reg->status_link, &pservice->waiting);\r
2415                 list_add_tail(&reg->session_link, &session.waiting);\r
2416                 mutex_unlock(&pservice->lock);\r
2417 \r
2418                 printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2419 \r
2420                 /* stuff hardware */\r
2421                 try_set_reg(pservice);\r
2422 \r
2423                 /* wait for result */\r
2424                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2425                 if (!list_empty(&session.done)) {\r
2426                         if (ret < 0)\r
2427                                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2428                         ret = 0;\r
2429                 } else {\r
2430                         if (unlikely(ret < 0)) {\r
2431                                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2432                         } else if (0 == ret) {\r
2433                                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2434                                 ret = -ETIMEDOUT;\r
2435                         }\r
2436                 }\r
2437                 if (ret < 0) {\r
2438                         int task_running = atomic_read(&session.task_running);\r
2439                         int n;\r
2440                         mutex_lock(&pservice->lock);\r
2441                         vpu_service_dump(pservice);\r
2442                         if (task_running) {\r
2443                                 atomic_set(&session.task_running, 0);\r
2444                                 atomic_sub(task_running, &pservice->total_running);\r
2445                                 printk("%d task is running but not return, reset hardware...", task_running);\r
2446                                 vpu_reset(pservice);\r
2447                                 printk("done\n");\r
2448                         }\r
2449                         vpu_service_session_clear(pservice, &session);\r
2450                         mutex_unlock(&pservice->lock);\r
2451 \r
2452                         printk("\nDEC Registers:\n");\r
2453                         n = pservice->dec_dev.iosize >> 2;\r
2454                         for (i=0; i<n; i++)\r
2455                                 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2456 \r
2457                         pr_err("test index %d failed\n", testidx);\r
2458                         break;\r
2459                 } else {\r
2460                         pr_info("test index %d success\n", testidx);\r
2461 \r
2462                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2463 \r
2464                         for (i=0; i<68; i++) {\r
2465                                 if (i % 4 == 0)\r
2466                                         printk("%02d: ", i);\r
2467                                 printk("%08x ", reg->reg[i]);\r
2468                                 if ((i+1) % 4 == 0)\r
2469                                         printk("\n");\r
2470                         }\r
2471 \r
2472                         testidx++;\r
2473                 }\r
2474 \r
2475                 reg_deinit(pservice, reg);\r
2476         }\r
2477 \r
2478         return 0;\r
2479 }\r
2480 \r
2481 #endif\r
2482 \r