arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
  47 #define CONFIG_VCODEC_MMU\r
  48 #endif\r
  49 \r
  50 #ifdef CONFIG_VCODEC_MMU\r
  51 #include <linux/rockchip/iovmm.h>\r
  52 #include <linux/rockchip/sysmmu.h>\r
  53 #include <linux/dma-buf.h>\r
  54 #endif\r
  55 \r
  56 #ifdef CONFIG_DEBUG_FS\r
  57 #include <linux/debugfs.h>\r
  58 #endif\r
  59 \r
  60 #if defined(CONFIG_ARCH_RK319X)\r
  61 #include <mach/grf.h>\r
  62 #endif\r
  63 \r
  64 #include "vcodec_service.h"\r
  65 \r
  66 #define HEVC_TEST_ENABLE    0\r
  67 #define HEVC_SIM_ENABLE     0\r
  68 #define VCODEC_CLOCK_ENABLE 1\r
  69 \r
  70 typedef enum {\r
  71         VPU_DEC_ID_9190         = 0x6731,\r
  72         VPU_ID_8270             = 0x8270,\r
  73         VPU_ID_4831             = 0x4831,\r
  74     HEVC_ID         = 0x6867,\r
  75 } VPU_HW_ID;\r
  76 \r
  77 typedef enum {\r
  78         VPU_DEC_TYPE_9190       = 0,\r
  79         VPU_ENC_TYPE_8270       = 0x100,\r
  80         VPU_ENC_TYPE_4831       ,\r
  81 } VPU_HW_TYPE_E;\r
  82 \r
  83 typedef enum VPU_FREQ {\r
  84         VPU_FREQ_200M,\r
  85         VPU_FREQ_266M,\r
  86         VPU_FREQ_300M,\r
  87         VPU_FREQ_400M,\r
  88     VPU_FREQ_500M,\r
  89     VPU_FREQ_600M,\r
  90         VPU_FREQ_DEFAULT,\r
  91         VPU_FREQ_BUT,\r
  92 } VPU_FREQ;\r
  93 \r
  94 typedef struct {\r
  95         VPU_HW_ID               hw_id;\r
  96         unsigned long           hw_addr;\r
  97         unsigned long           enc_offset;\r
  98         unsigned long           enc_reg_num;\r
  99         unsigned long           enc_io_size;\r
 100         unsigned long           dec_offset;\r
 101         unsigned long           dec_reg_num;\r
 102         unsigned long           dec_io_size;\r
 103 } VPU_HW_INFO_E;\r
 104 \r
 105 #define VPU_SERVICE_SHOW_TIME                   0\r
 106 \r
 107 #if VPU_SERVICE_SHOW_TIME\r
 108 static struct timeval enc_start, enc_end;\r
 109 static struct timeval dec_start, dec_end;\r
 110 static struct timeval pp_start,  pp_end;\r
 111 #endif\r
 112 \r
 113 #define MHZ                                     (1000*1000)\r
 114 \r
 115 #define REG_NUM_9190_DEC                        (60)\r
 116 #define REG_NUM_9190_PP                         (41)\r
 117 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 120 \r
 121 #define REG_NUM_ENC_8270                        (96)\r
 122 #define REG_SIZE_ENC_8270                       (0x200)\r
 123 #define REG_NUM_ENC_4831                        (164)\r
 124 #define REG_SIZE_ENC_4831                       (0x400)\r
 125 \r
 126 #define REG_NUM_HEVC_DEC            (68)\r
 127 \r
 128 #define SIZE_REG(reg)                           ((reg)*4)\r
 129 \r
 130 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 131         [0] = {\r
 132                 .hw_id          = VPU_ID_8270,\r
 133                 .hw_addr        = 0,\r
 134                 .enc_offset     = 0x0,\r
 135                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 136                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 137                 .dec_offset     = REG_SIZE_ENC_8270,\r
 138                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 139                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 140         },\r
 141         [1] = {\r
 142                 .hw_id          = VPU_ID_4831,\r
 143                 .hw_addr        = 0,\r
 144                 .enc_offset     = 0x0,\r
 145                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 146                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 147                 .dec_offset     = REG_SIZE_ENC_4831,\r
 148                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 149                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 150         },\r
 151     [2] = {\r
 152         .hw_id      = HEVC_ID,\r
 153         .hw_addr    = 0,\r
 154         .dec_offset = 0x0,\r
 155         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 156         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 157     },\r
 158 };\r
 159 \r
 160 \r
 161 #define DEC_INTERRUPT_REGISTER                  1\r
 162 #define PP_INTERRUPT_REGISTER                   60\r
 163 #define ENC_INTERRUPT_REGISTER                  1\r
 164 \r
 165 #define DEC_INTERRUPT_BIT                       0x100\r
 166 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 167 #define PP_INTERRUPT_BIT                        0x100\r
 168 #define ENC_INTERRUPT_BIT                       0x1\r
 169 \r
 170 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 171 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 172 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 173 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 174 \r
 175 #define VPU_REG_EN_ENC                          14\r
 176 #define VPU_REG_ENC_GATE                        2\r
 177 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 178 \r
 179 #define VPU_REG_EN_DEC                          1\r
 180 #define VPU_REG_DEC_GATE                        2\r
 181 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 182 #define VPU_REG_EN_PP                           0\r
 183 #define VPU_REG_PP_GATE                         1\r
 184 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 185 #define VPU_REG_EN_DEC_PP                       1\r
 186 #define VPU_REG_DEC_PP_GATE                     61\r
 187 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 188 \r
 189 #if defined(CONFIG_VCODEC_MMU)\r
 190 static u8 addr_tbl_vpu_h264dec[] = {\r
 191         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 192 };\r
 193 \r
 194 static u8 addr_tbl_vpu_vp8dec[] = {\r
 195         10,12,13, 14, 18, 19, 27, 40\r
 196 };\r
 197 \r
 198 static u8 addr_tbl_vpu_vp6dec[] = {\r
 199         12, 13, 14, 18, 27, 40\r
 200 };\r
 201 \r
 202 static u8 addr_tbl_vpu_vc1dec[] = {\r
 203         12, 13, 14, 15, 16, 17, 27, 41\r
 204 };\r
 205 \r
 206 static u8 addr_tbl_vpu_jpegdec[] = {\r
 207         12, 40, 66, 67\r
 208 };\r
 209 \r
 210 static u8 addr_tbl_vpu_defaultdec[] = {\r
 211         12, 13, 14, 15, 16, 17, 40, 41\r
 212 };\r
 213 \r
 214 static u8 addr_tbl_vpu_enc[] = {\r
 215         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 216 };\r
 217 \r
 218 static u8 addr_tbl_hevc_dec[] = {\r
 219         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 220 };\r
 221 #endif\r
 222 \r
 223 enum VPU_DEC_FMT {\r
 224         VPU_DEC_FMT_H264,\r
 225         VPU_DEC_FMT_MPEG4,\r
 226         VPU_DEC_FMT_H263,\r
 227         VPU_DEC_FMT_JPEG,\r
 228         VPU_DEC_FMT_VC1,\r
 229         VPU_DEC_FMT_MPEG2,\r
 230         VPU_DEC_FMT_MPEG1,\r
 231         VPU_DEC_FMT_VP6,\r
 232         VPU_DEC_FMT_RV,\r
 233         VPU_DEC_FMT_VP7,\r
 234         VPU_DEC_FMT_VP8,\r
 235         VPU_DEC_FMT_AVS,\r
 236         VPU_DEC_FMT_SVC,\r
 237         VPU_DEC_FMT_VC2,\r
 238         VPU_DEC_FMT_MVC,\r
 239         VPU_DEC_FMT_THEORA,\r
 240         VPU_DEC_FMT_RES\r
 241 };\r
 242 \r
 243 /**\r
 244  * struct for process session which connect to vpu\r
 245  *\r
 246  * @author ChenHengming (2011-5-3)\r
 247  */\r
 248 typedef struct vpu_session {\r
 249         VPU_CLIENT_TYPE         type;\r
 250         /* a linked list of data so we can access them for debugging */\r
 251         struct list_head        list_session;\r
 252         /* a linked list of register data waiting for process */\r
 253         struct list_head        waiting;\r
 254         /* a linked list of register data in processing */\r
 255         struct list_head        running;\r
 256         /* a linked list of register data processed */\r
 257         struct list_head        done;\r
 258         wait_queue_head_t       wait;\r
 259         pid_t                   pid;\r
 260         atomic_t                task_running;\r
 261 } vpu_session;\r
 262 \r
 263 /**\r
 264  * struct for process register set\r
 265  *\r
 266  * @author ChenHengming (2011-5-4)\r
 267  */\r
 268 typedef struct vpu_reg {\r
 269         VPU_CLIENT_TYPE         type;\r
 270         VPU_FREQ                    freq;\r
 271         vpu_session             *session;\r
 272         struct list_head        session_link;           /* link to vpu service session */\r
 273         struct list_head        status_link;            /* link to register set list */\r
 274         unsigned long           size;\r
 275 #if defined(CONFIG_VCODEC_MMU)\r
 276         struct list_head        mem_region_list;\r
 277 #endif\r
 278         unsigned long           *reg;\r
 279 } vpu_reg;\r
 280 \r
 281 typedef struct vpu_device {\r
 282         atomic_t                irq_count_codec;\r
 283         atomic_t                irq_count_pp;\r
 284         unsigned long           iobaseaddr;\r
 285         unsigned int            iosize;\r
 286         volatile u32            *hwregs;\r
 287 } vpu_device;\r
 288 \r
 289 enum vcodec_device_id {\r
 290         VCODEC_DEVICE_ID_VPU,\r
 291         VCODEC_DEVICE_ID_HEVC\r
 292 };\r
 293 \r
 294 struct vcodec_mem_region {\r
 295     struct list_head srv_lnk;\r
 296     struct list_head reg_lnk;\r
 297     struct list_head session_lnk;\r
 298     unsigned long iova;              /* virtual address for iommu */\r
 299     unsigned long len;\r
 300     struct ion_handle *hdl;\r
 301 };\r
 302 \r
 303 typedef struct vpu_service_info {\r
 304         struct wake_lock        wake_lock;\r
 305         struct delayed_work     power_off_work;\r
 306         struct mutex            lock;\r
 307         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 308         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 309         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 310         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 311         atomic_t                total_running;\r
 312         bool                    enabled;\r
 313         vpu_reg                 *reg_codec;\r
 314         vpu_reg                 *reg_pproc;\r
 315         vpu_reg                 *reg_resev;\r
 316         VPUHwDecConfig_t        dec_config;\r
 317         VPUHwEncConfig_t        enc_config;\r
 318         VPU_HW_INFO_E           *hw_info;\r
 319         unsigned long           reg_size;\r
 320         bool                    auto_freq;\r
 321         bool                    bug_dec_addr;\r
 322         atomic_t                freq_status;\r
 323 \r
 324     struct clk *aclk_vcodec;\r
 325     struct clk *hclk_vcodec;\r
 326     struct clk *clk_core;\r
 327     struct clk *clk_cabac;\r
 328     struct clk *pd_video;\r
 329 \r
 330     int irq_dec;\r
 331     int irq_enc;\r
 332 \r
 333     vpu_device enc_dev;\r
 334     vpu_device dec_dev;\r
 335 \r
 336     struct device   *dev;\r
 337 \r
 338     struct cdev     cdev;\r
 339     dev_t           dev_t;\r
 340     struct class    *cls;\r
 341     struct device   *child_dev;\r
 342 \r
 343     struct dentry   *debugfs_dir;\r
 344     struct dentry   *debugfs_file_regs;\r
 345 \r
 346     u32 irq_status;\r
 347 #if defined(CONFIG_VCODEC_MMU)  \r
 348         struct ion_client * ion_client;\r
 349     struct list_head mem_region_list;\r
 350     struct device *mmu_dev;\r
 351 #endif\r
 352 \r
 353         enum vcodec_device_id dev_id;\r
 354 \r
 355     struct delayed_work simulate_work;\r
 356 } vpu_service_info;\r
 357 \r
 358 typedef struct vpu_request\r
 359 {\r
 360         unsigned long   *req;\r
 361         unsigned long   size;\r
 362 } vpu_request;\r
 363 \r
 364 /// global variable\r
 365 //static struct clk *pd_video;\r
 366 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 367 \r
 368 #ifdef CONFIG_DEBUG_FS\r
 369 static int vcodec_debugfs_init(void);\r
 370 static void vcodec_debugfs_exit(void);\r
 371 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 372 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 373 \r
 374 static const struct file_operations debug_vcodec_fops = {\r
 375     .open = debug_vcodec_open,\r
 376     .read = seq_read,\r
 377     .llseek = seq_lseek,\r
 378     .release = single_release,\r
 379 };\r
 380 #endif\r
 381 \r
 382 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 383 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 384 \r
 385 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 386 \r
 387 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 388 {\r
 389 #if VCODEC_CLOCK_ENABLE\r
 390     do {\r
 391         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 392         if (IS_ERR(pservice->aclk_vcodec)) {\r
 393             dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 394             break;\r
 395         }\r
 396     \r
 397         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 398         if (IS_ERR(pservice->hclk_vcodec)) {\r
 399             dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 400             break;\r
 401         }\r
 402     \r
 403         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 404             pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 405             if (IS_ERR(pservice->clk_core)) {\r
 406                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 407                 break;\r
 408             }\r
 409     \r
 410             pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 411             if (IS_ERR(pservice->clk_cabac)) {\r
 412                 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 413                 break;\r
 414             }\r
 415             \r
 416             pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 417             if (IS_ERR(pservice->pd_video)) {\r
 418                 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 419                 break;\r
 420             }\r
 421         } else {\r
 422             pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 423             if (IS_ERR(pservice->pd_video)) {\r
 424                 dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 425                 break;\r
 426             }\r
 427         }\r
 428         \r
 429         return 0;\r
 430     } while (0);\r
 431     \r
 432     return -1;\r
 433 #endif\r
 434 }\r
 435 \r
 436 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 437 {\r
 438 #if VCODEC_CLOCK_ENABLE\r
 439     if (pservice->pd_video) {\r
 440         devm_clk_put(pservice->dev, pservice->pd_video);\r
 441     }\r
 442 \r
 443     if (pservice->aclk_vcodec) {\r
 444         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 445     }\r
 446 \r
 447     if (pservice->hclk_vcodec) {\r
 448         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 449     }\r
 450 \r
 451     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 452         if (pservice->clk_core) {\r
 453             devm_clk_put(pservice->dev, pservice->clk_core);\r
 454         }\r
 455         \r
 456         if (pservice->clk_cabac) {\r
 457             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 458         }\r
 459     }\r
 460 #endif\r
 461 }\r
 462 \r
 463 static void vpu_reset(struct vpu_service_info *pservice)\r
 464 {\r
 465 #if defined(CONFIG_ARCH_RK29)\r
 466         clk_disable(aclk_ddr_vepu);\r
 467         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 468         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 469         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 470         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 471         mdelay(10);\r
 472         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 473         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 474         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 475         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 476         clk_enable(aclk_ddr_vepu);\r
 477 #elif defined(CONFIG_ARCH_RK30)\r
 478         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 479         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 480         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 481         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 482         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 483         mdelay(1);\r
 484         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 485         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 486         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 487         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 488         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 489 #endif\r
 490         pservice->reg_codec = NULL;\r
 491         pservice->reg_pproc = NULL;\r
 492         pservice->reg_resev = NULL;\r
 493 }\r
 494 \r
 495 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 496 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 497 {\r
 498         vpu_reg *reg, *n;\r
 499         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 500                 reg_deinit(pservice, reg);\r
 501         }\r
 502         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 503                 reg_deinit(pservice, reg);\r
 504         }\r
 505         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 506                 reg_deinit(pservice, reg);\r
 507         }\r
 508 }\r
 509 \r
 510 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 511 {\r
 512         int running;\r
 513         vpu_reg *reg, *reg_tmp;\r
 514         vpu_session *session, *session_tmp;\r
 515 \r
 516         running = atomic_read(&pservice->total_running);\r
 517         printk("total_running %d\n", running);\r
 518 \r
 519         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 520         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 521         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 522 \r
 523         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 524                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 525                 running = atomic_read(&session->task_running);\r
 526                 printk("task_running %d\n", running);\r
 527                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 528                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 529                 }\r
 530                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 531                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 532                 }\r
 533                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 534                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 535                 }\r
 536         }\r
 537 }\r
 538 \r
 539 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 540 {\r
 541     int total_running;\r
 542     if (!pservice->enabled) {\r
 543         return;\r
 544     }\r
 545 \r
 546     pservice->enabled = false;\r
 547     total_running = atomic_read(&pservice->total_running);\r
 548     if (total_running) {\r
 549         pr_alert("alert: power off when %d task running!!\n", total_running);\r
 550         mdelay(50);\r
 551         pr_alert("alert: delay 50 ms for running task\n");\r
 552         vpu_service_dump(pservice);\r
 553     }\r
 554     \r
 555 #if defined(CONFIG_VCODEC_MMU)\r
 556     if (pservice->mmu_dev) {\r
 557         iovmm_deactivate(pservice->dev);\r
 558     }\r
 559 #endif \r
 560 \r
 561     printk("%s: power off...", dev_name(pservice->dev));\r
 562     udelay(10);\r
 563 #if VCODEC_CLOCK_ENABLE\r
 564     clk_disable_unprepare(pservice->pd_video);\r
 565     clk_disable_unprepare(pservice->hclk_vcodec);\r
 566     clk_disable_unprepare(pservice->aclk_vcodec);\r
 567     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 568         clk_disable_unprepare(pservice->clk_core);\r
 569         clk_disable_unprepare(pservice->clk_cabac);\r
 570     }\r
 571 #endif\r
 572     wake_unlock(&pservice->wake_lock);\r
 573     printk("done\n");\r
 574 }\r
 575 \r
 576 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 577 {\r
 578         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 579 }\r
 580 \r
 581 static void vpu_power_off_work(struct work_struct *work_s)\r
 582 {\r
 583     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 584     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 585 \r
 586         if (mutex_trylock(&pservice->lock)) {\r
 587                 vpu_service_power_off(pservice);\r
 588                 mutex_unlock(&pservice->lock);\r
 589         } else {\r
 590                 /* Come back later if the device is busy... */\r
 591                 vpu_queue_power_off_work(pservice);\r
 592         }\r
 593 }\r
 594 \r
 595 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 596 {\r
 597     static ktime_t last;\r
 598     ktime_t now = ktime_get();\r
 599     if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 600         cancel_delayed_work_sync(&pservice->power_off_work);\r
 601         vpu_queue_power_off_work(pservice);\r
 602         last = now;\r
 603     }\r
 604     if (pservice->enabled)\r
 605         return ;\r
 606 \r
 607     pservice->enabled = true;\r
 608     printk("%s: power on\n", dev_name(pservice->dev));\r
 609 \r
 610 #if VCODEC_CLOCK_ENABLE\r
 611     clk_prepare_enable(pservice->aclk_vcodec);\r
 612     clk_prepare_enable(pservice->hclk_vcodec);\r
 613 \r
 614     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 615         clk_prepare_enable(pservice->clk_core);\r
 616         clk_prepare_enable(pservice->clk_cabac);\r
 617     }\r
 618     \r
 619     clk_prepare_enable(pservice->pd_video);\r
 620 #endif\r
 621 \r
 622 #if defined(CONFIG_ARCH_RK319X)\r
 623     /// select aclk_vepu as vcodec clock source. \r
 624     #define BIT_VCODEC_SEL  (1<<7)\r
 625     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 626 #endif\r
 627     \r
 628     udelay(10);\r
 629     wake_lock(&pservice->wake_lock);\r
 630     \r
 631 #if defined(CONFIG_VCODEC_MMU)    \r
 632     if (pservice->mmu_dev) {\r
 633         iovmm_activate(pservice->dev);\r
 634     }\r
 635 #endif    \r
 636 }\r
 637 \r
 638 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 639 {\r
 640         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 641         return ((type == 8) || (type == 4));\r
 642 }\r
 643 \r
 644 static inline bool reg_check_interlace(vpu_reg *reg)\r
 645 {\r
 646         unsigned long type = (reg->reg[3] & (1 << 23));\r
 647         return (type > 0);\r
 648 }\r
 649 \r
 650 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
 651 {\r
 652         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
 653         return type;\r
 654 }\r
 655 \r
 656 static inline int reg_probe_width(vpu_reg *reg)\r
 657 {\r
 658     int width_in_mb = reg->reg[4] >> 23;\r
 659     \r
 660     return width_in_mb * 16;\r
 661 }\r
 662 \r
 663 #if defined(CONFIG_VCODEC_MMU)\r
 664 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 665 {\r
 666         int i;\r
 667         int usr_fd = 0;\r
 668         int offset = 0;\r
 669 \r
 670         if (tbl == NULL || size <= 0) {\r
 671                 dev_err(pservice->dev, "input arguments invalidate\n");\r
 672                 return -1;\r
 673         }\r
 674 \r
 675         vpu_service_power_on(pservice);\r
 676 \r
 677         for (i = 0; i < size; i++) {\r
 678                 usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 679 \r
 680                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID && (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {\r
 681                         /* special for vpu dec num 41 regitster */\r
 682                         offset = reg->reg[tbl[i]] >> 10 << 4;\r
 683                 } else {\r
 684                         offset = reg->reg[tbl[i]] >> 10;\r
 685                 }\r
 686 \r
 687                 if (usr_fd != 0) {\r
 688                         struct ion_handle *hdl;\r
 689                         int ret;\r
 690                         struct vcodec_mem_region *mem_region;\r
 691 \r
 692                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 693                         if (IS_ERR(hdl)) {\r
 694                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 695                                 return PTR_ERR(hdl);\r
 696                         }\r
 697 \r
 698                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 699 \r
 700                         if (mem_region == NULL) {\r
 701                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 702                                 ion_free(pservice->ion_client, hdl);\r
 703                                 return -1;\r
 704                         }\r
 705 \r
 706                         mem_region->hdl = hdl;\r
 707 \r
 708                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 709                         if (ret < 0) {\r
 710                                 dev_err(pservice->dev, "ion map iommu failed\n");\r
 711                                 kfree(mem_region);\r
 712                                 ion_free(pservice->ion_client, hdl);\r
 713                                 return ret;\r
 714                         }\r
 715                         reg->reg[tbl[i]] = mem_region->iova + offset;\r
 716                         INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 717                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 718                 }\r
 719         }\r
 720         return 0;\r
 721 }\r
 722 \r
 723 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 724 {\r
 725         VPU_HW_ID hw_id;\r
 726         u8 *tbl;\r
 727         int size = 0;\r
 728 \r
 729         hw_id = pservice->hw_info->hw_id;\r
 730 \r
 731         if (hw_id == HEVC_ID) {\r
 732                 tbl = addr_tbl_hevc_dec;\r
 733                 size = sizeof(addr_tbl_hevc_dec);\r
 734         } else {\r
 735                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 736                         switch (reg_check_fmt(reg)) {\r
 737                         case VPU_DEC_FMT_H264:\r
 738                                 {\r
 739                                         tbl = addr_tbl_vpu_h264dec;\r
 740                                         size = sizeof(addr_tbl_vpu_h264dec);\r
 741                                         break;\r
 742                                 }\r
 743                         case VPU_DEC_FMT_VP8:\r
 744                         case VPU_DEC_FMT_VP7:\r
 745                                 {\r
 746                                         tbl = addr_tbl_vpu_vp8dec;\r
 747                                         size = sizeof(addr_tbl_vpu_vp8dec);\r
 748                                         break;\r
 749                                 }\r
 750 \r
 751                         case VPU_DEC_FMT_VP6:\r
 752                                 {\r
 753                                         tbl = addr_tbl_vpu_vp6dec;\r
 754                                         size = sizeof(addr_tbl_vpu_vp6dec);\r
 755                                         break;\r
 756                                 }\r
 757                         case VPU_DEC_FMT_VC1:\r
 758                                 {\r
 759                                         tbl = addr_tbl_vpu_vc1dec;\r
 760                                         size = sizeof(addr_tbl_vpu_vc1dec);\r
 761                                         break;\r
 762                                 }\r
 763 \r
 764                         case VPU_DEC_FMT_JPEG:\r
 765                                 {\r
 766                                         tbl = addr_tbl_vpu_jpegdec;\r
 767                                         size = sizeof(addr_tbl_vpu_jpegdec);\r
 768                                         break;\r
 769                                 }\r
 770                         default:\r
 771                                 tbl = addr_tbl_vpu_defaultdec;\r
 772                                 size = sizeof(addr_tbl_vpu_defaultdec);\r
 773                                 break;\r
 774                         }\r
 775                 } else if (reg->type == VPU_ENC) {\r
 776                         tbl = addr_tbl_vpu_enc;\r
 777                         size = sizeof(addr_tbl_vpu_enc);\r
 778                 }\r
 779         }\r
 780 \r
 781         if (size != 0) {\r
 782                 return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 783         } else {\r
 784                 return -1;\r
 785         }\r
 786 }\r
 787 #endif\r
 788 \r
 789 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 790 {\r
 791         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 792         if (NULL == reg) {\r
 793                 pr_err("error: kmalloc fail in reg_init\n");\r
 794                 return NULL;\r
 795         }\r
 796 \r
 797         if (size > pservice->reg_size) {\r
 798                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 799                 size = pservice->reg_size;\r
 800         }\r
 801         reg->session = session;\r
 802         reg->type = session->type;\r
 803         reg->size = size;\r
 804         reg->freq = VPU_FREQ_DEFAULT;\r
 805         reg->reg = (unsigned long *)&reg[1];\r
 806         INIT_LIST_HEAD(&reg->session_link);\r
 807         INIT_LIST_HEAD(&reg->status_link);\r
 808 \r
 809 #if defined(CONFIG_VCODEC_MMU)  \r
 810         if (pservice->mmu_dev) {\r
 811             INIT_LIST_HEAD(&reg->mem_region_list);\r
 812         }\r
 813 #endif\r
 814 \r
 815         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 816                 pr_err("error: copy_from_user failed in reg_init\n");\r
 817                 kfree(reg);\r
 818                 return NULL;\r
 819         }\r
 820 \r
 821 #if defined(CONFIG_VCODEC_MMU)\r
 822         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg)) {\r
 823                 pr_err("error: translate reg address failed\n");\r
 824                 kfree(reg);\r
 825                 return NULL;\r
 826         }\r
 827 #endif\r
 828 \r
 829         mutex_lock(&pservice->lock);\r
 830         list_add_tail(&reg->status_link, &pservice->waiting);\r
 831         list_add_tail(&reg->session_link, &session->waiting);\r
 832         mutex_unlock(&pservice->lock);\r
 833 \r
 834         if (pservice->auto_freq) {\r
 835                 if (!soc_is_rk2928g()) {\r
 836                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 837                                 if (reg_check_rmvb_wmv(reg)) {\r
 838                                         reg->freq = VPU_FREQ_200M;\r
 839                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
 840                                         if (reg_probe_width(reg) > 3200) {\r
 841                                                 // raise frequency for 4k avc.\r
 842                                                 reg->freq = VPU_FREQ_500M;\r
 843                                         }\r
 844                                 } else {\r
 845                                         if (reg_check_interlace(reg)) {\r
 846                                                 reg->freq = VPU_FREQ_400M;\r
 847                                         }\r
 848                                 }\r
 849                         }\r
 850                         if (reg->type == VPU_PP) {\r
 851                                 reg->freq = VPU_FREQ_400M;\r
 852                         }\r
 853                 }\r
 854         }\r
 855 \r
 856         return reg;\r
 857 }\r
 858 \r
 859 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 860 {\r
 861 #if defined(CONFIG_VCODEC_MMU)\r
 862         struct vcodec_mem_region *mem_region = NULL, *n;\r
 863 #endif\r
 864 \r
 865         list_del_init(&reg->session_link);\r
 866         list_del_init(&reg->status_link);\r
 867         if (reg == pservice->reg_codec)\r
 868                 pservice->reg_codec = NULL;\r
 869         if (reg == pservice->reg_pproc)\r
 870                 pservice->reg_pproc = NULL;\r
 871 \r
 872 #if defined(CONFIG_VCODEC_MMU)\r
 873         // release memory region attach to this registers table.\r
 874         if (pservice->mmu_dev) {\r
 875                 list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 876                         /* do not unmap iommu manually,\r
 877                            unmap will proccess when memory release */\r
 878                         /*ion_unmap_iommu(pservice->dev,\r
 879                                         pservice->ion_client,\r
 880                                         mem_region->hdl);\r
 881                         vcodec_exit_mode();*/\r
 882                         ion_free(pservice->ion_client, mem_region->hdl);\r
 883                         list_del_init(&mem_region->reg_lnk);\r
 884                         kfree(mem_region);\r
 885                 }\r
 886         }\r
 887 #endif\r
 888 \r
 889         kfree(reg);\r
 890 }\r
 891 \r
 892 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 893 {\r
 894         list_del_init(&reg->status_link);\r
 895         list_add_tail(&reg->status_link, &pservice->running);\r
 896 \r
 897         list_del_init(&reg->session_link);\r
 898         list_add_tail(&reg->session_link, &reg->session->running);\r
 899 }\r
 900 \r
 901 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 902 {\r
 903         int i;\r
 904         u32 *dst = (u32 *)&reg->reg[0];\r
 905         for (i = 0; i < count; i++)\r
 906                 *dst++ = *src++;\r
 907 }\r
 908 \r
 909 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 910 {\r
 911         int irq_reg = -1;\r
 912         list_del_init(&reg->status_link);\r
 913         list_add_tail(&reg->status_link, &pservice->done);\r
 914 \r
 915         list_del_init(&reg->session_link);\r
 916         list_add_tail(&reg->session_link, &reg->session->done);\r
 917 \r
 918         switch (reg->type) {\r
 919         case VPU_ENC : {\r
 920                 pservice->reg_codec = NULL;\r
 921                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 922                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 923                 break;\r
 924         }\r
 925         case VPU_DEC : {\r
 926                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 927                 pservice->reg_codec = NULL;\r
 928                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 929                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 930                 break;\r
 931         }\r
 932         case VPU_PP : {\r
 933                 pservice->reg_pproc = NULL;\r
 934                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 935                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 936                 break;\r
 937         }\r
 938         case VPU_DEC_PP : {\r
 939                 pservice->reg_codec = NULL;\r
 940                 pservice->reg_pproc = NULL;\r
 941                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 942                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 943                 break;\r
 944         }\r
 945         default : {\r
 946                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 947                 break;\r
 948         }\r
 949         }\r
 950 \r
 951         if (irq_reg != -1) {\r
 952                 reg->reg[irq_reg] = pservice->irq_status;\r
 953         }\r
 954 \r
 955         atomic_sub(1, &reg->session->task_running);\r
 956         atomic_sub(1, &pservice->total_running);\r
 957         wake_up(&reg->session->wait);\r
 958 }\r
 959 \r
 960 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 961 {\r
 962         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 963         if (curr == reg->freq) {\r
 964                 return ;\r
 965         }\r
 966         atomic_set(&pservice->freq_status, reg->freq);\r
 967         switch (reg->freq) {\r
 968         case VPU_FREQ_200M : {\r
 969                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 970                 //printk("default: 200M\n");\r
 971         } break;\r
 972         case VPU_FREQ_266M : {\r
 973                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 974                 //printk("default: 266M\n");\r
 975         } break;\r
 976         case VPU_FREQ_300M : {\r
 977                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 978                 //printk("default: 300M\n");\r
 979         } break;\r
 980         case VPU_FREQ_400M : {\r
 981                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 982                 //printk("default: 400M\n");\r
 983         } break;\r
 984         case VPU_FREQ_500M : {\r
 985                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 986         } break;\r
 987         case VPU_FREQ_600M : {\r
 988                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 989         } break;\r
 990         default : {\r
 991                 if (soc_is_rk2928g()) {\r
 992                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 993                 } else {\r
 994                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 995                 }\r
 996                 //printk("default: 300M\n");\r
 997         } break;\r
 998         }\r
 999 }\r
1000 \r
1001 #if HEVC_SIM_ENABLE\r
1002 static void simulate_start(struct vpu_service_info *pservice);\r
1003 #endif\r
1004 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
1005 {\r
1006         int i;\r
1007         u32 *src = (u32 *)&reg->reg[0];\r
1008         atomic_add(1, &pservice->total_running);\r
1009         atomic_add(1, &reg->session->task_running);\r
1010         if (pservice->auto_freq) {\r
1011                 vpu_service_set_freq(pservice, reg);\r
1012         }\r
1013         switch (reg->type) {\r
1014         case VPU_ENC : {\r
1015                 int enc_count = pservice->hw_info->enc_reg_num;\r
1016                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
1017 \r
1018                 pservice->reg_codec = reg;\r
1019 \r
1020                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
1021 \r
1022                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
1023                         dst[i] = src[i];\r
1024 \r
1025                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
1026                         dst[i] = src[i];\r
1027 \r
1028                 dsb();\r
1029 \r
1030                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
1031                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
1032 \r
1033 #if VPU_SERVICE_SHOW_TIME\r
1034                 do_gettimeofday(&enc_start);\r
1035 #endif\r
1036 \r
1037         } break;\r
1038         case VPU_DEC : {\r
1039                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1040 \r
1041                 pservice->reg_codec = reg;\r
1042 \r
1043                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1044                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
1045                                 dst[i] = src[i];\r
1046                 } else {\r
1047                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
1048                                 dst[i] = src[i];\r
1049                         }\r
1050                 }\r
1051 \r
1052                 dsb();\r
1053 \r
1054                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1055                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
1056                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
1057                 } else {\r
1058                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
1059                 }\r
1060 \r
1061                 dsb();\r
1062                 dmb();\r
1063 \r
1064 #if VPU_SERVICE_SHOW_TIME\r
1065                 do_gettimeofday(&dec_start);\r
1066 #endif\r
1067 \r
1068         } break;\r
1069         case VPU_PP : {\r
1070                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1071                 pservice->reg_pproc = reg;\r
1072 \r
1073                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1074 \r
1075                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1076                         dst[i] = src[i];\r
1077 \r
1078                 dsb();\r
1079 \r
1080                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1081 \r
1082 #if VPU_SERVICE_SHOW_TIME\r
1083                 do_gettimeofday(&pp_start);\r
1084 #endif\r
1085 \r
1086         } break;\r
1087         case VPU_DEC_PP : {\r
1088                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1089                 pservice->reg_codec = reg;\r
1090                 pservice->reg_pproc = reg;\r
1091 \r
1092                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1093                         dst[i] = src[i];\r
1094 \r
1095                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1096                 dsb();\r
1097 \r
1098                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1099                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1100                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1101 \r
1102 #if VPU_SERVICE_SHOW_TIME\r
1103                 do_gettimeofday(&dec_start);\r
1104 #endif\r
1105 \r
1106         } break;\r
1107         default : {\r
1108                 pr_err("error: unsupport session type %d", reg->type);\r
1109                 atomic_sub(1, &pservice->total_running);\r
1110                 atomic_sub(1, &reg->session->task_running);\r
1111                 break;\r
1112         }\r
1113         }\r
1114 \r
1115 #if HEVC_SIM_ENABLE\r
1116         if (pservice->hw_info->hw_id == HEVC_ID) {\r
1117                 simulate_start(pservice);\r
1118         }\r
1119 #endif\r
1120 }\r
1121 \r
1122 static void try_set_reg(struct vpu_service_info *pservice)\r
1123 {\r
1124         // first get reg from reg list\r
1125         if (!list_empty(&pservice->waiting)) {\r
1126                 int can_set = 0;\r
1127                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1128 \r
1129                 vpu_service_power_on(pservice);\r
1130 \r
1131                 switch (reg->type) {\r
1132                 case VPU_ENC : {\r
1133                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1134                                 can_set = 1;\r
1135                 } break;\r
1136                 case VPU_DEC : {\r
1137                         if (NULL == pservice->reg_codec)\r
1138                                 can_set = 1;\r
1139                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1140                                 can_set = 0;\r
1141                         }\r
1142                 } break;\r
1143                 case VPU_PP : {\r
1144                         if (NULL == pservice->reg_codec) {\r
1145                                 if (NULL == pservice->reg_pproc)\r
1146                                         can_set = 1;\r
1147                         } else {\r
1148                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1149                                         can_set = 1;\r
1150                                 // can not charge frequency when vpu is working\r
1151                                 if (pservice->auto_freq) {\r
1152                                         can_set = 0;\r
1153                                 }\r
1154                         }\r
1155                 } break;\r
1156                 case VPU_DEC_PP : {\r
1157                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1158                                 can_set = 1;\r
1159                         } break;\r
1160                 default : {\r
1161                         printk("undefined reg type %d\n", reg->type);\r
1162                 } break;\r
1163                 }\r
1164                 if (can_set) {\r
1165                         reg_from_wait_to_run(pservice, reg);\r
1166                         reg_copy_to_hw(pservice, reg);\r
1167                 }\r
1168         }\r
1169 }\r
1170 \r
1171 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1172 {\r
1173         int ret = 0;\r
1174         switch (reg->type) {\r
1175         case VPU_ENC : {\r
1176                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1177                         ret = -EFAULT;\r
1178                 break;\r
1179         }\r
1180         case VPU_DEC : {\r
1181                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1182                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1183                         ret = -EFAULT;\r
1184                 break;\r
1185         }\r
1186         case VPU_PP : {\r
1187                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1188                         ret = -EFAULT;\r
1189                 break;\r
1190         }\r
1191         case VPU_DEC_PP : {\r
1192                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1193                         ret = -EFAULT;\r
1194                 break;\r
1195         }\r
1196         default : {\r
1197                 ret = -EFAULT;\r
1198                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1199                 break;\r
1200         }\r
1201         }\r
1202         reg_deinit(pservice, reg);\r
1203         return ret;\r
1204 }\r
1205 \r
1206 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1207 {\r
1208     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1209         vpu_session *session = (vpu_session *)filp->private_data;\r
1210         if (NULL == session) {\r
1211                 return -EINVAL;\r
1212         }\r
1213 \r
1214         switch (cmd) {\r
1215         case VPU_IOC_SET_CLIENT_TYPE : {\r
1216                 session->type = (VPU_CLIENT_TYPE)arg;\r
1217                 break;\r
1218         }\r
1219         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1220                 vpu_request req;\r
1221                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1222                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1223                         return -EFAULT;\r
1224                 } else {\r
1225                         if (VPU_ENC != session->type) {\r
1226                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1227                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1228                                         return -EFAULT;\r
1229                                 }\r
1230                         } else {\r
1231                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1232                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1233                                         return -EFAULT;\r
1234                                 }\r
1235                         }\r
1236                 }\r
1237 \r
1238                 break;\r
1239         }\r
1240         case VPU_IOC_SET_REG : {\r
1241                 vpu_request req;\r
1242                 vpu_reg *reg;\r
1243                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1244                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1245                         return -EFAULT;\r
1246                 }\r
1247                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1248                 if (NULL == reg) {\r
1249                         return -EFAULT;\r
1250                 } else {\r
1251                         mutex_lock(&pservice->lock);\r
1252                         try_set_reg(pservice);\r
1253                         mutex_unlock(&pservice->lock);\r
1254                 }\r
1255 \r
1256                 break;\r
1257         }\r
1258         case VPU_IOC_GET_REG : {\r
1259                 vpu_request req;\r
1260                 vpu_reg *reg;\r
1261                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1262                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1263                         return -EFAULT;\r
1264                 } else {\r
1265                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1266                         if (!list_empty(&session->done)) {\r
1267                                 if (ret < 0) {\r
1268                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1269                                 }\r
1270                                 ret = 0;\r
1271                         } else {\r
1272                                 if (unlikely(ret < 0)) {\r
1273                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1274                                 } else if (0 == ret) {\r
1275                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1276                                         ret = -ETIMEDOUT;\r
1277                                 }\r
1278                         }\r
1279                         if (ret < 0) {\r
1280                                 int task_running = atomic_read(&session->task_running);\r
1281                                 mutex_lock(&pservice->lock);\r
1282                                 vpu_service_dump(pservice);\r
1283                                 if (task_running) {\r
1284                                         atomic_set(&session->task_running, 0);\r
1285                                         atomic_sub(task_running, &pservice->total_running);\r
1286                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1287                                         vpu_reset(pservice);\r
1288                                         printk("done\n");\r
1289                                 }\r
1290                                 vpu_service_session_clear(pservice, session);\r
1291                                 mutex_unlock(&pservice->lock);\r
1292                                 return ret;\r
1293                         }\r
1294                 }\r
1295                 mutex_lock(&pservice->lock);\r
1296                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1297                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1298                 mutex_unlock(&pservice->lock);\r
1299                 break;\r
1300         }\r
1301         case VPU_IOC_PROBE_IOMMU_STATUS: {\r
1302                 int iommu_enable = 0;\r
1303 \r
1304 #if defined(CONFIG_VCODEC_MMU)                \r
1305                 iommu_enable = pservice->mmu_dev ? 1 : 0; \r
1306 #endif                \r
1307 \r
1308                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
1309                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
1310                         return -EFAULT;\r
1311                 }\r
1312                 break;\r
1313         }\r
1314         default : {\r
1315                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1316                 break;\r
1317         }\r
1318         }\r
1319 \r
1320         return 0;\r
1321 }\r
1322 \r
1323 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1324 {\r
1325         int ret = -EINVAL, i = 0;\r
1326         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1327         u32 enc_id = *tmp;\r
1328 \r
1329 #if HEVC_SIM_ENABLE\r
1330         /// temporary, hevc driver test.\r
1331         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1332                 p->hw_info = &vpu_hw_set[2];\r
1333                 return 0;\r
1334         }\r
1335 #endif\r
1336 \r
1337         enc_id = (enc_id >> 16) & 0xFFFF;\r
1338         pr_info("checking hw id %x\n", enc_id);\r
1339         p->hw_info = NULL;\r
1340         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1341                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1342                         p->hw_info = &vpu_hw_set[i];\r
1343                         ret = 0;\r
1344                         break;\r
1345                 }\r
1346         }\r
1347         iounmap((void *)tmp);\r
1348         return ret;\r
1349 }\r
1350 \r
1351 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1352 {\r
1353         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1354         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1355         if (NULL == session) {\r
1356                 pr_err("error: unable to allocate memory for vpu_session.");\r
1357                 return -ENOMEM;\r
1358         }\r
1359 \r
1360         session->type   = VPU_TYPE_BUTT;\r
1361         session->pid    = current->pid;\r
1362         INIT_LIST_HEAD(&session->waiting);\r
1363         INIT_LIST_HEAD(&session->running);\r
1364         INIT_LIST_HEAD(&session->done);\r
1365         INIT_LIST_HEAD(&session->list_session);\r
1366         init_waitqueue_head(&session->wait);\r
1367         atomic_set(&session->task_running, 0);\r
1368         mutex_lock(&pservice->lock);\r
1369         list_add_tail(&session->list_session, &pservice->session);\r
1370         filp->private_data = (void *)session;\r
1371         mutex_unlock(&pservice->lock);\r
1372 \r
1373         pr_debug("dev opened\n");\r
1374         return nonseekable_open(inode, filp);\r
1375 }\r
1376 \r
1377 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1378 {\r
1379         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1380         int task_running;\r
1381         vpu_session *session = (vpu_session *)filp->private_data;\r
1382         if (NULL == session)\r
1383                 return -EINVAL;\r
1384 \r
1385         task_running = atomic_read(&session->task_running);\r
1386         if (task_running) {\r
1387                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1388                 msleep(50);\r
1389         }\r
1390         wake_up(&session->wait);\r
1391 \r
1392         mutex_lock(&pservice->lock);\r
1393         /* remove this filp from the asynchronusly notified filp's */\r
1394         list_del_init(&session->list_session);\r
1395         vpu_service_session_clear(pservice, session);\r
1396         kfree(session);\r
1397         filp->private_data = NULL;\r
1398         mutex_unlock(&pservice->lock);\r
1399 \r
1400         pr_debug("dev closed\n");\r
1401         return 0;\r
1402 }\r
1403 \r
1404 static const struct file_operations vpu_service_fops = {\r
1405         .unlocked_ioctl = vpu_service_ioctl,\r
1406         .open           = vpu_service_open,\r
1407         .release        = vpu_service_release,\r
1408         //.fasync       = vpu_service_fasync,\r
1409 };\r
1410 \r
1411 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1412 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1413 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1414 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1415 static void get_hw_info(struct vpu_service_info *pservice);\r
1416 \r
1417 #if HEVC_SIM_ENABLE\r
1418 static void simulate_work(struct work_struct *work_s)\r
1419 {\r
1420     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1421     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1422     vpu_device *dev = &pservice->dec_dev;\r
1423 \r
1424     if (!list_empty(&pservice->running)) {\r
1425         atomic_add(1, &dev->irq_count_codec);\r
1426         vdpu_isr(0, (void*)pservice);\r
1427     } else {\r
1428         //simulate_start(pservice);\r
1429         pr_err("empty running queue\n");\r
1430     }\r
1431 }\r
1432 \r
1433 static void simulate_init(struct vpu_service_info *pservice)\r
1434 {\r
1435     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1436 }\r
1437 \r
1438 static void simulate_start(struct vpu_service_info *pservice)\r
1439 {\r
1440     cancel_delayed_work_sync(&pservice->power_off_work);\r
1441     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1442 }\r
1443 #endif\r
1444 \r
1445 #if HEVC_TEST_ENABLE\r
1446 static int hevc_test_case0(vpu_service_info *pservice);\r
1447 #endif\r
1448 #if defined(CONFIG_ION_ROCKCHIP)\r
1449 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1450 #endif\r
1451 static int vcodec_probe(struct platform_device *pdev)\r
1452 {\r
1453     int ret = 0;\r
1454     struct resource *res = NULL;\r
1455     struct device *dev = &pdev->dev;\r
1456     void __iomem *regs = NULL;\r
1457     struct device_node *np = pdev->dev.of_node;\r
1458     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1459     char *prop = (char*)dev_name(dev);\r
1460 #if defined(CONFIG_VCODEC_MMU)\r
1461         u32 iommu_en = 0;\r
1462         char mmu_dev_dts_name[40];\r
1463         of_property_read_u32(np, "iommu_enabled", &iommu_en);\r
1464 #endif\r
1465 \r
1466     pr_info("probe device %s\n", dev_name(dev));\r
1467 \r
1468     of_property_read_string(np, "name", (const char**)&prop);\r
1469     dev_set_name(dev, prop);\r
1470 \r
1471     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1472         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1473     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1474         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1475     } else {\r
1476         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1477         return -1;\r
1478     }\r
1479 \r
1480     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1481     INIT_LIST_HEAD(&pservice->waiting);\r
1482     INIT_LIST_HEAD(&pservice->running);\r
1483     INIT_LIST_HEAD(&pservice->done);\r
1484     INIT_LIST_HEAD(&pservice->session);\r
1485     mutex_init(&pservice->lock);\r
1486     pservice->reg_codec = NULL;\r
1487     pservice->reg_pproc = NULL;\r
1488     atomic_set(&pservice->total_running, 0);\r
1489     pservice->enabled = false;\r
1490 #if defined(CONFIG_VCODEC_MMU)    \r
1491     pservice->mmu_dev = NULL;\r
1492 #endif    \r
1493     pservice->dev = dev;\r
1494 \r
1495     if (0 > vpu_get_clk(pservice)) {\r
1496         goto err;\r
1497     }\r
1498 \r
1499     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1500 \r
1501     vpu_service_power_on(pservice);\r
1502     \r
1503     mdelay(1);\r
1504 \r
1505     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1506 \r
1507     regs = devm_ioremap_resource(pservice->dev, res);\r
1508     if (IS_ERR(regs)) {\r
1509         ret = PTR_ERR(regs);\r
1510         goto err;\r
1511     }\r
1512 \r
1513     ret = vpu_service_check_hw(pservice, res->start);\r
1514     if (ret < 0) {\r
1515         pr_err("error: hw info check faild\n");\r
1516         goto err;\r
1517     }\r
1518 \r
1519     /// define regs address.\r
1520     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1521     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1522 \r
1523     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1524 \r
1525     pservice->reg_size   = pservice->dec_dev.iosize;\r
1526 \r
1527     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1528         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1529         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1530 \r
1531         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1532 \r
1533         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1534 \r
1535         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1536         if (pservice->irq_enc < 0) {\r
1537             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1538             ret = -ENXIO;\r
1539             goto err;\r
1540         }\r
1541 \r
1542         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1543         if (ret) {\r
1544             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1545             goto err;\r
1546         }\r
1547     }\r
1548 \r
1549     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1550     if (pservice->irq_dec < 0) {\r
1551         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1552         ret = -ENXIO;\r
1553         goto err;\r
1554     }\r
1555 \r
1556     /* get the IRQ line */\r
1557     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1558     if (ret) {\r
1559         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1560         goto err;\r
1561     }\r
1562 \r
1563     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1564     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1565     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1566     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1567 \r
1568     /// create device\r
1569     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1570     if (ret) {\r
1571         dev_err(dev, "alloc dev_t failed\n");\r
1572         goto err;\r
1573     }\r
1574 \r
1575     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1576 \r
1577     pservice->cdev.owner = THIS_MODULE;\r
1578     pservice->cdev.ops = &vpu_service_fops;\r
1579 \r
1580     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1581 \r
1582     if (ret) {\r
1583         dev_err(dev, "add dev_t failed\n");\r
1584         goto err;\r
1585     }\r
1586 \r
1587     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1588 \r
1589     if (IS_ERR(pservice->cls)) {\r
1590         ret = PTR_ERR(pservice->cls);\r
1591         dev_err(dev, "class_create err:%d\n", ret);\r
1592         goto err;\r
1593     }\r
1594 \r
1595     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1596 \r
1597     platform_set_drvdata(pdev, pservice);\r
1598 \r
1599     get_hw_info(pservice);\r
1600 \r
1601 \r
1602 #ifdef CONFIG_DEBUG_FS\r
1603     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1604     \r
1605     if (pservice->debugfs_dir == NULL) {\r
1606         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1607     }\r
1608 \r
1609     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1610                     pservice->debugfs_dir, pservice,\r
1611                     &debug_vcodec_fops);\r
1612 #endif\r
1613 \r
1614 #if defined(CONFIG_VCODEC_MMU)\r
1615         if (iommu_en) {\r
1616                 pservice->ion_client = rockchip_ion_client_create("vpu");\r
1617                 if (IS_ERR(pservice->ion_client)) {\r
1618                         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1619                         return PTR_ERR(pservice->ion_client);\r
1620                 } else {\r
1621                         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1622                 }\r
1623 \r
1624                 if (pservice->hw_info->hw_id == HEVC_ID)\r
1625                         sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1626                 else\r
1627                         sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1628 \r
1629                 pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1630 \r
1631                 if (pservice->mmu_dev) {\r
1632                         platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
1633                         iovmm_activate(pservice->dev);\r
1634                 }\r
1635         }\r
1636 #endif\r
1637 \r
1638     vpu_service_power_off(pservice);\r
1639     pr_info("init success\n");\r
1640 \r
1641 #if HEVC_SIM_ENABLE\r
1642     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1643         simulate_init(pservice);\r
1644     }\r
1645 #endif\r
1646 \r
1647 #if HEVC_TEST_ENABLE\r
1648     hevc_test_case0(pservice);\r
1649 #endif\r
1650 \r
1651     return 0;\r
1652 \r
1653 err:\r
1654     pr_info("init failed\n");\r
1655     vpu_service_power_off(pservice);\r
1656     vpu_put_clk(pservice);\r
1657     wake_lock_destroy(&pservice->wake_lock);\r
1658 \r
1659     if (res) {\r
1660         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1661     }\r
1662 \r
1663     if (pservice->irq_enc > 0) {\r
1664         free_irq(pservice->irq_enc, (void *)pservice);\r
1665     }\r
1666 \r
1667     if (pservice->irq_dec > 0) {\r
1668         free_irq(pservice->irq_dec, (void *)pservice);\r
1669     }\r
1670 \r
1671     if (pservice->child_dev) {\r
1672         device_destroy(pservice->cls, pservice->dev_t);\r
1673         cdev_del(&pservice->cdev);\r
1674         unregister_chrdev_region(pservice->dev_t, 1);\r
1675     }\r
1676 \r
1677     if (pservice->cls) {\r
1678         class_destroy(pservice->cls);\r
1679     }\r
1680 \r
1681     return ret;\r
1682 }\r
1683 \r
1684 static int vcodec_remove(struct platform_device *pdev)\r
1685 {\r
1686     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1687     struct resource *res;\r
1688 \r
1689     device_destroy(pservice->cls, pservice->dev_t);\r
1690     class_destroy(pservice->cls);\r
1691     cdev_del(&pservice->cdev);\r
1692     unregister_chrdev_region(pservice->dev_t, 1);\r
1693 \r
1694     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1695     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1696     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1697     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1698     vpu_put_clk(pservice);\r
1699     wake_lock_destroy(&pservice->wake_lock);\r
1700     \r
1701 #ifdef CONFIG_DEBUG_FS\r
1702     if (pservice->debugfs_file_regs) {\r
1703         debugfs_remove(pservice->debugfs_file_regs);\r
1704     }\r
1705 \r
1706     if (pservice->debugfs_dir) {\r
1707         debugfs_remove(pservice->debugfs_dir);\r
1708     }\r
1709 #endif\r
1710 \r
1711     return 0;\r
1712 }\r
1713 \r
1714 #if defined(CONFIG_OF)\r
1715 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1716     {.compatible = "vpu_service",},\r
1717     {.compatible = "rockchip,hevc_service",},\r
1718     {},\r
1719 };\r
1720 #endif\r
1721 \r
1722 static struct platform_driver vcodec_driver = {\r
1723     .probe     = vcodec_probe,\r
1724     .remove        = vcodec_remove,\r
1725     .driver = {\r
1726         .name = "vcodec",\r
1727         .owner = THIS_MODULE,\r
1728 #if defined(CONFIG_OF)\r
1729         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1730 #endif\r
1731     },\r
1732 };\r
1733 \r
1734 static void get_hw_info(struct vpu_service_info *pservice)\r
1735 {\r
1736     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1737     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1738 \r
1739     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1740         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1741         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1742     \r
1743         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1744         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1745         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1746             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1747         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1748         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1749         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1750         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1751         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1752         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1753     \r
1754         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1755             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1756         } else {\r
1757             dec->maxDecPicWidth = 4096;\r
1758         }\r
1759     \r
1760         /* 2nd Config register */\r
1761         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1762         if (dec->refBufSupport) {\r
1763             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1764                 dec->refBufSupport |= 2;\r
1765             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1766                 dec->refBufSupport |= 4;\r
1767         }\r
1768         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1769         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1770         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1771         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1772     \r
1773         /* JPEG xtensions */\r
1774         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1775             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1776         } else {\r
1777             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1778         }\r
1779     \r
1780         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1781             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1782         } else {\r
1783             dec->rvSupport = RV_NOT_SUPPORTED;\r
1784         }\r
1785     \r
1786         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1787     \r
1788         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1789             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1790         }\r
1791     \r
1792         /// invalidate fuse register value in rk319x vpu and following.\r
1793         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1794             VPUHwFuseStatus_t hwFuseSts;\r
1795             /* Decoder fuse configuration */\r
1796             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1797     \r
1798             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1799             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1800             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1801             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1802             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1803             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1804             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1805             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1806             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1807             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1808             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1809             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1810             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1811             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1812     \r
1813             /* check max. decoder output width */\r
1814     \r
1815             if (fuseReg & 0x8000U)\r
1816                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1817             else if (fuseReg & 0x4000U)\r
1818                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1819             else if (fuseReg & 0x2000U)\r
1820                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1821             else if (fuseReg & 0x1000U)\r
1822                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1823             else    /* remove warning */\r
1824                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1825     \r
1826             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1827     \r
1828             /* Pp configuration */\r
1829             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1830     \r
1831             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1832                 dec->ppSupport = 1;\r
1833                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1834                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1835                 dec->ppConfig = configReg;\r
1836             } else {\r
1837                 dec->ppSupport = 0;\r
1838                 dec->maxPpOutPicWidth = 0;\r
1839                 dec->ppConfig = 0;\r
1840             }\r
1841     \r
1842             /* check the HW versio */\r
1843             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1844                 /* Pp configuration */\r
1845                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1846     \r
1847                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1848                     /* Pp fuse configuration */\r
1849                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1850     \r
1851                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1852                         hwFuseSts.ppSupportFuse = 1;\r
1853                         /* check max. pp output width */\r
1854                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1855                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1856                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1857                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1858                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1859                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1860                     } else {\r
1861                         hwFuseSts.ppSupportFuse = 0;\r
1862                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1863                         hwFuseSts.ppConfigFuse = 0;\r
1864                     }\r
1865                 } else {\r
1866                     hwFuseSts.ppSupportFuse = 0;\r
1867                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1868                     hwFuseSts.ppConfigFuse = 0;\r
1869                 }\r
1870     \r
1871                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1872                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1873                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1874                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1875                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1876                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1877                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1878                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1879                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1880                     dec->jpegSupport = JPEG_BASELINE;\r
1881                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1882                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1883                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1884                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1885                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1886                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1887     \r
1888                 /* check the pp config vs fuse status */\r
1889                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1890                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1891                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1892                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1893                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1894     \r
1895                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1896                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1897                 }\r
1898                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1899                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1900                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1901                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1902                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1903             }\r
1904         }\r
1905     \r
1906         configReg = pservice->enc_dev.hwregs[63];\r
1907         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1908         enc->h264Enabled = (configReg >> 27) & 1;\r
1909         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1910         enc->jpegEnabled = (configReg >> 25) & 1;\r
1911         enc->vsEnabled = (configReg >> 24) & 1;\r
1912         enc->rgbEnabled = (configReg >> 28) & 1;\r
1913         //enc->busType = (configReg >> 20) & 15;\r
1914         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1915         //enc->busWidth = (configReg >> 12) & 15;\r
1916         enc->reg_size = pservice->reg_size;\r
1917         enc->reserv[0] = enc->reserv[1] = 0;\r
1918     \r
1919         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1920         if (pservice->auto_freq) {\r
1921             pr_info("vpu_service set to auto frequency mode\n");\r
1922             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1923         }\r
1924         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1925         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1926     } else {\r
1927         // disable frequency switch in hevc.\r
1928         pservice->auto_freq = false;\r
1929     }\r
1930 }\r
1931 \r
1932 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1933 {\r
1934     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1935     vpu_device *dev = &pservice->dec_dev;\r
1936     u32 raw_status;\r
1937     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1938 \r
1939         pr_debug("dec_irq\n");\r
1940 \r
1941         if (irq_status & DEC_INTERRUPT_BIT) {\r
1942                 pr_debug("dec_isr dec %x\n", irq_status);\r
1943                 if ((irq_status & 0x40001) == 0x40001)\r
1944                 {\r
1945                         do {\r
1946                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1947                         } while ((irq_status & 0x40001) == 0x40001);\r
1948                 }\r
1949 \r
1950                 /* clear dec IRQ */\r
1951         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1952             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1953         } else {\r
1954             /*writel(irq_status \r
1955               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1956                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1957 \r
1958             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1959         }\r
1960                 atomic_add(1, &dev->irq_count_codec);\r
1961         }\r
1962 \r
1963     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1964         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1965         if (irq_status & PP_INTERRUPT_BIT) {\r
1966             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1967             /* clear pp IRQ */\r
1968             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1969             atomic_add(1, &dev->irq_count_pp);\r
1970         }\r
1971     }\r
1972 \r
1973     pservice->irq_status = raw_status;\r
1974 \r
1975         return IRQ_WAKE_THREAD;\r
1976 }\r
1977 \r
1978 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1979 {\r
1980     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1981     vpu_device *dev = &pservice->dec_dev;\r
1982 \r
1983         mutex_lock(&pservice->lock);\r
1984         if (atomic_read(&dev->irq_count_codec)) {\r
1985 #if VPU_SERVICE_SHOW_TIME\r
1986                 do_gettimeofday(&dec_end);\r
1987                 pr_info("dec task: %ld ms\n",\r
1988                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1989                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1990 #endif\r
1991                 atomic_sub(1, &dev->irq_count_codec);\r
1992                 if (NULL == pservice->reg_codec) {\r
1993                         pr_err("error: dec isr with no task waiting\n");\r
1994                 } else {\r
1995                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1996                 }\r
1997         }\r
1998 \r
1999         if (atomic_read(&dev->irq_count_pp)) {\r
2000 \r
2001 #if VPU_SERVICE_SHOW_TIME\r
2002                 do_gettimeofday(&pp_end);\r
2003                 printk("pp  task: %ld ms\n",\r
2004                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
2005                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
2006 #endif\r
2007 \r
2008                 atomic_sub(1, &dev->irq_count_pp);\r
2009                 if (NULL == pservice->reg_pproc) {\r
2010                         pr_err("error: pp isr with no task waiting\n");\r
2011                 } else {\r
2012                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
2013                 }\r
2014         }\r
2015         try_set_reg(pservice);\r
2016         mutex_unlock(&pservice->lock);\r
2017         return IRQ_HANDLED;\r
2018 }\r
2019 \r
2020 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
2021 {\r
2022         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2023     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2024     vpu_device *dev = &pservice->enc_dev;\r
2025         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2026 \r
2027         pr_debug("vepu_irq irq status %x\n", irq_status);\r
2028 \r
2029 #if VPU_SERVICE_SHOW_TIME\r
2030         do_gettimeofday(&enc_end);\r
2031         pr_info("enc task: %ld ms\n",\r
2032                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
2033                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
2034 #endif\r
2035     \r
2036         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
2037                 /* clear enc IRQ */\r
2038                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2039                 atomic_add(1, &dev->irq_count_codec);\r
2040         }\r
2041     \r
2042     pservice->irq_status = irq_status;\r
2043 \r
2044         return IRQ_WAKE_THREAD;\r
2045 }\r
2046 \r
2047 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
2048 {\r
2049         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2050     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2051     vpu_device *dev = &pservice->enc_dev;\r
2052 \r
2053         mutex_lock(&pservice->lock);\r
2054         if (atomic_read(&dev->irq_count_codec)) {\r
2055                 atomic_sub(1, &dev->irq_count_codec);\r
2056                 if (NULL == pservice->reg_codec) {\r
2057                         pr_err("error: enc isr with no task waiting\n");\r
2058                 } else {\r
2059                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2060                 }\r
2061         }\r
2062         try_set_reg(pservice);\r
2063         mutex_unlock(&pservice->lock);\r
2064         return IRQ_HANDLED;\r
2065 }\r
2066 \r
2067 static int __init vcodec_service_init(void)\r
2068 {\r
2069     int ret;\r
2070 \r
2071     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
2072         pr_err("Platform device register failed (%d).\n", ret);\r
2073         return ret;\r
2074     }\r
2075 \r
2076 #ifdef CONFIG_DEBUG_FS\r
2077     vcodec_debugfs_init();\r
2078 #endif\r
2079 \r
2080     return ret;\r
2081 }\r
2082 \r
2083 static void __exit vcodec_service_exit(void)\r
2084 {\r
2085 #ifdef CONFIG_DEBUG_FS\r
2086     vcodec_debugfs_exit();\r
2087 #endif\r
2088 \r
2089         platform_driver_unregister(&vcodec_driver);\r
2090 }\r
2091 \r
2092 module_init(vcodec_service_init);\r
2093 module_exit(vcodec_service_exit);\r
2094 \r
2095 #ifdef CONFIG_DEBUG_FS\r
2096 #include <linux/seq_file.h>\r
2097 \r
2098 static int vcodec_debugfs_init()\r
2099 {\r
2100     parent = debugfs_create_dir("vcodec", NULL);\r
2101     if (!parent)\r
2102         return -1;\r
2103 \r
2104     return 0;\r
2105 }\r
2106 \r
2107 static void vcodec_debugfs_exit()\r
2108 {\r
2109     debugfs_remove(parent);\r
2110 }\r
2111 \r
2112 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2113 {\r
2114     return debugfs_create_dir(dirname, parent);\r
2115 }\r
2116 \r
2117 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2118 {\r
2119         struct vpu_service_info *pservice = s->private;\r
2120     unsigned int i, n;\r
2121         vpu_reg *reg, *reg_tmp;\r
2122         vpu_session *session, *session_tmp;\r
2123 \r
2124         mutex_lock(&pservice->lock);\r
2125         vpu_service_power_on(pservice);\r
2126     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2127         seq_printf(s, "\nENC Registers:\n");\r
2128         n = pservice->enc_dev.iosize >> 2;\r
2129         for (i = 0; i < n; i++) {\r
2130             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2131         }\r
2132     }\r
2133         seq_printf(s, "\nDEC Registers:\n");\r
2134         n = pservice->dec_dev.iosize >> 2;\r
2135         for (i = 0; i < n; i++) {\r
2136                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2137         }\r
2138 \r
2139         seq_printf(s, "\nvpu service status:\n");\r
2140         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2141                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2142                 //seq_printf(s, "waiting reg set %d\n");\r
2143                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2144                         seq_printf(s, "waiting register set\n");\r
2145                 }\r
2146                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2147                         seq_printf(s, "running register set\n");\r
2148                 }\r
2149                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2150                         seq_printf(s, "done    register set\n");\r
2151                 }\r
2152         }\r
2153         mutex_unlock(&pservice->lock);\r
2154 \r
2155     return 0;\r
2156 }\r
2157 \r
2158 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2159 {\r
2160         return single_open(file, debug_vcodec_show, inode->i_private);\r
2161 }\r
2162 \r
2163 #endif\r
2164 \r
2165 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2166 #include "hevc_test_inc/pps_00.h"\r
2167 #include "hevc_test_inc/register_00.h"\r
2168 #include "hevc_test_inc/rps_00.h"\r
2169 #include "hevc_test_inc/scaling_list_00.h"\r
2170 #include "hevc_test_inc/stream_00.h"\r
2171 \r
2172 #include "hevc_test_inc/pps_01.h"\r
2173 #include "hevc_test_inc/register_01.h"\r
2174 #include "hevc_test_inc/rps_01.h"\r
2175 #include "hevc_test_inc/scaling_list_01.h"\r
2176 #include "hevc_test_inc/stream_01.h"\r
2177 \r
2178 #include "hevc_test_inc/cabac.h"\r
2179 \r
2180 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2181 \r
2182 static struct ion_client *ion_client = NULL;\r
2183 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2184 {\r
2185         int size = (len+15) & (~15);\r
2186     struct ion_handle *handle;\r
2187         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2188 \r
2189     if (ion_client == NULL) {\r
2190         ion_client = rockchip_ion_client_create("vcodec");\r
2191     }\r
2192 \r
2193     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2194 \r
2195     ptr = ion_map_kernel(ion_client, handle);\r
2196 \r
2197     ion_phys(ion_client, handle, phy, &size);\r
2198 \r
2199         memcpy(ptr, tbl, len);\r
2200 \r
2201         return ptr;\r
2202 }\r
2203 \r
2204 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2205 {\r
2206         int size = (len+15) & (~15);\r
2207     struct ion_handle *handle;\r
2208         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2209 \r
2210     if (ion_client == NULL) {\r
2211         ion_client = rockchip_ion_client_create("vcodec");\r
2212     }\r
2213 \r
2214     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2215 \r
2216     ptr = ion_map_kernel(ion_client, handle);\r
2217 \r
2218     ion_phys(ion_client, handle, phy, &size);\r
2219 \r
2220         return ptr;\r
2221 }\r
2222 \r
2223 #define TEST_CNT    2\r
2224 static int hevc_test_case0(vpu_service_info *pservice)\r
2225 {\r
2226     vpu_session session;\r
2227     vpu_reg *reg; \r
2228     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2229     int testidx = 0;\r
2230     int ret = 0;\r
2231 \r
2232     u8 *pps_tbl[TEST_CNT];\r
2233     u8 *register_tbl[TEST_CNT];\r
2234     u8 *rps_tbl[TEST_CNT];\r
2235     u8 *scaling_list_tbl[TEST_CNT];\r
2236     u8 *stream_tbl[TEST_CNT];\r
2237 \r
2238         int stream_size[2];\r
2239         int pps_size[2];\r
2240         int rps_size[2];\r
2241         int scl_size[2];\r
2242         int cabac_size[2];\r
2243         \r
2244     u32 phy_pps;\r
2245     u32 phy_rps;\r
2246     u32 phy_scl;\r
2247     u32 phy_str;\r
2248     u32 phy_yuv;\r
2249     u32 phy_ref;\r
2250     u32 phy_cabac;\r
2251 \r
2252         volatile u8 *stream_buf;\r
2253         volatile u8 *pps_buf;\r
2254         volatile u8 *rps_buf;\r
2255         volatile u8 *scl_buf;\r
2256         volatile u8 *yuv_buf;\r
2257         volatile u8 *cabac_buf;\r
2258         volatile u8 *ref_buf;\r
2259 \r
2260     u8 *pps;\r
2261     u8 *yuv[2];\r
2262     int i;\r
2263     \r
2264     pps_tbl[0] = pps_00;\r
2265     pps_tbl[1] = pps_01;\r
2266 \r
2267     register_tbl[0] = register_00;\r
2268     register_tbl[1] = register_01;\r
2269     \r
2270     rps_tbl[0] = rps_00;\r
2271     rps_tbl[1] = rps_01;\r
2272     \r
2273     scaling_list_tbl[0] = scaling_list_00;\r
2274     scaling_list_tbl[1] = scaling_list_01;\r
2275 \r
2276     stream_tbl[0] = stream_00;\r
2277     stream_tbl[1] = stream_01;\r
2278 \r
2279     stream_size[0] = sizeof(stream_00);\r
2280     stream_size[1] = sizeof(stream_01);\r
2281 \r
2282         pps_size[0] = sizeof(pps_00);\r
2283         pps_size[1] = sizeof(pps_01);\r
2284 \r
2285         rps_size[0] = sizeof(rps_00);\r
2286         rps_size[1] = sizeof(rps_01);\r
2287 \r
2288         scl_size[0] = sizeof(scaling_list_00);\r
2289         scl_size[1] = sizeof(scaling_list_01);\r
2290         \r
2291         cabac_size[0] = sizeof(Cabac_table);\r
2292         cabac_size[1] = sizeof(Cabac_table);\r
2293 \r
2294     // create session\r
2295     session.pid = current->pid;\r
2296     session.type = VPU_DEC;\r
2297     INIT_LIST_HEAD(&session.waiting);\r
2298         INIT_LIST_HEAD(&session.running);\r
2299         INIT_LIST_HEAD(&session.done);\r
2300         INIT_LIST_HEAD(&session.list_session);\r
2301         init_waitqueue_head(&session.wait);\r
2302         atomic_set(&session.task_running, 0);\r
2303         list_add_tail(&session.list_session, &pservice->session);\r
2304 \r
2305     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2306     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2307 \r
2308         while (testidx < TEST_CNT) {\r
2309         \r
2310         // create registers\r
2311         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2312         if (NULL == reg) {\r
2313             pr_err("error: kmalloc fail in reg_init\n");\r
2314             return -1;\r
2315         }\r
2316 \r
2317 \r
2318         if (size > pservice->reg_size) {\r
2319             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2320             size = pservice->reg_size;\r
2321         }\r
2322         reg->session = &session;\r
2323         reg->type = session.type;\r
2324         reg->size = size;\r
2325         reg->freq = VPU_FREQ_DEFAULT;\r
2326         reg->reg = (unsigned long *)&reg[1];\r
2327         INIT_LIST_HEAD(&reg->session_link);\r
2328         INIT_LIST_HEAD(&reg->status_link);\r
2329 \r
2330         // TODO: stuff registers\r
2331         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2332 \r
2333                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2334                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2335                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2336                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2337                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2338 \r
2339                 pps = pps_buf;\r
2340 \r
2341         // TODO: replace reigster address\r
2342 \r
2343         for (i=0; i<64; i++) {\r
2344             u32 scaling_offset;\r
2345             u32 tmp;\r
2346 \r
2347             scaling_offset = (u32)pps[i*80+74];\r
2348             scaling_offset += (u32)pps[i*80+75] << 8;\r
2349             scaling_offset += (u32)pps[i*80+76] << 16;\r
2350             scaling_offset += (u32)pps[i*80+77] << 24;\r
2351 \r
2352             tmp = phy_scl + scaling_offset;\r
2353 \r
2354             pps[i*80+74] = tmp & 0xff;\r
2355             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2356             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2357             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2358         }\r
2359 \r
2360         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2361 \r
2362         reg->reg[1] = 0x21;\r
2363         reg->reg[4] = phy_str;\r
2364         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2365         reg->reg[6] = phy_cabac;\r
2366         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2367         reg->reg[42] = phy_pps;\r
2368         reg->reg[43] = phy_rps;\r
2369         for (i = 10; i <= 24; i++) {\r
2370             reg->reg[i] = phy_yuv;\r
2371         }\r
2372 \r
2373         mutex_lock(&pservice->lock);\r
2374         list_add_tail(&reg->status_link, &pservice->waiting);\r
2375         list_add_tail(&reg->session_link, &session.waiting);\r
2376         mutex_unlock(&pservice->lock);\r
2377 \r
2378         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2379 \r
2380         // stuff hardware\r
2381         try_set_reg(pservice);\r
2382 \r
2383         // wait for result\r
2384         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2385         if (!list_empty(&session.done)) {\r
2386             if (ret < 0) {\r
2387                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2388             }\r
2389             ret = 0;\r
2390         } else {\r
2391             if (unlikely(ret < 0)) {\r
2392                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2393             } else if (0 == ret) {\r
2394                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2395                 ret = -ETIMEDOUT;\r
2396             }\r
2397         }\r
2398         if (ret < 0) {\r
2399             int task_running = atomic_read(&session.task_running);\r
2400             int n;\r
2401             mutex_lock(&pservice->lock);\r
2402             vpu_service_dump(pservice);\r
2403             if (task_running) {\r
2404                 atomic_set(&session.task_running, 0);\r
2405                 atomic_sub(task_running, &pservice->total_running);\r
2406                 printk("%d task is running but not return, reset hardware...", task_running);\r
2407                 vpu_reset(pservice);\r
2408                 printk("done\n");\r
2409             }\r
2410             vpu_service_session_clear(pservice, &session);\r
2411             mutex_unlock(&pservice->lock);\r
2412 \r
2413             printk("\nDEC Registers:\n");\r
2414                 n = pservice->dec_dev.iosize >> 2;\r
2415                 for (i=0; i<n; i++) {\r
2416                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2417                 }\r
2418 \r
2419             pr_err("test index %d failed\n", testidx);\r
2420             break;\r
2421         } else {\r
2422             pr_info("test index %d success\n", testidx);\r
2423 \r
2424             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2425 \r
2426             for (i=0; i<68; i++) {\r
2427                 if (i % 4 == 0) {\r
2428                     printk("%02d: ", i);\r
2429                 }\r
2430                 printk("%08x ", reg->reg[i]);\r
2431                 if ((i+1) % 4 == 0) {\r
2432                     printk("\n");\r
2433                 }\r
2434             }\r
2435 \r
2436             testidx++;\r
2437         }\r
2438 \r
2439         reg_deinit(pservice, reg);\r
2440     }\r
2441 \r
2442     return 0;\r
2443 }\r
2444 \r
2445 #endif\r
2446 \r