arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 //#define CONFIG_VCODEC_MMU\r
  47 \r
  48 #ifdef CONFIG_VCODEC_MMU\r
  49 #include <linux/rockchip/iovmm.h>\r
  50 #include <linux/rockchip/sysmmu.h>\r
  51 #include <linux/dma-buf.h>\r
  52 #endif\r
  53 \r
  54 #ifdef CONFIG_DEBUG_FS\r
  55 #include <linux/debugfs.h>\r
  56 #endif\r
  57 \r
  58 #if defined(CONFIG_ARCH_RK319X)\r
  59 #include <mach/grf.h>\r
  60 #endif\r
  61 \r
  62 #include "vcodec_service.h"\r
  63 \r
  64 #define HEVC_TEST_ENABLE    0\r
  65 #define HEVC_SIM_ENABLE         0\r
  66 #define VCODEC_CLOCK_ENABLE 1\r
  67 \r
  68 typedef enum {\r
  69         VPU_DEC_ID_9190         = 0x6731,\r
  70         VPU_ID_8270             = 0x8270,\r
  71         VPU_ID_4831             = 0x4831,\r
  72     HEVC_ID         = 0x6867,\r
  73 } VPU_HW_ID;\r
  74 \r
  75 typedef enum {\r
  76         VPU_DEC_TYPE_9190       = 0,\r
  77         VPU_ENC_TYPE_8270       = 0x100,\r
  78         VPU_ENC_TYPE_4831       ,\r
  79 } VPU_HW_TYPE_E;\r
  80 \r
  81 typedef enum VPU_FREQ {\r
  82         VPU_FREQ_200M,\r
  83         VPU_FREQ_266M,\r
  84         VPU_FREQ_300M,\r
  85         VPU_FREQ_400M,\r
  86         VPU_FREQ_DEFAULT,\r
  87         VPU_FREQ_BUT,\r
  88 } VPU_FREQ;\r
  89 \r
  90 typedef struct {\r
  91         VPU_HW_ID               hw_id;\r
  92         unsigned long           hw_addr;\r
  93         unsigned long           enc_offset;\r
  94         unsigned long           enc_reg_num;\r
  95         unsigned long           enc_io_size;\r
  96         unsigned long           dec_offset;\r
  97         unsigned long           dec_reg_num;\r
  98         unsigned long           dec_io_size;\r
  99 } VPU_HW_INFO_E;\r
 100 \r
 101 #define VPU_SERVICE_SHOW_TIME                   0\r
 102 \r
 103 #if VPU_SERVICE_SHOW_TIME\r
 104 static struct timeval enc_start, enc_end;\r
 105 static struct timeval dec_start, dec_end;\r
 106 static struct timeval pp_start,  pp_end;\r
 107 #endif\r
 108 \r
 109 #define MHZ                                     (1000*1000)\r
 110 \r
 111 #define REG_NUM_9190_DEC                        (60)\r
 112 #define REG_NUM_9190_PP                         (41)\r
 113 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 114 \r
 115 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 116 \r
 117 #define REG_NUM_ENC_8270                        (96)\r
 118 #define REG_SIZE_ENC_8270                       (0x200)\r
 119 #define REG_NUM_ENC_4831                        (164)\r
 120 #define REG_SIZE_ENC_4831                       (0x400)\r
 121 \r
 122 #define REG_NUM_HEVC_DEC            (68)\r
 123 \r
 124 #define SIZE_REG(reg)                           ((reg)*4)\r
 125 \r
 126 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 127         [0] = {\r
 128                 .hw_id          = VPU_ID_8270,\r
 129                 .hw_addr        = 0,\r
 130                 .enc_offset     = 0x0,\r
 131                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 132                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 133                 .dec_offset     = REG_SIZE_ENC_8270,\r
 134                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 135                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 136         },\r
 137         [1] = {\r
 138                 .hw_id          = VPU_ID_4831,\r
 139                 .hw_addr        = 0,\r
 140                 .enc_offset     = 0x0,\r
 141                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 142                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 143                 .dec_offset     = REG_SIZE_ENC_4831,\r
 144                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 145                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 146         },\r
 147     [2] = {\r
 148         .hw_id      = HEVC_ID,\r
 149         .hw_addr    = 0,\r
 150         .dec_offset = 0x0,\r
 151         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 152         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 153     },\r
 154 };\r
 155 \r
 156 \r
 157 #define DEC_INTERRUPT_REGISTER                  1\r
 158 #define PP_INTERRUPT_REGISTER                   60\r
 159 #define ENC_INTERRUPT_REGISTER                  1\r
 160 \r
 161 #define DEC_INTERRUPT_BIT                       0x100\r
 162 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 163 #define PP_INTERRUPT_BIT                        0x100\r
 164 #define ENC_INTERRUPT_BIT                       0x1\r
 165 \r
 166 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 167 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 168 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 169 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 170 \r
 171 #define VPU_REG_EN_ENC                          14\r
 172 #define VPU_REG_ENC_GATE                        2\r
 173 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 174 \r
 175 #define VPU_REG_EN_DEC                          1\r
 176 #define VPU_REG_DEC_GATE                        2\r
 177 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 178 #define VPU_REG_EN_PP                           0\r
 179 #define VPU_REG_PP_GATE                         1\r
 180 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 181 #define VPU_REG_EN_DEC_PP                       1\r
 182 #define VPU_REG_DEC_PP_GATE                     61\r
 183 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 184 \r
 185 /**\r
 186  * struct for process session which connect to vpu\r
 187  *\r
 188  * @author ChenHengming (2011-5-3)\r
 189  */\r
 190 typedef struct vpu_session {\r
 191         VPU_CLIENT_TYPE         type;\r
 192         /* a linked list of data so we can access them for debugging */\r
 193         struct list_head        list_session;\r
 194         /* a linked list of register data waiting for process */\r
 195         struct list_head        waiting;\r
 196         /* a linked list of register data in processing */\r
 197         struct list_head        running;\r
 198         /* a linked list of register data processed */\r
 199         struct list_head        done;\r
 200         wait_queue_head_t       wait;\r
 201         pid_t                   pid;\r
 202         atomic_t                task_running;\r
 203 } vpu_session;\r
 204 \r
 205 /**\r
 206  * struct for process register set\r
 207  *\r
 208  * @author ChenHengming (2011-5-4)\r
 209  */\r
 210 typedef struct vpu_reg {\r
 211         VPU_CLIENT_TYPE         type;\r
 212         VPU_FREQ                    freq;\r
 213         vpu_session             *session;\r
 214         struct list_head        session_link;           /* link to vpu service session */\r
 215         struct list_head        status_link;            /* link to register set list */\r
 216         unsigned long           size;\r
 217 #if defined(CONFIG_VCODEC_MMU)    \r
 218     struct list_head    mem_region_list;\r
 219 #endif    \r
 220         unsigned long           *reg;\r
 221 } vpu_reg;\r
 222 \r
 223 typedef struct vpu_device {\r
 224         atomic_t                irq_count_codec;\r
 225         atomic_t                irq_count_pp;\r
 226         unsigned long           iobaseaddr;\r
 227         unsigned int            iosize;\r
 228         volatile u32            *hwregs;\r
 229 } vpu_device;\r
 230 \r
 231 enum vcodec_device_id {\r
 232         VCODEC_DEVICE_ID_VPU,\r
 233         VCODEC_DEVICE_ID_HEVC\r
 234 };\r
 235 \r
 236 struct vcodec_mem_region {\r
 237     struct list_head srv_lnk;\r
 238     struct list_head reg_lnk;\r
 239     struct list_head session_lnk;\r
 240     dma_addr_t       iova;              /* virtual address for iommu */\r
 241     struct dma_buf   *buf;\r
 242     struct dma_buf_attachment *attachment;\r
 243     struct sg_table *sg_table;\r
 244     struct ion_handle *hdl;\r
 245 };\r
 246 \r
 247 typedef struct vpu_service_info {\r
 248         struct wake_lock        wake_lock;\r
 249         struct delayed_work     power_off_work;\r
 250         struct mutex            lock;\r
 251         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 252         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 253         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 254         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 255         atomic_t                total_running;\r
 256         bool                    enabled;\r
 257         vpu_reg                 *reg_codec;\r
 258         vpu_reg                 *reg_pproc;\r
 259         vpu_reg                 *reg_resev;\r
 260         VPUHwDecConfig_t        dec_config;\r
 261         VPUHwEncConfig_t        enc_config;\r
 262         VPU_HW_INFO_E           *hw_info;\r
 263         unsigned long           reg_size;\r
 264         bool                    auto_freq;\r
 265         bool                    bug_dec_addr;\r
 266         atomic_t                freq_status;\r
 267 \r
 268     struct clk *aclk_vcodec;\r
 269     struct clk *hclk_vcodec;\r
 270     struct clk *clk_core;\r
 271     struct clk *clk_cabac;\r
 272 \r
 273     int irq_dec;\r
 274     int irq_enc;\r
 275 \r
 276     vpu_device enc_dev;\r
 277     vpu_device dec_dev;\r
 278 \r
 279     struct device   *dev;\r
 280 \r
 281     struct cdev     cdev;\r
 282     dev_t           dev_t;\r
 283     struct class    *cls;\r
 284     struct device   *child_dev;\r
 285 \r
 286     struct dentry   *debugfs_dir;\r
 287     struct dentry   *debugfs_file_regs;\r
 288 \r
 289     u32 irq_status;\r
 290 #if defined(CONFIG_ION_ROCKCHIP)        \r
 291         struct ion_client * ion_client;\r
 292 #endif  \r
 293 \r
 294 #if defined(CONFIG_VCODEC_MMU)\r
 295     struct list_head mem_region_list;\r
 296 #endif\r
 297 \r
 298         enum vcodec_device_id dev_id;\r
 299 \r
 300     struct delayed_work simulate_work;\r
 301 } vpu_service_info;\r
 302 \r
 303 typedef struct vpu_request\r
 304 {\r
 305         unsigned long   *req;\r
 306         unsigned long   size;\r
 307 } vpu_request;\r
 308 \r
 309 /// global variable\r
 310 //static struct clk *pd_video;\r
 311 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 312 \r
 313 #ifdef CONFIG_DEBUG_FS\r
 314 static int vcodec_debugfs_init(void);\r
 315 static void vcodec_debugfs_exit(void);\r
 316 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 317 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 318 \r
 319 static const struct file_operations debug_vcodec_fops = {\r
 320         .open = debug_vcodec_open,\r
 321         .read = seq_read,\r
 322         .llseek = seq_lseek,\r
 323         .release = single_release,\r
 324 };\r
 325 #endif\r
 326 \r
 327 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 328 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 329 \r
 330 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 331 \r
 332 static void vpu_get_clk(struct vpu_service_info *pservice)\r
 333 {\r
 334 #if VCODEC_CLOCK_ENABLE\r
 335         /*pd_video      = clk_get(NULL, "pd_video");\r
 336         if (IS_ERR(pd_video)) {\r
 337                 pr_err("failed on clk_get pd_video\n");\r
 338         }*/\r
 339 \r
 340         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 341         if (IS_ERR(pservice->aclk_vcodec)) {\r
 342                 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 343         }\r
 344 \r
 345         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 346         if (IS_ERR(pservice->hclk_vcodec)) {\r
 347                 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 348         }\r
 349 \r
 350         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 351                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 352                 if (IS_ERR(pservice->clk_core)) {\r
 353                         dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 354                 }\r
 355 \r
 356                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 357                 if (IS_ERR(pservice->clk_cabac)) {\r
 358                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 359                 }\r
 360         }\r
 361 #endif\r
 362 }\r
 363 \r
 364 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 365 {\r
 366 #if VCODEC_CLOCK_ENABLE\r
 367     //clk_put(pd_video);\r
 368 \r
 369     if (pservice->aclk_vcodec) {\r
 370         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 371     }\r
 372 \r
 373     if (pservice->hclk_vcodec) {\r
 374         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 375     }\r
 376 \r
 377     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 378         if (pservice->clk_core) {\r
 379             devm_clk_put(pservice->dev, pservice->clk_core);\r
 380         }\r
 381         \r
 382         if (pservice->clk_cabac) {\r
 383             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 384         }\r
 385     }\r
 386 #endif\r
 387 }\r
 388 \r
 389 static void vpu_reset(struct vpu_service_info *pservice)\r
 390 {\r
 391 #if defined(CONFIG_ARCH_RK29)\r
 392         clk_disable(aclk_ddr_vepu);\r
 393         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 394         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 395         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 396         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 397         mdelay(10);\r
 398         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 399         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 400         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 401         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 402         clk_enable(aclk_ddr_vepu);\r
 403 #elif defined(CONFIG_ARCH_RK30)\r
 404         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 405         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 406         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 407         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 408         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 409         mdelay(1);\r
 410         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 411         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 412         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 413         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 414         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 415 #endif\r
 416         pservice->reg_codec = NULL;\r
 417         pservice->reg_pproc = NULL;\r
 418         pservice->reg_resev = NULL;\r
 419 }\r
 420 \r
 421 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 422 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 423 {\r
 424         vpu_reg *reg, *n;\r
 425         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 426                 reg_deinit(pservice, reg);\r
 427         }\r
 428         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 429                 reg_deinit(pservice, reg);\r
 430         }\r
 431         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 432                 reg_deinit(pservice, reg);\r
 433         }\r
 434 }\r
 435 \r
 436 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 437 {\r
 438         int running;\r
 439         vpu_reg *reg, *reg_tmp;\r
 440         vpu_session *session, *session_tmp;\r
 441 \r
 442         running = atomic_read(&pservice->total_running);\r
 443         printk("total_running %d\n", running);\r
 444 \r
 445         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 446         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 447         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 448 \r
 449         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 450                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 451                 running = atomic_read(&session->task_running);\r
 452                 printk("task_running %d\n", running);\r
 453                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 454                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 455                 }\r
 456                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 457                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 458                 }\r
 459                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 460                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 461                 }\r
 462         }\r
 463 }\r
 464 \r
 465 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 466 {\r
 467         int total_running;\r
 468         if (!pservice->enabled) {\r
 469                 return;\r
 470         }\r
 471 \r
 472         pservice->enabled = false;\r
 473         total_running = atomic_read(&pservice->total_running);\r
 474         if (total_running) {\r
 475                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 476                 mdelay(50);\r
 477                 pr_alert("alert: delay 50 ms for running task\n");\r
 478                 vpu_service_dump(pservice);\r
 479         }\r
 480 \r
 481         printk("%s: power off...", dev_name(pservice->dev));\r
 482 #ifdef CONFIG_ARCH_RK29\r
 483         pmu_set_power_domain(PD_VCODEC, false);\r
 484 #else\r
 485         //clk_disable(pd_video);\r
 486 #endif\r
 487         udelay(10);\r
 488 #if VCODEC_CLOCK_ENABLE\r
 489         clk_disable_unprepare(pservice->hclk_vcodec);\r
 490         clk_disable_unprepare(pservice->aclk_vcodec);\r
 491     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 492         clk_disable_unprepare(pservice->clk_core);\r
 493         clk_disable_unprepare(pservice->clk_cabac);\r
 494     }\r
 495 #endif\r
 496         wake_unlock(&pservice->wake_lock);\r
 497         printk("done\n");\r
 498 }\r
 499 \r
 500 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 501 {\r
 502         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 503 }\r
 504 \r
 505 static void vpu_power_off_work(struct work_struct *work_s)\r
 506 {\r
 507     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 508     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 509 \r
 510         if (mutex_trylock(&pservice->lock)) {\r
 511                 vpu_service_power_off(pservice);\r
 512                 mutex_unlock(&pservice->lock);\r
 513         } else {\r
 514                 /* Come back later if the device is busy... */\r
 515                 vpu_queue_power_off_work(pservice);\r
 516         }\r
 517 }\r
 518 \r
 519 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 520 {\r
 521         static ktime_t last;\r
 522         ktime_t now = ktime_get();\r
 523         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 524                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 525                 vpu_queue_power_off_work(pservice);\r
 526                 last = now;\r
 527         }\r
 528         if (pservice->enabled)\r
 529                 return ;\r
 530 \r
 531         pservice->enabled = true;\r
 532         printk("%s: power on\n", dev_name(pservice->dev));\r
 533 \r
 534 #if VCODEC_CLOCK_ENABLE\r
 535     clk_prepare_enable(pservice->aclk_vcodec);\r
 536         clk_prepare_enable(pservice->hclk_vcodec);\r
 537 \r
 538     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 539         clk_prepare_enable(pservice->clk_core);\r
 540         clk_prepare_enable(pservice->clk_cabac);\r
 541     }\r
 542 #endif\r
 543 \r
 544 #if defined(CONFIG_ARCH_RK319X)\r
 545     /// select aclk_vepu as vcodec clock source. \r
 546     #define BIT_VCODEC_SEL  (1<<7)\r
 547     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 548 #endif\r
 549         udelay(10);\r
 550 #ifdef CONFIG_ARCH_RK29\r
 551         pmu_set_power_domain(PD_VCODEC, true);\r
 552 #else\r
 553         //clk_enable(pd_video);\r
 554 #endif\r
 555         udelay(10);\r
 556         wake_lock(&pservice->wake_lock);\r
 557 }\r
 558 \r
 559 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 560 {\r
 561         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 562         return ((type == 8) || (type == 4));\r
 563 }\r
 564 \r
 565 static inline bool reg_check_interlace(vpu_reg *reg)\r
 566 {\r
 567         unsigned long type = (reg->reg[3] & (1 << 23));\r
 568         return (type > 0);\r
 569 }\r
 570 \r
 571 #if defined(CONFIG_VCODEC_MMU)\r
 572 \r
 573 static unsigned int vcodec_map_ion_handle(vpu_service_info *pservice, \r
 574                                           vpu_reg *reg,\r
 575                                           struct ion_handle *ion_handle,\r
 576                                           struct dma_buf *buf, int offset)\r
 577 {\r
 578     struct vcodec_mem_region *mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 579     if (mem_region == NULL) {\r
 580         dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 581         return -1;\r
 582     }\r
 583     \r
 584     mem_region->buf = buf;\r
 585     mem_region->hdl = ion_handle;\r
 586     \r
 587     mem_region->attachment = dma_buf_attach(buf, pservice->dev);\r
 588     if (IS_ERR_OR_NULL(mem_region->attachment)) {\r
 589         dev_err(pservice->dev, "dma_buf_attach() failed: %ld\n", PTR_ERR(mem_region->attachment));\r
 590         goto err_buf_map_attach;\r
 591     }\r
 592     \r
 593     mem_region->sg_table = dma_buf_map_attachment(mem_region->attachment, DMA_BIDIRECTIONAL);\r
 594     if (IS_ERR_OR_NULL(mem_region->sg_table)) {\r
 595         dev_err(pservice->dev, "dma_buf_map_attachment() failed: %ld\n", PTR_ERR(mem_region->sg_table));\r
 596         goto err_buf_map_attachment;\r
 597     }\r
 598     \r
 599     mem_region->iova = iovmm_map(pservice->dev, mem_region->sg_table->sgl, offset, buf->size);\r
 600     if (mem_region->iova == 0 || IS_ERR_VALUE(mem_region->iova)) {\r
 601         dev_err(pservice->dev, "iovmm_map() failed: %d\n", mem_region->iova);\r
 602         goto err_iovmm_map;\r
 603     }\r
 604     \r
 605     INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 606     list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 607     \r
 608     return mem_region->iova;\r
 609     \r
 610 err_iovmm_map:\r
 611         dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);\r
 612 err_buf_map_attachment:\r
 613         dma_buf_detach(buf, mem_region->attachment);\r
 614 err_buf_map_attach:\r
 615     kfree(mem_region);\r
 616         return 0;\r
 617 }\r
 618 \r
 619 static u8 table_vpu_dec[] = {\r
 620         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 621 };\r
 622 \r
 623 static u8 table_vpu_enc[] = {\r
 624         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 625 };\r
 626 \r
 627 static u8 table_hevc_dec[1] = {\r
 628 \r
 629 };\r
 630 \r
 631 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 632 {\r
 633         VPU_HW_ID hw_id;\r
 634         int i;\r
 635 \r
 636         hw_id = pservice->hw_info->hw_id;\r
 637 \r
 638     if (hw_id == HEVC_ID) {\r
 639 \r
 640     } else {\r
 641         if (reg->type == VPU_DEC) {\r
 642             for (i=0; i<sizeof(table_vpu_dec); i++) {\r
 643                                 int usr_fd;\r
 644                                 struct ion_handle *hdl;\r
 645                                 //ion_phys_addr_t phy_addr;\r
 646                 struct dma_buf *buf;\r
 647                                 //size_t len;\r
 648                                 int offset;\r
 649 \r
 650 #if 0\r
 651                                 if (copy_from_user(&usr_fd, &reg->reg[table_vpu_dec[i]], sizeof(usr_fd)))\r
 652                                         return -EFAULT;\r
 653 #else\r
 654                                 usr_fd = reg->reg[table_vpu_dec[i]] & 0xFF;\r
 655                                 offset = reg->reg[table_vpu_dec[i]] >> 8;\r
 656 #endif\r
 657                 if (usr_fd != 0) {\r
 658 \r
 659                                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 660                     if (IS_ERR(hdl)) {\r
 661                                                 pr_err("import dma-buf from fd %d failed\n", usr_fd);\r
 662                                                 return PTR_ERR(hdl);\r
 663                     }\r
 664 \r
 665 #if 0\r
 666                                         ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 667 \r
 668                                         reg->reg[table_vpu_dec[i]] = phy_addr + offset;\r
 669                     \r
 670                     ion_free(pservice->ion_client, hdl);\r
 671 #else \r
 672                     buf = ion_share_dma_buf(pservice->ion_client, hdl);\r
 673                     if (IS_ERR_OR_NULL(buf)) {\r
 674                         dev_err(pservice->dev, "ion_share_dma_buf() failed\n");\r
 675                         ion_free(pservice->ion_client, hdl);\r
 676                         return PTR_ERR(buf);\r
 677                     }\r
 678                     \r
 679                     reg->reg[table_vpu_dec[i]] = vcodec_map_ion_handle(pservice, reg, hdl, buf, offset);\r
 680 #endif\r
 681                                         \r
 682                 }\r
 683             }\r
 684         } else if (reg->type == VPU_ENC) {\r
 685 \r
 686         }\r
 687         }\r
 688 \r
 689         return 0;\r
 690 }\r
 691 #endif\r
 692 \r
 693 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 694 {\r
 695         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 696         if (NULL == reg) {\r
 697                 pr_err("error: kmalloc fail in reg_init\n");\r
 698                 return NULL;\r
 699         }\r
 700 \r
 701         if (size > pservice->reg_size) {\r
 702                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 703                 size = pservice->reg_size;\r
 704         }\r
 705         reg->session = session;\r
 706         reg->type = session->type;\r
 707         reg->size = size;\r
 708         reg->freq = VPU_FREQ_DEFAULT;\r
 709         reg->reg = (unsigned long *)&reg[1];\r
 710         INIT_LIST_HEAD(&reg->session_link);\r
 711         INIT_LIST_HEAD(&reg->status_link);\r
 712 \r
 713 #if defined(CONFIG_VCODEC_MMU)    \r
 714     INIT_LIST_HEAD(&reg->mem_region_list);\r
 715 #endif    \r
 716 \r
 717         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 718                 pr_err("error: copy_from_user failed in reg_init\n");\r
 719                 kfree(reg);\r
 720                 return NULL;\r
 721         }\r
 722 \r
 723 #if defined(CONFIG_VCODEC_MMU)\r
 724     if (0 > vcodec_reg_address_translate(pservice, reg)) {\r
 725                 pr_err("error: translate reg address failed\n");\r
 726                 kfree(reg);\r
 727                 return NULL;\r
 728     }\r
 729 #endif\r
 730 \r
 731         mutex_lock(&pservice->lock);\r
 732         list_add_tail(&reg->status_link, &pservice->waiting);\r
 733         list_add_tail(&reg->session_link, &session->waiting);\r
 734         mutex_unlock(&pservice->lock);\r
 735 \r
 736         if (pservice->auto_freq) {\r
 737                 if (!soc_is_rk2928g()) {\r
 738                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 739                                 if (reg_check_rmvb_wmv(reg)) {\r
 740                                         reg->freq = VPU_FREQ_200M;\r
 741                                 } else {\r
 742                                         if (reg_check_interlace(reg)) {\r
 743                                                 reg->freq = VPU_FREQ_400M;\r
 744                                         }\r
 745                                 }\r
 746                         }\r
 747                         if (reg->type == VPU_PP) {\r
 748                                 reg->freq = VPU_FREQ_400M;\r
 749                         }\r
 750                 }\r
 751         }\r
 752 \r
 753         return reg;\r
 754 }\r
 755 \r
 756 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 757 {\r
 758 #if defined(CONFIG_VCODEC_MMU)    \r
 759     struct vcodec_mem_region *mem_region = NULL, *n;\r
 760 #endif\r
 761     \r
 762         list_del_init(&reg->session_link);\r
 763         list_del_init(&reg->status_link);\r
 764         if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 765         if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 766     \r
 767 #if defined(CONFIG_VCODEC_MMU)\r
 768     // release memory region attach to this registers table.\r
 769     list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 770         iovmm_unmap(pservice->dev, mem_region->iova);\r
 771         \r
 772         dma_buf_unmap_attachment(mem_region->attachment, mem_region->sg_table, DMA_BIDIRECTIONAL);\r
 773         dma_buf_detach(mem_region->buf, mem_region->attachment);\r
 774         \r
 775         dma_buf_put(mem_region->buf);\r
 776         ion_free(pservice->ion_client, mem_region->hdl);\r
 777         \r
 778         list_del_init(&mem_region->reg_lnk);\r
 779         \r
 780         kfree(mem_region);\r
 781     }\r
 782 #endif    \r
 783     \r
 784         kfree(reg);\r
 785 }\r
 786 \r
 787 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 788 {\r
 789         list_del_init(&reg->status_link);\r
 790         list_add_tail(&reg->status_link, &pservice->running);\r
 791 \r
 792         list_del_init(&reg->session_link);\r
 793         list_add_tail(&reg->session_link, &reg->session->running);\r
 794 }\r
 795 \r
 796 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 797 {\r
 798         int i;\r
 799         u32 *dst = (u32 *)&reg->reg[0];\r
 800         for (i = 0; i < count; i++)\r
 801                 *dst++ = *src++;\r
 802 }\r
 803 \r
 804 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 805 {\r
 806     int irq_reg = -1;\r
 807         list_del_init(&reg->status_link);\r
 808         list_add_tail(&reg->status_link, &pservice->done);\r
 809 \r
 810         list_del_init(&reg->session_link);\r
 811         list_add_tail(&reg->session_link, &reg->session->done);\r
 812 \r
 813         switch (reg->type) {\r
 814         case VPU_ENC : {\r
 815                 pservice->reg_codec = NULL;\r
 816                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 817                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 818                 break;\r
 819         }\r
 820         case VPU_DEC : {\r
 821         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 822                 pservice->reg_codec = NULL;\r
 823                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 824                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 825                 break;\r
 826         }\r
 827         case VPU_PP : {\r
 828                 pservice->reg_pproc = NULL;\r
 829                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 830                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 831                 break;\r
 832         }\r
 833         case VPU_DEC_PP : {\r
 834                 pservice->reg_codec = NULL;\r
 835                 pservice->reg_pproc = NULL;\r
 836                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 837                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 838                 break;\r
 839         }\r
 840         default : {\r
 841                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 842                 break;\r
 843         }\r
 844         }\r
 845 \r
 846     if (irq_reg != -1) {\r
 847         reg->reg[irq_reg] = pservice->irq_status;\r
 848     }\r
 849 \r
 850         atomic_sub(1, &reg->session->task_running);\r
 851         atomic_sub(1, &pservice->total_running);\r
 852         wake_up(&reg->session->wait);\r
 853 }\r
 854 \r
 855 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 856 {\r
 857         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 858         if (curr == reg->freq) {\r
 859                 return ;\r
 860         }\r
 861         atomic_set(&pservice->freq_status, reg->freq);\r
 862         switch (reg->freq) {\r
 863         case VPU_FREQ_200M : {\r
 864                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 865                 //printk("default: 200M\n");\r
 866         } break;\r
 867         case VPU_FREQ_266M : {\r
 868                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 869                 //printk("default: 266M\n");\r
 870         } break;\r
 871         case VPU_FREQ_300M : {\r
 872                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 873                 //printk("default: 300M\n");\r
 874         } break;\r
 875         case VPU_FREQ_400M : {\r
 876                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 877                 //printk("default: 400M\n");\r
 878         } break;\r
 879         default : {\r
 880                 if (soc_is_rk2928g()) {\r
 881                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 882                 } else {\r
 883                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 884                 }\r
 885                 //printk("default: 300M\n");\r
 886         } break;\r
 887         }\r
 888 }\r
 889 \r
 890 #if HEVC_SIM_ENABLE\r
 891 static void simulate_start(struct vpu_service_info *pservice);\r
 892 #endif\r
 893 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 894 {\r
 895         int i;\r
 896         u32 *src = (u32 *)&reg->reg[0];\r
 897         atomic_add(1, &pservice->total_running);\r
 898         atomic_add(1, &reg->session->task_running);\r
 899         if (pservice->auto_freq) {\r
 900                 vpu_service_set_freq(pservice, reg);\r
 901         }\r
 902         switch (reg->type) {\r
 903         case VPU_ENC : {\r
 904                 int enc_count = pservice->hw_info->enc_reg_num;\r
 905                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 906 #if 0\r
 907                 if (pservice->bug_dec_addr) {\r
 908 #if !defined(CONFIG_ARCH_RK319X)\r
 909                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 910 #endif\r
 911                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 912                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 913 #if !defined(CONFIG_ARCH_RK319X)\r
 914                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 915 #endif\r
 916                 }\r
 917 #endif\r
 918                 pservice->reg_codec = reg;\r
 919 \r
 920                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 921 \r
 922                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 923                         dst[i] = src[i];\r
 924 \r
 925                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 926                         dst[i] = src[i];\r
 927 \r
 928                 dsb();\r
 929 \r
 930                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 931                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 932 \r
 933 #if VPU_SERVICE_SHOW_TIME\r
 934                 do_gettimeofday(&enc_start);\r
 935 #endif\r
 936 \r
 937         } break;\r
 938         case VPU_DEC : {\r
 939                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 940 \r
 941                 pservice->reg_codec = reg;\r
 942 \r
 943         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 944                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 945                                 dst[i] = src[i];\r
 946         } else {\r
 947             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 948                                 dst[i] = src[i];\r
 949             }\r
 950                 }\r
 951 \r
 952                 dsb();\r
 953 \r
 954                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 955                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 956                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 957                 } else {\r
 958                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 959                 }\r
 960         dsb();\r
 961         dmb();\r
 962 \r
 963 #if VPU_SERVICE_SHOW_TIME\r
 964                 do_gettimeofday(&dec_start);\r
 965 #endif\r
 966 \r
 967         } break;\r
 968         case VPU_PP : {\r
 969                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 970                 pservice->reg_pproc = reg;\r
 971 \r
 972                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 973 \r
 974                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
 975                         dst[i] = src[i];\r
 976 \r
 977                 dsb();\r
 978 \r
 979                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
 980 \r
 981 #if VPU_SERVICE_SHOW_TIME\r
 982                 do_gettimeofday(&pp_start);\r
 983 #endif\r
 984 \r
 985         } break;\r
 986         case VPU_DEC_PP : {\r
 987                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 988                 pservice->reg_codec = reg;\r
 989                 pservice->reg_pproc = reg;\r
 990 \r
 991                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
 992                         dst[i] = src[i];\r
 993 \r
 994                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
 995                 dsb();\r
 996 \r
 997                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 998                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
 999                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1000 \r
1001 #if VPU_SERVICE_SHOW_TIME\r
1002                 do_gettimeofday(&dec_start);\r
1003 #endif\r
1004 \r
1005         } break;\r
1006         default : {\r
1007                 pr_err("error: unsupport session type %d", reg->type);\r
1008                 atomic_sub(1, &pservice->total_running);\r
1009                 atomic_sub(1, &reg->session->task_running);\r
1010                 break;\r
1011         }\r
1012         }\r
1013 \r
1014 #if HEVC_SIM_ENABLE\r
1015     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1016         simulate_start(pservice);\r
1017     }\r
1018 #endif\r
1019 }\r
1020 \r
1021 static void try_set_reg(struct vpu_service_info *pservice)\r
1022 {\r
1023         // first get reg from reg list\r
1024         if (!list_empty(&pservice->waiting)) {\r
1025                 int can_set = 0;\r
1026                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1027 \r
1028                 vpu_service_power_on(pservice);\r
1029 \r
1030                 switch (reg->type) {\r
1031                 case VPU_ENC : {\r
1032                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1033                                 can_set = 1;\r
1034                 } break;\r
1035                 case VPU_DEC : {\r
1036                         if (NULL == pservice->reg_codec)\r
1037                                 can_set = 1;\r
1038                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1039                                 can_set = 0;\r
1040                         }\r
1041                 } break;\r
1042                 case VPU_PP : {\r
1043                         if (NULL == pservice->reg_codec) {\r
1044                                 if (NULL == pservice->reg_pproc)\r
1045                                         can_set = 1;\r
1046                         } else {\r
1047                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1048                                         can_set = 1;\r
1049                                 // can not charge frequency when vpu is working\r
1050                                 if (pservice->auto_freq) {\r
1051                                         can_set = 0;\r
1052                                 }\r
1053                         }\r
1054                 } break;\r
1055                 case VPU_DEC_PP : {\r
1056                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1057                                 can_set = 1;\r
1058                         } break;\r
1059                 default : {\r
1060                         printk("undefined reg type %d\n", reg->type);\r
1061                 } break;\r
1062                 }\r
1063                 if (can_set) {\r
1064                         reg_from_wait_to_run(pservice, reg);\r
1065                         reg_copy_to_hw(pservice, reg);\r
1066                 }\r
1067         }\r
1068 }\r
1069 \r
1070 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1071 {\r
1072         int ret = 0;\r
1073         switch (reg->type) {\r
1074         case VPU_ENC : {\r
1075                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1076                         ret = -EFAULT;\r
1077                 break;\r
1078         }\r
1079         case VPU_DEC : {\r
1080         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1081                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1082                         ret = -EFAULT;\r
1083                 break;\r
1084         }\r
1085         case VPU_PP : {\r
1086                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1087                         ret = -EFAULT;\r
1088                 break;\r
1089         }\r
1090         case VPU_DEC_PP : {\r
1091                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1092                         ret = -EFAULT;\r
1093                 break;\r
1094         }\r
1095         default : {\r
1096                 ret = -EFAULT;\r
1097                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1098                 break;\r
1099         }\r
1100         }\r
1101         reg_deinit(pservice, reg);\r
1102         return ret;\r
1103 }\r
1104 \r
1105 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1106 {\r
1107     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1108         vpu_session *session = (vpu_session *)filp->private_data;\r
1109         if (NULL == session) {\r
1110                 return -EINVAL;\r
1111         }\r
1112 \r
1113         switch (cmd) {\r
1114         case VPU_IOC_SET_CLIENT_TYPE : {\r
1115                 session->type = (VPU_CLIENT_TYPE)arg;\r
1116                 break;\r
1117         }\r
1118         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1119                 vpu_request req;\r
1120                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1121                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1122                         return -EFAULT;\r
1123                 } else {\r
1124                         if (VPU_ENC != session->type) {\r
1125                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1126                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1127                                         return -EFAULT;\r
1128                                 }\r
1129                         } else {\r
1130                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1131                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1132                                         return -EFAULT;\r
1133                                 }\r
1134                         }\r
1135                 }\r
1136 \r
1137                 break;\r
1138         }\r
1139         case VPU_IOC_SET_REG : {\r
1140                 vpu_request req;\r
1141                 vpu_reg *reg;\r
1142                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1143                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1144                         return -EFAULT;\r
1145                 }\r
1146                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1147                 if (NULL == reg) {\r
1148                         return -EFAULT;\r
1149                 } else {\r
1150                         mutex_lock(&pservice->lock);\r
1151                         try_set_reg(pservice);\r
1152                         mutex_unlock(&pservice->lock);\r
1153                 }\r
1154 \r
1155                 break;\r
1156         }\r
1157         case VPU_IOC_GET_REG : {\r
1158                 vpu_request req;\r
1159                 vpu_reg *reg;\r
1160                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1161                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1162                         return -EFAULT;\r
1163                 } else {\r
1164                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1165                         if (!list_empty(&session->done)) {\r
1166                                 if (ret < 0) {\r
1167                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1168                                 }\r
1169                                 ret = 0;\r
1170                         } else {\r
1171                                 if (unlikely(ret < 0)) {\r
1172                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1173                                 } else if (0 == ret) {\r
1174                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1175                                         ret = -ETIMEDOUT;\r
1176                                 }\r
1177                         }\r
1178                         if (ret < 0) {\r
1179                                 int task_running = atomic_read(&session->task_running);\r
1180                                 mutex_lock(&pservice->lock);\r
1181                                 vpu_service_dump(pservice);\r
1182                                 if (task_running) {\r
1183                                         atomic_set(&session->task_running, 0);\r
1184                                         atomic_sub(task_running, &pservice->total_running);\r
1185                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1186                                         vpu_reset(pservice);\r
1187                                         printk("done\n");\r
1188                                 }\r
1189                                 vpu_service_session_clear(pservice, session);\r
1190                                 mutex_unlock(&pservice->lock);\r
1191                                 return ret;\r
1192                         }\r
1193                 }\r
1194                 mutex_lock(&pservice->lock);\r
1195                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1196                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1197                 mutex_unlock(&pservice->lock);\r
1198                 break;\r
1199         }\r
1200         default : {\r
1201                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1202                 break;\r
1203         }\r
1204         }\r
1205 \r
1206         return 0;\r
1207 }\r
1208 \r
1209 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1210 {\r
1211         int ret = -EINVAL, i = 0;\r
1212         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1213         u32 enc_id = *tmp;\r
1214 \r
1215 #if HEVC_SIM_ENABLE\r
1216     /// temporary, hevc driver test.\r
1217     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1218         p->hw_info = &vpu_hw_set[2];\r
1219         return 0;\r
1220     }\r
1221 #endif\r
1222 \r
1223         enc_id = (enc_id >> 16) & 0xFFFF;\r
1224         pr_info("checking hw id %x\n", enc_id);\r
1225     p->hw_info = NULL;\r
1226         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1227                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1228                         p->hw_info = &vpu_hw_set[i];\r
1229                         ret = 0;\r
1230                         break;\r
1231                 }\r
1232         }\r
1233         iounmap((void *)tmp);\r
1234         return ret;\r
1235 }\r
1236 \r
1237 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1238 {\r
1239     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1240         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1241         if (NULL == session) {\r
1242                 pr_err("error: unable to allocate memory for vpu_session.");\r
1243                 return -ENOMEM;\r
1244         }\r
1245 \r
1246         session->type   = VPU_TYPE_BUTT;\r
1247         session->pid    = current->pid;\r
1248         INIT_LIST_HEAD(&session->waiting);\r
1249         INIT_LIST_HEAD(&session->running);\r
1250         INIT_LIST_HEAD(&session->done);\r
1251         INIT_LIST_HEAD(&session->list_session);\r
1252         init_waitqueue_head(&session->wait);\r
1253         atomic_set(&session->task_running, 0);\r
1254         mutex_lock(&pservice->lock);\r
1255         list_add_tail(&session->list_session, &pservice->session);\r
1256         filp->private_data = (void *)session;\r
1257         mutex_unlock(&pservice->lock);\r
1258 \r
1259         pr_debug("dev opened\n");\r
1260         return nonseekable_open(inode, filp);\r
1261 }\r
1262 \r
1263 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1264 {\r
1265     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1266         int task_running;\r
1267         vpu_session *session = (vpu_session *)filp->private_data;\r
1268         if (NULL == session)\r
1269                 return -EINVAL;\r
1270 \r
1271         task_running = atomic_read(&session->task_running);\r
1272         if (task_running) {\r
1273                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1274                 msleep(50);\r
1275         }\r
1276         wake_up(&session->wait);\r
1277 \r
1278         mutex_lock(&pservice->lock);\r
1279         /* remove this filp from the asynchronusly notified filp's */\r
1280         list_del_init(&session->list_session);\r
1281         vpu_service_session_clear(pservice, session);\r
1282         kfree(session);\r
1283         filp->private_data = NULL;\r
1284         mutex_unlock(&pservice->lock);\r
1285 \r
1286     pr_debug("dev closed\n");\r
1287         return 0;\r
1288 }\r
1289 \r
1290 static const struct file_operations vpu_service_fops = {\r
1291         .unlocked_ioctl = vpu_service_ioctl,\r
1292         .open           = vpu_service_open,\r
1293         .release        = vpu_service_release,\r
1294         //.fasync       = vpu_service_fasync,\r
1295 };\r
1296 \r
1297 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1298 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1299 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1300 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1301 static void get_hw_info(struct vpu_service_info *pservice);\r
1302 \r
1303 #if HEVC_SIM_ENABLE\r
1304 static void simulate_work(struct work_struct *work_s)\r
1305 {\r
1306     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1307     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1308     vpu_device *dev = &pservice->dec_dev;\r
1309 \r
1310     if (!list_empty(&pservice->running)) {\r
1311         atomic_add(1, &dev->irq_count_codec);\r
1312         vdpu_isr(0, (void*)pservice);\r
1313     } else {\r
1314         //simulate_start(pservice);\r
1315         pr_err("empty running queue\n");\r
1316     }\r
1317 }\r
1318 \r
1319 static void simulate_init(struct vpu_service_info *pservice)\r
1320 {\r
1321     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1322 }\r
1323 \r
1324 static void simulate_start(struct vpu_service_info *pservice)\r
1325 {\r
1326     cancel_delayed_work_sync(&pservice->power_off_work);\r
1327     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1328 }\r
1329 #endif\r
1330 \r
1331 #if HEVC_TEST_ENABLE\r
1332 static int hevc_test_case0(vpu_service_info *pservice);\r
1333 #endif\r
1334 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1335 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1336 #endif\r
1337 static int vcodec_probe(struct platform_device *pdev)\r
1338 {\r
1339     int ret = 0;\r
1340     struct resource *res = NULL;\r
1341     struct device *dev = &pdev->dev;\r
1342     void __iomem *regs = NULL;\r
1343     struct device_node *np = pdev->dev.of_node;\r
1344     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1345     char *prop = (char*)dev_name(dev);\r
1346 #if defined(CONFIG_VCODEC_MMU)\r
1347     struct device *mmu_dev = NULL;\r
1348     char mmu_dev_dts_name[40];\r
1349 #endif\r
1350 \r
1351     pr_info("probe device %s\n", dev_name(dev));\r
1352 \r
1353     of_property_read_string(np, "name", (const char**)&prop);\r
1354     dev_set_name(dev, prop);\r
1355 \r
1356         if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1357                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1358     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1359                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1360     } else {\r
1361                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1362                 return -1;\r
1363         }\r
1364 \r
1365     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1366     INIT_LIST_HEAD(&pservice->waiting);\r
1367     INIT_LIST_HEAD(&pservice->running);\r
1368     INIT_LIST_HEAD(&pservice->done);\r
1369     INIT_LIST_HEAD(&pservice->session);\r
1370     mutex_init(&pservice->lock);\r
1371     pservice->reg_codec = NULL;\r
1372     pservice->reg_pproc = NULL;\r
1373     atomic_set(&pservice->total_running, 0);\r
1374     pservice->enabled = false;\r
1375 \r
1376     pservice->dev = dev;\r
1377 \r
1378     vpu_get_clk(pservice);\r
1379 \r
1380     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1381 \r
1382     vpu_service_power_on(pservice);\r
1383 \r
1384     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1385 \r
1386     regs = devm_ioremap_resource(pservice->dev, res);\r
1387     if (IS_ERR(regs)) {\r
1388         ret = PTR_ERR(regs);\r
1389         goto err;\r
1390     }\r
1391 \r
1392     ret = vpu_service_check_hw(pservice, res->start);\r
1393     if (ret < 0) {\r
1394         pr_err("error: hw info check faild\n");\r
1395         goto err;\r
1396     }\r
1397 \r
1398     /// define regs address.\r
1399     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1400     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1401 \r
1402     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1403 \r
1404     pservice->reg_size   = pservice->dec_dev.iosize;\r
1405 \r
1406     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1407         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1408         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1409 \r
1410         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1411 \r
1412         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1413 \r
1414         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1415         if (pservice->irq_enc < 0) {\r
1416             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1417             ret = -ENXIO;\r
1418             goto err;\r
1419         }\r
1420 \r
1421         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1422         if (ret) {\r
1423             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1424             goto err;\r
1425         }\r
1426     }\r
1427 \r
1428     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1429     if (pservice->irq_dec < 0) {\r
1430         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1431         ret = -ENXIO;\r
1432         goto err;\r
1433     }\r
1434 \r
1435     /* get the IRQ line */\r
1436     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1437     if (ret) {\r
1438         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1439         goto err;\r
1440     }\r
1441 \r
1442     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1443     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1444     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1445     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1446 \r
1447     /// create device\r
1448     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1449     if (ret) {\r
1450         dev_err(dev, "alloc dev_t failed\n");\r
1451         goto err;\r
1452     }\r
1453 \r
1454     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1455 \r
1456     pservice->cdev.owner = THIS_MODULE;\r
1457     pservice->cdev.ops = &vpu_service_fops;\r
1458 \r
1459     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1460 \r
1461     if (ret) {\r
1462         dev_err(dev, "add dev_t failed\n");\r
1463         goto err;\r
1464     }\r
1465 \r
1466     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1467 \r
1468     if (IS_ERR(pservice->cls)) {\r
1469         ret = PTR_ERR(pservice->cls);\r
1470         dev_err(dev, "class_create err:%d\n", ret);\r
1471         goto err;\r
1472     }\r
1473 \r
1474     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1475 \r
1476     platform_set_drvdata(pdev, pservice);\r
1477 \r
1478     get_hw_info(pservice);\r
1479 \r
1480 \r
1481 #ifdef CONFIG_DEBUG_FS\r
1482     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1483     \r
1484     if (pservice->debugfs_dir == NULL) {\r
1485         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1486     }\r
1487 \r
1488     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1489                     pservice->debugfs_dir, pservice,\r
1490                     &debug_vcodec_fops);\r
1491 #endif\r
1492 \r
1493     vpu_service_power_off(pservice);\r
1494     pr_info("init success\n");\r
1495 \r
1496 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1497         pservice->ion_client = rockchip_ion_client_create("vpu");\r
1498         if (IS_ERR(pservice->ion_client)) {\r
1499                 dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1500                 return PTR_ERR(pservice->ion_client);\r
1501         } else {\r
1502                 dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1503         }\r
1504     \r
1505     sprintf(mmu_dev_dts_name, "iommu,%s", dev_name(dev));\r
1506     \r
1507     mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1508     platform_set_sysmmu(mmu_dev, pservice->dev);\r
1509     \r
1510     iovmm_activate(pservice->dev);\r
1511 #endif\r
1512 \r
1513 #if HEVC_SIM_ENABLE\r
1514     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1515         simulate_init(pservice);\r
1516     }\r
1517 #endif\r
1518 \r
1519 #if HEVC_TEST_ENABLE\r
1520     hevc_test_case0(pservice);\r
1521 #endif\r
1522 \r
1523     return 0;\r
1524 \r
1525 err:\r
1526     pr_info("init failed\n");\r
1527     vpu_service_power_off(pservice);\r
1528     vpu_put_clk(pservice);\r
1529     wake_lock_destroy(&pservice->wake_lock);\r
1530 \r
1531     if (res) {\r
1532         if (regs) {\r
1533             devm_ioremap_release(&pdev->dev, res);\r
1534         }\r
1535         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1536     }\r
1537 \r
1538     if (pservice->irq_enc > 0) {\r
1539         free_irq(pservice->irq_enc, (void *)pservice);\r
1540     }\r
1541 \r
1542     if (pservice->irq_dec > 0) {\r
1543         free_irq(pservice->irq_dec, (void *)pservice);\r
1544     }\r
1545 \r
1546     if (pservice->child_dev) {\r
1547         device_destroy(pservice->cls, pservice->dev_t);\r
1548         cdev_del(&pservice->cdev);\r
1549         unregister_chrdev_region(pservice->dev_t, 1);\r
1550     }\r
1551 \r
1552     if (pservice->cls) {\r
1553         class_destroy(pservice->cls);\r
1554     }\r
1555 \r
1556     return ret;\r
1557 }\r
1558 \r
1559 static int vcodec_remove(struct platform_device *pdev)\r
1560 {\r
1561     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1562     struct resource *res;\r
1563 \r
1564     device_destroy(pservice->cls, pservice->dev_t);\r
1565     class_destroy(pservice->cls);\r
1566     cdev_del(&pservice->cdev);\r
1567     unregister_chrdev_region(pservice->dev_t, 1);\r
1568 \r
1569     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1570     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1571     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1572     devm_ioremap_release(&pdev->dev, res);\r
1573     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1574     vpu_put_clk(pservice);\r
1575     wake_lock_destroy(&pservice->wake_lock);\r
1576     \r
1577 #ifdef CONFIG_DEBUG_FS\r
1578     if (pservice->debugfs_file_regs) {\r
1579         debugfs_remove(pservice->debugfs_file_regs);\r
1580     }\r
1581 \r
1582     if (pservice->debugfs_dir) {\r
1583         debugfs_remove(pservice->debugfs_dir);\r
1584     }\r
1585 #endif\r
1586 \r
1587     return 0;\r
1588 }\r
1589 \r
1590 #if defined(CONFIG_OF)\r
1591 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1592         {.compatible = "vpu_service",},\r
1593         {.compatible = "rockchip,hevc_service",},\r
1594     {},\r
1595 };\r
1596 #endif\r
1597 \r
1598 static struct platform_driver vcodec_driver = {\r
1599         .probe     = vcodec_probe,\r
1600     .remove        = vcodec_remove,\r
1601     .driver = {\r
1602         .name = "vcodec",\r
1603         .owner = THIS_MODULE,\r
1604 #if defined(CONFIG_OF)\r
1605         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1606 #endif\r
1607         },\r
1608 };\r
1609 \r
1610 static void get_hw_info(struct vpu_service_info *pservice)\r
1611 {\r
1612     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {\r
1613         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1614         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1615         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1616         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1617     \r
1618         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1619         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1620         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1621             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1622         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1623         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1624         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1625         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1626         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1627         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1628     \r
1629         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1630             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1631         } else {\r
1632             dec->maxDecPicWidth = 3840;\r
1633         }\r
1634     \r
1635         /* 2nd Config register */\r
1636         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1637         if (dec->refBufSupport) {\r
1638             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1639                 dec->refBufSupport |= 2;\r
1640             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1641                 dec->refBufSupport |= 4;\r
1642         }\r
1643         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1644         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1645         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1646         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1647     \r
1648         /* JPEG xtensions */\r
1649         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1650             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1651         } else {\r
1652             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1653         }\r
1654     \r
1655         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1656             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1657         } else {\r
1658             dec->rvSupport = RV_NOT_SUPPORTED;\r
1659         }\r
1660     \r
1661         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1662     \r
1663         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1664             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1665         }\r
1666     \r
1667         /// invalidate fuse register value in rk319x vpu and following.\r
1668         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1669             VPUHwFuseStatus_t hwFuseSts;\r
1670             /* Decoder fuse configuration */\r
1671             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1672     \r
1673             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1674             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1675             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1676             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1677             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1678             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1679             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1680             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1681             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1682             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1683             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1684             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1685             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1686             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1687     \r
1688             /* check max. decoder output width */\r
1689     \r
1690             if (fuseReg & 0x8000U)\r
1691                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1692             else if (fuseReg & 0x4000U)\r
1693                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1694             else if (fuseReg & 0x2000U)\r
1695                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1696             else if (fuseReg & 0x1000U)\r
1697                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1698             else    /* remove warning */\r
1699                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1700     \r
1701             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1702     \r
1703             /* Pp configuration */\r
1704             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1705     \r
1706             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1707                 dec->ppSupport = 1;\r
1708                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1709                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1710                 dec->ppConfig = configReg;\r
1711             } else {\r
1712                 dec->ppSupport = 0;\r
1713                 dec->maxPpOutPicWidth = 0;\r
1714                 dec->ppConfig = 0;\r
1715             }\r
1716     \r
1717             /* check the HW versio */\r
1718             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1719                 /* Pp configuration */\r
1720                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1721     \r
1722                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1723                     /* Pp fuse configuration */\r
1724                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1725     \r
1726                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1727                         hwFuseSts.ppSupportFuse = 1;\r
1728                         /* check max. pp output width */\r
1729                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1730                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1731                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1732                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1733                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1734                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1735                     } else {\r
1736                         hwFuseSts.ppSupportFuse = 0;\r
1737                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1738                         hwFuseSts.ppConfigFuse = 0;\r
1739                     }\r
1740                 } else {\r
1741                     hwFuseSts.ppSupportFuse = 0;\r
1742                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1743                     hwFuseSts.ppConfigFuse = 0;\r
1744                 }\r
1745     \r
1746                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1747                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1748                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1749                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1750                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1751                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1752                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1753                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1754                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1755                     dec->jpegSupport = JPEG_BASELINE;\r
1756                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1757                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1758                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1759                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1760                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1761                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1762     \r
1763                 /* check the pp config vs fuse status */\r
1764                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1765                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1766                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1767                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1768                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1769     \r
1770                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1771                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1772                 }\r
1773                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1774                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1775                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1776                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1777                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1778             }\r
1779         }\r
1780     \r
1781         configReg = pservice->enc_dev.hwregs[63];\r
1782         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1783         enc->h264Enabled = (configReg >> 27) & 1;\r
1784         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1785         enc->jpegEnabled = (configReg >> 25) & 1;\r
1786         enc->vsEnabled = (configReg >> 24) & 1;\r
1787         enc->rgbEnabled = (configReg >> 28) & 1;\r
1788         //enc->busType = (configReg >> 20) & 15;\r
1789         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1790         //enc->busWidth = (configReg >> 12) & 15;\r
1791         enc->reg_size = pservice->reg_size;\r
1792         enc->reserv[0] = enc->reserv[1] = 0;\r
1793     \r
1794         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();\r
1795         if (pservice->auto_freq) {\r
1796             pr_info("vpu_service set to auto frequency mode\n");\r
1797             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1798         }\r
1799         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1800         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1801     }\r
1802 }\r
1803 \r
1804 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1805 {\r
1806     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1807     vpu_device *dev = &pservice->dec_dev;\r
1808     u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1809 \r
1810         pr_debug("dec_irq\n");\r
1811 \r
1812         if (irq_status & DEC_INTERRUPT_BIT) {\r
1813                 pr_debug("dec_isr dec %x\n", irq_status);\r
1814                 if ((irq_status & 0x40001) == 0x40001)\r
1815                 {\r
1816                         do {\r
1817                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1818                         } while ((irq_status & 0x40001) == 0x40001);\r
1819                 }\r
1820 \r
1821                 /* clear dec IRQ */\r
1822         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1823             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1824         } else {\r
1825             /*writel(irq_status \r
1826               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1827                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1828 \r
1829             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1830         }\r
1831                 atomic_add(1, &dev->irq_count_codec);\r
1832         }\r
1833 \r
1834     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1835         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1836         if (irq_status & PP_INTERRUPT_BIT) {\r
1837             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1838             /* clear pp IRQ */\r
1839             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1840             atomic_add(1, &dev->irq_count_pp);\r
1841         }\r
1842     }\r
1843 \r
1844     pservice->irq_status = irq_status;\r
1845 \r
1846         return IRQ_WAKE_THREAD;\r
1847 }\r
1848 \r
1849 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1850 {\r
1851     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1852     vpu_device *dev = &pservice->dec_dev;\r
1853 \r
1854         mutex_lock(&pservice->lock);\r
1855         if (atomic_read(&dev->irq_count_codec)) {\r
1856 #if VPU_SERVICE_SHOW_TIME\r
1857                 do_gettimeofday(&dec_end);\r
1858                 pr_info("dec task: %ld ms\n",\r
1859                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1860                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1861 #endif\r
1862                 atomic_sub(1, &dev->irq_count_codec);\r
1863                 if (NULL == pservice->reg_codec) {\r
1864                         pr_err("error: dec isr with no task waiting\n");\r
1865                 } else {\r
1866                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1867                 }\r
1868         }\r
1869 \r
1870         if (atomic_read(&dev->irq_count_pp)) {\r
1871 \r
1872 #if VPU_SERVICE_SHOW_TIME\r
1873                 do_gettimeofday(&pp_end);\r
1874                 printk("pp  task: %ld ms\n",\r
1875                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1876                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1877 #endif\r
1878 \r
1879                 atomic_sub(1, &dev->irq_count_pp);\r
1880                 if (NULL == pservice->reg_pproc) {\r
1881                         pr_err("error: pp isr with no task waiting\n");\r
1882                 } else {\r
1883                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1884                 }\r
1885         }\r
1886         try_set_reg(pservice);\r
1887         mutex_unlock(&pservice->lock);\r
1888         return IRQ_HANDLED;\r
1889 }\r
1890 \r
1891 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1892 {\r
1893         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1894     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1895     vpu_device *dev = &pservice->enc_dev;\r
1896         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1897 \r
1898         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1899 \r
1900 #if VPU_SERVICE_SHOW_TIME\r
1901         do_gettimeofday(&enc_end);\r
1902         pr_info("enc task: %ld ms\n",\r
1903                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1904                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1905 #endif\r
1906 \r
1907         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1908                 /* clear enc IRQ */\r
1909                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1910                 atomic_add(1, &dev->irq_count_codec);\r
1911         }\r
1912 \r
1913         return IRQ_WAKE_THREAD;\r
1914 }\r
1915 \r
1916 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1917 {\r
1918         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1919     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1920     vpu_device *dev = &pservice->enc_dev;\r
1921 \r
1922         mutex_lock(&pservice->lock);\r
1923         if (atomic_read(&dev->irq_count_codec)) {\r
1924                 atomic_sub(1, &dev->irq_count_codec);\r
1925                 if (NULL == pservice->reg_codec) {\r
1926                         pr_err("error: enc isr with no task waiting\n");\r
1927                 } else {\r
1928                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1929                 }\r
1930         }\r
1931         try_set_reg(pservice);\r
1932         mutex_unlock(&pservice->lock);\r
1933         return IRQ_HANDLED;\r
1934 }\r
1935 \r
1936 static int __init vcodec_service_init(void)\r
1937 {\r
1938     int ret;\r
1939 \r
1940     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1941         pr_err("Platform device register failed (%d).\n", ret);\r
1942         return ret;\r
1943     }\r
1944 \r
1945 #ifdef CONFIG_DEBUG_FS\r
1946     vcodec_debugfs_init();\r
1947 #endif\r
1948 \r
1949     return ret;\r
1950 }\r
1951 \r
1952 static void __exit vcodec_service_exit(void)\r
1953 {\r
1954 #ifdef CONFIG_DEBUG_FS\r
1955     vcodec_debugfs_exit();\r
1956 #endif\r
1957 \r
1958         platform_driver_unregister(&vcodec_driver);\r
1959 }\r
1960 \r
1961 module_init(vcodec_service_init);\r
1962 module_exit(vcodec_service_exit);\r
1963 \r
1964 #ifdef CONFIG_DEBUG_FS\r
1965 #include <linux/seq_file.h>\r
1966 \r
1967 static int vcodec_debugfs_init()\r
1968 {\r
1969     parent = debugfs_create_dir("vcodec", NULL);\r
1970     if (!parent)\r
1971         return -1;\r
1972 \r
1973     return 0;\r
1974 }\r
1975 \r
1976 static void vcodec_debugfs_exit()\r
1977 {\r
1978     debugfs_remove(parent);\r
1979 }\r
1980 \r
1981 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
1982 {\r
1983     return debugfs_create_dir(dirname, parent);\r
1984 }\r
1985 \r
1986 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
1987 {\r
1988         struct vpu_service_info *pservice = s->private;\r
1989     unsigned int i, n;\r
1990         vpu_reg *reg, *reg_tmp;\r
1991         vpu_session *session, *session_tmp;\r
1992 \r
1993         mutex_lock(&pservice->lock);\r
1994         vpu_service_power_on(pservice);\r
1995     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1996         seq_printf(s, "\nENC Registers:\n");\r
1997         n = pservice->enc_dev.iosize >> 2;\r
1998         for (i = 0; i < n; i++) {\r
1999             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2000         }\r
2001     }\r
2002         seq_printf(s, "\nDEC Registers:\n");\r
2003         n = pservice->dec_dev.iosize >> 2;\r
2004         for (i = 0; i < n; i++) {\r
2005                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2006         }\r
2007 \r
2008         seq_printf(s, "\nvpu service status:\n");\r
2009         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2010                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2011                 //seq_printf(s, "waiting reg set %d\n");\r
2012                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2013                         seq_printf(s, "waiting register set\n");\r
2014                 }\r
2015                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2016                         seq_printf(s, "running register set\n");\r
2017                 }\r
2018                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2019                         seq_printf(s, "done    register set\n");\r
2020                 }\r
2021         }\r
2022         mutex_unlock(&pservice->lock);\r
2023 \r
2024     return 0;\r
2025 }\r
2026 \r
2027 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2028 {\r
2029         return single_open(file, debug_vcodec_show, inode->i_private);\r
2030 }\r
2031 \r
2032 #endif\r
2033 \r
2034 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2035 #include "hevc_test_inc/pps_00.h"\r
2036 #include "hevc_test_inc/register_00.h"\r
2037 #include "hevc_test_inc/rps_00.h"\r
2038 #include "hevc_test_inc/scaling_list_00.h"\r
2039 #include "hevc_test_inc/stream_00.h"\r
2040 \r
2041 #include "hevc_test_inc/pps_01.h"\r
2042 #include "hevc_test_inc/register_01.h"\r
2043 #include "hevc_test_inc/rps_01.h"\r
2044 #include "hevc_test_inc/scaling_list_01.h"\r
2045 #include "hevc_test_inc/stream_01.h"\r
2046 \r
2047 #include "hevc_test_inc/cabac.h"\r
2048 \r
2049 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2050 \r
2051 static struct ion_client *ion_client = NULL;\r
2052 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2053 {\r
2054         int size = (len+15) & (~15);\r
2055     struct ion_handle *handle;\r
2056         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2057 \r
2058     if (ion_client == NULL) {\r
2059         ion_client = rockchip_ion_client_create("vcodec");\r
2060     }\r
2061 \r
2062     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2063 \r
2064     ptr = ion_map_kernel(ion_client, handle);\r
2065 \r
2066     ion_phys(ion_client, handle, phy, &size);\r
2067 \r
2068         memcpy(ptr, tbl, len);\r
2069 \r
2070         return ptr;\r
2071 }\r
2072 \r
2073 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2074 {\r
2075         int size = (len+15) & (~15);\r
2076     struct ion_handle *handle;\r
2077         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2078 \r
2079     if (ion_client == NULL) {\r
2080         ion_client = rockchip_ion_client_create("vcodec");\r
2081     }\r
2082 \r
2083     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2084 \r
2085     ptr = ion_map_kernel(ion_client, handle);\r
2086 \r
2087     ion_phys(ion_client, handle, phy, &size);\r
2088 \r
2089         return ptr;\r
2090 }\r
2091 \r
2092 #define TEST_CNT    2\r
2093 static int hevc_test_case0(vpu_service_info *pservice)\r
2094 {\r
2095     vpu_session session;\r
2096     vpu_reg *reg; \r
2097     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2098     int testidx = 0;\r
2099     int ret = 0;\r
2100 \r
2101     u8 *pps_tbl[TEST_CNT];\r
2102     u8 *register_tbl[TEST_CNT];\r
2103     u8 *rps_tbl[TEST_CNT];\r
2104     u8 *scaling_list_tbl[TEST_CNT];\r
2105     u8 *stream_tbl[TEST_CNT];\r
2106 \r
2107         int stream_size[2];\r
2108         int pps_size[2];\r
2109         int rps_size[2];\r
2110         int scl_size[2];\r
2111         int cabac_size[2];\r
2112         \r
2113     u32 phy_pps;\r
2114     u32 phy_rps;\r
2115     u32 phy_scl;\r
2116     u32 phy_str;\r
2117     u32 phy_yuv;\r
2118     u32 phy_ref;\r
2119     u32 phy_cabac;\r
2120 \r
2121         volatile u8 *stream_buf;\r
2122         volatile u8 *pps_buf;\r
2123         volatile u8 *rps_buf;\r
2124         volatile u8 *scl_buf;\r
2125         volatile u8 *yuv_buf;\r
2126         volatile u8 *cabac_buf;\r
2127         volatile u8 *ref_buf;\r
2128 \r
2129     u8 *pps;\r
2130     u8 *yuv[2];\r
2131     int i;\r
2132     \r
2133     pps_tbl[0] = pps_00;\r
2134     pps_tbl[1] = pps_01;\r
2135 \r
2136     register_tbl[0] = register_00;\r
2137     register_tbl[1] = register_01;\r
2138     \r
2139     rps_tbl[0] = rps_00;\r
2140     rps_tbl[1] = rps_01;\r
2141     \r
2142     scaling_list_tbl[0] = scaling_list_00;\r
2143     scaling_list_tbl[1] = scaling_list_01;\r
2144 \r
2145     stream_tbl[0] = stream_00;\r
2146     stream_tbl[1] = stream_01;\r
2147 \r
2148     stream_size[0] = sizeof(stream_00);\r
2149     stream_size[1] = sizeof(stream_01);\r
2150 \r
2151         pps_size[0] = sizeof(pps_00);\r
2152         pps_size[1] = sizeof(pps_01);\r
2153 \r
2154         rps_size[0] = sizeof(rps_00);\r
2155         rps_size[1] = sizeof(rps_01);\r
2156 \r
2157         scl_size[0] = sizeof(scaling_list_00);\r
2158         scl_size[1] = sizeof(scaling_list_01);\r
2159         \r
2160         cabac_size[0] = sizeof(Cabac_table);\r
2161         cabac_size[1] = sizeof(Cabac_table);\r
2162 \r
2163     // create session\r
2164     session.pid = current->pid;\r
2165     session.type = VPU_DEC;\r
2166     INIT_LIST_HEAD(&session.waiting);\r
2167         INIT_LIST_HEAD(&session.running);\r
2168         INIT_LIST_HEAD(&session.done);\r
2169         INIT_LIST_HEAD(&session.list_session);\r
2170         init_waitqueue_head(&session.wait);\r
2171         atomic_set(&session.task_running, 0);\r
2172         list_add_tail(&session.list_session, &pservice->session);\r
2173 \r
2174     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2175     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2176 \r
2177         while (testidx < TEST_CNT) {\r
2178         \r
2179         // create registers\r
2180         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2181         if (NULL == reg) {\r
2182             pr_err("error: kmalloc fail in reg_init\n");\r
2183             return -1;\r
2184         }\r
2185 \r
2186 \r
2187         if (size > pservice->reg_size) {\r
2188             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2189             size = pservice->reg_size;\r
2190         }\r
2191         reg->session = &session;\r
2192         reg->type = session.type;\r
2193         reg->size = size;\r
2194         reg->freq = VPU_FREQ_DEFAULT;\r
2195         reg->reg = (unsigned long *)&reg[1];\r
2196         INIT_LIST_HEAD(&reg->session_link);\r
2197         INIT_LIST_HEAD(&reg->status_link);\r
2198 \r
2199         // TODO: stuff registers\r
2200         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2201 \r
2202                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2203                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2204                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2205                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2206                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2207 \r
2208                 pps = pps_buf;\r
2209 \r
2210         // TODO: replace reigster address\r
2211 \r
2212         for (i=0; i<64; i++) {\r
2213             u32 scaling_offset;\r
2214             u32 tmp;\r
2215 \r
2216             scaling_offset = (u32)pps[i*80+74];\r
2217             scaling_offset += (u32)pps[i*80+75] << 8;\r
2218             scaling_offset += (u32)pps[i*80+76] << 16;\r
2219             scaling_offset += (u32)pps[i*80+77] << 24;\r
2220 \r
2221             tmp = phy_scl + scaling_offset;\r
2222 \r
2223             pps[i*80+74] = tmp & 0xff;\r
2224             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2225             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2226             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2227         }\r
2228 \r
2229         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2230 \r
2231         reg->reg[1] = 0x21;\r
2232         reg->reg[4] = phy_str;\r
2233         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2234         reg->reg[6] = phy_cabac;\r
2235         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2236         reg->reg[42] = phy_pps;\r
2237         reg->reg[43] = phy_rps;\r
2238         for (i = 10; i <= 24; i++) {\r
2239             reg->reg[i] = phy_yuv;\r
2240         }\r
2241 \r
2242         mutex_lock(&pservice->lock);\r
2243         list_add_tail(&reg->status_link, &pservice->waiting);\r
2244         list_add_tail(&reg->session_link, &session.waiting);\r
2245         mutex_unlock(&pservice->lock);\r
2246 \r
2247         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2248 \r
2249         // stuff hardware\r
2250         try_set_reg(pservice);\r
2251 \r
2252         // wait for result\r
2253         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2254         if (!list_empty(&session.done)) {\r
2255             if (ret < 0) {\r
2256                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2257             }\r
2258             ret = 0;\r
2259         } else {\r
2260             if (unlikely(ret < 0)) {\r
2261                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2262             } else if (0 == ret) {\r
2263                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2264                 ret = -ETIMEDOUT;\r
2265             }\r
2266         }\r
2267         if (ret < 0) {\r
2268             int task_running = atomic_read(&session.task_running);\r
2269             int n;\r
2270             mutex_lock(&pservice->lock);\r
2271             vpu_service_dump(pservice);\r
2272             if (task_running) {\r
2273                 atomic_set(&session.task_running, 0);\r
2274                 atomic_sub(task_running, &pservice->total_running);\r
2275                 printk("%d task is running but not return, reset hardware...", task_running);\r
2276                 vpu_reset(pservice);\r
2277                 printk("done\n");\r
2278             }\r
2279             vpu_service_session_clear(pservice, &session);\r
2280             mutex_unlock(&pservice->lock);\r
2281 \r
2282             printk("\nDEC Registers:\n");\r
2283                 n = pservice->dec_dev.iosize >> 2;\r
2284                 for (i=0; i<n; i++) {\r
2285                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2286                 }\r
2287 \r
2288             pr_err("test index %d failed\n", testidx);\r
2289             break;\r
2290         } else {\r
2291             pr_info("test index %d success\n", testidx);\r
2292 \r
2293             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2294 \r
2295             for (i=0; i<68; i++) {\r
2296                 if (i % 4 == 0) {\r
2297                     printk("%02d: ", i);\r
2298                 }\r
2299                 printk("%08x ", reg->reg[i]);\r
2300                 if ((i+1) % 4 == 0) {\r
2301                     printk("\n");\r
2302                 }\r
2303             }\r
2304 \r
2305             testidx++;\r
2306         }\r
2307 \r
2308         reg_deinit(pservice, reg);\r
2309     }\r
2310 \r
2311     return 0;\r
2312 }\r
2313 \r
2314 #endif\r
2315 \r