arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #ifdef CONFIG_DEBUG_FS\r
  47 #include <linux/debugfs.h>\r
  48 #endif\r
  49 \r
  50 #if defined(CONFIG_ARCH_RK319X)\r
  51 #include <mach/grf.h>\r
  52 #endif\r
  53 \r
  54 #include "vcodec_service.h"\r
  55 \r
  56 #define HEVC_TEST_ENABLE    0\r
  57 #define HEVC_SIM_ENABLE         0\r
  58 #define VCODEC_CLOCK_ENABLE 1\r
  59 \r
  60 typedef enum {\r
  61         VPU_DEC_ID_9190         = 0x6731,\r
  62         VPU_ID_8270             = 0x8270,\r
  63         VPU_ID_4831             = 0x4831,\r
  64     HEVC_ID         = 0x6867,\r
  65 } VPU_HW_ID;\r
  66 \r
  67 typedef enum {\r
  68         VPU_DEC_TYPE_9190       = 0,\r
  69         VPU_ENC_TYPE_8270       = 0x100,\r
  70         VPU_ENC_TYPE_4831       ,\r
  71 } VPU_HW_TYPE_E;\r
  72 \r
  73 typedef enum VPU_FREQ {\r
  74         VPU_FREQ_200M,\r
  75         VPU_FREQ_266M,\r
  76         VPU_FREQ_300M,\r
  77         VPU_FREQ_400M,\r
  78         VPU_FREQ_DEFAULT,\r
  79         VPU_FREQ_BUT,\r
  80 } VPU_FREQ;\r
  81 \r
  82 typedef struct {\r
  83         VPU_HW_ID               hw_id;\r
  84         unsigned long           hw_addr;\r
  85         unsigned long           enc_offset;\r
  86         unsigned long           enc_reg_num;\r
  87         unsigned long           enc_io_size;\r
  88         unsigned long           dec_offset;\r
  89         unsigned long           dec_reg_num;\r
  90         unsigned long           dec_io_size;\r
  91 } VPU_HW_INFO_E;\r
  92 \r
  93 #define VPU_SERVICE_SHOW_TIME                   0\r
  94 \r
  95 #if VPU_SERVICE_SHOW_TIME\r
  96 static struct timeval enc_start, enc_end;\r
  97 static struct timeval dec_start, dec_end;\r
  98 static struct timeval pp_start,  pp_end;\r
  99 #endif\r
 100 \r
 101 #define MHZ                                     (1000*1000)\r
 102 \r
 103 #define REG_NUM_9190_DEC                        (60)\r
 104 #define REG_NUM_9190_PP                         (41)\r
 105 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 106 \r
 107 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 108 \r
 109 #define REG_NUM_ENC_8270                        (96)\r
 110 #define REG_SIZE_ENC_8270                       (0x200)\r
 111 #define REG_NUM_ENC_4831                        (164)\r
 112 #define REG_SIZE_ENC_4831                       (0x400)\r
 113 \r
 114 #define REG_NUM_HEVC_DEC            (68)\r
 115 \r
 116 #define SIZE_REG(reg)                           ((reg)*4)\r
 117 \r
 118 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 119         [0] = {\r
 120                 .hw_id          = VPU_ID_8270,\r
 121                 .hw_addr        = 0,\r
 122                 .enc_offset     = 0x0,\r
 123                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 124                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 125                 .dec_offset     = REG_SIZE_ENC_8270,\r
 126                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 127                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 128         },\r
 129         [1] = {\r
 130                 .hw_id          = VPU_ID_4831,\r
 131                 .hw_addr        = 0,\r
 132                 .enc_offset     = 0x0,\r
 133                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 134                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 135                 .dec_offset     = REG_SIZE_ENC_4831,\r
 136                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 137                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 138         },\r
 139     [2] = {\r
 140         .hw_id      = HEVC_ID,\r
 141         .hw_addr    = 0,\r
 142         .dec_offset = 0x0,\r
 143         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 144         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 145     },\r
 146 };\r
 147 \r
 148 \r
 149 #define DEC_INTERRUPT_REGISTER                  1\r
 150 #define PP_INTERRUPT_REGISTER                   60\r
 151 #define ENC_INTERRUPT_REGISTER                  1\r
 152 \r
 153 #define DEC_INTERRUPT_BIT                       0x100\r
 154 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 155 #define PP_INTERRUPT_BIT                        0x100\r
 156 #define ENC_INTERRUPT_BIT                       0x1\r
 157 \r
 158 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 159 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 160 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 161 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 162 \r
 163 #define VPU_REG_EN_ENC                          14\r
 164 #define VPU_REG_ENC_GATE                        2\r
 165 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 166 \r
 167 #define VPU_REG_EN_DEC                          1\r
 168 #define VPU_REG_DEC_GATE                        2\r
 169 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 170 #define VPU_REG_EN_PP                           0\r
 171 #define VPU_REG_PP_GATE                         1\r
 172 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 173 #define VPU_REG_EN_DEC_PP                       1\r
 174 #define VPU_REG_DEC_PP_GATE                     61\r
 175 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 176 \r
 177 /**\r
 178  * struct for process session which connect to vpu\r
 179  *\r
 180  * @author ChenHengming (2011-5-3)\r
 181  */\r
 182 typedef struct vpu_session {\r
 183         VPU_CLIENT_TYPE         type;\r
 184         /* a linked list of data so we can access them for debugging */\r
 185         struct list_head        list_session;\r
 186         /* a linked list of register data waiting for process */\r
 187         struct list_head        waiting;\r
 188         /* a linked list of register data in processing */\r
 189         struct list_head        running;\r
 190         /* a linked list of register data processed */\r
 191         struct list_head        done;\r
 192         wait_queue_head_t       wait;\r
 193         pid_t                   pid;\r
 194         atomic_t                task_running;\r
 195 } vpu_session;\r
 196 \r
 197 /**\r
 198  * struct for process register set\r
 199  *\r
 200  * @author ChenHengming (2011-5-4)\r
 201  */\r
 202 typedef struct vpu_reg {\r
 203         VPU_CLIENT_TYPE         type;\r
 204         VPU_FREQ                freq;\r
 205         vpu_session             *session;\r
 206         struct list_head        session_link;           /* link to vpu service session */\r
 207         struct list_head        status_link;            /* link to register set list */\r
 208         unsigned long           size;\r
 209         unsigned long           *reg;\r
 210 } vpu_reg;\r
 211 \r
 212 typedef struct vpu_device {\r
 213         atomic_t                irq_count_codec;\r
 214         atomic_t                irq_count_pp;\r
 215         unsigned long           iobaseaddr;\r
 216         unsigned int            iosize;\r
 217         volatile u32            *hwregs;\r
 218 } vpu_device;\r
 219 \r
 220 enum vcodec_device_id {\r
 221         VCODEC_DEVICE_ID_VPU,\r
 222         VCODEC_DEVICE_ID_HEVC\r
 223 };\r
 224 \r
 225 typedef struct vpu_service_info {\r
 226         struct wake_lock        wake_lock;\r
 227         struct delayed_work     power_off_work;\r
 228         struct mutex            lock;\r
 229         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 230         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 231         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 232         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 233         atomic_t                total_running;\r
 234         bool                    enabled;\r
 235         vpu_reg                 *reg_codec;\r
 236         vpu_reg                 *reg_pproc;\r
 237         vpu_reg                 *reg_resev;\r
 238         VPUHwDecConfig_t        dec_config;\r
 239         VPUHwEncConfig_t        enc_config;\r
 240         VPU_HW_INFO_E           *hw_info;\r
 241         unsigned long           reg_size;\r
 242         bool                    auto_freq;\r
 243         bool                    bug_dec_addr;\r
 244         atomic_t                freq_status;\r
 245 \r
 246     struct clk *aclk_vcodec;\r
 247     struct clk *hclk_vcodec;\r
 248     struct clk *clk_core;\r
 249     struct clk *clk_cabac;\r
 250 \r
 251     int irq_dec;\r
 252     int irq_enc;\r
 253 \r
 254     vpu_device enc_dev;\r
 255     vpu_device dec_dev;\r
 256 \r
 257     struct device   *dev;\r
 258 \r
 259     struct cdev     cdev;\r
 260     dev_t           dev_t;\r
 261     struct class    *cls;\r
 262     struct device   *child_dev;\r
 263 \r
 264     struct dentry   *debugfs_dir;\r
 265     struct dentry   *debugfs_file_regs;\r
 266 \r
 267     u32 irq_status;\r
 268 #if defined(CONFIG_ION_ROCKCHIP)        \r
 269         struct ion_client * ion_client;\r
 270 #endif  \r
 271 \r
 272         enum vcodec_device_id dev_id;\r
 273 \r
 274     struct delayed_work simulate_work;\r
 275 } vpu_service_info;\r
 276 \r
 277 typedef struct vpu_request\r
 278 {\r
 279         unsigned long   *req;\r
 280         unsigned long   size;\r
 281 } vpu_request;\r
 282 \r
 283 /// global variable\r
 284 //static struct clk *pd_video;\r
 285 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 286 \r
 287 #ifdef CONFIG_DEBUG_FS\r
 288 static int vcodec_debugfs_init(void);\r
 289 static void vcodec_debugfs_exit(void);\r
 290 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 291 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 292 \r
 293 static const struct file_operations debug_vcodec_fops = {\r
 294         .open = debug_vcodec_open,\r
 295         .read = seq_read,\r
 296         .llseek = seq_lseek,\r
 297         .release = single_release,\r
 298 };\r
 299 #endif\r
 300 \r
 301 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 302 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 303 \r
 304 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 305 \r
 306 static void vpu_get_clk(struct vpu_service_info *pservice)\r
 307 {\r
 308 #if VCODEC_CLOCK_ENABLE\r
 309         /*pd_video      = clk_get(NULL, "pd_video");\r
 310         if (IS_ERR(pd_video)) {\r
 311                 pr_err("failed on clk_get pd_video\n");\r
 312         }*/\r
 313 \r
 314         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 315         if (IS_ERR(pservice->aclk_vcodec)) {\r
 316                 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 317         }\r
 318 \r
 319         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 320         if (IS_ERR(pservice->hclk_vcodec)) {\r
 321                 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 322         }\r
 323 \r
 324         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 325                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 326                 if (IS_ERR(pservice->clk_core)) {\r
 327                         dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 328                 }\r
 329 \r
 330                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 331                 if (IS_ERR(pservice->clk_cabac)) {\r
 332                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 333                 }\r
 334         }\r
 335 #endif\r
 336 }\r
 337 \r
 338 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 339 {\r
 340 #if VCODEC_CLOCK_ENABLE\r
 341     //clk_put(pd_video);\r
 342 \r
 343     if (pservice->aclk_vcodec) {\r
 344         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 345     }\r
 346 \r
 347     if (pservice->hclk_vcodec) {\r
 348         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 349     }\r
 350 \r
 351     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 352         if (pservice->clk_core) {\r
 353             devm_clk_put(pservice->dev, pservice->clk_core);\r
 354         }\r
 355         \r
 356         if (pservice->clk_cabac) {\r
 357             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 358         }\r
 359     }\r
 360 #endif\r
 361 }\r
 362 \r
 363 static void vpu_reset(struct vpu_service_info *pservice)\r
 364 {\r
 365 #if defined(CONFIG_ARCH_RK29)\r
 366         clk_disable(aclk_ddr_vepu);\r
 367         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 368         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 369         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 370         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 371         mdelay(10);\r
 372         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 373         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 374         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 375         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 376         clk_enable(aclk_ddr_vepu);\r
 377 #elif defined(CONFIG_ARCH_RK30)\r
 378         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 379         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 380         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 381         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 382         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 383         mdelay(1);\r
 384         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 385         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 386         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 387         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 388         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 389 #endif\r
 390         pservice->reg_codec = NULL;\r
 391         pservice->reg_pproc = NULL;\r
 392         pservice->reg_resev = NULL;\r
 393 }\r
 394 \r
 395 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 396 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 397 {\r
 398         vpu_reg *reg, *n;\r
 399         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 400                 reg_deinit(pservice, reg);\r
 401         }\r
 402         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 403                 reg_deinit(pservice, reg);\r
 404         }\r
 405         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 406                 reg_deinit(pservice, reg);\r
 407         }\r
 408 }\r
 409 \r
 410 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 411 {\r
 412         int running;\r
 413         vpu_reg *reg, *reg_tmp;\r
 414         vpu_session *session, *session_tmp;\r
 415 \r
 416         running = atomic_read(&pservice->total_running);\r
 417         printk("total_running %d\n", running);\r
 418 \r
 419         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 420         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 421         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 422 \r
 423         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 424                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 425                 running = atomic_read(&session->task_running);\r
 426                 printk("task_running %d\n", running);\r
 427                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 428                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 429                 }\r
 430                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 431                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 432                 }\r
 433                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 434                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 435                 }\r
 436         }\r
 437 }\r
 438 \r
 439 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 440 {\r
 441         int total_running;\r
 442         if (!pservice->enabled) {\r
 443                 return;\r
 444         }\r
 445 \r
 446         pservice->enabled = false;\r
 447         total_running = atomic_read(&pservice->total_running);\r
 448         if (total_running) {\r
 449                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 450                 mdelay(50);\r
 451                 pr_alert("alert: delay 50 ms for running task\n");\r
 452                 vpu_service_dump(pservice);\r
 453         }\r
 454 \r
 455         printk("%s: power off...", dev_name(pservice->dev));\r
 456 #ifdef CONFIG_ARCH_RK29\r
 457         pmu_set_power_domain(PD_VCODEC, false);\r
 458 #else\r
 459         //clk_disable(pd_video);\r
 460 #endif\r
 461         udelay(10);\r
 462 #if VCODEC_CLOCK_ENABLE\r
 463         clk_disable_unprepare(pservice->hclk_vcodec);\r
 464         clk_disable_unprepare(pservice->aclk_vcodec);\r
 465     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 466         clk_disable_unprepare(pservice->clk_core);\r
 467         clk_disable_unprepare(pservice->clk_cabac);\r
 468     }\r
 469 #endif\r
 470         wake_unlock(&pservice->wake_lock);\r
 471         printk("done\n");\r
 472 }\r
 473 \r
 474 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 475 {\r
 476         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 477 }\r
 478 \r
 479 static void vpu_power_off_work(struct work_struct *work_s)\r
 480 {\r
 481     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 482     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 483 \r
 484         if (mutex_trylock(&pservice->lock)) {\r
 485                 vpu_service_power_off(pservice);\r
 486                 mutex_unlock(&pservice->lock);\r
 487         } else {\r
 488                 /* Come back later if the device is busy... */\r
 489                 vpu_queue_power_off_work(pservice);\r
 490         }\r
 491 }\r
 492 \r
 493 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 494 {\r
 495         static ktime_t last;\r
 496         ktime_t now = ktime_get();\r
 497         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 498                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 499                 vpu_queue_power_off_work(pservice);\r
 500                 last = now;\r
 501         }\r
 502         if (pservice->enabled)\r
 503                 return ;\r
 504 \r
 505         pservice->enabled = true;\r
 506         printk("%s: power on\n", dev_name(pservice->dev));\r
 507 \r
 508 #if VCODEC_CLOCK_ENABLE\r
 509     clk_prepare_enable(pservice->aclk_vcodec);\r
 510         clk_prepare_enable(pservice->hclk_vcodec);\r
 511 \r
 512     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 513         clk_prepare_enable(pservice->clk_core);\r
 514         clk_prepare_enable(pservice->clk_cabac);\r
 515     }\r
 516 #endif\r
 517 \r
 518 #if defined(CONFIG_ARCH_RK319X)\r
 519     /// select aclk_vepu as vcodec clock source. \r
 520     #define BIT_VCODEC_SEL  (1<<7)\r
 521     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 522 #endif\r
 523         udelay(10);\r
 524 #ifdef CONFIG_ARCH_RK29\r
 525         pmu_set_power_domain(PD_VCODEC, true);\r
 526 #else\r
 527         //clk_enable(pd_video);\r
 528 #endif\r
 529         udelay(10);\r
 530         wake_lock(&pservice->wake_lock);\r
 531 }\r
 532 \r
 533 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 534 {\r
 535         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 536         return ((type == 8) || (type == 4));\r
 537 }\r
 538 \r
 539 static inline bool reg_check_interlace(vpu_reg *reg)\r
 540 {\r
 541         unsigned long type = (reg->reg[3] & (1 << 23));\r
 542         return (type > 0);\r
 543 }\r
 544 \r
 545 #if defined(CONFIG_VCODEC_MMU)\r
 546 static u8 table_vpu_dec[] = {\r
 547         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 548 };\r
 549 \r
 550 static u8 table_vpu_enc[] = {\r
 551         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 552 };\r
 553 \r
 554 static u8 table_hevc_dec[1] = {\r
 555 \r
 556 };\r
 557 \r
 558 static int reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 559 {\r
 560         VPU_HW_ID hw_id;\r
 561         int i;\r
 562 \r
 563         hw_id = pservice->hw_info->hw_id;\r
 564 \r
 565     if (hw_id == HEVC_ID) {\r
 566 \r
 567     } else {\r
 568         if (reg->type == VPU_DEC) {\r
 569             for (i=0; i<sizeof(table_vpu_dec); i++) {\r
 570                                 int usr_fd;\r
 571                                 struct ion_handle *hdl;\r
 572                                 ion_phys_addr_t phy_addr;\r
 573                                 size_t len;\r
 574                                 int offset;\r
 575 \r
 576 #if 0\r
 577                                 if (copy_from_user(&usr_fd, &reg->reg[table_vpu_dec[i]], sizeof(usr_fd)))\r
 578                                         return -EFAULT;\r
 579 #else\r
 580                                 usr_fd = reg->reg[table_vpu_dec[i]] & 0xFF;\r
 581                                 offset = reg->reg[table_vpu_dec[i]] >> 8;\r
 582 #endif\r
 583                 if (usr_fd != 0) {\r
 584 \r
 585                                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 586                     if (IS_ERR(hdl)) {\r
 587                                                 pr_err("import dma-buf from fd %d failed\n", usr_fd);\r
 588                                                 return ERR_PTR(hdl);\r
 589                     }\r
 590 \r
 591                                         ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 592 \r
 593                                         reg->reg[table_vpu_dec[i]] = phy_addr + offset;\r
 594 \r
 595                                         ion_free(pservice->ion_client, hdl);\r
 596                 }\r
 597             }\r
 598         } else if (reg->type == VPU_ENC) {\r
 599 \r
 600         }\r
 601         }\r
 602 \r
 603         return 0;\r
 604 }\r
 605 #endif\r
 606 \r
 607 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 608 {\r
 609         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 610         if (NULL == reg) {\r
 611                 pr_err("error: kmalloc fail in reg_init\n");\r
 612                 return NULL;\r
 613         }\r
 614 \r
 615         if (size > pservice->reg_size) {\r
 616                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 617                 size = pservice->reg_size;\r
 618         }\r
 619         reg->session = session;\r
 620         reg->type = session->type;\r
 621         reg->size = size;\r
 622         reg->freq = VPU_FREQ_DEFAULT;\r
 623         reg->reg = (unsigned long *)&reg[1];\r
 624         INIT_LIST_HEAD(&reg->session_link);\r
 625         INIT_LIST_HEAD(&reg->status_link);\r
 626 \r
 627         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 628                 pr_err("error: copy_from_user failed in reg_init\n");\r
 629                 kfree(reg);\r
 630                 return NULL;\r
 631         }\r
 632 \r
 633 #if defined(CONFIG_VCODEC_MMU)\r
 634     if (0 > reg_address_translate(pservice, reg)) {\r
 635                 pr_err("error: translate reg address failed\n");\r
 636                 kfree(reg);\r
 637                 return NULL;\r
 638     }\r
 639 #endif\r
 640 \r
 641         mutex_lock(&pservice->lock);\r
 642         list_add_tail(&reg->status_link, &pservice->waiting);\r
 643         list_add_tail(&reg->session_link, &session->waiting);\r
 644         mutex_unlock(&pservice->lock);\r
 645 \r
 646         if (pservice->auto_freq) {\r
 647                 if (!soc_is_rk2928g()) {\r
 648                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 649                                 if (reg_check_rmvb_wmv(reg)) {\r
 650                                         reg->freq = VPU_FREQ_200M;\r
 651                                 } else {\r
 652                                         if (reg_check_interlace(reg)) {\r
 653                                                 reg->freq = VPU_FREQ_400M;\r
 654                                         }\r
 655                                 }\r
 656                         }\r
 657                         if (reg->type == VPU_PP) {\r
 658                                 reg->freq = VPU_FREQ_400M;\r
 659                         }\r
 660                 }\r
 661         }\r
 662 \r
 663         return reg;\r
 664 }\r
 665 \r
 666 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 667 {\r
 668         list_del_init(&reg->session_link);\r
 669         list_del_init(&reg->status_link);\r
 670         if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 671         if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 672         kfree(reg);\r
 673 }\r
 674 \r
 675 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 676 {\r
 677         list_del_init(&reg->status_link);\r
 678         list_add_tail(&reg->status_link, &pservice->running);\r
 679 \r
 680         list_del_init(&reg->session_link);\r
 681         list_add_tail(&reg->session_link, &reg->session->running);\r
 682 }\r
 683 \r
 684 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 685 {\r
 686         int i;\r
 687         u32 *dst = (u32 *)&reg->reg[0];\r
 688         for (i = 0; i < count; i++)\r
 689                 *dst++ = *src++;\r
 690 }\r
 691 \r
 692 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 693 {\r
 694     int irq_reg = -1;\r
 695         list_del_init(&reg->status_link);\r
 696         list_add_tail(&reg->status_link, &pservice->done);\r
 697 \r
 698         list_del_init(&reg->session_link);\r
 699         list_add_tail(&reg->session_link, &reg->session->done);\r
 700 \r
 701         switch (reg->type) {\r
 702         case VPU_ENC : {\r
 703                 pservice->reg_codec = NULL;\r
 704                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 705                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 706                 break;\r
 707         }\r
 708         case VPU_DEC : {\r
 709         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 710                 pservice->reg_codec = NULL;\r
 711                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 712                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 713                 break;\r
 714         }\r
 715         case VPU_PP : {\r
 716                 pservice->reg_pproc = NULL;\r
 717                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 718                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 719                 break;\r
 720         }\r
 721         case VPU_DEC_PP : {\r
 722                 pservice->reg_codec = NULL;\r
 723                 pservice->reg_pproc = NULL;\r
 724                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 725                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 726                 break;\r
 727         }\r
 728         default : {\r
 729                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 730                 break;\r
 731         }\r
 732         }\r
 733 \r
 734     if (irq_reg != -1) {\r
 735         reg->reg[irq_reg] = pservice->irq_status;\r
 736     }\r
 737 \r
 738         atomic_sub(1, &reg->session->task_running);\r
 739         atomic_sub(1, &pservice->total_running);\r
 740         wake_up(&reg->session->wait);\r
 741 }\r
 742 \r
 743 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 744 {\r
 745         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 746         if (curr == reg->freq) {\r
 747                 return ;\r
 748         }\r
 749         atomic_set(&pservice->freq_status, reg->freq);\r
 750         switch (reg->freq) {\r
 751         case VPU_FREQ_200M : {\r
 752                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 753                 //printk("default: 200M\n");\r
 754         } break;\r
 755         case VPU_FREQ_266M : {\r
 756                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 757                 //printk("default: 266M\n");\r
 758         } break;\r
 759         case VPU_FREQ_300M : {\r
 760                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 761                 //printk("default: 300M\n");\r
 762         } break;\r
 763         case VPU_FREQ_400M : {\r
 764                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 765                 //printk("default: 400M\n");\r
 766         } break;\r
 767         default : {\r
 768                 if (soc_is_rk2928g()) {\r
 769                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 770                 } else {\r
 771                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 772                 }\r
 773                 //printk("default: 300M\n");\r
 774         } break;\r
 775         }\r
 776 }\r
 777 \r
 778 #if HEVC_SIM_ENABLE\r
 779 static void simulate_start(struct vpu_service_info *pservice);\r
 780 #endif\r
 781 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 782 {\r
 783         int i;\r
 784         u32 *src = (u32 *)&reg->reg[0];\r
 785         atomic_add(1, &pservice->total_running);\r
 786         atomic_add(1, &reg->session->task_running);\r
 787         if (pservice->auto_freq) {\r
 788                 vpu_service_set_freq(pservice, reg);\r
 789         }\r
 790         switch (reg->type) {\r
 791         case VPU_ENC : {\r
 792                 int enc_count = pservice->hw_info->enc_reg_num;\r
 793                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 794 #if 0\r
 795                 if (pservice->bug_dec_addr) {\r
 796 #if !defined(CONFIG_ARCH_RK319X)\r
 797                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 798 #endif\r
 799                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 800                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 801 #if !defined(CONFIG_ARCH_RK319X)\r
 802                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 803 #endif\r
 804                 }\r
 805 #endif\r
 806                 pservice->reg_codec = reg;\r
 807 \r
 808                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 809 \r
 810                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 811                         dst[i] = src[i];\r
 812 \r
 813                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 814                         dst[i] = src[i];\r
 815 \r
 816                 dsb();\r
 817 \r
 818                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 819                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 820 \r
 821 #if VPU_SERVICE_SHOW_TIME\r
 822                 do_gettimeofday(&enc_start);\r
 823 #endif\r
 824 \r
 825         } break;\r
 826         case VPU_DEC : {\r
 827                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 828 \r
 829                 pservice->reg_codec = reg;\r
 830 \r
 831         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 832                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 833                                 dst[i] = src[i];\r
 834         } else {\r
 835             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 836                                 dst[i] = src[i];\r
 837             }\r
 838                 }\r
 839 \r
 840                 dsb();\r
 841 \r
 842                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 843                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 844                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 845                 } else {\r
 846                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 847                 }\r
 848         dsb();\r
 849         dmb();\r
 850 \r
 851 #if VPU_SERVICE_SHOW_TIME\r
 852                 do_gettimeofday(&dec_start);\r
 853 #endif\r
 854 \r
 855         } break;\r
 856         case VPU_PP : {\r
 857                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 858                 pservice->reg_pproc = reg;\r
 859 \r
 860                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 861 \r
 862                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
 863                         dst[i] = src[i];\r
 864 \r
 865                 dsb();\r
 866 \r
 867                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
 868 \r
 869 #if VPU_SERVICE_SHOW_TIME\r
 870                 do_gettimeofday(&pp_start);\r
 871 #endif\r
 872 \r
 873         } break;\r
 874         case VPU_DEC_PP : {\r
 875                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 876                 pservice->reg_codec = reg;\r
 877                 pservice->reg_pproc = reg;\r
 878 \r
 879                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
 880                         dst[i] = src[i];\r
 881 \r
 882                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
 883                 dsb();\r
 884 \r
 885                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 886                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
 887                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
 888 \r
 889 #if VPU_SERVICE_SHOW_TIME\r
 890                 do_gettimeofday(&dec_start);\r
 891 #endif\r
 892 \r
 893         } break;\r
 894         default : {\r
 895                 pr_err("error: unsupport session type %d", reg->type);\r
 896                 atomic_sub(1, &pservice->total_running);\r
 897                 atomic_sub(1, &reg->session->task_running);\r
 898                 break;\r
 899         }\r
 900         }\r
 901 \r
 902 #if HEVC_SIM_ENABLE\r
 903     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 904         simulate_start(pservice);\r
 905     }\r
 906 #endif\r
 907 }\r
 908 \r
 909 static void try_set_reg(struct vpu_service_info *pservice)\r
 910 {\r
 911         // first get reg from reg list\r
 912         if (!list_empty(&pservice->waiting)) {\r
 913                 int can_set = 0;\r
 914                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
 915 \r
 916                 vpu_service_power_on(pservice);\r
 917 \r
 918                 switch (reg->type) {\r
 919                 case VPU_ENC : {\r
 920                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
 921                                 can_set = 1;\r
 922                 } break;\r
 923                 case VPU_DEC : {\r
 924                         if (NULL == pservice->reg_codec)\r
 925                                 can_set = 1;\r
 926                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
 927                                 can_set = 0;\r
 928                         }\r
 929                 } break;\r
 930                 case VPU_PP : {\r
 931                         if (NULL == pservice->reg_codec) {\r
 932                                 if (NULL == pservice->reg_pproc)\r
 933                                         can_set = 1;\r
 934                         } else {\r
 935                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
 936                                         can_set = 1;\r
 937                                 // can not charge frequency when vpu is working\r
 938                                 if (pservice->auto_freq) {\r
 939                                         can_set = 0;\r
 940                                 }\r
 941                         }\r
 942                 } break;\r
 943                 case VPU_DEC_PP : {\r
 944                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
 945                                 can_set = 1;\r
 946                         } break;\r
 947                 default : {\r
 948                         printk("undefined reg type %d\n", reg->type);\r
 949                 } break;\r
 950                 }\r
 951                 if (can_set) {\r
 952                         reg_from_wait_to_run(pservice, reg);\r
 953                         reg_copy_to_hw(pservice, reg);\r
 954                 }\r
 955         }\r
 956 }\r
 957 \r
 958 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
 959 {\r
 960         int ret = 0;\r
 961         switch (reg->type) {\r
 962         case VPU_ENC : {\r
 963                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
 964                         ret = -EFAULT;\r
 965                 break;\r
 966         }\r
 967         case VPU_DEC : {\r
 968         int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 969                 if (copy_to_user(dst, &reg->reg[0], reg_len))\r
 970                         ret = -EFAULT;\r
 971                 break;\r
 972         }\r
 973         case VPU_PP : {\r
 974                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
 975                         ret = -EFAULT;\r
 976                 break;\r
 977         }\r
 978         case VPU_DEC_PP : {\r
 979                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
 980                         ret = -EFAULT;\r
 981                 break;\r
 982         }\r
 983         default : {\r
 984                 ret = -EFAULT;\r
 985                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
 986                 break;\r
 987         }\r
 988         }\r
 989         reg_deinit(pservice, reg);\r
 990         return ret;\r
 991 }\r
 992 \r
 993 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
 994 {\r
 995     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
 996         vpu_session *session = (vpu_session *)filp->private_data;\r
 997         if (NULL == session) {\r
 998                 return -EINVAL;\r
 999         }\r
1000 \r
1001         switch (cmd) {\r
1002         case VPU_IOC_SET_CLIENT_TYPE : {\r
1003                 session->type = (VPU_CLIENT_TYPE)arg;\r
1004                 break;\r
1005         }\r
1006         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1007                 vpu_request req;\r
1008                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1009                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1010                         return -EFAULT;\r
1011                 } else {\r
1012                         if (VPU_ENC != session->type) {\r
1013                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1014                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1015                                         return -EFAULT;\r
1016                                 }\r
1017                         } else {\r
1018                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1019                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1020                                         return -EFAULT;\r
1021                                 }\r
1022                         }\r
1023                 }\r
1024 \r
1025                 break;\r
1026         }\r
1027         case VPU_IOC_SET_REG : {\r
1028                 vpu_request req;\r
1029                 vpu_reg *reg;\r
1030                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1031                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1032                         return -EFAULT;\r
1033                 }\r
1034                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1035                 if (NULL == reg) {\r
1036                         return -EFAULT;\r
1037                 } else {\r
1038                         mutex_lock(&pservice->lock);\r
1039                         try_set_reg(pservice);\r
1040                         mutex_unlock(&pservice->lock);\r
1041                 }\r
1042 \r
1043                 break;\r
1044         }\r
1045         case VPU_IOC_GET_REG : {\r
1046                 vpu_request req;\r
1047                 vpu_reg *reg;\r
1048                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1049                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1050                         return -EFAULT;\r
1051                 } else {\r
1052                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1053                         if (!list_empty(&session->done)) {\r
1054                                 if (ret < 0) {\r
1055                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1056                                 }\r
1057                                 ret = 0;\r
1058                         } else {\r
1059                                 if (unlikely(ret < 0)) {\r
1060                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1061                                 } else if (0 == ret) {\r
1062                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1063                                         ret = -ETIMEDOUT;\r
1064                                 }\r
1065                         }\r
1066                         if (ret < 0) {\r
1067                                 int task_running = atomic_read(&session->task_running);\r
1068                                 mutex_lock(&pservice->lock);\r
1069                                 vpu_service_dump(pservice);\r
1070                                 if (task_running) {\r
1071                                         atomic_set(&session->task_running, 0);\r
1072                                         atomic_sub(task_running, &pservice->total_running);\r
1073                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1074                                         vpu_reset(pservice);\r
1075                                         printk("done\n");\r
1076                                 }\r
1077                                 vpu_service_session_clear(pservice, session);\r
1078                                 mutex_unlock(&pservice->lock);\r
1079                                 return ret;\r
1080                         }\r
1081                 }\r
1082                 mutex_lock(&pservice->lock);\r
1083                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1084                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1085                 mutex_unlock(&pservice->lock);\r
1086                 break;\r
1087         }\r
1088         default : {\r
1089                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1090                 break;\r
1091         }\r
1092         }\r
1093 \r
1094         return 0;\r
1095 }\r
1096 \r
1097 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1098 {\r
1099         int ret = -EINVAL, i = 0;\r
1100         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1101         u32 enc_id = *tmp;\r
1102 \r
1103 #if HEVC_SIM_ENABLE\r
1104     /// temporary, hevc driver test.\r
1105     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1106         p->hw_info = &vpu_hw_set[2];\r
1107         return 0;\r
1108     }\r
1109 #endif\r
1110 \r
1111         enc_id = (enc_id >> 16) & 0xFFFF;\r
1112         pr_info("checking hw id %x\n", enc_id);\r
1113     p->hw_info = NULL;\r
1114         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1115                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1116                         p->hw_info = &vpu_hw_set[i];\r
1117                         ret = 0;\r
1118                         break;\r
1119                 }\r
1120         }\r
1121         iounmap((void *)tmp);\r
1122         return ret;\r
1123 }\r
1124 \r
1125 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1126 {\r
1127     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1128         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1129         if (NULL == session) {\r
1130                 pr_err("error: unable to allocate memory for vpu_session.");\r
1131                 return -ENOMEM;\r
1132         }\r
1133 \r
1134         session->type   = VPU_TYPE_BUTT;\r
1135         session->pid    = current->pid;\r
1136         INIT_LIST_HEAD(&session->waiting);\r
1137         INIT_LIST_HEAD(&session->running);\r
1138         INIT_LIST_HEAD(&session->done);\r
1139         INIT_LIST_HEAD(&session->list_session);\r
1140         init_waitqueue_head(&session->wait);\r
1141         atomic_set(&session->task_running, 0);\r
1142         mutex_lock(&pservice->lock);\r
1143         list_add_tail(&session->list_session, &pservice->session);\r
1144         filp->private_data = (void *)session;\r
1145         mutex_unlock(&pservice->lock);\r
1146 \r
1147         pr_debug("dev opened\n");\r
1148         return nonseekable_open(inode, filp);\r
1149 }\r
1150 \r
1151 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1152 {\r
1153     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1154         int task_running;\r
1155         vpu_session *session = (vpu_session *)filp->private_data;\r
1156         if (NULL == session)\r
1157                 return -EINVAL;\r
1158 \r
1159         task_running = atomic_read(&session->task_running);\r
1160         if (task_running) {\r
1161                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1162                 msleep(50);\r
1163         }\r
1164         wake_up(&session->wait);\r
1165 \r
1166         mutex_lock(&pservice->lock);\r
1167         /* remove this filp from the asynchronusly notified filp's */\r
1168         list_del_init(&session->list_session);\r
1169         vpu_service_session_clear(pservice, session);\r
1170         kfree(session);\r
1171         filp->private_data = NULL;\r
1172         mutex_unlock(&pservice->lock);\r
1173 \r
1174     pr_debug("dev closed\n");\r
1175         return 0;\r
1176 }\r
1177 \r
1178 static const struct file_operations vpu_service_fops = {\r
1179         .unlocked_ioctl = vpu_service_ioctl,\r
1180         .open           = vpu_service_open,\r
1181         .release        = vpu_service_release,\r
1182         //.fasync       = vpu_service_fasync,\r
1183 };\r
1184 \r
1185 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1186 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1187 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1188 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1189 static void get_hw_info(struct vpu_service_info *pservice);\r
1190 \r
1191 #if HEVC_SIM_ENABLE\r
1192 static void simulate_work(struct work_struct *work_s)\r
1193 {\r
1194     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1195     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1196     vpu_device *dev = &pservice->dec_dev;\r
1197 \r
1198     if (!list_empty(&pservice->running)) {\r
1199         atomic_add(1, &dev->irq_count_codec);\r
1200         vdpu_isr(0, (void*)pservice);\r
1201     } else {\r
1202         //simulate_start(pservice);\r
1203         pr_err("empty running queue\n");\r
1204     }\r
1205 }\r
1206 \r
1207 static void simulate_init(struct vpu_service_info *pservice)\r
1208 {\r
1209     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1210 }\r
1211 \r
1212 static void simulate_start(struct vpu_service_info *pservice)\r
1213 {\r
1214     cancel_delayed_work_sync(&pservice->power_off_work);\r
1215     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1216 }\r
1217 #endif\r
1218 \r
1219 #if HEVC_TEST_ENABLE\r
1220 static int hevc_test_case0(vpu_service_info *pservice);\r
1221 #endif\r
1222 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1223 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1224 #endif\r
1225 static int vcodec_probe(struct platform_device *pdev)\r
1226 {\r
1227     int ret = 0;\r
1228     struct resource *res = NULL;\r
1229     struct device *dev = &pdev->dev;\r
1230     void __iomem *regs = NULL;\r
1231     struct device_node *np = pdev->dev.of_node;\r
1232     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1233     char *prop = (char*)dev_name(dev);\r
1234 \r
1235     pr_info("probe device %s\n", dev_name(dev));\r
1236 \r
1237     of_property_read_string(np, "name", (const char**)&prop);\r
1238     dev_set_name(dev, prop);\r
1239 \r
1240         if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1241                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1242     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1243                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1244     } else {\r
1245                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1246                 return -1;\r
1247         }\r
1248 \r
1249     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1250     INIT_LIST_HEAD(&pservice->waiting);\r
1251     INIT_LIST_HEAD(&pservice->running);\r
1252     INIT_LIST_HEAD(&pservice->done);\r
1253     INIT_LIST_HEAD(&pservice->session);\r
1254     mutex_init(&pservice->lock);\r
1255     pservice->reg_codec = NULL;\r
1256     pservice->reg_pproc = NULL;\r
1257     atomic_set(&pservice->total_running, 0);\r
1258     pservice->enabled = false;\r
1259 \r
1260     pservice->dev = dev;\r
1261 \r
1262     vpu_get_clk(pservice);\r
1263 \r
1264     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1265 \r
1266     vpu_service_power_on(pservice);\r
1267 \r
1268     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1269 \r
1270     regs = devm_ioremap_resource(pservice->dev, res);\r
1271     if (IS_ERR(regs)) {\r
1272         ret = PTR_ERR(regs);\r
1273         goto err;\r
1274     }\r
1275 \r
1276     ret = vpu_service_check_hw(pservice, res->start);\r
1277     if (ret < 0) {\r
1278         pr_err("error: hw info check faild\n");\r
1279         goto err;\r
1280     }\r
1281 \r
1282     /// define regs address.\r
1283     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1284     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1285 \r
1286     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1287 \r
1288     pservice->reg_size   = pservice->dec_dev.iosize;\r
1289 \r
1290     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1291         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1292         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1293 \r
1294         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1295 \r
1296         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1297 \r
1298         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1299         if (pservice->irq_enc < 0) {\r
1300             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1301             ret = -ENXIO;\r
1302             goto err;\r
1303         }\r
1304 \r
1305         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1306         if (ret) {\r
1307             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1308             goto err;\r
1309         }\r
1310     }\r
1311 \r
1312     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1313     if (pservice->irq_dec < 0) {\r
1314         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1315         ret = -ENXIO;\r
1316         goto err;\r
1317     }\r
1318 \r
1319     /* get the IRQ line */\r
1320     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1321     if (ret) {\r
1322         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1323         goto err;\r
1324     }\r
1325 \r
1326     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1327     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1328     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1329     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1330 \r
1331     /// create device\r
1332     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1333     if (ret) {\r
1334         dev_err(dev, "alloc dev_t failed\n");\r
1335         goto err;\r
1336     }\r
1337 \r
1338     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1339 \r
1340     pservice->cdev.owner = THIS_MODULE;\r
1341     pservice->cdev.ops = &vpu_service_fops;\r
1342 \r
1343     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1344 \r
1345     if (ret) {\r
1346         dev_err(dev, "add dev_t failed\n");\r
1347         goto err;\r
1348     }\r
1349 \r
1350     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1351 \r
1352     if (IS_ERR(pservice->cls)) {\r
1353         ret = PTR_ERR(pservice->cls);\r
1354         dev_err(dev, "class_create err:%d\n", ret);\r
1355         goto err;\r
1356     }\r
1357 \r
1358     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1359 \r
1360     platform_set_drvdata(pdev, pservice);\r
1361 \r
1362     get_hw_info(pservice);\r
1363 \r
1364 \r
1365 #ifdef CONFIG_DEBUG_FS\r
1366     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1367     \r
1368     if (pservice->debugfs_dir == NULL) {\r
1369         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1370     }\r
1371 \r
1372     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1373                     pservice->debugfs_dir, pservice,\r
1374                     &debug_vcodec_fops);\r
1375 #endif\r
1376 \r
1377     vpu_service_power_off(pservice);\r
1378     pr_info("init success\n");\r
1379 \r
1380 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1381         pservice->ion_client = rockchip_ion_client_create("vpu");\r
1382         if (IS_ERR(pservice->ion_client)) {\r
1383                 dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1384                 return PTR_ERR(pservice->ion_client);\r
1385         } else {\r
1386                 dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1387         }\r
1388 #endif\r
1389 \r
1390 #if HEVC_SIM_ENABLE\r
1391     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1392         simulate_init(pservice);\r
1393     }\r
1394 #endif\r
1395 \r
1396 #if HEVC_TEST_ENABLE\r
1397     hevc_test_case0(pservice);\r
1398 #endif\r
1399 \r
1400     return 0;\r
1401 \r
1402 err:\r
1403     pr_info("init failed\n");\r
1404     vpu_service_power_off(pservice);\r
1405     vpu_put_clk(pservice);\r
1406     wake_lock_destroy(&pservice->wake_lock);\r
1407 \r
1408     if (res) {\r
1409         if (regs) {\r
1410             devm_ioremap_release(&pdev->dev, res);\r
1411         }\r
1412         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1413     }\r
1414 \r
1415     if (pservice->irq_enc > 0) {\r
1416         free_irq(pservice->irq_enc, (void *)pservice);\r
1417     }\r
1418 \r
1419     if (pservice->irq_dec > 0) {\r
1420         free_irq(pservice->irq_dec, (void *)pservice);\r
1421     }\r
1422 \r
1423     if (pservice->child_dev) {\r
1424         device_destroy(pservice->cls, pservice->dev_t);\r
1425         cdev_del(&pservice->cdev);\r
1426         unregister_chrdev_region(pservice->dev_t, 1);\r
1427     }\r
1428 \r
1429     if (pservice->cls) {\r
1430         class_destroy(pservice->cls);\r
1431     }\r
1432 \r
1433     return ret;\r
1434 }\r
1435 \r
1436 static int vcodec_remove(struct platform_device *pdev)\r
1437 {\r
1438     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1439     struct resource *res;\r
1440 \r
1441     device_destroy(pservice->cls, pservice->dev_t);\r
1442     class_destroy(pservice->cls);\r
1443     cdev_del(&pservice->cdev);\r
1444     unregister_chrdev_region(pservice->dev_t, 1);\r
1445 \r
1446     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1447     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1448     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1449     devm_ioremap_release(&pdev->dev, res);\r
1450     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1451     vpu_put_clk(pservice);\r
1452     wake_lock_destroy(&pservice->wake_lock);\r
1453     \r
1454 #ifdef CONFIG_DEBUG_FS\r
1455     if (pservice->debugfs_file_regs) {\r
1456         debugfs_remove(pservice->debugfs_file_regs);\r
1457     }\r
1458 \r
1459     if (pservice->debugfs_dir) {\r
1460         debugfs_remove(pservice->debugfs_dir);\r
1461     }\r
1462 #endif\r
1463 \r
1464     return 0;\r
1465 }\r
1466 \r
1467 #if defined(CONFIG_OF)\r
1468 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1469         {.compatible = "vpu_service",},\r
1470         {.compatible = "rockchip,hevc_service",},\r
1471     {},\r
1472 };\r
1473 #endif\r
1474 \r
1475 static struct platform_driver vcodec_driver = {\r
1476         .probe     = vcodec_probe,\r
1477     .remove        = vcodec_remove,\r
1478     .driver = {\r
1479         .name = "vcodec",\r
1480         .owner = THIS_MODULE,\r
1481 #if defined(CONFIG_OF)\r
1482         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1483 #endif\r
1484         },\r
1485 };\r
1486 \r
1487 static void get_hw_info(struct vpu_service_info *pservice)\r
1488 {\r
1489     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {\r
1490         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1491         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1492         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1493         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1494     \r
1495         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1496         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1497         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1498             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1499         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1500         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1501         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1502         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1503         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1504         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1505     \r
1506         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1507             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1508         } else {\r
1509             dec->maxDecPicWidth = 3840;\r
1510         }\r
1511     \r
1512         /* 2nd Config register */\r
1513         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1514         if (dec->refBufSupport) {\r
1515             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1516                 dec->refBufSupport |= 2;\r
1517             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1518                 dec->refBufSupport |= 4;\r
1519         }\r
1520         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1521         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1522         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1523         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1524     \r
1525         /* JPEG xtensions */\r
1526         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1527             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1528         } else {\r
1529             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1530         }\r
1531     \r
1532         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1533             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1534         } else {\r
1535             dec->rvSupport = RV_NOT_SUPPORTED;\r
1536         }\r
1537     \r
1538         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1539     \r
1540         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1541             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1542         }\r
1543     \r
1544         /// invalidate fuse register value in rk319x vpu and following.\r
1545         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1546             VPUHwFuseStatus_t hwFuseSts;\r
1547             /* Decoder fuse configuration */\r
1548             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1549     \r
1550             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1551             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1552             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1553             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1554             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1555             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1556             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1557             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1558             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1559             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1560             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1561             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1562             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1563             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1564     \r
1565             /* check max. decoder output width */\r
1566     \r
1567             if (fuseReg & 0x8000U)\r
1568                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1569             else if (fuseReg & 0x4000U)\r
1570                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1571             else if (fuseReg & 0x2000U)\r
1572                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1573             else if (fuseReg & 0x1000U)\r
1574                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1575             else    /* remove warning */\r
1576                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1577     \r
1578             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1579     \r
1580             /* Pp configuration */\r
1581             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1582     \r
1583             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1584                 dec->ppSupport = 1;\r
1585                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1586                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1587                 dec->ppConfig = configReg;\r
1588             } else {\r
1589                 dec->ppSupport = 0;\r
1590                 dec->maxPpOutPicWidth = 0;\r
1591                 dec->ppConfig = 0;\r
1592             }\r
1593     \r
1594             /* check the HW versio */\r
1595             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1596                 /* Pp configuration */\r
1597                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1598     \r
1599                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1600                     /* Pp fuse configuration */\r
1601                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1602     \r
1603                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1604                         hwFuseSts.ppSupportFuse = 1;\r
1605                         /* check max. pp output width */\r
1606                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1607                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1608                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1609                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1610                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1611                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1612                     } else {\r
1613                         hwFuseSts.ppSupportFuse = 0;\r
1614                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1615                         hwFuseSts.ppConfigFuse = 0;\r
1616                     }\r
1617                 } else {\r
1618                     hwFuseSts.ppSupportFuse = 0;\r
1619                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1620                     hwFuseSts.ppConfigFuse = 0;\r
1621                 }\r
1622     \r
1623                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1624                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1625                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1626                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1627                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1628                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1629                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1630                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1631                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1632                     dec->jpegSupport = JPEG_BASELINE;\r
1633                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1634                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1635                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1636                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1637                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1638                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1639     \r
1640                 /* check the pp config vs fuse status */\r
1641                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1642                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1643                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1644                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1645                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1646     \r
1647                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1648                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1649                 }\r
1650                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1651                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1652                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1653                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1654                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1655             }\r
1656         }\r
1657     \r
1658         configReg = pservice->enc_dev.hwregs[63];\r
1659         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1660         enc->h264Enabled = (configReg >> 27) & 1;\r
1661         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1662         enc->jpegEnabled = (configReg >> 25) & 1;\r
1663         enc->vsEnabled = (configReg >> 24) & 1;\r
1664         enc->rgbEnabled = (configReg >> 28) & 1;\r
1665         //enc->busType = (configReg >> 20) & 15;\r
1666         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1667         //enc->busWidth = (configReg >> 12) & 15;\r
1668         enc->reg_size = pservice->reg_size;\r
1669         enc->reserv[0] = enc->reserv[1] = 0;\r
1670     \r
1671         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();\r
1672         if (pservice->auto_freq) {\r
1673             pr_info("vpu_service set to auto frequency mode\n");\r
1674             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1675         }\r
1676         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1677         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1678     }\r
1679 }\r
1680 \r
1681 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1682 {\r
1683     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1684     vpu_device *dev = &pservice->dec_dev;\r
1685     u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1686 \r
1687         pr_debug("dec_irq\n");\r
1688 \r
1689         if (irq_status & DEC_INTERRUPT_BIT) {\r
1690                 pr_debug("dec_isr dec %x\n", irq_status);\r
1691                 if ((irq_status & 0x40001) == 0x40001)\r
1692                 {\r
1693                         do {\r
1694                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1695                         } while ((irq_status & 0x40001) == 0x40001);\r
1696                 }\r
1697 \r
1698                 /* clear dec IRQ */\r
1699         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1700             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1701         } else {\r
1702             /*writel(irq_status \r
1703               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1704                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1705 \r
1706             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1707         }\r
1708                 atomic_add(1, &dev->irq_count_codec);\r
1709         }\r
1710 \r
1711     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1712         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1713         if (irq_status & PP_INTERRUPT_BIT) {\r
1714             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1715             /* clear pp IRQ */\r
1716             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1717             atomic_add(1, &dev->irq_count_pp);\r
1718         }\r
1719     }\r
1720 \r
1721     pservice->irq_status = irq_status;\r
1722 \r
1723         return IRQ_WAKE_THREAD;\r
1724 }\r
1725 \r
1726 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1727 {\r
1728     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1729     vpu_device *dev = &pservice->dec_dev;\r
1730 \r
1731         mutex_lock(&pservice->lock);\r
1732         if (atomic_read(&dev->irq_count_codec)) {\r
1733 #if VPU_SERVICE_SHOW_TIME\r
1734                 do_gettimeofday(&dec_end);\r
1735                 pr_info("dec task: %ld ms\n",\r
1736                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1737                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1738 #endif\r
1739                 atomic_sub(1, &dev->irq_count_codec);\r
1740                 if (NULL == pservice->reg_codec) {\r
1741                         pr_err("error: dec isr with no task waiting\n");\r
1742                 } else {\r
1743                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1744                 }\r
1745         }\r
1746 \r
1747         if (atomic_read(&dev->irq_count_pp)) {\r
1748 \r
1749 #if VPU_SERVICE_SHOW_TIME\r
1750                 do_gettimeofday(&pp_end);\r
1751                 printk("pp  task: %ld ms\n",\r
1752                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1753                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1754 #endif\r
1755 \r
1756                 atomic_sub(1, &dev->irq_count_pp);\r
1757                 if (NULL == pservice->reg_pproc) {\r
1758                         pr_err("error: pp isr with no task waiting\n");\r
1759                 } else {\r
1760                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1761                 }\r
1762         }\r
1763         try_set_reg(pservice);\r
1764         mutex_unlock(&pservice->lock);\r
1765         return IRQ_HANDLED;\r
1766 }\r
1767 \r
1768 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1769 {\r
1770         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1771     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1772     vpu_device *dev = &pservice->enc_dev;\r
1773         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1774 \r
1775         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1776 \r
1777 #if VPU_SERVICE_SHOW_TIME\r
1778         do_gettimeofday(&enc_end);\r
1779         pr_info("enc task: %ld ms\n",\r
1780                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1781                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1782 #endif\r
1783 \r
1784         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1785                 /* clear enc IRQ */\r
1786                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1787                 atomic_add(1, &dev->irq_count_codec);\r
1788         }\r
1789 \r
1790         return IRQ_WAKE_THREAD;\r
1791 }\r
1792 \r
1793 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1794 {\r
1795         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1796     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1797     vpu_device *dev = &pservice->enc_dev;\r
1798 \r
1799         mutex_lock(&pservice->lock);\r
1800         if (atomic_read(&dev->irq_count_codec)) {\r
1801                 atomic_sub(1, &dev->irq_count_codec);\r
1802                 if (NULL == pservice->reg_codec) {\r
1803                         pr_err("error: enc isr with no task waiting\n");\r
1804                 } else {\r
1805                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1806                 }\r
1807         }\r
1808         try_set_reg(pservice);\r
1809         mutex_unlock(&pservice->lock);\r
1810         return IRQ_HANDLED;\r
1811 }\r
1812 \r
1813 static int __init vcodec_service_init(void)\r
1814 {\r
1815     int ret;\r
1816 \r
1817     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1818         pr_err("Platform device register failed (%d).\n", ret);\r
1819         return ret;\r
1820     }\r
1821 \r
1822 #ifdef CONFIG_DEBUG_FS\r
1823     vcodec_debugfs_init();\r
1824 #endif\r
1825 \r
1826     return ret;\r
1827 }\r
1828 \r
1829 static void __exit vcodec_service_exit(void)\r
1830 {\r
1831 #ifdef CONFIG_DEBUG_FS\r
1832     vcodec_debugfs_exit();\r
1833 #endif\r
1834 \r
1835         platform_driver_unregister(&vcodec_driver);\r
1836 }\r
1837 \r
1838 module_init(vcodec_service_init);\r
1839 module_exit(vcodec_service_exit);\r
1840 \r
1841 #ifdef CONFIG_DEBUG_FS\r
1842 #include <linux/seq_file.h>\r
1843 \r
1844 static int vcodec_debugfs_init()\r
1845 {\r
1846     parent = debugfs_create_dir("vcodec", NULL);\r
1847     if (!parent)\r
1848         return -1;\r
1849 \r
1850     return 0;\r
1851 }\r
1852 \r
1853 static void vcodec_debugfs_exit()\r
1854 {\r
1855     debugfs_remove(parent);\r
1856 }\r
1857 \r
1858 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
1859 {\r
1860     return debugfs_create_dir(dirname, parent);\r
1861 }\r
1862 \r
1863 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
1864 {\r
1865         struct vpu_service_info *pservice = s->private;\r
1866     unsigned int i, n;\r
1867         vpu_reg *reg, *reg_tmp;\r
1868         vpu_session *session, *session_tmp;\r
1869 \r
1870         mutex_lock(&pservice->lock);\r
1871         vpu_service_power_on(pservice);\r
1872     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1873         seq_printf(s, "\nENC Registers:\n");\r
1874         n = pservice->enc_dev.iosize >> 2;\r
1875         for (i = 0; i < n; i++) {\r
1876             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
1877         }\r
1878     }\r
1879         seq_printf(s, "\nDEC Registers:\n");\r
1880         n = pservice->dec_dev.iosize >> 2;\r
1881         for (i = 0; i < n; i++) {\r
1882                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
1883         }\r
1884 \r
1885         seq_printf(s, "\nvpu service status:\n");\r
1886         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
1887                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
1888                 //seq_printf(s, "waiting reg set %d\n");\r
1889                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
1890                         seq_printf(s, "waiting register set\n");\r
1891                 }\r
1892                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
1893                         seq_printf(s, "running register set\n");\r
1894                 }\r
1895                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
1896                         seq_printf(s, "done    register set\n");\r
1897                 }\r
1898         }\r
1899         mutex_unlock(&pservice->lock);\r
1900 \r
1901     return 0;\r
1902 }\r
1903 \r
1904 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
1905 {\r
1906         return single_open(file, debug_vcodec_show, inode->i_private);\r
1907 }\r
1908 \r
1909 #endif\r
1910 \r
1911 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
1912 #include "hevc_test_inc/pps_00.h"\r
1913 #include "hevc_test_inc/register_00.h"\r
1914 #include "hevc_test_inc/rps_00.h"\r
1915 #include "hevc_test_inc/scaling_list_00.h"\r
1916 #include "hevc_test_inc/stream_00.h"\r
1917 \r
1918 #include "hevc_test_inc/pps_01.h"\r
1919 #include "hevc_test_inc/register_01.h"\r
1920 #include "hevc_test_inc/rps_01.h"\r
1921 #include "hevc_test_inc/scaling_list_01.h"\r
1922 #include "hevc_test_inc/stream_01.h"\r
1923 \r
1924 #include "hevc_test_inc/cabac.h"\r
1925 \r
1926 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1927 \r
1928 static struct ion_client *ion_client = NULL;\r
1929 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
1930 {\r
1931         int size = (len+15) & (~15);\r
1932     struct ion_handle *handle;\r
1933         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
1934 \r
1935     if (ion_client == NULL) {\r
1936         ion_client = rockchip_ion_client_create("vcodec");\r
1937     }\r
1938 \r
1939     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
1940 \r
1941     ptr = ion_map_kernel(ion_client, handle);\r
1942 \r
1943     ion_phys(ion_client, handle, phy, &size);\r
1944 \r
1945         memcpy(ptr, tbl, len);\r
1946 \r
1947         return ptr;\r
1948 }\r
1949 \r
1950 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
1951 {\r
1952         int size = (len+15) & (~15);\r
1953     struct ion_handle *handle;\r
1954         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
1955 \r
1956     if (ion_client == NULL) {\r
1957         ion_client = rockchip_ion_client_create("vcodec");\r
1958     }\r
1959 \r
1960     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
1961 \r
1962     ptr = ion_map_kernel(ion_client, handle);\r
1963 \r
1964     ion_phys(ion_client, handle, phy, &size);\r
1965 \r
1966         return ptr;\r
1967 }\r
1968 \r
1969 #define TEST_CNT    2\r
1970 static int hevc_test_case0(vpu_service_info *pservice)\r
1971 {\r
1972     vpu_session session;\r
1973     vpu_reg *reg; \r
1974     unsigned long size = 272;//sizeof(register_00); // registers array length\r
1975     int testidx = 0;\r
1976     int ret = 0;\r
1977 \r
1978     u8 *pps_tbl[TEST_CNT];\r
1979     u8 *register_tbl[TEST_CNT];\r
1980     u8 *rps_tbl[TEST_CNT];\r
1981     u8 *scaling_list_tbl[TEST_CNT];\r
1982     u8 *stream_tbl[TEST_CNT];\r
1983 \r
1984         int stream_size[2];\r
1985         int pps_size[2];\r
1986         int rps_size[2];\r
1987         int scl_size[2];\r
1988         int cabac_size[2];\r
1989         \r
1990     u32 phy_pps;\r
1991     u32 phy_rps;\r
1992     u32 phy_scl;\r
1993     u32 phy_str;\r
1994     u32 phy_yuv;\r
1995     u32 phy_ref;\r
1996     u32 phy_cabac;\r
1997 \r
1998         volatile u8 *stream_buf;\r
1999         volatile u8 *pps_buf;\r
2000         volatile u8 *rps_buf;\r
2001         volatile u8 *scl_buf;\r
2002         volatile u8 *yuv_buf;\r
2003         volatile u8 *cabac_buf;\r
2004         volatile u8 *ref_buf;\r
2005 \r
2006     u8 *pps;\r
2007     u8 *yuv[2];\r
2008     int i;\r
2009     \r
2010     pps_tbl[0] = pps_00;\r
2011     pps_tbl[1] = pps_01;\r
2012 \r
2013     register_tbl[0] = register_00;\r
2014     register_tbl[1] = register_01;\r
2015     \r
2016     rps_tbl[0] = rps_00;\r
2017     rps_tbl[1] = rps_01;\r
2018     \r
2019     scaling_list_tbl[0] = scaling_list_00;\r
2020     scaling_list_tbl[1] = scaling_list_01;\r
2021 \r
2022     stream_tbl[0] = stream_00;\r
2023     stream_tbl[1] = stream_01;\r
2024 \r
2025     stream_size[0] = sizeof(stream_00);\r
2026     stream_size[1] = sizeof(stream_01);\r
2027 \r
2028         pps_size[0] = sizeof(pps_00);\r
2029         pps_size[1] = sizeof(pps_01);\r
2030 \r
2031         rps_size[0] = sizeof(rps_00);\r
2032         rps_size[1] = sizeof(rps_01);\r
2033 \r
2034         scl_size[0] = sizeof(scaling_list_00);\r
2035         scl_size[1] = sizeof(scaling_list_01);\r
2036         \r
2037         cabac_size[0] = sizeof(Cabac_table);\r
2038         cabac_size[1] = sizeof(Cabac_table);\r
2039 \r
2040     // create session\r
2041     session.pid = current->pid;\r
2042     session.type = VPU_DEC;\r
2043     INIT_LIST_HEAD(&session.waiting);\r
2044         INIT_LIST_HEAD(&session.running);\r
2045         INIT_LIST_HEAD(&session.done);\r
2046         INIT_LIST_HEAD(&session.list_session);\r
2047         init_waitqueue_head(&session.wait);\r
2048         atomic_set(&session.task_running, 0);\r
2049         list_add_tail(&session.list_session, &pservice->session);\r
2050 \r
2051     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2052     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2053 \r
2054         while (testidx < TEST_CNT) {\r
2055         \r
2056         // create registers\r
2057         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2058         if (NULL == reg) {\r
2059             pr_err("error: kmalloc fail in reg_init\n");\r
2060             return -1;\r
2061         }\r
2062 \r
2063 \r
2064         if (size > pservice->reg_size) {\r
2065             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2066             size = pservice->reg_size;\r
2067         }\r
2068         reg->session = &session;\r
2069         reg->type = session.type;\r
2070         reg->size = size;\r
2071         reg->freq = VPU_FREQ_DEFAULT;\r
2072         reg->reg = (unsigned long *)&reg[1];\r
2073         INIT_LIST_HEAD(&reg->session_link);\r
2074         INIT_LIST_HEAD(&reg->status_link);\r
2075 \r
2076         // TODO: stuff registers\r
2077         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2078 \r
2079                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2080                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2081                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2082                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2083                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2084 \r
2085                 pps = pps_buf;\r
2086 \r
2087         // TODO: replace reigster address\r
2088 \r
2089         for (i=0; i<64; i++) {\r
2090             u32 scaling_offset;\r
2091             u32 tmp;\r
2092 \r
2093             scaling_offset = (u32)pps[i*80+74];\r
2094             scaling_offset += (u32)pps[i*80+75] << 8;\r
2095             scaling_offset += (u32)pps[i*80+76] << 16;\r
2096             scaling_offset += (u32)pps[i*80+77] << 24;\r
2097 \r
2098             tmp = phy_scl + scaling_offset;\r
2099 \r
2100             pps[i*80+74] = tmp & 0xff;\r
2101             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2102             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2103             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2104         }\r
2105 \r
2106         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2107 \r
2108         reg->reg[1] = 0x21;\r
2109         reg->reg[4] = phy_str;\r
2110         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2111         reg->reg[6] = phy_cabac;\r
2112         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2113         reg->reg[42] = phy_pps;\r
2114         reg->reg[43] = phy_rps;\r
2115         for (i = 10; i <= 24; i++) {\r
2116             reg->reg[i] = phy_yuv;\r
2117         }\r
2118 \r
2119         mutex_lock(&pservice->lock);\r
2120         list_add_tail(&reg->status_link, &pservice->waiting);\r
2121         list_add_tail(&reg->session_link, &session.waiting);\r
2122         mutex_unlock(&pservice->lock);\r
2123 \r
2124         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2125 \r
2126         // stuff hardware\r
2127         try_set_reg(pservice);\r
2128 \r
2129         // wait for result\r
2130         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2131         if (!list_empty(&session.done)) {\r
2132             if (ret < 0) {\r
2133                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2134             }\r
2135             ret = 0;\r
2136         } else {\r
2137             if (unlikely(ret < 0)) {\r
2138                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2139             } else if (0 == ret) {\r
2140                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2141                 ret = -ETIMEDOUT;\r
2142             }\r
2143         }\r
2144         if (ret < 0) {\r
2145             int task_running = atomic_read(&session.task_running);\r
2146             int n;\r
2147             mutex_lock(&pservice->lock);\r
2148             vpu_service_dump(pservice);\r
2149             if (task_running) {\r
2150                 atomic_set(&session.task_running, 0);\r
2151                 atomic_sub(task_running, &pservice->total_running);\r
2152                 printk("%d task is running but not return, reset hardware...", task_running);\r
2153                 vpu_reset(pservice);\r
2154                 printk("done\n");\r
2155             }\r
2156             vpu_service_session_clear(pservice, &session);\r
2157             mutex_unlock(&pservice->lock);\r
2158 \r
2159             printk("\nDEC Registers:\n");\r
2160                 n = pservice->dec_dev.iosize >> 2;\r
2161                 for (i=0; i<n; i++) {\r
2162                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2163                 }\r
2164 \r
2165             pr_err("test index %d failed\n", testidx);\r
2166             break;\r
2167         } else {\r
2168             pr_info("test index %d success\n", testidx);\r
2169 \r
2170             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2171 \r
2172             for (i=0; i<68; i++) {\r
2173                 if (i % 4 == 0) {\r
2174                     printk("%02d: ", i);\r
2175                 }\r
2176                 printk("%08x ", reg->reg[i]);\r
2177                 if ((i+1) % 4 == 0) {\r
2178                     printk("\n");\r
2179                 }\r
2180             }\r
2181 \r
2182             testidx++;\r
2183         }\r
2184 \r
2185         reg_deinit(pservice, reg);\r
2186     }\r
2187 \r
2188     return 0;\r
2189 }\r
2190 \r
2191 #endif\r
2192 \r