arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/clk.h>
  20 #include <linux/compat.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/fs.h>
  28 #include <linux/ioport.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/mm.h>
  31 #include <linux/poll.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35 #include <linux/wakelock.h>
  36 #include <linux/cdev.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <linux/of_irq.h>
  40 #include <linux/rockchip/cpu.h>
  41 #include <linux/rockchip/cru.h>
  42 #include <linux/rockchip/pmu.h>
  43 #ifdef CONFIG_MFD_SYSCON
  44 #include <linux/regmap.h>
  45 #endif
  46 #include <linux/mfd/syscon.h>
  47
  48 #include <asm/cacheflush.h>
  49 #include <linux/uaccess.h>
  50 #include <linux/rockchip/grf.h>
  51
  52 #if defined(CONFIG_ION_ROCKCHIP)
  53 #include <linux/rockchip_ion.h>
  54 #endif
  55
  56 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  57 #define CONFIG_VCODEC_MMU
  58 #endif
  59
  60 #ifdef CONFIG_VCODEC_MMU
  61 #include <linux/rockchip-iovmm.h>
  62 #include <linux/dma-buf.h>
  63 #endif
  64
  65 #ifdef CONFIG_DEBUG_FS
  66 #include <linux/debugfs.h>
  67 #endif
  68
  69 #if defined(CONFIG_ARCH_RK319X)
  70 #include <mach/grf.h>
  71 #endif
  72
  73 #include "vcodec_service.h"
  74
  75 /*
  76  * debug flag usage:
  77  * +------+-------------------+
  78  * | 8bit |      24bit        |
  79  * +------+-------------------+
  80  *  0~23 bit is for different information type
  81  * 24~31 bit is for information print format
  82  */
  83
  84 #define DEBUG_POWER                             0x00000001
  85 #define DEBUG_CLOCK                             0x00000002
  86 #define DEBUG_IRQ_STATUS                        0x00000004
  87 #define DEBUG_IOMMU                             0x00000008
  88 #define DEBUG_IOCTL                             0x00000010
  89 #define DEBUG_FUNCTION                          0x00000020
  90 #define DEBUG_REGISTER                          0x00000040
  91 #define DEBUG_EXTRA_INFO                        0x00000080
  92 #define DEBUG_TIMING                            0x00000100
  93
  94 #define PRINT_FUNCTION                          0x80000000
  95 #define PRINT_LINE                              0x40000000
  96
  97 static int debug;
  98 module_param(debug, int, S_IRUGO | S_IWUSR);
  99 MODULE_PARM_DESC(debug,
 100                  "Debug level - higher value produces more verbose messages");
 101
 102 #define HEVC_TEST_ENABLE        0
 103 #define VCODEC_CLOCK_ENABLE     1
 104
 105 typedef enum {
 106         VPU_DEC_ID_9190         = 0x6731,
 107         VPU_ID_8270             = 0x8270,
 108         VPU_ID_4831             = 0x4831,
 109         HEVC_ID                 = 0x6867,
 110 } VPU_HW_ID;
 111
 112 enum VPU_HW_SPEC {
 113         VPU_TYPE_VPU,
 114         VPU_TYPE_HEVC,
 115         VPU_TYPE_COMBO_NOENC,
 116         VPU_TYPE_COMBO
 117 };
 118
 119 typedef enum {
 120         VPU_DEC_TYPE_9190       = 0,
 121         VPU_ENC_TYPE_8270       = 0x100,
 122         VPU_ENC_TYPE_4831       ,
 123 } VPU_HW_TYPE_E;
 124
 125 typedef enum VPU_FREQ {
 126         VPU_FREQ_200M,
 127         VPU_FREQ_266M,
 128         VPU_FREQ_300M,
 129         VPU_FREQ_400M,
 130         VPU_FREQ_500M,
 131         VPU_FREQ_600M,
 132         VPU_FREQ_DEFAULT,
 133         VPU_FREQ_BUT,
 134 } VPU_FREQ;
 135
 136 typedef struct {
 137         VPU_HW_ID               hw_id;
 138         unsigned long           hw_addr;
 139         unsigned long           enc_offset;
 140         unsigned long           enc_reg_num;
 141         unsigned long           enc_io_size;
 142         unsigned long           dec_offset;
 143         unsigned long           dec_reg_num;
 144         unsigned long           dec_io_size;
 145 } VPU_HW_INFO_E;
 146
 147 struct extra_info_elem {
 148         u32 index;
 149         u32 offset;
 150 };
 151
 152 #define EXTRA_INFO_MAGIC        0x4C4A46
 153
 154 struct extra_info_for_iommu {
 155         u32 magic;
 156         u32 cnt;
 157         struct extra_info_elem elem[20];
 158 };
 159
 160 #define MHZ                                     (1000*1000)
 161
 162 #define REG_NUM_9190_DEC                        (60)
 163 #define REG_NUM_9190_PP                         (41)
 164 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 165
 166 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 167
 168 #define REG_NUM_ENC_8270                        (96)
 169 #define REG_SIZE_ENC_8270                       (0x200)
 170 #define REG_NUM_ENC_4831                        (164)
 171 #define REG_SIZE_ENC_4831                       (0x400)
 172
 173 #define REG_NUM_HEVC_DEC                        (68)
 174
 175 #define SIZE_REG(reg)                           ((reg)*4)
 176
 177 static VPU_HW_INFO_E vpu_hw_set[] = {
 178         [0] = {
 179                 .hw_id          = VPU_ID_8270,
 180                 .hw_addr        = 0,
 181                 .enc_offset     = 0x0,
 182                 .enc_reg_num    = REG_NUM_ENC_8270,
 183                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 184                 .dec_offset     = REG_SIZE_ENC_8270,
 185                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 186                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 187         },
 188         [1] = {
 189                 .hw_id          = VPU_ID_4831,
 190                 .hw_addr        = 0,
 191                 .enc_offset     = 0x0,
 192                 .enc_reg_num    = REG_NUM_ENC_4831,
 193                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 194                 .dec_offset     = REG_SIZE_ENC_4831,
 195                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 196                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 197         },
 198         [2] = {
 199                 .hw_id          = HEVC_ID,
 200                 .hw_addr        = 0,
 201                 .dec_offset     = 0x0,
 202                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 203                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 204         },
 205         [3] = {
 206                 .hw_id          = VPU_DEC_ID_9190,
 207                 .hw_addr        = 0,
 208                 .enc_offset     = 0x0,
 209                 .enc_reg_num    = 0,
 210                 .enc_io_size    = 0,
 211                 .dec_offset     = 0,
 212                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 213                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 214         },
 215 };
 216
 217 #ifndef BIT
 218 #define BIT(x)                                  (1<<(x))
 219 #endif
 220
 221 // interrupt and error status register
 222 #define DEC_INTERRUPT_REGISTER                  1
 223 #define DEC_INTERRUPT_BIT                       BIT(8)
 224 #define DEC_READY_BIT                           BIT(12)
 225 #define DEC_BUS_ERROR_BIT                       BIT(13)
 226 #define DEC_BUFFER_EMPTY_BIT                    BIT(14)
 227 #define DEC_ASO_ERROR_BIT                       BIT(15)
 228 #define DEC_STREAM_ERROR_BIT                    BIT(16)
 229 #define DEC_SLICE_DONE_BIT                      BIT(17)
 230 #define DEC_TIMEOUT_BIT                         BIT(18)
 231 #define DEC_ERR_MASK                            DEC_BUS_ERROR_BIT \
 232                                                 |DEC_BUFFER_EMPTY_BIT \
 233                                                 |DEC_STREAM_ERROR_BIT \
 234                                                 |DEC_TIMEOUT_BIT
 235
 236 #define PP_INTERRUPT_REGISTER                   60
 237 #define PP_INTERRUPT_BIT                        BIT(8)
 238 #define PP_READY_BIT                            BIT(12)
 239 #define PP_BUS_ERROR_BIT                        BIT(13)
 240 #define PP_ERR_MASK                             PP_BUS_ERROR_BIT
 241
 242 #define ENC_INTERRUPT_REGISTER                  1
 243 #define ENC_INTERRUPT_BIT                       BIT(0)
 244 #define ENC_READY_BIT                           BIT(2)
 245 #define ENC_BUS_ERROR_BIT                       BIT(3)
 246 #define ENC_BUFFER_FULL_BIT                     BIT(5)
 247 #define ENC_TIMEOUT_BIT                         BIT(6)
 248 #define ENC_ERR_MASK                            ENC_BUS_ERROR_BIT \
 249                                                 |ENC_BUFFER_FULL_BIT \
 250                                                 |ENC_TIMEOUT_BIT
 251
 252 #define HEVC_INTERRUPT_REGISTER                 1
 253 #define HEVC_DEC_INT_RAW_BIT                    BIT(9)
 254 #define HEVC_DEC_BUS_ERROR_BIT                  BIT(13)
 255 #define HEVC_DEC_STR_ERROR_BIT                  BIT(14)
 256 #define HEVC_DEC_TIMEOUT_BIT                    BIT(15)
 257 #define HEVC_DEC_BUFFER_EMPTY_BIT               BIT(16)
 258 #define HEVC_DEC_COLMV_ERROR_BIT                BIT(17)
 259 #define HEVC_DEC_ERR_MASK                       HEVC_DEC_BUS_ERROR_BIT \
 260                                                 |HEVC_DEC_STR_ERROR_BIT \
 261                                                 |HEVC_DEC_TIMEOUT_BIT \
 262                                                 |HEVC_DEC_BUFFER_EMPTY_BIT \
 263                                                 |HEVC_DEC_COLMV_ERROR_BIT
 264
 265
 266 // gating configuration set
 267 #define VPU_REG_EN_ENC                          14
 268 #define VPU_REG_ENC_GATE                        2
 269 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 270
 271 #define VPU_REG_EN_DEC                          1
 272 #define VPU_REG_DEC_GATE                        2
 273 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 274 #define VPU_REG_EN_PP                           0
 275 #define VPU_REG_PP_GATE                         1
 276 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 277 #define VPU_REG_EN_DEC_PP                       1
 278 #define VPU_REG_DEC_PP_GATE                     61
 279 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 280
 281 #define DEBUG
 282 #ifdef DEBUG
 283 #define vpu_debug_func(type, fmt, args...)                      \
 284         do {                                                    \
 285                 if (unlikely(debug & type)) {                   \
 286                         pr_info("%s:%d: " fmt,                  \
 287                                  __func__, __LINE__, ##args);   \
 288                 }                                               \
 289         } while (0)
 290 #define vpu_debug(type, fmt, args...)                           \
 291         do {                                                    \
 292                 if (unlikely(debug & type)) {                   \
 293                         pr_info(fmt, ##args);                   \
 294                 }                                               \
 295         } while (0)
 296 #else
 297 #define vpu_debug_func(level, fmt, args...)
 298 #define vpu_debug(level, fmt, args...)
 299 #endif
 300
 301 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
 302 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
 303
 304 #define vpu_err(fmt, args...)                           \
 305                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 306
 307 #if defined(CONFIG_VCODEC_MMU)
 308 static u8 addr_tbl_vpu_h264dec[] = {
 309         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 310         25, 26, 27, 28, 29, 40, 41
 311 };
 312
 313 static u8 addr_tbl_vpu_vp8dec[] = {
 314         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 315 };
 316
 317 static u8 addr_tbl_vpu_vp6dec[] = {
 318         12, 13, 14, 18, 27, 40
 319 };
 320
 321 static u8 addr_tbl_vpu_vc1dec[] = {
 322         12, 13, 14, 15, 16, 17, 27, 41
 323 };
 324
 325 static u8 addr_tbl_vpu_jpegdec[] = {
 326         12, 40, 66, 67
 327 };
 328
 329 static u8 addr_tbl_vpu_defaultdec[] = {
 330         12, 13, 14, 15, 16, 17, 40, 41
 331 };
 332
 333 static u8 addr_tbl_vpu_enc[] = {
 334         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 335 };
 336
 337 static u8 addr_tbl_hevc_dec[] = {
 338         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 339         21, 22, 23, 24, 42, 43
 340 };
 341 #endif
 342
 343 enum VPU_DEC_FMT {
 344         VPU_DEC_FMT_H264,
 345         VPU_DEC_FMT_MPEG4,
 346         VPU_DEC_FMT_H263,
 347         VPU_DEC_FMT_JPEG,
 348         VPU_DEC_FMT_VC1,
 349         VPU_DEC_FMT_MPEG2,
 350         VPU_DEC_FMT_MPEG1,
 351         VPU_DEC_FMT_VP6,
 352         VPU_DEC_FMT_RV,
 353         VPU_DEC_FMT_VP7,
 354         VPU_DEC_FMT_VP8,
 355         VPU_DEC_FMT_AVS,
 356         VPU_DEC_FMT_SVC,
 357         VPU_DEC_FMT_VC2,
 358         VPU_DEC_FMT_MVC,
 359         VPU_DEC_FMT_THEORA,
 360         VPU_DEC_FMT_RES
 361 };
 362
 363 /**
 364  * struct for process session which connect to vpu
 365  *
 366  * @author ChenHengming (2011-5-3)
 367  */
 368 typedef struct vpu_session {
 369         enum VPU_CLIENT_TYPE type;
 370         /* a linked list of data so we can access them for debugging */
 371         struct list_head list_session;
 372         /* a linked list of register data waiting for process */
 373         struct list_head waiting;
 374         /* a linked list of register data in processing */
 375         struct list_head running;
 376         /* a linked list of register data processed */
 377         struct list_head done;
 378         wait_queue_head_t wait;
 379         pid_t pid;
 380         atomic_t task_running;
 381 } vpu_session;
 382
 383 /**
 384  * struct for process register set
 385  *
 386  * @author ChenHengming (2011-5-4)
 387  */
 388 typedef struct vpu_reg {
 389         enum VPU_CLIENT_TYPE type;
 390         VPU_FREQ freq;
 391         vpu_session *session;
 392         struct vpu_subdev_data *data;
 393         struct list_head session_link;          /* link to vpu service session */
 394         struct list_head status_link;           /* link to register set list */
 395         unsigned long size;
 396 #if defined(CONFIG_VCODEC_MMU)
 397         struct list_head mem_region_list;
 398 #endif
 399         u32 *reg;
 400 } vpu_reg;
 401
 402 typedef struct vpu_device {
 403         atomic_t                irq_count_codec;
 404         atomic_t                irq_count_pp;
 405         unsigned long           iobaseaddr;
 406         unsigned int            iosize;
 407         volatile u32            *hwregs;
 408 } vpu_device;
 409
 410 enum vcodec_device_id {
 411         VCODEC_DEVICE_ID_VPU,
 412         VCODEC_DEVICE_ID_HEVC,
 413         VCODEC_DEVICE_ID_COMBO
 414 };
 415
 416 enum VCODEC_RUNNING_MODE {
 417         VCODEC_RUNNING_MODE_NONE = -1,
 418         VCODEC_RUNNING_MODE_VPU,
 419         VCODEC_RUNNING_MODE_HEVC,
 420 };
 421
 422 struct vcodec_mem_region {
 423         struct list_head srv_lnk;
 424         struct list_head reg_lnk;
 425         struct list_head session_lnk;
 426         unsigned long iova;     /* virtual address for iommu */
 427         unsigned long len;
 428         u32 reg_idx;
 429         struct ion_handle *hdl;
 430 };
 431
 432 enum vpu_ctx_state {
 433         MMU_ACTIVATED   = BIT(0)
 434 };
 435
 436 struct vpu_subdev_data {
 437         struct cdev cdev;
 438         dev_t dev_t;
 439         struct class *cls;
 440         struct device *child_dev;
 441
 442         int irq_enc;
 443         int irq_dec;
 444         struct vpu_service_info *pservice;
 445
 446         u32 *regs;
 447         enum VCODEC_RUNNING_MODE mode;
 448         struct list_head lnk_service;
 449
 450         struct device *dev;
 451
 452         vpu_device enc_dev;
 453         vpu_device dec_dev;
 454         VPU_HW_INFO_E *hw_info;
 455
 456         u32 reg_size;
 457         unsigned long state;
 458
 459 #ifdef CONFIG_DEBUG_FS
 460         struct dentry *debugfs_dir;
 461         struct dentry *debugfs_file_regs;
 462 #endif
 463
 464 #if defined(CONFIG_VCODEC_MMU)
 465         struct device *mmu_dev;
 466 #endif
 467 };
 468
 469 typedef struct vpu_service_info {
 470         struct wake_lock wake_lock;
 471         struct delayed_work power_off_work;
 472         struct mutex lock;
 473         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 474         struct list_head running;               /* link to link_reg in struct vpu_reg */
 475         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 476         struct list_head session;               /* link to list_session in struct vpu_session */
 477         atomic_t total_running;
 478         atomic_t enabled;
 479         atomic_t power_on_cnt;
 480         atomic_t power_off_cnt;
 481         vpu_reg *reg_codec;
 482         vpu_reg *reg_pproc;
 483         vpu_reg *reg_resev;
 484         struct vpu_dec_config dec_config;
 485         struct vpu_enc_config enc_config;
 486
 487         bool auto_freq;
 488         bool bug_dec_addr;
 489         atomic_t freq_status;
 490
 491         struct clk *aclk_vcodec;
 492         struct clk *hclk_vcodec;
 493         struct clk *clk_core;
 494         struct clk *clk_cabac;
 495         struct clk *pd_video;
 496
 497         struct device *dev;
 498
 499         u32 irq_status;
 500         atomic_t reset_request;
 501 #if defined(CONFIG_VCODEC_MMU)
 502         struct ion_client *ion_client;
 503         struct list_head mem_region_list;
 504 #endif
 505
 506         enum vcodec_device_id dev_id;
 507
 508         enum VCODEC_RUNNING_MODE curr_mode;
 509         u32 prev_mode;
 510
 511         struct delayed_work simulate_work;
 512
 513         u32 mode_bit;
 514         u32 mode_ctrl;
 515         u32 *reg_base;
 516         u32 ioaddr;
 517 #ifdef CONFIG_MFD_SYSCON
 518         struct regmap *grf_base;
 519 #else
 520         u32 *grf_base;
 521 #endif
 522         char *name;
 523
 524         u32 subcnt;
 525         struct list_head subdev_list;
 526 } vpu_service_info;
 527
 528 struct vcodec_combo {
 529         struct vpu_service_info *vpu_srv;
 530         struct vpu_service_info *hevc_srv;
 531         struct list_head waiting;
 532         struct list_head running;
 533         struct mutex run_lock;
 534         vpu_reg *reg_codec;
 535         enum vcodec_device_id current_hw_mode;
 536 };
 537
 538 struct vpu_request {
 539         u32 *req;
 540         u32 size;
 541 };
 542
 543 struct compat_vpu_request {
 544         compat_uptr_t req;
 545         u32 size;
 546 };
 547
 548 /* debugfs root directory for all device (vpu, hevc).*/
 549 static struct dentry *parent;
 550
 551 #ifdef CONFIG_DEBUG_FS
 552 static int vcodec_debugfs_init(void);
 553 static void vcodec_debugfs_exit(void);
 554 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 555 static int debug_vcodec_open(struct inode *inode, struct file *file);
 556
 557 static const struct file_operations debug_vcodec_fops = {
 558         .open = debug_vcodec_open,
 559         .read = seq_read,
 560         .llseek = seq_lseek,
 561         .release = single_release,
 562 };
 563 #endif
 564
 565 #define VDPU_SOFT_RESET_REG     101
 566 #define VDPU_CLEAN_CACHE_REG    516
 567 #define VEPU_CLEAN_CACHE_REG    772
 568 #define HEVC_CLEAN_CACHE_REG    260
 569
 570 #define VPU_REG_ENABLE(base, reg)       do { \
 571                                                 base[reg] = 1; \
 572                                         } while (0)
 573
 574 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 575 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 576 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 577 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 578
 579 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 580 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 581
 582 typedef struct {
 583         char *name;
 584         struct timeval start;
 585         struct timeval end;
 586         u32 error_mask;
 587 } task_info;
 588
 589 typedef enum {
 590         TASK_VPU_ENC,
 591         TASK_VPU_DEC,
 592         TASK_VPU_PP,
 593         TASK_RKDEC_HEVC,
 594         TASK_TYPE_BUTT,
 595 } TASK_TYPE;
 596
 597 task_info tasks[TASK_TYPE_BUTT] = {
 598         {
 599                 .name = "enc",
 600                 .error_mask = ENC_ERR_MASK
 601         },
 602         {
 603                 .name = "dec",
 604                 .error_mask = DEC_ERR_MASK
 605         },
 606         {
 607                 .name = "pp",
 608                 .error_mask = PP_ERR_MASK
 609         },
 610         {
 611                 .name = "hevc",
 612                 .error_mask = HEVC_DEC_ERR_MASK
 613         },
 614 };
 615
 616 static void time_record(task_info *task, int is_end)
 617 {
 618         if (unlikely(debug & DEBUG_TIMING)) {
 619                 do_gettimeofday((is_end)?(&task->end):(&task->start));
 620         }
 621 }
 622
 623 static void time_diff(task_info *task)
 624 {
 625         vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
 626                         (task->end.tv_sec  - task->start.tv_sec)  * 1000 +
 627                         (task->end.tv_usec - task->start.tv_usec) / 1000);
 628 }
 629
 630 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 631 {
 632         int bits;
 633         u32 raw = 0;
 634         struct vpu_service_info *pservice = data->pservice;
 635         struct vpu_subdev_data *subdata, *n;
 636         if (pservice->subcnt < 2) {
 637 #if defined(CONFIG_VCODEC_MMU)
 638                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 639                         set_bit(MMU_ACTIVATED, &data->state);
 640                         if (atomic_read(&pservice->enabled))
 641                                 rockchip_iovmm_activate(data->dev);
 642                         else
 643                                 BUG_ON(!atomic_read(&pservice->enabled));
 644                 }
 645 #endif
 646                 return;
 647         }
 648
 649         if (pservice->curr_mode == data->mode)
 650                 return;
 651
 652         vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
 653 #if defined(CONFIG_VCODEC_MMU)
 654         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 655                 if (data != subdata && subdata->mmu_dev &&
 656                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 657                         clear_bit(MMU_ACTIVATED, &subdata->state);
 658                         rockchip_iovmm_deactivate(subdata->dev);
 659                 }
 660         }
 661 #endif
 662         bits = 1 << pservice->mode_bit;
 663 #ifdef CONFIG_MFD_SYSCON
 664         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 665
 666         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 667                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 668                         raw | bits | (bits << 16));
 669         else
 670                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 671                         (raw & (~bits)) | (bits << 16));
 672 #else
 673         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 674         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 675                 writel_relaxed(raw | bits | (bits << 16),
 676                         pservice->grf_base + pservice->mode_ctrl / 4);
 677         else
 678                 writel_relaxed((raw & (~bits)) | (bits << 16),
 679                         pservice->grf_base + pservice->mode_ctrl / 4);
 680 #endif
 681 #if defined(CONFIG_VCODEC_MMU)
 682         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 683                 set_bit(MMU_ACTIVATED, &data->state);
 684                 if (atomic_read(&pservice->enabled))
 685                         rockchip_iovmm_activate(data->dev);
 686                 else
 687                         BUG_ON(!atomic_read(&pservice->enabled));
 688         }
 689 #endif
 690         pservice->prev_mode = pservice->curr_mode;
 691         pservice->curr_mode = data->mode;
 692 }
 693
 694 static void vcodec_exit_mode(struct vpu_subdev_data *data)
 695 {
 696         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 697                 clear_bit(MMU_ACTIVATED, &data->state);
 698                 rockchip_iovmm_deactivate(data->dev);
 699                 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 700         }
 701 }
 702
 703 static int vpu_get_clk(struct vpu_service_info *pservice)
 704 {
 705 #if VCODEC_CLOCK_ENABLE
 706         switch (pservice->dev_id) {
 707         case VCODEC_DEVICE_ID_HEVC:
 708                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 709                 if (IS_ERR(pservice->pd_video)) {
 710                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 711                         return -1;
 712                 }
 713         case VCODEC_DEVICE_ID_COMBO:
 714                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 715                 if (IS_ERR(pservice->clk_cabac)) {
 716                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 717                         pservice->clk_cabac = NULL;
 718                 }
 719                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 720                 if (IS_ERR(pservice->clk_core)) {
 721                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 722                         return -1;
 723                 }
 724         case VCODEC_DEVICE_ID_VPU:
 725                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 726                 if (IS_ERR(pservice->aclk_vcodec)) {
 727                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 728                         return -1;
 729                 }
 730
 731                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 732                 if (IS_ERR(pservice->hclk_vcodec)) {
 733                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 734                         return -1;
 735                 }
 736                 if (pservice->pd_video == NULL) {
 737                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 738                         if (IS_ERR(pservice->pd_video)) {
 739                                 pservice->pd_video = NULL;
 740                                 dev_info(pservice->dev, "do not have pd_video\n");
 741                         }
 742                 }
 743                 break;
 744         default:
 745                 ;
 746         }
 747
 748         return 0;
 749 #else
 750         return 0;
 751 #endif
 752 }
 753
 754 static void vpu_put_clk(struct vpu_service_info *pservice)
 755 {
 756 #if VCODEC_CLOCK_ENABLE
 757         if (pservice->pd_video)
 758                 devm_clk_put(pservice->dev, pservice->pd_video);
 759         if (pservice->aclk_vcodec)
 760                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 761         if (pservice->hclk_vcodec)
 762                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 763         if (pservice->clk_core)
 764                 devm_clk_put(pservice->dev, pservice->clk_core);
 765         if (pservice->clk_cabac)
 766                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 767 #endif
 768 }
 769
 770 static const u8 pmu_idle_map[] = {
 771         [IDLE_REQ_VIDEO] = 7,
 772 };
 773
 774 extern void __iomem *rk_cru_base;
 775 static void cru_writel(u32 val, u32 offset)
 776 {
 777         writel_relaxed(val, rk_cru_base + (offset));
 778         dsb(sy);
 779 }
 780
 781 extern int rk3368_pmu_set_idle_request(enum pmu_idle_req req, bool idle);
 782 static inline void rk3368_cru_set_soft_reset(u32 idx, bool on)
 783 {
 784         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
 785         cru_writel(val, 0x31c);
 786 }
 787 #define SOFT_RST_VCODEC_AXI     (7*16)
 788 #define SOFT_RST_VCODEC_AHB     (7*16+1)
 789
 790 static void vpu_reset(struct vpu_subdev_data *data)
 791 {
 792         struct vpu_service_info *pservice = data->pservice;
 793         pr_info("%s: resetting...", dev_name(pservice->dev));
 794
 795 #if defined(CONFIG_ARCH_RK29)
 796         clk_disable(aclk_ddr_vepu);
 797         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 798         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 799         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 800         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 801         mdelay(10);
 802         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 803         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 804         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 805         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 806         clk_enable(aclk_ddr_vepu);
 807 #elif defined(CONFIG_ARCH_RK30)
 808         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 809         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 810         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 811         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 812         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 813         mdelay(1);
 814         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 815         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 816         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 817         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 818         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 819 #else
 820 #endif
 821         WARN_ON(pservice->reg_codec != NULL);
 822         WARN_ON(pservice->reg_pproc != NULL);
 823         WARN_ON(pservice->reg_resev != NULL);
 824         pservice->reg_codec = NULL;
 825         pservice->reg_pproc = NULL;
 826         pservice->reg_resev = NULL;
 827
 828         pr_info("for 3288/3368...");
 829         /**rk3368_pmu_set_idle_request(IDLE_REQ_VIDEO, true);*/
 830         /*rockchip_pmu_ops.set_idle_request(IDLE_REQ_VIDEO, true);*/
 831         /**rockchip_pmu_ops.set_power_domain(PD_VIDEO, false);*/
 832         /*rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 833         rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 834         mdelay(1);
 835         rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 836         rk3368_cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);*/
 837         /**rockchip_pmu_ops.set_power_domain(PD_VIDEO, true);*/
 838         /*rockchip_pmu_ops.set_idle_request(IDLE_REQ_VIDEO, false);*/
 839         /**rk3368_pmu_set_idle_request(IDLE_REQ_VIDEO, false);*/
 840
 841 #if defined(CONFIG_VCODEC_MMU)
 842         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 843                 clear_bit(MMU_ACTIVATED, &data->state);
 844                 if (atomic_read(&pservice->enabled))
 845                         rockchip_iovmm_deactivate(data->dev);
 846                 else
 847                         BUG_ON(!atomic_read(&pservice->enabled));
 848         }
 849 #endif
 850         atomic_set(&pservice->reset_request, 0);
 851         pr_info("done\n");
 852 }
 853
 854 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 855 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 856 {
 857         vpu_reg *reg, *n;
 858         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 859                 reg_deinit(data, reg);
 860         }
 861         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 862                 reg_deinit(data, reg);
 863         }
 864         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 865                 reg_deinit(data, reg);
 866         }
 867 }
 868
 869 static void vpu_service_dump(struct vpu_service_info *pservice)
 870 {
 871 }
 872
 873 static void vpu_service_power_off(struct vpu_service_info *pservice)
 874 {
 875         int total_running;
 876         struct vpu_subdev_data *data = NULL, *n;
 877         int ret = atomic_add_unless(&pservice->enabled, -1, 0);
 878         if (!ret)
 879                 return;
 880
 881         total_running = atomic_read(&pservice->total_running);
 882         if (total_running) {
 883                 pr_alert("alert: power off when %d task running!!\n", total_running);
 884                 mdelay(50);
 885                 pr_alert("alert: delay 50 ms for running task\n");
 886                 vpu_service_dump(pservice);
 887         }
 888
 889         pr_info("%s: power off...", dev_name(pservice->dev));
 890         udelay(10);
 891 #if defined(CONFIG_VCODEC_MMU)
 892         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 893                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 894                         clear_bit(MMU_ACTIVATED, &data->state);
 895                         rockchip_iovmm_deactivate(data->dev);
 896                 }
 897         }
 898         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 899 #endif
 900
 901 #if VCODEC_CLOCK_ENABLE
 902         if (pservice->pd_video)
 903                 clk_disable_unprepare(pservice->pd_video);
 904         if (pservice->hclk_vcodec)
 905                 clk_disable_unprepare(pservice->hclk_vcodec);
 906         if (pservice->aclk_vcodec)
 907                 clk_disable_unprepare(pservice->aclk_vcodec);
 908         if (pservice->clk_core)
 909                 clk_disable_unprepare(pservice->clk_core);
 910         if (pservice->clk_cabac)
 911                 clk_disable_unprepare(pservice->clk_cabac);
 912 #endif
 913
 914         atomic_add(1, &pservice->power_off_cnt);
 915         wake_unlock(&pservice->wake_lock);
 916         pr_info("done\n");
 917 }
 918
 919 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 920 {
 921         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 922 }
 923
 924 static void vpu_power_off_work(struct work_struct *work_s)
 925 {
 926         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 927         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 928
 929         if (mutex_trylock(&pservice->lock)) {
 930                 vpu_service_power_off(pservice);
 931                 mutex_unlock(&pservice->lock);
 932         } else {
 933                 /* Come back later if the device is busy... */
 934                 vpu_queue_power_off_work(pservice);
 935         }
 936 }
 937
 938 static void vpu_service_power_on(struct vpu_service_info *pservice)
 939 {
 940         int ret;
 941         static ktime_t last;
 942         ktime_t now = ktime_get();
 943         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 944                 cancel_delayed_work_sync(&pservice->power_off_work);
 945                 vpu_queue_power_off_work(pservice);
 946                 last = now;
 947         }
 948         ret = atomic_add_unless(&pservice->enabled, 1, 1);
 949         if (!ret)
 950                 return ;
 951
 952         pr_info("%s: power on\n", dev_name(pservice->dev));
 953
 954 #define BIT_VCODEC_CLK_SEL      (1<<10)
 955         if (cpu_is_rk312x())
 956                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 957                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 958                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 959
 960 #if VCODEC_CLOCK_ENABLE
 961         if (pservice->aclk_vcodec)
 962                 clk_prepare_enable(pservice->aclk_vcodec);
 963         if (pservice->hclk_vcodec)
 964                 clk_prepare_enable(pservice->hclk_vcodec);
 965         if (pservice->clk_core)
 966                 clk_prepare_enable(pservice->clk_core);
 967         if (pservice->clk_cabac)
 968                 clk_prepare_enable(pservice->clk_cabac);
 969         if (pservice->pd_video)
 970                 clk_prepare_enable(pservice->pd_video);
 971 #endif
 972
 973         udelay(10);
 974         atomic_add(1, &pservice->power_on_cnt);
 975         wake_lock(&pservice->wake_lock);
 976 }
 977
 978 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 979 {
 980         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 981         return ((type == 8) || (type == 4));
 982 }
 983
 984 static inline bool reg_check_interlace(vpu_reg *reg)
 985 {
 986         u32 type = (reg->reg[3] & (1 << 23));
 987         return (type > 0);
 988 }
 989
 990 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 991 {
 992         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 993         return type;
 994 }
 995
 996 static inline int reg_probe_width(vpu_reg *reg)
 997 {
 998         int width_in_mb = reg->reg[4] >> 23;
 999         return width_in_mb * 16;
1000 }
1001
1002 #if defined(CONFIG_VCODEC_MMU)
1003 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
1004 {
1005         struct vpu_service_info *pservice = data->pservice;
1006         struct ion_handle *hdl;
1007         int ret = 0;
1008         struct vcodec_mem_region *mem_region;
1009
1010         hdl = ion_import_dma_buf(pservice->ion_client, fd);
1011         if (IS_ERR(hdl)) {
1012                 vpu_err("import dma-buf from fd %d failed\n", fd);
1013                 return PTR_ERR(hdl);
1014         }
1015         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1016
1017         if (mem_region == NULL) {
1018                 vpu_err("allocate memory for iommu memory region failed\n");
1019                 ion_free(pservice->ion_client, hdl);
1020                 return -1;
1021         }
1022
1023         mem_region->hdl = hdl;
1024         ret = ion_map_iommu(data->dev, pservice->ion_client,
1025                 mem_region->hdl, &mem_region->iova, &mem_region->len);
1026
1027         if (ret < 0) {
1028                 vpu_err("ion map iommu failed\n");
1029                 kfree(mem_region);
1030                 ion_free(pservice->ion_client, hdl);
1031                 return ret;
1032         }
1033         INIT_LIST_HEAD(&mem_region->reg_lnk);
1034         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1035         return mem_region->iova;
1036 }
1037
1038 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1039                                 int size, vpu_reg *reg,
1040                                 struct extra_info_for_iommu *ext_inf)
1041 {
1042         struct vpu_service_info *pservice = data->pservice;
1043         int i;
1044         int usr_fd = 0;
1045         int offset = 0;
1046
1047         if (tbl == NULL || size <= 0) {
1048                 dev_err(pservice->dev, "input arguments invalidate\n");
1049                 return -1;
1050         }
1051
1052         for (i = 0; i < size; i++) {
1053                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1054
1055                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1056                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1057                         /* special for vpu dec num 41 regitster */
1058                         offset = reg->reg[tbl[i]] >> 10 << 4;
1059                 else
1060                         offset = reg->reg[tbl[i]] >> 10;
1061
1062                 if (usr_fd != 0) {
1063                         struct ion_handle *hdl;
1064                         int ret = 0;
1065                         struct vcodec_mem_region *mem_region;
1066
1067                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1068                         if (IS_ERR(hdl)) {
1069                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1070                                 return PTR_ERR(hdl);
1071                         }
1072
1073                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1074                                 int i = 0;
1075                                 char *pps;
1076                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1077                                 for (i=0; i<64; i++) {
1078                                         u32 scaling_offset;
1079                                         u32 tmp;
1080                                         int scaling_fd= 0;
1081                                         scaling_offset = (u32)pps[i*80+74];
1082                                         scaling_offset += (u32)pps[i*80+75] << 8;
1083                                         scaling_offset += (u32)pps[i*80+76] << 16;
1084                                         scaling_offset += (u32)pps[i*80+77] << 24;
1085                                         scaling_fd = scaling_offset&0x3ff;
1086                                         scaling_offset = scaling_offset >> 10;
1087                                         if(scaling_fd > 0) {
1088                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1089                                                 tmp += scaling_offset;
1090                                                 pps[i*80+74] = tmp & 0xff;
1091                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
1092                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
1093                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
1094                                         }
1095                                 }
1096                         }
1097
1098                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1099
1100                         if (mem_region == NULL) {
1101                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1102                                 ion_free(pservice->ion_client, hdl);
1103                                 return -1;
1104                         }
1105
1106                         mem_region->hdl = hdl;
1107                         mem_region->reg_idx = tbl[i];
1108                         ret = ion_map_iommu(data->dev,
1109                                             pservice->ion_client,
1110                                             mem_region->hdl,
1111                                             &mem_region->iova,
1112                                             &mem_region->len);
1113
1114                         if (ret < 0) {
1115                                 dev_err(pservice->dev, "ion map iommu failed\n");
1116                                 kfree(mem_region);
1117                                 ion_free(pservice->ion_client, hdl);
1118                                 return ret;
1119                         }
1120                         reg->reg[tbl[i]] = mem_region->iova + offset;
1121                         INIT_LIST_HEAD(&mem_region->reg_lnk);
1122                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1123                 }
1124         }
1125
1126         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1127                 for (i=0; i<ext_inf->cnt; i++) {
1128                         vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1129                                   ext_inf->elem[i].index,
1130                                   ext_inf->elem[i].offset);
1131                         reg->reg[ext_inf->elem[i].index] +=
1132                                 ext_inf->elem[i].offset;
1133                 }
1134         }
1135
1136         return 0;
1137 }
1138
1139 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1140                                         vpu_reg *reg,
1141                                         struct extra_info_for_iommu *ext_inf)
1142 {
1143         VPU_HW_ID hw_id;
1144         u8 *tbl;
1145         int size = 0;
1146
1147         hw_id = data->hw_info->hw_id;
1148
1149         if (hw_id == HEVC_ID) {
1150                 tbl = addr_tbl_hevc_dec;
1151                 size = sizeof(addr_tbl_hevc_dec);
1152         } else {
1153                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1154                         switch (reg_check_fmt(reg)) {
1155                         case VPU_DEC_FMT_H264:
1156                                 {
1157                                         tbl = addr_tbl_vpu_h264dec;
1158                                         size = sizeof(addr_tbl_vpu_h264dec);
1159                                         break;
1160                                 }
1161                         case VPU_DEC_FMT_VP8:
1162                         case VPU_DEC_FMT_VP7:
1163                                 {
1164                                         tbl = addr_tbl_vpu_vp8dec;
1165                                         size = sizeof(addr_tbl_vpu_vp8dec);
1166                                         break;
1167                                 }
1168
1169                         case VPU_DEC_FMT_VP6:
1170                                 {
1171                                         tbl = addr_tbl_vpu_vp6dec;
1172                                         size = sizeof(addr_tbl_vpu_vp6dec);
1173                                         break;
1174                                 }
1175                         case VPU_DEC_FMT_VC1:
1176                                 {
1177                                         tbl = addr_tbl_vpu_vc1dec;
1178                                         size = sizeof(addr_tbl_vpu_vc1dec);
1179                                         break;
1180                                 }
1181
1182                         case VPU_DEC_FMT_JPEG:
1183                                 {
1184                                         tbl = addr_tbl_vpu_jpegdec;
1185                                         size = sizeof(addr_tbl_vpu_jpegdec);
1186                                         break;
1187                                 }
1188                         default:
1189                                 tbl = addr_tbl_vpu_defaultdec;
1190                                 size = sizeof(addr_tbl_vpu_defaultdec);
1191                                 break;
1192                         }
1193                 } else if (reg->type == VPU_ENC) {
1194                         tbl = addr_tbl_vpu_enc;
1195                         size = sizeof(addr_tbl_vpu_enc);
1196                 }
1197         }
1198
1199         if (size != 0) {
1200                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1201         } else {
1202                 return -1;
1203         }
1204 }
1205 #endif
1206
1207 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1208         vpu_session *session, void __user *src, u32 size)
1209 {
1210         struct vpu_service_info *pservice = data->pservice;
1211         int extra_size = 0;
1212         struct extra_info_for_iommu extra_info;
1213         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1214
1215         vpu_debug_enter();
1216
1217         if (NULL == reg) {
1218                 vpu_err("error: kmalloc fail in reg_init\n");
1219                 return NULL;
1220         }
1221
1222         if (size > data->reg_size) {
1223                 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1224                   size, data->reg_size);*/
1225                 extra_size = size - data->reg_size;
1226                 size = data->reg_size;
1227         }
1228         reg->session = session;
1229         reg->data = data;
1230         reg->type = session->type;
1231         reg->size = size;
1232         reg->freq = VPU_FREQ_DEFAULT;
1233         reg->reg = (u32 *)&reg[1];
1234         INIT_LIST_HEAD(&reg->session_link);
1235         INIT_LIST_HEAD(&reg->status_link);
1236
1237 #if defined(CONFIG_VCODEC_MMU)
1238         if (data->mmu_dev)
1239                 INIT_LIST_HEAD(&reg->mem_region_list);
1240 #endif
1241
1242         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1243                 vpu_err("error: copy_from_user failed in reg_init\n");
1244                 kfree(reg);
1245                 return NULL;
1246         }
1247
1248         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1249                 vpu_err("error: copy_from_user failed in reg_init\n");
1250                 kfree(reg);
1251                 return NULL;
1252         }
1253
1254 #if defined(CONFIG_VCODEC_MMU)
1255         if (data->mmu_dev &&
1256             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1257                 vpu_err("error: translate reg address failed\n");
1258                 kfree(reg);
1259                 return NULL;
1260         }
1261 #endif
1262
1263         mutex_lock(&pservice->lock);
1264         list_add_tail(&reg->status_link, &pservice->waiting);
1265         list_add_tail(&reg->session_link, &session->waiting);
1266         mutex_unlock(&pservice->lock);
1267
1268         if (pservice->auto_freq) {
1269                 if (!soc_is_rk2928g()) {
1270                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1271                                 if (reg_check_rmvb_wmv(reg)) {
1272                                         reg->freq = VPU_FREQ_200M;
1273                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1274                                         if (reg_probe_width(reg) > 3200) {
1275                                                 /*raise frequency for 4k avc.*/
1276                                                 reg->freq = VPU_FREQ_500M;
1277                                         }
1278                                 } else {
1279                                         if (reg_check_interlace(reg)) {
1280                                                 reg->freq = VPU_FREQ_400M;
1281                                         }
1282                                 }
1283                         }
1284                         if (reg->type == VPU_PP) {
1285                                 reg->freq = VPU_FREQ_400M;
1286                         }
1287                 }
1288         }
1289         vpu_debug_leave();
1290         return reg;
1291 }
1292
1293 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1294 {
1295         struct vpu_service_info *pservice = data->pservice;
1296 #if defined(CONFIG_VCODEC_MMU)
1297         struct vcodec_mem_region *mem_region = NULL, *n;
1298 #endif
1299
1300         list_del_init(&reg->session_link);
1301         list_del_init(&reg->status_link);
1302         if (reg == pservice->reg_codec)
1303                 pservice->reg_codec = NULL;
1304         if (reg == pservice->reg_pproc)
1305                 pservice->reg_pproc = NULL;
1306
1307 #if defined(CONFIG_VCODEC_MMU)
1308         /* release memory region attach to this registers table. */
1309         if (data->mmu_dev) {
1310                 list_for_each_entry_safe(mem_region, n,
1311                         &reg->mem_region_list, reg_lnk) {
1312                         /* do not unmap iommu manually,
1313                            unmap will proccess when memory release */
1314                         /*vcodec_enter_mode(data);
1315                         ion_unmap_iommu(data->dev,
1316                                         pservice->ion_client,
1317                                         mem_region->hdl);
1318                         vcodec_exit_mode();*/
1319                         ion_free(pservice->ion_client, mem_region->hdl);
1320                         list_del_init(&mem_region->reg_lnk);
1321                         kfree(mem_region);
1322                 }
1323         }
1324 #endif
1325
1326         kfree(reg);
1327 }
1328
1329 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1330 {
1331         vpu_debug_enter();
1332         list_del_init(&reg->status_link);
1333         list_add_tail(&reg->status_link, &pservice->running);
1334
1335         list_del_init(&reg->session_link);
1336         list_add_tail(&reg->session_link, &reg->session->running);
1337         vpu_debug_leave();
1338 }
1339
1340 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1341 {
1342         int i;
1343         u32 *dst = (u32 *)&reg->reg[0];
1344         vpu_debug_enter();
1345         for (i = 0; i < count; i++)
1346                 *dst++ = *src++;
1347         vpu_debug_leave();
1348 }
1349
1350 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1351         vpu_reg *reg)
1352 {
1353         struct vpu_service_info *pservice = data->pservice;
1354         int irq_reg = -1;
1355
1356         vpu_debug_enter();
1357
1358         list_del_init(&reg->status_link);
1359         list_add_tail(&reg->status_link, &pservice->done);
1360
1361         list_del_init(&reg->session_link);
1362         list_add_tail(&reg->session_link, &reg->session->done);
1363
1364         /*vcodec_enter_mode(data);*/
1365         switch (reg->type) {
1366         case VPU_ENC : {
1367                 pservice->reg_codec = NULL;
1368                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1369                 irq_reg = ENC_INTERRUPT_REGISTER;
1370                 break;
1371         }
1372         case VPU_DEC : {
1373                 int reg_len = REG_NUM_9190_DEC;
1374                 pservice->reg_codec = NULL;
1375                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1376                 irq_reg = DEC_INTERRUPT_REGISTER;
1377                 break;
1378         }
1379         case VPU_PP : {
1380                 pservice->reg_pproc = NULL;
1381                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1382                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1383                 break;
1384         }
1385         case VPU_DEC_PP : {
1386                 pservice->reg_codec = NULL;
1387                 pservice->reg_pproc = NULL;
1388                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1389                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1390                 break;
1391         }
1392         default : {
1393                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1394                 break;
1395         }
1396         }
1397         vcodec_exit_mode(data);
1398
1399         if (irq_reg != -1)
1400                 reg->reg[irq_reg] = pservice->irq_status;
1401
1402         atomic_sub(1, &reg->session->task_running);
1403         atomic_sub(1, &pservice->total_running);
1404         wake_up(&reg->session->wait);
1405
1406         vpu_debug_leave();
1407 }
1408
1409 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1410 {
1411         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1412         if (curr == reg->freq)
1413                 return;
1414         atomic_set(&pservice->freq_status, reg->freq);
1415         switch (reg->freq) {
1416         case VPU_FREQ_200M : {
1417                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1418         } break;
1419         case VPU_FREQ_266M : {
1420                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1421         } break;
1422         case VPU_FREQ_300M : {
1423                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1424         } break;
1425         case VPU_FREQ_400M : {
1426                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1427         } break;
1428         case VPU_FREQ_500M : {
1429                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1430         } break;
1431         case VPU_FREQ_600M : {
1432                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1433         } break;
1434         default : {
1435                 if (soc_is_rk2928g())
1436                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1437                 else
1438                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1439         } break;
1440         }
1441 }
1442
1443 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1444 {
1445         struct vpu_service_info *pservice = data->pservice;
1446         int i;
1447         u32 *src = (u32 *)&reg->reg[0];
1448         vpu_debug_enter();
1449
1450         atomic_add(1, &pservice->total_running);
1451         atomic_add(1, &reg->session->task_running);
1452         if (pservice->auto_freq)
1453                 vpu_service_set_freq(pservice, reg);
1454
1455         vcodec_enter_mode(data);
1456
1457         switch (reg->type) {
1458         case VPU_ENC : {
1459                 int enc_count = data->hw_info->enc_reg_num;
1460                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1461
1462                 pservice->reg_codec = reg;
1463
1464                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1465
1466                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1467                         dst[i] = src[i];
1468
1469                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1470                         dst[i] = src[i];
1471
1472                 VEPU_CLEAN_CACHE(dst);
1473
1474                 dsb(sy);
1475
1476                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1477                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1478
1479                 time_record(&tasks[TASK_VPU_ENC], 0);
1480         } break;
1481         case VPU_DEC : {
1482                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1483
1484                 pservice->reg_codec = reg;
1485
1486                 if (data->hw_info->hw_id != HEVC_ID) {
1487                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1488                                 dst[i] = src[i];
1489                         VDPU_CLEAN_CACHE(dst);
1490                 } else {
1491                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1492                                 dst[i] = src[i];
1493                         HEVC_CLEAN_CACHE(dst);
1494                 }
1495
1496                 dsb(sy);
1497
1498                 if (data->hw_info->hw_id != HEVC_ID) {
1499                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1500                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1501                 } else {
1502                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1503                 }
1504                 dsb(sy);
1505                 dmb(sy);
1506
1507                 time_record(&tasks[TASK_VPU_DEC], 0);
1508         } break;
1509         case VPU_PP : {
1510                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1511                 pservice->reg_pproc = reg;
1512
1513                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1514
1515                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1516                         dst[i] = src[i];
1517
1518                 dsb(sy);
1519
1520                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1521
1522                 time_record(&tasks[TASK_VPU_PP], 0);
1523         } break;
1524         case VPU_DEC_PP : {
1525                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1526                 pservice->reg_codec = reg;
1527                 pservice->reg_pproc = reg;
1528
1529                 VDPU_SOFT_RESET(dst);
1530                 VDPU_CLEAN_CACHE(dst);
1531
1532                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1533                         dst[i] = src[i];
1534
1535                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1536                 dsb(sy);
1537
1538                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1539                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1540                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1541
1542                 time_record(&tasks[TASK_VPU_DEC], 0);
1543         } break;
1544         default : {
1545                 vpu_err("error: unsupport session type %d", reg->type);
1546                 atomic_sub(1, &pservice->total_running);
1547                 atomic_sub(1, &reg->session->task_running);
1548         } break;
1549         }
1550
1551         /*vcodec_exit_mode(data);*/
1552         vpu_debug_leave();
1553 }
1554
1555 static void try_set_reg(struct vpu_subdev_data *data)
1556 {
1557         struct vpu_service_info *pservice = data->pservice;
1558         vpu_debug_enter();
1559         if (!list_empty(&pservice->waiting)) {
1560                 int can_set = 0;
1561                 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1562                 int reset_request = atomic_read(&pservice->reset_request);
1563                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1564
1565                 vpu_service_power_on(pservice);
1566
1567                 // first check can_set flag
1568                 if (change_able || !reset_request) {
1569                         switch (reg->type) {
1570                         case VPU_ENC : {
1571                                 if (change_able)
1572                                         can_set = 1;
1573                         } break;
1574                         case VPU_DEC : {
1575                                 if (NULL == pservice->reg_codec)
1576                                         can_set = 1;
1577                                 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1578                                         can_set = 0;
1579                         } break;
1580                         case VPU_PP : {
1581                                 if (NULL == pservice->reg_codec) {
1582                                         if (NULL == pservice->reg_pproc)
1583                                                 can_set = 1;
1584                                 } else {
1585                                         if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1586                                                 can_set = 1;
1587                                         /* can not charge frequency when vpu is working */
1588                                         if (pservice->auto_freq)
1589                                                 can_set = 0;
1590                                 }
1591                         } break;
1592                         case VPU_DEC_PP : {
1593                                 if (change_able)
1594                                         can_set = 1;
1595                                 } break;
1596                         default : {
1597                                 printk("undefined reg type %d\n", reg->type);
1598                         } break;
1599                         }
1600                 }
1601
1602                 // then check reset request
1603                 if (reset_request && !change_able)
1604                         reset_request = 0;
1605
1606                 // do reset before setting registers
1607                 if (reset_request)
1608                         vpu_reset(data);
1609
1610                 if (can_set) {
1611                         reg_from_wait_to_run(pservice, reg);
1612                         reg_copy_to_hw(reg->data, reg);
1613                 }
1614         }
1615         vpu_debug_leave();
1616 }
1617
1618 static int return_reg(struct vpu_subdev_data *data,
1619         vpu_reg *reg, u32 __user *dst)
1620 {
1621         int ret = 0;
1622         vpu_debug_enter();
1623         switch (reg->type) {
1624         case VPU_ENC : {
1625                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1626                         ret = -EFAULT;
1627                 break;
1628         }
1629         case VPU_DEC : {
1630                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1631                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1632                         ret = -EFAULT;
1633                 break;
1634         }
1635         case VPU_PP : {
1636                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1637                         ret = -EFAULT;
1638                 break;
1639         }
1640         case VPU_DEC_PP : {
1641                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1642                         ret = -EFAULT;
1643                 break;
1644         }
1645         default : {
1646                 ret = -EFAULT;
1647                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1648                 break;
1649         }
1650         }
1651         reg_deinit(data, reg);
1652         vpu_debug_leave();
1653         return ret;
1654 }
1655
1656 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1657         unsigned long arg)
1658 {
1659         struct vpu_subdev_data *data =
1660                 container_of(filp->f_dentry->d_inode->i_cdev,
1661                         struct vpu_subdev_data, cdev);
1662         struct vpu_service_info *pservice = data->pservice;
1663         vpu_session *session = (vpu_session *)filp->private_data;
1664         vpu_debug_enter();
1665         if (NULL == session)
1666                 return -EINVAL;
1667
1668         switch (cmd) {
1669         case VPU_IOC_SET_CLIENT_TYPE : {
1670                 session->type = (enum VPU_CLIENT_TYPE)arg;
1671                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1672                 break;
1673         }
1674         case VPU_IOC_GET_HW_FUSE_STATUS : {
1675                 struct vpu_request req;
1676                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1677                 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1678                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1679                         return -EFAULT;
1680                 } else {
1681                         if (VPU_ENC != session->type) {
1682                                 if (copy_to_user((void __user *)req.req,
1683                                         &pservice->dec_config,
1684                                         sizeof(struct vpu_dec_config))) {
1685                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1686                                                 session->type);
1687                                         return -EFAULT;
1688                                 }
1689                         } else {
1690                                 if (copy_to_user((void __user *)req.req,
1691                                         &pservice->enc_config,
1692                                         sizeof(struct vpu_enc_config ))) {
1693                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1694                                                 session->type);
1695                                         return -EFAULT;
1696                                 }
1697                         }
1698                 }
1699
1700                 break;
1701         }
1702         case VPU_IOC_SET_REG : {
1703                 struct vpu_request req;
1704                 vpu_reg *reg;
1705                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1706                 if (copy_from_user(&req, (void __user *)arg,
1707                         sizeof(struct vpu_request))) {
1708                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1709                         return -EFAULT;
1710                 }
1711                 reg = reg_init(data, session,
1712                         (void __user *)req.req, req.size);
1713                 if (NULL == reg) {
1714                         return -EFAULT;
1715                 } else {
1716                         mutex_lock(&pservice->lock);
1717                         try_set_reg(data);
1718                         mutex_unlock(&pservice->lock);
1719                 }
1720
1721                 break;
1722         }
1723         case VPU_IOC_GET_REG : {
1724                 struct vpu_request req;
1725                 vpu_reg *reg;
1726                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1727                 if (copy_from_user(&req, (void __user *)arg,
1728                         sizeof(struct vpu_request))) {
1729                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1730                         return -EFAULT;
1731                 } else {
1732                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1733                         if (!list_empty(&session->done)) {
1734                                 if (ret < 0) {
1735                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1736                                 }
1737                                 ret = 0;
1738                         } else {
1739                                 if (unlikely(ret < 0)) {
1740                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1741                                 } else if (0 == ret) {
1742                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1743                                         ret = -ETIMEDOUT;
1744                                 }
1745                         }
1746                         if (ret < 0) {
1747                                 int task_running = atomic_read(&session->task_running);
1748                                 mutex_lock(&pservice->lock);
1749                                 vpu_service_dump(pservice);
1750                                 if (task_running) {
1751                                         atomic_set(&session->task_running, 0);
1752                                         atomic_sub(task_running, &pservice->total_running);
1753                                         printk("%d task is running but not return, reset hardware...", task_running);
1754                                         vpu_reset(data);
1755                                         printk("done\n");
1756                                 }
1757                                 vpu_service_session_clear(data, session);
1758                                 mutex_unlock(&pservice->lock);
1759                                 return ret;
1760                         }
1761                 }
1762                 mutex_lock(&pservice->lock);
1763                 reg = list_entry(session->done.next, vpu_reg, session_link);
1764                 return_reg(data, reg, (u32 __user *)req.req);
1765                 mutex_unlock(&pservice->lock);
1766                 break;
1767         }
1768         case VPU_IOC_PROBE_IOMMU_STATUS: {
1769                 int iommu_enable = 0;
1770
1771                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1772
1773 #if defined(CONFIG_VCODEC_MMU)
1774                 iommu_enable = data->mmu_dev ? 1 : 0;
1775 #endif
1776
1777                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1778                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1779                         return -EFAULT;
1780                 }
1781                 break;
1782         }
1783         default : {
1784                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1785                 break;
1786         }
1787         }
1788         vpu_debug_leave();
1789         return 0;
1790 }
1791
1792 #ifdef CONFIG_COMPAT
1793 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1794         unsigned long arg)
1795 {
1796         struct vpu_subdev_data *data =
1797                 container_of(filp->f_dentry->d_inode->i_cdev,
1798                         struct vpu_subdev_data, cdev);
1799         struct vpu_service_info *pservice = data->pservice;
1800         vpu_session *session = (vpu_session *)filp->private_data;
1801         vpu_debug_enter();
1802         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1803                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1804         if (NULL == session)
1805                 return -EINVAL;
1806
1807         switch (cmd) {
1808         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1809                 session->type = (enum VPU_CLIENT_TYPE)arg;
1810                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1811                 break;
1812         }
1813         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1814                 struct compat_vpu_request req;
1815                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1816                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1817                                    sizeof(struct compat_vpu_request))) {
1818                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1819                                 " copy_from_user failed\n");
1820                         return -EFAULT;
1821                 } else {
1822                         if (VPU_ENC != session->type) {
1823                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1824                                                  &pservice->dec_config,
1825                                                  sizeof(struct vpu_dec_config))) {
1826                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1827                                                 "copy_to_user failed type %d\n",
1828                                                 session->type);
1829                                         return -EFAULT;
1830                                 }
1831                         } else {
1832                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1833                                                  &pservice->enc_config,
1834                                                  sizeof(struct vpu_enc_config ))) {
1835                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1836                                                 " copy_to_user failed type %d\n",
1837                                                 session->type);
1838                                         return -EFAULT;
1839                                 }
1840                         }
1841                 }
1842
1843                 break;
1844         }
1845         case COMPAT_VPU_IOC_SET_REG : {
1846                 struct compat_vpu_request req;
1847                 vpu_reg *reg;
1848                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1849                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1850                                    sizeof(struct compat_vpu_request))) {
1851                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1852                         return -EFAULT;
1853                 }
1854                 reg = reg_init(data, session,
1855                                compat_ptr((compat_uptr_t)req.req), req.size);
1856                 if (NULL == reg) {
1857                         return -EFAULT;
1858                 } else {
1859                         mutex_lock(&pservice->lock);
1860                         try_set_reg(data);
1861                         mutex_unlock(&pservice->lock);
1862                 }
1863
1864                 break;
1865         }
1866         case COMPAT_VPU_IOC_GET_REG : {
1867                 struct compat_vpu_request req;
1868                 vpu_reg *reg;
1869                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1870                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1871                                    sizeof(struct compat_vpu_request))) {
1872                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1873                         return -EFAULT;
1874                 } else {
1875                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1876                         if (!list_empty(&session->done)) {
1877                                 if (ret < 0) {
1878                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1879                                 }
1880                                 ret = 0;
1881                         } else {
1882                                 if (unlikely(ret < 0)) {
1883                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1884                                 } else if (0 == ret) {
1885                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1886                                         ret = -ETIMEDOUT;
1887                                 }
1888                         }
1889                         if (ret < 0) {
1890                                 int task_running = atomic_read(&session->task_running);
1891                                 mutex_lock(&pservice->lock);
1892                                 vpu_service_dump(pservice);
1893                                 if (task_running) {
1894                                         atomic_set(&session->task_running, 0);
1895                                         atomic_sub(task_running, &pservice->total_running);
1896                                         printk("%d task is running but not return, reset hardware...", task_running);
1897                                         vpu_reset(data);
1898                                         printk("done\n");
1899                                 }
1900                                 vpu_service_session_clear(data, session);
1901                                 mutex_unlock(&pservice->lock);
1902                                 return ret;
1903                         }
1904                 }
1905                 mutex_lock(&pservice->lock);
1906                 reg = list_entry(session->done.next, vpu_reg, session_link);
1907                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1908                 mutex_unlock(&pservice->lock);
1909                 break;
1910         }
1911         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1912                 int iommu_enable = 0;
1913
1914                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1915 #if defined(CONFIG_VCODEC_MMU)
1916                 iommu_enable = data->mmu_dev ? 1 : 0;
1917 #endif
1918
1919                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1920                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1921                         return -EFAULT;
1922                 }
1923                 break;
1924         }
1925         default : {
1926                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1927                 break;
1928         }
1929         }
1930         vpu_debug_leave();
1931         return 0;
1932 }
1933 #endif
1934
1935 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1936 {
1937         int ret = -EINVAL, i = 0;
1938         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1939         u32 enc_id = *tmp;
1940
1941         enc_id = (enc_id >> 16) & 0xFFFF;
1942         pr_info("checking hw id %x\n", enc_id);
1943         data->hw_info = NULL;
1944         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1945                 if (enc_id == vpu_hw_set[i].hw_id) {
1946                         data->hw_info = &vpu_hw_set[i];
1947                         ret = 0;
1948                         break;
1949                 }
1950         }
1951         iounmap((void *)tmp);
1952         return ret;
1953 }
1954
1955 static int vpu_service_open(struct inode *inode, struct file *filp)
1956 {
1957         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1958         struct vpu_service_info *pservice = data->pservice;
1959         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1960
1961         vpu_debug_enter();
1962
1963         if (NULL == session) {
1964                 vpu_err("error: unable to allocate memory for vpu_session.");
1965                 return -ENOMEM;
1966         }
1967
1968         session->type   = VPU_TYPE_BUTT;
1969         session->pid    = current->pid;
1970         INIT_LIST_HEAD(&session->waiting);
1971         INIT_LIST_HEAD(&session->running);
1972         INIT_LIST_HEAD(&session->done);
1973         INIT_LIST_HEAD(&session->list_session);
1974         init_waitqueue_head(&session->wait);
1975         atomic_set(&session->task_running, 0);
1976         mutex_lock(&pservice->lock);
1977         list_add_tail(&session->list_session, &pservice->session);
1978         filp->private_data = (void *)session;
1979         mutex_unlock(&pservice->lock);
1980
1981         pr_debug("dev opened\n");
1982         vpu_debug_leave();
1983         return nonseekable_open(inode, filp);
1984 }
1985
1986 static int vpu_service_release(struct inode *inode, struct file *filp)
1987 {
1988         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1989         struct vpu_service_info *pservice = data->pservice;
1990         int task_running;
1991         vpu_session *session = (vpu_session *)filp->private_data;
1992         vpu_debug_enter();
1993         if (NULL == session)
1994                 return -EINVAL;
1995
1996         task_running = atomic_read(&session->task_running);
1997         if (task_running) {
1998                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1999                 msleep(50);
2000         }
2001         wake_up(&session->wait);
2002
2003         mutex_lock(&pservice->lock);
2004         /* remove this filp from the asynchronusly notified filp's */
2005         list_del_init(&session->list_session);
2006         vpu_service_session_clear(data, session);
2007         kfree(session);
2008         filp->private_data = NULL;
2009         mutex_unlock(&pservice->lock);
2010
2011         pr_debug("dev closed\n");
2012         vpu_debug_leave();
2013         return 0;
2014 }
2015
2016 static const struct file_operations vpu_service_fops = {
2017         .unlocked_ioctl = vpu_service_ioctl,
2018         .open           = vpu_service_open,
2019         .release        = vpu_service_release,
2020 #ifdef CONFIG_COMPAT
2021         .compat_ioctl   = compat_vpu_service_ioctl,
2022 #endif
2023 };
2024
2025 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2026 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2027 static irqreturn_t vepu_irq(int irq, void *dev_id);
2028 static irqreturn_t vepu_isr(int irq, void *dev_id);
2029 static void get_hw_info(struct vpu_subdev_data *data);
2030
2031 #ifdef CONFIG_VCODEC_MMU
2032 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2033 {
2034         struct device_node *dn = NULL;
2035         struct platform_device *pd = NULL;
2036         struct device *ret = NULL ;
2037
2038         dn = of_find_compatible_node(NULL,NULL,compt);
2039         if(!dn) {
2040                 printk("can't find device node %s \r\n",compt);
2041                 return NULL;
2042         }
2043
2044         pd = of_find_device_by_node(dn);
2045         if(!pd) {
2046                 printk("can't find platform device in device node %s\n",compt);
2047                 return  NULL;
2048         }
2049         ret = &pd->dev;
2050
2051         return ret;
2052
2053 }
2054 #ifdef CONFIG_IOMMU_API
2055 static inline void platform_set_sysmmu(struct device *iommu,
2056         struct device *dev)
2057 {
2058         dev->archdata.iommu = iommu;
2059 }
2060 #else
2061 static inline void platform_set_sysmmu(struct device *iommu,
2062         struct device *dev)
2063 {
2064 }
2065 #endif
2066
2067 int vcodec_sysmmu_fault_hdl(struct device *dev,
2068                                 enum rk_iommu_inttype itype,
2069                                 unsigned long pgtable_base,
2070                                 unsigned long fault_addr, unsigned int status)
2071 {
2072         struct platform_device *pdev;
2073         struct vpu_subdev_data *data;
2074         struct vpu_service_info *pservice;
2075
2076         vpu_debug_enter();
2077
2078         pdev = container_of(dev, struct platform_device, dev);
2079
2080         data = platform_get_drvdata(pdev);
2081         pservice = data->pservice;
2082
2083         if (pservice->reg_codec) {
2084                 struct vcodec_mem_region *mem, *n;
2085                 int i = 0;
2086                 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2087                 list_for_each_entry_safe(mem, n,
2088                                          &pservice->reg_codec->mem_region_list,
2089                                          reg_lnk) {
2090                         vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2091                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
2092                         i++;
2093                 }
2094
2095                 pr_alert("vcodec, page fault occur, reset hw\n");
2096                 pservice->reg_codec->reg[101] = 1;
2097                 vpu_reset(data);
2098         }
2099
2100         return 0;
2101 }
2102 #endif
2103
2104 #if HEVC_TEST_ENABLE
2105 static int hevc_test_case0(vpu_service_info *pservice);
2106 #endif
2107 #if defined(CONFIG_ION_ROCKCHIP)
2108 extern struct ion_client *rockchip_ion_client_create(const char * name);
2109 #endif
2110
2111 static int vcodec_subdev_probe(struct platform_device *pdev,
2112         struct vpu_service_info *pservice)
2113 {
2114         int ret = 0;
2115         struct resource *res = NULL;
2116         u32 ioaddr = 0;
2117         struct device *dev = &pdev->dev;
2118         char *name = (char*)dev_name(dev);
2119         struct device_node *np = pdev->dev.of_node;
2120         struct vpu_subdev_data *data =
2121                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2122 #if defined(CONFIG_VCODEC_MMU)
2123         u32 iommu_en = 0;
2124         char mmu_dev_dts_name[40];
2125         of_property_read_u32(np, "iommu_enabled", &iommu_en);
2126 #endif
2127         pr_info("probe device %s\n", dev_name(dev));
2128
2129         data->pservice = pservice;
2130         data->dev = dev;
2131
2132         of_property_read_string(np, "name", (const char**)&name);
2133         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2134         /*dev_set_name(dev, name);*/
2135
2136         if (pservice->reg_base == 0) {
2137                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2138                 data->regs = devm_ioremap_resource(dev, res);
2139                 if (IS_ERR(data->regs)) {
2140                         ret = PTR_ERR(data->regs);
2141                         goto err;
2142                 }
2143                 ioaddr = res->start;
2144         } else {
2145                 data->regs = pservice->reg_base;
2146                 ioaddr = pservice->ioaddr;
2147         }
2148
2149         clear_bit(MMU_ACTIVATED, &data->state);
2150         vcodec_enter_mode(data);
2151         ret = vpu_service_check_hw(data, ioaddr);
2152         if (ret < 0) {
2153                 vpu_err("error: hw info check faild\n");
2154                 goto err;
2155         }
2156
2157         data->dec_dev.iosize = data->hw_info->dec_io_size;
2158         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2159         data->reg_size = data->dec_dev.iosize;
2160
2161         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2162                 data->enc_dev.iosize = data->hw_info->enc_io_size;
2163                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2164                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2165         }
2166
2167         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2168         if (data->irq_enc > 0) {
2169                 ret = devm_request_threaded_irq(dev,
2170                         data->irq_enc, vepu_irq, vepu_isr,
2171                         IRQF_SHARED, dev_name(dev),
2172                         (void *)data);
2173                 if (ret) {
2174                         dev_err(dev,
2175                                 "error: can't request vepu irq %d\n",
2176                                 data->irq_enc);
2177                         goto err;
2178                 }
2179         }
2180         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2181         if (data->irq_dec > 0) {
2182                 ret = devm_request_threaded_irq(dev,
2183                         data->irq_dec, vdpu_irq, vdpu_isr,
2184                         IRQF_SHARED, dev_name(dev),
2185                         (void *)data);
2186                 if (ret) {
2187                         dev_err(dev,
2188                                 "error: can't request vdpu irq %d\n",
2189                                 data->irq_dec);
2190                         goto err;
2191                 }
2192         }
2193         atomic_set(&data->dec_dev.irq_count_codec, 0);
2194         atomic_set(&data->dec_dev.irq_count_pp, 0);
2195         atomic_set(&data->enc_dev.irq_count_codec, 0);
2196         atomic_set(&data->enc_dev.irq_count_pp, 0);
2197 #if defined(CONFIG_VCODEC_MMU)
2198         if (iommu_en) {
2199                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2200                         sprintf(mmu_dev_dts_name,
2201                                 HEVC_IOMMU_COMPATIBLE_NAME);
2202                 else
2203                         sprintf(mmu_dev_dts_name,
2204                                 VPU_IOMMU_COMPATIBLE_NAME);
2205
2206                 data->mmu_dev =
2207                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2208
2209                 if (data->mmu_dev)
2210                         platform_set_sysmmu(data->mmu_dev, dev);
2211
2212                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2213         }
2214 #endif
2215         vcodec_exit_mode(data);
2216         /* create device node */
2217         ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2218         if (ret) {
2219                 dev_err(dev, "alloc dev_t failed\n");
2220                 goto err;
2221         }
2222
2223         cdev_init(&data->cdev, &vpu_service_fops);
2224
2225         data->cdev.owner = THIS_MODULE;
2226         data->cdev.ops = &vpu_service_fops;
2227
2228         ret = cdev_add(&data->cdev, data->dev_t, 1);
2229
2230         if (ret) {
2231                 dev_err(dev, "add dev_t failed\n");
2232                 goto err;
2233         }
2234
2235         data->cls = class_create(THIS_MODULE, name);
2236
2237         if (IS_ERR(data->cls)) {
2238                 ret = PTR_ERR(data->cls);
2239                 dev_err(dev, "class_create err:%d\n", ret);
2240                 goto err;
2241         }
2242
2243         data->child_dev = device_create(data->cls, dev,
2244                 data->dev_t, NULL, name);
2245
2246         get_hw_info(data);
2247
2248         platform_set_drvdata(pdev, data);
2249
2250         INIT_LIST_HEAD(&data->lnk_service);
2251         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2252
2253 #ifdef CONFIG_DEBUG_FS
2254         data->debugfs_dir =
2255                 vcodec_debugfs_create_device_dir((char*)name, parent);
2256         if (data->debugfs_dir == NULL)
2257                 vpu_err("create debugfs dir %s failed\n", name);
2258
2259         data->debugfs_file_regs =
2260                 debugfs_create_file("regs", 0664,
2261                                     data->debugfs_dir, data,
2262                                     &debug_vcodec_fops);
2263 #endif
2264         return 0;
2265 err:
2266         if (data->irq_enc > 0)
2267                 free_irq(data->irq_enc, (void *)data);
2268         if (data->irq_dec > 0)
2269                 free_irq(data->irq_dec, (void *)data);
2270
2271         if (data->child_dev) {
2272                 device_destroy(data->cls, data->dev_t);
2273                 cdev_del(&data->cdev);
2274                 unregister_chrdev_region(data->dev_t, 1);
2275         }
2276
2277         if (data->cls)
2278                 class_destroy(data->cls);
2279         return -1;
2280 }
2281
2282 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2283 {
2284         device_destroy(data->cls, data->dev_t);
2285         class_destroy(data->cls);
2286         cdev_del(&data->cdev);
2287         unregister_chrdev_region(data->dev_t, 1);
2288
2289         free_irq(data->irq_enc, (void *)&data);
2290         free_irq(data->irq_dec, (void *)&data);
2291
2292 #ifdef CONFIG_DEBUG_FS
2293         debugfs_remove_recursive(data->debugfs_dir);
2294 #endif
2295 }
2296
2297 static void vcodec_read_property(struct device_node *np,
2298         struct vpu_service_info *pservice)
2299 {
2300         pservice->mode_bit = 0;
2301         pservice->mode_ctrl = 0;
2302         pservice->subcnt = 0;
2303
2304         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2305
2306         if (pservice->subcnt > 1) {
2307                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2308                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2309         }
2310 #ifdef CONFIG_MFD_SYSCON
2311         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2312 #else
2313         pservice->grf_base = (u32*)RK_GRF_VIRT;
2314 #endif
2315         if (IS_ERR(pservice->grf_base)) {
2316 #ifdef CONFIG_ARM
2317                 pservice->grf_base = RK_GRF_VIRT;
2318 #else
2319                 vpu_err("can't find vpu grf property\n");
2320                 return;
2321 #endif
2322         }
2323         of_property_read_string(np, "name", (const char**)&pservice->name);
2324 }
2325
2326 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2327 {
2328         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2329         pservice->curr_mode = -1;
2330
2331         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2332         INIT_LIST_HEAD(&pservice->waiting);
2333         INIT_LIST_HEAD(&pservice->running);
2334         mutex_init(&pservice->lock);
2335
2336         INIT_LIST_HEAD(&pservice->done);
2337         INIT_LIST_HEAD(&pservice->session);
2338         INIT_LIST_HEAD(&pservice->subdev_list);
2339
2340         pservice->reg_pproc     = NULL;
2341         atomic_set(&pservice->total_running, 0);
2342         atomic_set(&pservice->enabled,       0);
2343         atomic_set(&pservice->power_on_cnt,  0);
2344         atomic_set(&pservice->power_off_cnt, 0);
2345         atomic_set(&pservice->reset_request, 0);
2346
2347         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2348
2349         pservice->ion_client = rockchip_ion_client_create("vpu");
2350         if (IS_ERR(pservice->ion_client)) {
2351                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2352                         PTR_ERR(pservice->ion_client));
2353         } else {
2354                 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2355         }
2356 }
2357
2358 static int vcodec_probe(struct platform_device *pdev)
2359 {
2360         int i;
2361         int ret = 0;
2362         struct resource *res = NULL;
2363         struct device *dev = &pdev->dev;
2364         struct device_node *np = pdev->dev.of_node;
2365         struct vpu_service_info *pservice =
2366                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2367
2368         pr_info("probe device %s\n", dev_name(dev));
2369
2370         vcodec_read_property(np, pservice);
2371         vcodec_init_drvdata(pservice);
2372
2373         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2374                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2375         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2376                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2377         else
2378                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2379
2380         pservice->dev = dev;
2381
2382         if (0 > vpu_get_clk(pservice))
2383                 goto err;
2384
2385         vpu_service_power_on(pservice);
2386
2387         if (of_property_read_bool(np, "reg")) {
2388                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2389
2390                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2391                 if (IS_ERR(pservice->reg_base)) {
2392                         vpu_err("ioremap registers base failed\n");
2393                         ret = PTR_ERR(pservice->reg_base);
2394                         goto err;
2395                 }
2396                 pservice->ioaddr = res->start;
2397         } else {
2398                 pservice->reg_base = 0;
2399         }
2400
2401         if (of_property_read_bool(np, "subcnt")) {
2402                 for (i = 0; i<pservice->subcnt; i++) {
2403                         struct device_node *sub_np;
2404                         struct platform_device *sub_pdev;
2405                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2406                         sub_pdev = of_find_device_by_node(sub_np);
2407
2408                         vcodec_subdev_probe(sub_pdev, pservice);
2409                 }
2410         } else {
2411                 vcodec_subdev_probe(pdev, pservice);
2412         }
2413         platform_set_drvdata(pdev, pservice);
2414
2415         vpu_service_power_off(pservice);
2416
2417         pr_info("init success\n");
2418
2419         return 0;
2420
2421 err:
2422         pr_info("init failed\n");
2423         vpu_service_power_off(pservice);
2424         vpu_put_clk(pservice);
2425         wake_lock_destroy(&pservice->wake_lock);
2426
2427         if (res)
2428                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2429
2430         return ret;
2431 }
2432
2433 static int vcodec_remove(struct platform_device *pdev)
2434 {
2435         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2436         struct resource *res;
2437         struct vpu_subdev_data *data, *n;
2438
2439         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2440                 vcodec_subdev_remove(data);
2441         }
2442
2443         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2444         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2445         vpu_put_clk(pservice);
2446         wake_lock_destroy(&pservice->wake_lock);
2447
2448         return 0;
2449 }
2450
2451 #if defined(CONFIG_OF)
2452 static const struct of_device_id vcodec_service_dt_ids[] = {
2453         {.compatible = "vpu_service",},
2454         {.compatible = "rockchip,hevc_service",},
2455         {.compatible = "rockchip,vpu_combo",},
2456         {},
2457 };
2458 #endif
2459
2460 static struct platform_driver vcodec_driver = {
2461         .probe = vcodec_probe,
2462         .remove = vcodec_remove,
2463         .driver = {
2464                 .name = "vcodec",
2465                 .owner = THIS_MODULE,
2466 #if defined(CONFIG_OF)
2467                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2468 #endif
2469         },
2470 };
2471
2472 static void get_hw_info(struct vpu_subdev_data *data)
2473 {
2474         struct vpu_service_info *pservice = data->pservice;
2475         struct vpu_dec_config *dec = &pservice->dec_config;
2476         struct vpu_enc_config *enc = &pservice->enc_config;
2477         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2478                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2479                 u32 asicID      = data->dec_dev.hwregs[0];
2480
2481                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2482                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2483                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2484                         dec->jpegSupport = JPEG_PROGRESSIVE;
2485                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2486                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2487                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2488                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2489                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2490                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2491
2492                 dec->maxDecPicWidth = 4096;
2493
2494                 /* 2nd Config register */
2495                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2496                 if (dec->refBufSupport) {
2497                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2498                                 dec->refBufSupport |= 2;
2499                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2500                                 dec->refBufSupport |= 4;
2501                 }
2502                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2503                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2504                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2505                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2506
2507                 /* JPEG xtensions */
2508                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2509                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2510                 else
2511                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2512
2513                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2514                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2515                 else
2516                         dec->rvSupport = RV_NOT_SUPPORTED;
2517                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2518
2519                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2520                         dec->refBufSupport |= 8; /* enable HW support for offset */
2521
2522                 if (!cpu_is_rk3036()) {
2523                         configReg = data->enc_dev.hwregs[63];
2524                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2525                         enc->h264Enabled = (configReg >> 27) & 1;
2526                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2527                         enc->jpegEnabled = (configReg >> 25) & 1;
2528                         enc->vsEnabled = (configReg >> 24) & 1;
2529                         enc->rgbEnabled = (configReg >> 28) & 1;
2530                         enc->reg_size = data->reg_size;
2531                         enc->reserv[0] = enc->reserv[1] = 0;
2532                 }
2533                 pservice->auto_freq = true;
2534                 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2535                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2536
2537                 pservice->bug_dec_addr = cpu_is_rk30xx();
2538         } else {
2539                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2540                         dec->maxDecPicWidth = 1920;
2541                 else
2542                         dec->maxDecPicWidth = 4096;
2543                 /* disable frequency switch in hevc.*/
2544                 pservice->auto_freq = false;
2545         }
2546 }
2547
2548 static bool check_irq_err(task_info *task, u32 irq_status)
2549 {
2550         return (task->error_mask & irq_status) ? true : false;
2551 }
2552
2553 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2554 {
2555         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2556         struct vpu_service_info *pservice = data->pservice;
2557         vpu_device *dev = &data->dec_dev;
2558         u32 raw_status;
2559         u32 dec_status;
2560
2561         /*vcodec_enter_mode(data);*/
2562
2563         dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2564
2565         if (dec_status & DEC_INTERRUPT_BIT) {
2566                 time_record(&tasks[TASK_VPU_DEC], 1);
2567                 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2568                 if ((dec_status & 0x40001) == 0x40001) {
2569                         do {
2570                                 dec_status =
2571                                         readl(dev->hwregs +
2572                                                 DEC_INTERRUPT_REGISTER);
2573                         } while ((dec_status & 0x40001) == 0x40001);
2574                 }
2575
2576                 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2577                                         (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2578                                         dec_status)) {
2579                         atomic_add(1, &pservice->reset_request);
2580                 }
2581
2582                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2583                 atomic_add(1, &dev->irq_count_codec);
2584                 time_diff(&tasks[TASK_VPU_DEC]);
2585         }
2586
2587         if (data->hw_info->hw_id != HEVC_ID) {
2588                 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2589                 if (pp_status & PP_INTERRUPT_BIT) {
2590                         time_record(&tasks[TASK_VPU_PP], 1);
2591                         vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2592
2593                         if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2594                                 atomic_add(1, &pservice->reset_request);
2595
2596                         /* clear pp IRQ */
2597                         writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2598                         atomic_add(1, &dev->irq_count_pp);
2599                         time_diff(&tasks[TASK_VPU_PP]);
2600                 }
2601         }
2602
2603         pservice->irq_status = raw_status;
2604
2605         /*vcodec_exit_mode(pservice);*/
2606
2607         if (atomic_read(&dev->irq_count_pp) ||
2608             atomic_read(&dev->irq_count_codec))
2609                 return IRQ_WAKE_THREAD;
2610         else
2611                 return IRQ_NONE;
2612 }
2613
2614 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2615 {
2616         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2617         struct vpu_service_info *pservice = data->pservice;
2618         vpu_device *dev = &data->dec_dev;
2619
2620         mutex_lock(&pservice->lock);
2621         if (atomic_read(&dev->irq_count_codec)) {
2622                 atomic_sub(1, &dev->irq_count_codec);
2623                 if (NULL == pservice->reg_codec) {
2624                         vpu_err("error: dec isr with no task waiting\n");
2625                 } else {
2626                         reg_from_run_to_done(data, pservice->reg_codec);
2627                         /* avoid vpu timeout and can't recover problem */
2628                         VDPU_SOFT_RESET(data->regs);
2629                 }
2630         }
2631
2632         if (atomic_read(&dev->irq_count_pp)) {
2633                 atomic_sub(1, &dev->irq_count_pp);
2634                 if (NULL == pservice->reg_pproc) {
2635                         vpu_err("error: pp isr with no task waiting\n");
2636                 } else {
2637                         reg_from_run_to_done(data, pservice->reg_pproc);
2638                 }
2639         }
2640         try_set_reg(data);
2641         mutex_unlock(&pservice->lock);
2642         return IRQ_HANDLED;
2643 }
2644
2645 static irqreturn_t vepu_irq(int irq, void *dev_id)
2646 {
2647         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2648         struct vpu_service_info *pservice = data->pservice;
2649         vpu_device *dev = &data->enc_dev;
2650         u32 irq_status;
2651
2652         /*vcodec_enter_mode(data);*/
2653         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2654
2655         vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2656
2657         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2658                 time_record(&tasks[TASK_VPU_ENC], 1);
2659
2660                 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2661                         atomic_add(1, &pservice->reset_request);
2662
2663                 /* clear enc IRQ */
2664                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2665                 atomic_add(1, &dev->irq_count_codec);
2666                 time_diff(&tasks[TASK_VPU_ENC]);
2667         }
2668
2669         pservice->irq_status = irq_status;
2670
2671         /*vcodec_exit_mode(pservice);*/
2672
2673         if (atomic_read(&dev->irq_count_codec))
2674                 return IRQ_WAKE_THREAD;
2675         else
2676                 return IRQ_NONE;
2677 }
2678
2679 static irqreturn_t vepu_isr(int irq, void *dev_id)
2680 {
2681         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2682         struct vpu_service_info *pservice = data->pservice;
2683         vpu_device *dev = &data->enc_dev;
2684
2685         mutex_lock(&pservice->lock);
2686         if (atomic_read(&dev->irq_count_codec)) {
2687                 atomic_sub(1, &dev->irq_count_codec);
2688                 if (NULL == pservice->reg_codec) {
2689                         vpu_err("error: enc isr with no task waiting\n");
2690                 } else {
2691                         reg_from_run_to_done(data, pservice->reg_codec);
2692                 }
2693         }
2694         try_set_reg(data);
2695         mutex_unlock(&pservice->lock);
2696         return IRQ_HANDLED;
2697 }
2698
2699 static int __init vcodec_service_init(void)
2700 {
2701         int ret;
2702
2703         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2704                 vpu_err("Platform device register failed (%d).\n", ret);
2705                 return ret;
2706         }
2707
2708 #ifdef CONFIG_DEBUG_FS
2709         vcodec_debugfs_init();
2710 #endif
2711
2712         return ret;
2713 }
2714
2715 static void __exit vcodec_service_exit(void)
2716 {
2717 #ifdef CONFIG_DEBUG_FS
2718         vcodec_debugfs_exit();
2719 #endif
2720
2721         platform_driver_unregister(&vcodec_driver);
2722 }
2723
2724 module_init(vcodec_service_init);
2725 module_exit(vcodec_service_exit);
2726
2727 #ifdef CONFIG_DEBUG_FS
2728 #include <linux/seq_file.h>
2729
2730 static int vcodec_debugfs_init()
2731 {
2732         parent = debugfs_create_dir("vcodec", NULL);
2733         if (!parent)
2734                 return -1;
2735
2736         return 0;
2737 }
2738
2739 static void vcodec_debugfs_exit()
2740 {
2741         debugfs_remove(parent);
2742 }
2743
2744 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2745 {
2746         return debugfs_create_dir(dirname, parent);
2747 }
2748
2749 static int debug_vcodec_show(struct seq_file *s, void *unused)
2750 {
2751         struct vpu_subdev_data *data = s->private;
2752         struct vpu_service_info *pservice = data->pservice;
2753         unsigned int i, n;
2754         vpu_reg *reg, *reg_tmp;
2755         vpu_session *session, *session_tmp;
2756
2757         mutex_lock(&pservice->lock);
2758         vpu_service_power_on(pservice);
2759         if (data->hw_info->hw_id != HEVC_ID) {
2760                 seq_printf(s, "\nENC Registers:\n");
2761                 n = data->enc_dev.iosize >> 2;
2762                 for (i = 0; i < n; i++)
2763                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2764         }
2765         seq_printf(s, "\nDEC Registers:\n");
2766         n = data->dec_dev.iosize >> 2;
2767         for (i = 0; i < n; i++)
2768                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2769
2770         seq_printf(s, "\nvpu service status:\n");
2771         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2772                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2773                 /*seq_printf(s, "waiting reg set %d\n");*/
2774                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2775                         seq_printf(s, "waiting register set\n");
2776                 }
2777                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2778                         seq_printf(s, "running register set\n");
2779                 }
2780                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2781                         seq_printf(s, "done    register set\n");
2782                 }
2783         }
2784
2785         seq_printf(s, "\npower counter: on %d off %d\n",
2786                         atomic_read(&pservice->power_on_cnt),
2787                         atomic_read(&pservice->power_off_cnt));
2788         mutex_unlock(&pservice->lock);
2789         vpu_service_power_off(pservice);
2790
2791         return 0;
2792 }
2793
2794 static int debug_vcodec_open(struct inode *inode, struct file *file)
2795 {
2796         return single_open(file, debug_vcodec_show, inode->i_private);
2797 }
2798
2799 #endif
2800
2801 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2802 #include "hevc_test_inc/pps_00.h"
2803 #include "hevc_test_inc/register_00.h"
2804 #include "hevc_test_inc/rps_00.h"
2805 #include "hevc_test_inc/scaling_list_00.h"
2806 #include "hevc_test_inc/stream_00.h"
2807
2808 #include "hevc_test_inc/pps_01.h"
2809 #include "hevc_test_inc/register_01.h"
2810 #include "hevc_test_inc/rps_01.h"
2811 #include "hevc_test_inc/scaling_list_01.h"
2812 #include "hevc_test_inc/stream_01.h"
2813
2814 #include "hevc_test_inc/cabac.h"
2815
2816 extern struct ion_client *rockchip_ion_client_create(const char * name);
2817
2818 static struct ion_client *ion_client = NULL;
2819 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2820 {
2821         int size = (len+15) & (~15);
2822         struct ion_handle *handle;
2823         u8 *ptr;
2824
2825         if (ion_client == NULL)
2826                 ion_client = rockchip_ion_client_create("vcodec");
2827
2828         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2829
2830         ptr = ion_map_kernel(ion_client, handle);
2831
2832         ion_phys(ion_client, handle, phy, &size);
2833
2834         memcpy(ptr, tbl, len);
2835
2836         return ptr;
2837 }
2838
2839 u8* get_align_ptr_no_copy(int len, u32 *phy)
2840 {
2841         int size = (len+15) & (~15);
2842         struct ion_handle *handle;
2843         u8 *ptr;
2844
2845         if (ion_client == NULL)
2846                 ion_client = rockchip_ion_client_create("vcodec");
2847
2848         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2849
2850         ptr = ion_map_kernel(ion_client, handle);
2851
2852         ion_phys(ion_client, handle, phy, &size);
2853
2854         return ptr;
2855 }
2856
2857 #define TEST_CNT    2
2858 static int hevc_test_case0(vpu_service_info *pservice)
2859 {
2860         vpu_session session;
2861         vpu_reg *reg;
2862         unsigned long size = 272;
2863         int testidx = 0;
2864         int ret = 0;
2865         u8 *pps_tbl[TEST_CNT];
2866         u8 *register_tbl[TEST_CNT];
2867         u8 *rps_tbl[TEST_CNT];
2868         u8 *scaling_list_tbl[TEST_CNT];
2869         u8 *stream_tbl[TEST_CNT];
2870
2871         int stream_size[2];
2872         int pps_size[2];
2873         int rps_size[2];
2874         int scl_size[2];
2875         int cabac_size[2];
2876
2877         u32 phy_pps;
2878         u32 phy_rps;
2879         u32 phy_scl;
2880         u32 phy_str;
2881         u32 phy_yuv;
2882         u32 phy_ref;
2883         u32 phy_cabac;
2884
2885         volatile u8 *stream_buf;
2886         volatile u8 *pps_buf;
2887         volatile u8 *rps_buf;
2888         volatile u8 *scl_buf;
2889         volatile u8 *yuv_buf;
2890         volatile u8 *cabac_buf;
2891         volatile u8 *ref_buf;
2892
2893         u8 *pps;
2894         u8 *yuv[2];
2895         int i;
2896
2897         pps_tbl[0] = pps_00;
2898         pps_tbl[1] = pps_01;
2899
2900         register_tbl[0] = register_00;
2901         register_tbl[1] = register_01;
2902
2903         rps_tbl[0] = rps_00;
2904         rps_tbl[1] = rps_01;
2905
2906         scaling_list_tbl[0] = scaling_list_00;
2907         scaling_list_tbl[1] = scaling_list_01;
2908
2909         stream_tbl[0] = stream_00;
2910         stream_tbl[1] = stream_01;
2911
2912         stream_size[0] = sizeof(stream_00);
2913         stream_size[1] = sizeof(stream_01);
2914
2915         pps_size[0] = sizeof(pps_00);
2916         pps_size[1] = sizeof(pps_01);
2917
2918         rps_size[0] = sizeof(rps_00);
2919         rps_size[1] = sizeof(rps_01);
2920
2921         scl_size[0] = sizeof(scaling_list_00);
2922         scl_size[1] = sizeof(scaling_list_01);
2923
2924         cabac_size[0] = sizeof(Cabac_table);
2925         cabac_size[1] = sizeof(Cabac_table);
2926
2927         /* create session */
2928         session.pid = current->pid;
2929         session.type = VPU_DEC;
2930         INIT_LIST_HEAD(&session.waiting);
2931         INIT_LIST_HEAD(&session.running);
2932         INIT_LIST_HEAD(&session.done);
2933         INIT_LIST_HEAD(&session.list_session);
2934         init_waitqueue_head(&session.wait);
2935         atomic_set(&session.task_running, 0);
2936         list_add_tail(&session.list_session, &pservice->session);
2937
2938         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2939         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2940
2941         while (testidx < TEST_CNT) {
2942                 /* create registers */
2943                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2944                 if (NULL == reg) {
2945                         vpu_err("error: kmalloc fail in reg_init\n");
2946                         return -1;
2947                 }
2948
2949                 if (size > pservice->reg_size) {
2950                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2951                         size = pservice->reg_size;
2952                 }
2953                 reg->session = &session;
2954                 reg->type = session.type;
2955                 reg->size = size;
2956                 reg->freq = VPU_FREQ_DEFAULT;
2957                 reg->reg = (unsigned long *)&reg[1];
2958                 INIT_LIST_HEAD(&reg->session_link);
2959                 INIT_LIST_HEAD(&reg->status_link);
2960
2961                 /* TODO: stuff registers */
2962                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2963
2964                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2965                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2966                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2967                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2968                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2969
2970                 pps = pps_buf;
2971
2972                 /* TODO: replace reigster address */
2973                 for (i=0; i<64; i++) {
2974                         u32 scaling_offset;
2975                         u32 tmp;
2976
2977                         scaling_offset = (u32)pps[i*80+74];
2978                         scaling_offset += (u32)pps[i*80+75] << 8;
2979                         scaling_offset += (u32)pps[i*80+76] << 16;
2980                         scaling_offset += (u32)pps[i*80+77] << 24;
2981
2982                         tmp = phy_scl + scaling_offset;
2983
2984                         pps[i*80+74] = tmp & 0xff;
2985                         pps[i*80+75] = (tmp >> 8) & 0xff;
2986                         pps[i*80+76] = (tmp >> 16) & 0xff;
2987                         pps[i*80+77] = (tmp >> 24) & 0xff;
2988                 }
2989
2990                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2991                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2992
2993                 reg->reg[1] = 0x21;
2994                 reg->reg[4] = phy_str;
2995                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2996                 reg->reg[6] = phy_cabac;
2997                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2998                 reg->reg[42] = phy_pps;
2999                 reg->reg[43] = phy_rps;
3000                 for (i = 10; i <= 24; i++)
3001                         reg->reg[i] = phy_yuv;
3002
3003                 mutex_lock(pservice->lock);
3004                 list_add_tail(&reg->status_link, &pservice->waiting);
3005                 list_add_tail(&reg->session_link, &session.waiting);
3006                 mutex_unlock(pservice->lock);
3007
3008                 /* stuff hardware */
3009                 try_set_reg(data);
3010
3011                 /* wait for result */
3012                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3013                 if (!list_empty(&session.done)) {
3014                         if (ret < 0)
3015                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3016                         ret = 0;
3017                 } else {
3018                         if (unlikely(ret < 0)) {
3019                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3020                         } else if (0 == ret) {
3021                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3022                                 ret = -ETIMEDOUT;
3023                         }
3024                 }
3025                 if (ret < 0) {
3026                         int task_running = atomic_read(&session.task_running);
3027                         int n;
3028                         mutex_lock(pservice->lock);
3029                         vpu_service_dump(pservice);
3030                         if (task_running) {
3031                                 atomic_set(&session.task_running, 0);
3032                                 atomic_sub(task_running, &pservice->total_running);
3033                                 printk("%d task is running but not return, reset hardware...", task_running);
3034                                 vpu_reset(data);
3035                                 printk("done\n");
3036                         }
3037                         vpu_service_session_clear(pservice, &session);
3038                         mutex_unlock(pservice->lock);
3039
3040                         printk("\nDEC Registers:\n");
3041                         n = data->dec_dev.iosize >> 2;
3042                         for (i=0; i<n; i++)
3043                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3044
3045                         vpu_err("test index %d failed\n", testidx);
3046                         break;
3047                 } else {
3048                         vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3049
3050                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3051
3052                         for (i=0; i<68; i++) {
3053                                 if (i % 4 == 0)
3054                                         printk("%02d: ", i);
3055                                 printk("%08x ", reg->reg[i]);
3056                                 if ((i+1) % 4 == 0)
3057                                         printk("\n");
3058                         }
3059
3060                         testidx++;
3061                 }
3062
3063                 reg_deinit(data, reg);
3064         }
3065
3066         return 0;
3067 }
3068
3069 #endif
3070