arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)\r
  47 #define CONFIG_VCODEC_MMU\r
  48 #endif\r
  49 \r
  50 #ifdef CONFIG_VCODEC_MMU\r
  51 #include <linux/rockchip/iovmm.h>\r
  52 #include <linux/rockchip/sysmmu.h>\r
  53 #include <linux/dma-buf.h>\r
  54 #endif\r
  55 \r
  56 #ifdef CONFIG_DEBUG_FS\r
  57 #include <linux/debugfs.h>\r
  58 #endif\r
  59 \r
  60 #if defined(CONFIG_ARCH_RK319X)\r
  61 #include <mach/grf.h>\r
  62 #endif\r
  63 \r
  64 #include "vcodec_service.h"\r
  65 \r
  66 #define HEVC_TEST_ENABLE    0\r
  67 #define HEVC_SIM_ENABLE     0\r
  68 #define VCODEC_CLOCK_ENABLE 1\r
  69 \r
  70 typedef enum {\r
  71         VPU_DEC_ID_9190         = 0x6731,\r
  72         VPU_ID_8270             = 0x8270,\r
  73         VPU_ID_4831             = 0x4831,\r
  74     HEVC_ID         = 0x6867,\r
  75 } VPU_HW_ID;\r
  76 \r
  77 typedef enum {\r
  78         VPU_DEC_TYPE_9190       = 0,\r
  79         VPU_ENC_TYPE_8270       = 0x100,\r
  80         VPU_ENC_TYPE_4831       ,\r
  81 } VPU_HW_TYPE_E;\r
  82 \r
  83 typedef enum VPU_FREQ {\r
  84         VPU_FREQ_200M,\r
  85         VPU_FREQ_266M,\r
  86         VPU_FREQ_300M,\r
  87         VPU_FREQ_400M,\r
  88     VPU_FREQ_500M,\r
  89     VPU_FREQ_600M,\r
  90         VPU_FREQ_DEFAULT,\r
  91         VPU_FREQ_BUT,\r
  92 } VPU_FREQ;\r
  93 \r
  94 typedef struct {\r
  95         VPU_HW_ID               hw_id;\r
  96         unsigned long           hw_addr;\r
  97         unsigned long           enc_offset;\r
  98         unsigned long           enc_reg_num;\r
  99         unsigned long           enc_io_size;\r
 100         unsigned long           dec_offset;\r
 101         unsigned long           dec_reg_num;\r
 102         unsigned long           dec_io_size;\r
 103 } VPU_HW_INFO_E;\r
 104 \r
 105 #define VPU_SERVICE_SHOW_TIME                   0\r
 106 \r
 107 #if VPU_SERVICE_SHOW_TIME\r
 108 static struct timeval enc_start, enc_end;\r
 109 static struct timeval dec_start, dec_end;\r
 110 static struct timeval pp_start,  pp_end;\r
 111 #endif\r
 112 \r
 113 #define MHZ                                     (1000*1000)\r
 114 \r
 115 #define REG_NUM_9190_DEC                        (60)\r
 116 #define REG_NUM_9190_PP                         (41)\r
 117 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 118 \r
 119 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 120 \r
 121 #define REG_NUM_ENC_8270                        (96)\r
 122 #define REG_SIZE_ENC_8270                       (0x200)\r
 123 #define REG_NUM_ENC_4831                        (164)\r
 124 #define REG_SIZE_ENC_4831                       (0x400)\r
 125 \r
 126 #define REG_NUM_HEVC_DEC            (68)\r
 127 \r
 128 #define SIZE_REG(reg)                           ((reg)*4)\r
 129 \r
 130 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 131         [0] = {\r
 132                 .hw_id          = VPU_ID_8270,\r
 133                 .hw_addr        = 0,\r
 134                 .enc_offset     = 0x0,\r
 135                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 136                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 137                 .dec_offset     = REG_SIZE_ENC_8270,\r
 138                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 139                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 140         },\r
 141         [1] = {\r
 142                 .hw_id          = VPU_ID_4831,\r
 143                 .hw_addr        = 0,\r
 144                 .enc_offset     = 0x0,\r
 145                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 146                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 147                 .dec_offset     = REG_SIZE_ENC_4831,\r
 148                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 149                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 150         },\r
 151     [2] = {\r
 152         .hw_id      = HEVC_ID,\r
 153         .hw_addr    = 0,\r
 154         .dec_offset = 0x0,\r
 155         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 156         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 157     },\r
 158 };\r
 159 \r
 160 \r
 161 #define DEC_INTERRUPT_REGISTER                  1\r
 162 #define PP_INTERRUPT_REGISTER                   60\r
 163 #define ENC_INTERRUPT_REGISTER                  1\r
 164 \r
 165 #define DEC_INTERRUPT_BIT                       0x100\r
 166 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 167 #define PP_INTERRUPT_BIT                        0x100\r
 168 #define ENC_INTERRUPT_BIT                       0x1\r
 169 \r
 170 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 171 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 172 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 173 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 174 \r
 175 #define VPU_REG_EN_ENC                          14\r
 176 #define VPU_REG_ENC_GATE                        2\r
 177 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 178 \r
 179 #define VPU_REG_EN_DEC                          1\r
 180 #define VPU_REG_DEC_GATE                        2\r
 181 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 182 #define VPU_REG_EN_PP                           0\r
 183 #define VPU_REG_PP_GATE                         1\r
 184 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 185 #define VPU_REG_EN_DEC_PP                       1\r
 186 #define VPU_REG_DEC_PP_GATE                     61\r
 187 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 188 \r
 189 #if defined(CONFIG_VCODEC_MMU)\r
 190 static u8 addr_tbl_vpu_h264dec[] = {\r
 191         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 192 };\r
 193 \r
 194 static u8 addr_tbl_vpu_vp8dec[] = {\r
 195         10,12,13, 14, 18, 19, 27, 40\r
 196 };\r
 197 \r
 198 static u8 addr_tbl_vpu_vp6dec[] = {\r
 199         12, 13, 14, 18, 27, 40\r
 200 };\r
 201 \r
 202 static u8 addr_tbl_vpu_vc1dec[] = {\r
 203         12, 13, 14, 15, 16, 17, 27, 41\r
 204 };\r
 205 \r
 206 static u8 addr_tbl_vpu_jpegdec[] = {\r
 207         12, 40, 66, 67\r
 208 };\r
 209 \r
 210 static u8 addr_tbl_vpu_defaultdec[] = {\r
 211         12, 13, 14, 15, 16, 17, 40, 41\r
 212 };\r
 213 \r
 214 static u8 addr_tbl_vpu_enc[] = {\r
 215         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 216 };\r
 217 \r
 218 static u8 addr_tbl_hevc_dec[] = {\r
 219         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 42, 43\r
 220 };\r
 221 #endif\r
 222 \r
 223 enum VPU_DEC_FMT {\r
 224         VPU_DEC_FMT_H264,\r
 225         VPU_DEC_FMT_MPEG4,\r
 226         VPU_DEC_FMT_H263,\r
 227         VPU_DEC_FMT_JPEG,\r
 228         VPU_DEC_FMT_VC1,\r
 229         VPU_DEC_FMT_MPEG2,\r
 230         VPU_DEC_FMT_MPEG1,\r
 231         VPU_DEC_FMT_VP6,\r
 232         VPU_DEC_FMT_RV,\r
 233         VPU_DEC_FMT_VP7,\r
 234         VPU_DEC_FMT_VP8,\r
 235         VPU_DEC_FMT_AVS,\r
 236         VPU_DEC_FMT_SVC,\r
 237         VPU_DEC_FMT_VC2,\r
 238         VPU_DEC_FMT_MVC,\r
 239         VPU_DEC_FMT_THEORA,\r
 240         VPU_DEC_FMT_RES\r
 241 };\r
 242 \r
 243 /**\r
 244  * struct for process session which connect to vpu\r
 245  *\r
 246  * @author ChenHengming (2011-5-3)\r
 247  */\r
 248 typedef struct vpu_session {\r
 249         VPU_CLIENT_TYPE         type;\r
 250         /* a linked list of data so we can access them for debugging */\r
 251         struct list_head        list_session;\r
 252         /* a linked list of register data waiting for process */\r
 253         struct list_head        waiting;\r
 254         /* a linked list of register data in processing */\r
 255         struct list_head        running;\r
 256         /* a linked list of register data processed */\r
 257         struct list_head        done;\r
 258         wait_queue_head_t       wait;\r
 259         pid_t                   pid;\r
 260         atomic_t                task_running;\r
 261 } vpu_session;\r
 262 \r
 263 /**\r
 264  * struct for process register set\r
 265  *\r
 266  * @author ChenHengming (2011-5-4)\r
 267  */\r
 268 typedef struct vpu_reg {\r
 269         VPU_CLIENT_TYPE         type;\r
 270         VPU_FREQ                    freq;\r
 271         vpu_session             *session;\r
 272         struct list_head        session_link;           /* link to vpu service session */\r
 273         struct list_head        status_link;            /* link to register set list */\r
 274         unsigned long           size;\r
 275 #if defined(CONFIG_VCODEC_MMU)\r
 276         struct list_head        mem_region_list;\r
 277 #endif\r
 278         unsigned long           *reg;\r
 279 } vpu_reg;\r
 280 \r
 281 typedef struct vpu_device {\r
 282         atomic_t                irq_count_codec;\r
 283         atomic_t                irq_count_pp;\r
 284         unsigned long           iobaseaddr;\r
 285         unsigned int            iosize;\r
 286         volatile u32            *hwregs;\r
 287 } vpu_device;\r
 288 \r
 289 enum vcodec_device_id {\r
 290         VCODEC_DEVICE_ID_VPU,\r
 291         VCODEC_DEVICE_ID_HEVC\r
 292 };\r
 293 \r
 294 struct vcodec_mem_region {\r
 295     struct list_head srv_lnk;\r
 296     struct list_head reg_lnk;\r
 297     struct list_head session_lnk;\r
 298     unsigned long iova;              /* virtual address for iommu */\r
 299     unsigned long len;\r
 300     struct ion_handle *hdl;\r
 301 };\r
 302 \r
 303 typedef struct vpu_service_info {\r
 304         struct wake_lock        wake_lock;\r
 305         struct delayed_work     power_off_work;\r
 306         struct mutex            lock;\r
 307         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 308         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 309         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 310         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 311         atomic_t                total_running;\r
 312         bool                    enabled;\r
 313         vpu_reg                 *reg_codec;\r
 314         vpu_reg                 *reg_pproc;\r
 315         vpu_reg                 *reg_resev;\r
 316         VPUHwDecConfig_t        dec_config;\r
 317         VPUHwEncConfig_t        enc_config;\r
 318         VPU_HW_INFO_E           *hw_info;\r
 319         unsigned long           reg_size;\r
 320         bool                    auto_freq;\r
 321         bool                    bug_dec_addr;\r
 322         atomic_t                freq_status;\r
 323 \r
 324     struct clk *aclk_vcodec;\r
 325     struct clk *hclk_vcodec;\r
 326     struct clk *clk_core;\r
 327     struct clk *clk_cabac;\r
 328     struct clk *pd_video;\r
 329 \r
 330     int irq_dec;\r
 331     int irq_enc;\r
 332 \r
 333     vpu_device enc_dev;\r
 334     vpu_device dec_dev;\r
 335 \r
 336     struct device   *dev;\r
 337 \r
 338     struct cdev     cdev;\r
 339     dev_t           dev_t;\r
 340     struct class    *cls;\r
 341     struct device   *child_dev;\r
 342 \r
 343     struct dentry   *debugfs_dir;\r
 344     struct dentry   *debugfs_file_regs;\r
 345 \r
 346     u32 irq_status;\r
 347 #if defined(CONFIG_VCODEC_MMU)  \r
 348         struct ion_client * ion_client;\r
 349     struct list_head mem_region_list;\r
 350     struct device *mmu_dev;\r
 351 #endif\r
 352 \r
 353         enum vcodec_device_id dev_id;\r
 354 \r
 355     struct delayed_work simulate_work;\r
 356 } vpu_service_info;\r
 357 \r
 358 typedef struct vpu_request\r
 359 {\r
 360         unsigned long   *req;\r
 361         unsigned long   size;\r
 362 } vpu_request;\r
 363 \r
 364 /// global variable\r
 365 //static struct clk *pd_video;\r
 366 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 367 \r
 368 #ifdef CONFIG_DEBUG_FS\r
 369 static int vcodec_debugfs_init(void);\r
 370 static void vcodec_debugfs_exit(void);\r
 371 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 372 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 373 \r
 374 static const struct file_operations debug_vcodec_fops = {\r
 375     .open = debug_vcodec_open,\r
 376     .read = seq_read,\r
 377     .llseek = seq_lseek,\r
 378     .release = single_release,\r
 379 };\r
 380 #endif\r
 381 \r
 382 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 383 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 384 \r
 385 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 386 \r
 387 static int vpu_get_clk(struct vpu_service_info *pservice)\r
 388 {\r
 389 #if VCODEC_CLOCK_ENABLE\r
 390     do {\r
 391         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 392         if (IS_ERR(pservice->aclk_vcodec)) {\r
 393             dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 394             break;\r
 395         }\r
 396     \r
 397         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 398         if (IS_ERR(pservice->hclk_vcodec)) {\r
 399             dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 400             break;\r
 401         }\r
 402     \r
 403         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 404             pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 405             if (IS_ERR(pservice->clk_core)) {\r
 406                 dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 407                 break;\r
 408             }\r
 409     \r
 410             pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 411             if (IS_ERR(pservice->clk_cabac)) {\r
 412                 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 413                 break;\r
 414             }\r
 415             \r
 416             pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");\r
 417             if (IS_ERR(pservice->pd_video)) {\r
 418                 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");\r
 419                 break;\r
 420             }\r
 421         } else {\r
 422             pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");\r
 423             if (IS_ERR(pservice->pd_video)) {\r
 424                 dev_err(pservice->dev, "failed on clk_get pd_video\n");\r
 425                 break;\r
 426             }\r
 427         }\r
 428         \r
 429         return 0;\r
 430     } while (0);\r
 431     \r
 432     return -1;\r
 433 #endif\r
 434 }\r
 435 \r
 436 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 437 {\r
 438 #if VCODEC_CLOCK_ENABLE\r
 439     if (pservice->pd_video) {\r
 440         devm_clk_put(pservice->dev, pservice->pd_video);\r
 441     }\r
 442 \r
 443     if (pservice->aclk_vcodec) {\r
 444         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 445     }\r
 446 \r
 447     if (pservice->hclk_vcodec) {\r
 448         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 449     }\r
 450 \r
 451     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 452         if (pservice->clk_core) {\r
 453             devm_clk_put(pservice->dev, pservice->clk_core);\r
 454         }\r
 455         \r
 456         if (pservice->clk_cabac) {\r
 457             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 458         }\r
 459     }\r
 460 #endif\r
 461 }\r
 462 \r
 463 static void vpu_reset(struct vpu_service_info *pservice)\r
 464 {\r
 465 #if defined(CONFIG_ARCH_RK29)\r
 466         clk_disable(aclk_ddr_vepu);\r
 467         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 468         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 469         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 470         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 471         mdelay(10);\r
 472         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 473         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 474         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 475         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 476         clk_enable(aclk_ddr_vepu);\r
 477 #elif defined(CONFIG_ARCH_RK30)\r
 478         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 479         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 480         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 481         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 482         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 483         mdelay(1);\r
 484         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 485         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 486         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 487         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 488         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 489 #endif\r
 490         pservice->reg_codec = NULL;\r
 491         pservice->reg_pproc = NULL;\r
 492         pservice->reg_resev = NULL;\r
 493 }\r
 494 \r
 495 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 496 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 497 {\r
 498         vpu_reg *reg, *n;\r
 499         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 500                 reg_deinit(pservice, reg);\r
 501         }\r
 502         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 503                 reg_deinit(pservice, reg);\r
 504         }\r
 505         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 506                 reg_deinit(pservice, reg);\r
 507         }\r
 508 }\r
 509 \r
 510 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 511 {\r
 512         int running;\r
 513         vpu_reg *reg, *reg_tmp;\r
 514         vpu_session *session, *session_tmp;\r
 515 \r
 516         running = atomic_read(&pservice->total_running);\r
 517         printk("total_running %d\n", running);\r
 518 \r
 519         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 520         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 521         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 522 \r
 523         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 524                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 525                 running = atomic_read(&session->task_running);\r
 526                 printk("task_running %d\n", running);\r
 527                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 528                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 529                 }\r
 530                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 531                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 532                 }\r
 533                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 534                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 535                 }\r
 536         }\r
 537 }\r
 538 \r
 539 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 540 {\r
 541     int total_running;\r
 542     if (!pservice->enabled) {\r
 543         return;\r
 544     }\r
 545 \r
 546     pservice->enabled = false;\r
 547     total_running = atomic_read(&pservice->total_running);\r
 548     if (total_running) {\r
 549         pr_alert("alert: power off when %d task running!!\n", total_running);\r
 550         mdelay(50);\r
 551         pr_alert("alert: delay 50 ms for running task\n");\r
 552         vpu_service_dump(pservice);\r
 553     }\r
 554     \r
 555 #if defined(CONFIG_VCODEC_MMU)\r
 556     if (pservice->mmu_dev) {\r
 557         iovmm_deactivate(pservice->dev);\r
 558     }\r
 559 #endif \r
 560 \r
 561     printk("%s: power off...", dev_name(pservice->dev));\r
 562     udelay(10);\r
 563 #if VCODEC_CLOCK_ENABLE\r
 564     clk_disable_unprepare(pservice->pd_video);\r
 565     clk_disable_unprepare(pservice->hclk_vcodec);\r
 566     clk_disable_unprepare(pservice->aclk_vcodec);\r
 567     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 568         clk_disable_unprepare(pservice->clk_core);\r
 569         clk_disable_unprepare(pservice->clk_cabac);\r
 570     }\r
 571 #endif\r
 572     wake_unlock(&pservice->wake_lock);\r
 573     printk("done\n");\r
 574 }\r
 575 \r
 576 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 577 {\r
 578         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 579 }\r
 580 \r
 581 static void vpu_power_off_work(struct work_struct *work_s)\r
 582 {\r
 583     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 584     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 585 \r
 586         if (mutex_trylock(&pservice->lock)) {\r
 587                 vpu_service_power_off(pservice);\r
 588                 mutex_unlock(&pservice->lock);\r
 589         } else {\r
 590                 /* Come back later if the device is busy... */\r
 591                 vpu_queue_power_off_work(pservice);\r
 592         }\r
 593 }\r
 594 \r
 595 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 596 {\r
 597     static ktime_t last;\r
 598     ktime_t now = ktime_get();\r
 599     if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 600         cancel_delayed_work_sync(&pservice->power_off_work);\r
 601         vpu_queue_power_off_work(pservice);\r
 602         last = now;\r
 603     }\r
 604     if (pservice->enabled)\r
 605         return ;\r
 606 \r
 607     pservice->enabled = true;\r
 608     printk("%s: power on\n", dev_name(pservice->dev));\r
 609 \r
 610 #if VCODEC_CLOCK_ENABLE\r
 611     clk_prepare_enable(pservice->aclk_vcodec);\r
 612     clk_prepare_enable(pservice->hclk_vcodec);\r
 613 \r
 614     if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 615         clk_prepare_enable(pservice->clk_core);\r
 616         clk_prepare_enable(pservice->clk_cabac);\r
 617     }\r
 618     \r
 619     clk_prepare_enable(pservice->pd_video);\r
 620 #endif\r
 621 \r
 622 #if defined(CONFIG_ARCH_RK319X)\r
 623     /// select aclk_vepu as vcodec clock source. \r
 624     #define BIT_VCODEC_SEL  (1<<7)\r
 625     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 626 #endif\r
 627     \r
 628     udelay(10);\r
 629     wake_lock(&pservice->wake_lock);\r
 630     \r
 631 #if defined(CONFIG_VCODEC_MMU)    \r
 632     if (pservice->mmu_dev) {\r
 633         iovmm_activate(pservice->dev);\r
 634     }\r
 635 #endif    \r
 636 }\r
 637 \r
 638 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 639 {\r
 640         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 641         return ((type == 8) || (type == 4));\r
 642 }\r
 643 \r
 644 static inline bool reg_check_interlace(vpu_reg *reg)\r
 645 {\r
 646         unsigned long type = (reg->reg[3] & (1 << 23));\r
 647         return (type > 0);\r
 648 }\r
 649 \r
 650 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)\r
 651 {\r
 652         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);\r
 653         return type;\r
 654 }\r
 655 \r
 656 static inline int reg_probe_width(vpu_reg *reg)\r
 657 {\r
 658     int width_in_mb = reg->reg[4] >> 23;\r
 659     \r
 660     return width_in_mb * 16;\r
 661 }\r
 662 \r
 663 #if defined(CONFIG_VCODEC_MMU)\r
 664 static int vcodec_bufid_to_iova(struct vpu_service_info *pservice, u8 *tbl, int size, vpu_reg *reg)\r
 665 {\r
 666         int i;\r
 667         int usr_fd = 0;\r
 668         int offset = 0;\r
 669 \r
 670         if (tbl == NULL || size <= 0) {\r
 671                 dev_err(pservice->dev, "input arguments invalidate\n");\r
 672                 return -1;\r
 673         }\r
 674 \r
 675         vpu_service_power_on(pservice);\r
 676 \r
 677         for (i = 0; i < size; i++) {\r
 678                 usr_fd = reg->reg[tbl[i]] & 0x3FF;\r
 679 \r
 680                 if (tbl[i] == 41 && pservice->hw_info->hw_id != HEVC_ID && (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {\r
 681                         /* special for vpu dec num 41 regitster */\r
 682                         offset = reg->reg[tbl[i]] >> 10 << 4;\r
 683                 } else {\r
 684                         offset = reg->reg[tbl[i]] >> 10;\r
 685                 }\r
 686 \r
 687                 if (usr_fd != 0) {\r
 688                         struct ion_handle *hdl;\r
 689                         int ret;\r
 690                         struct vcodec_mem_region *mem_region;\r
 691 \r
 692                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 693                         if (IS_ERR(hdl)) {\r
 694                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);\r
 695                                 return PTR_ERR(hdl);\r
 696                         }\r
 697 \r
 698                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);\r
 699 \r
 700                         if (mem_region == NULL) {\r
 701                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");\r
 702                                 ion_free(pservice->ion_client, hdl);\r
 703                                 return -1;\r
 704                         }\r
 705 \r
 706                         mem_region->hdl = hdl;\r
 707 \r
 708                         ret = ion_map_iommu(pservice->dev, pservice->ion_client, mem_region->hdl, &mem_region->iova, &mem_region->len);\r
 709                         if (ret < 0) {\r
 710                                 dev_err(pservice->dev, "ion map iommu failed\n");\r
 711                                 kfree(mem_region);\r
 712                                 ion_free(pservice->ion_client, hdl);\r
 713                                 return ret;\r
 714                         }\r
 715                         reg->reg[tbl[i]] = mem_region->iova + offset;\r
 716                         INIT_LIST_HEAD(&mem_region->reg_lnk);\r
 717                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);\r
 718                 }\r
 719         }\r
 720         return 0;\r
 721 }\r
 722 \r
 723 static int vcodec_reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 724 {\r
 725         VPU_HW_ID hw_id;\r
 726         u8 *tbl;\r
 727         int size = 0;\r
 728 \r
 729         hw_id = pservice->hw_info->hw_id;\r
 730 \r
 731         if (hw_id == HEVC_ID) {\r
 732                 tbl = addr_tbl_hevc_dec;\r
 733                 size = sizeof(addr_tbl_hevc_dec);\r
 734         } else {\r
 735                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 736                         switch (reg_check_fmt(reg)) {\r
 737                         case VPU_DEC_FMT_H264:\r
 738                                 {\r
 739                                         tbl = addr_tbl_vpu_h264dec;\r
 740                                         size = sizeof(addr_tbl_vpu_h264dec);\r
 741                                         break;\r
 742                                 }\r
 743                         case VPU_DEC_FMT_VP8:\r
 744                         case VPU_DEC_FMT_VP7:\r
 745                                 {\r
 746                                         tbl = addr_tbl_vpu_vp8dec;\r
 747                                         size = sizeof(addr_tbl_vpu_vp8dec);\r
 748                                         break;\r
 749                                 }\r
 750 \r
 751                         case VPU_DEC_FMT_VP6:\r
 752                                 {\r
 753                                         tbl = addr_tbl_vpu_vp6dec;\r
 754                                         size = sizeof(addr_tbl_vpu_vp6dec);\r
 755                                         break;\r
 756                                 }\r
 757                         case VPU_DEC_FMT_VC1:\r
 758                                 {\r
 759                                         tbl = addr_tbl_vpu_vc1dec;\r
 760                                         size = sizeof(addr_tbl_vpu_vc1dec);\r
 761                                         break;\r
 762                                 }\r
 763 \r
 764                         case VPU_DEC_FMT_JPEG:\r
 765                                 {\r
 766                                         tbl = addr_tbl_vpu_jpegdec;\r
 767                                         size = sizeof(addr_tbl_vpu_jpegdec);\r
 768                                         break;\r
 769                                 }\r
 770                         default:\r
 771                                 tbl = addr_tbl_vpu_defaultdec;\r
 772                                 size = sizeof(addr_tbl_vpu_defaultdec);\r
 773                                 break;\r
 774                         }\r
 775                 } else if (reg->type == VPU_ENC) {\r
 776                         tbl = addr_tbl_vpu_enc;\r
 777                         size = sizeof(addr_tbl_vpu_enc);\r
 778                 }\r
 779         }\r
 780 \r
 781         if (size != 0) {\r
 782                 return vcodec_bufid_to_iova(pservice, tbl, size, reg);\r
 783         } else {\r
 784                 return -1;\r
 785         }\r
 786 }\r
 787 #endif\r
 788 \r
 789 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 790 {\r
 791         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 792         if (NULL == reg) {\r
 793                 pr_err("error: kmalloc fail in reg_init\n");\r
 794                 return NULL;\r
 795         }\r
 796 \r
 797         if (size > pservice->reg_size) {\r
 798                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 799                 size = pservice->reg_size;\r
 800         }\r
 801         reg->session = session;\r
 802         reg->type = session->type;\r
 803         reg->size = size;\r
 804         reg->freq = VPU_FREQ_DEFAULT;\r
 805         reg->reg = (unsigned long *)&reg[1];\r
 806         INIT_LIST_HEAD(&reg->session_link);\r
 807         INIT_LIST_HEAD(&reg->status_link);\r
 808 \r
 809 #if defined(CONFIG_VCODEC_MMU)  \r
 810         if (pservice->mmu_dev) {\r
 811             INIT_LIST_HEAD(&reg->mem_region_list);\r
 812         }\r
 813 #endif\r
 814 \r
 815         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 816                 pr_err("error: copy_from_user failed in reg_init\n");\r
 817                 kfree(reg);\r
 818                 return NULL;\r
 819         }\r
 820 \r
 821 #if defined(CONFIG_VCODEC_MMU)\r
 822         if (pservice->mmu_dev && 0 > vcodec_reg_address_translate(pservice, reg)) {\r
 823                 pr_err("error: translate reg address failed\n");\r
 824                 kfree(reg);\r
 825                 return NULL;\r
 826         }\r
 827 #endif\r
 828 \r
 829         mutex_lock(&pservice->lock);\r
 830         list_add_tail(&reg->status_link, &pservice->waiting);\r
 831         list_add_tail(&reg->session_link, &session->waiting);\r
 832         mutex_unlock(&pservice->lock);\r
 833 \r
 834         if (pservice->auto_freq) {\r
 835                 if (!soc_is_rk2928g()) {\r
 836                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 837                                 if (reg_check_rmvb_wmv(reg)) {\r
 838                                         reg->freq = VPU_FREQ_200M;\r
 839                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {\r
 840                                         if (reg_probe_width(reg) > 3200) {\r
 841                                                 // raise frequency for 4k avc.\r
 842                                                 reg->freq = VPU_FREQ_500M;\r
 843                                         }\r
 844                                 } else {\r
 845                                         if (reg_check_interlace(reg)) {\r
 846                                                 reg->freq = VPU_FREQ_400M;\r
 847                                         }\r
 848                                 }\r
 849                         }\r
 850                         if (reg->type == VPU_PP) {\r
 851                                 reg->freq = VPU_FREQ_400M;\r
 852                         }\r
 853                 }\r
 854         }\r
 855 \r
 856         return reg;\r
 857 }\r
 858 \r
 859 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 860 {\r
 861 #if defined(CONFIG_VCODEC_MMU)\r
 862         struct vcodec_mem_region *mem_region = NULL, *n;\r
 863 #endif\r
 864 \r
 865         list_del_init(&reg->session_link);\r
 866         list_del_init(&reg->status_link);\r
 867         if (reg == pservice->reg_codec)\r
 868                 pservice->reg_codec = NULL;\r
 869         if (reg == pservice->reg_pproc)\r
 870                 pservice->reg_pproc = NULL;\r
 871 \r
 872 #if defined(CONFIG_VCODEC_MMU)\r
 873         // release memory region attach to this registers table.\r
 874         list_for_each_entry_safe(mem_region, n, &reg->mem_region_list, reg_lnk) {\r
 875                 ion_unmap_iommu(pservice->dev, pservice->ion_client, mem_region->hdl);\r
 876                 ion_free(pservice->ion_client, mem_region->hdl);\r
 877                 list_del_init(&mem_region->reg_lnk);\r
 878                 kfree(mem_region);\r
 879         }\r
 880 #endif\r
 881 \r
 882         kfree(reg);\r
 883 }\r
 884 \r
 885 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 886 {\r
 887         list_del_init(&reg->status_link);\r
 888         list_add_tail(&reg->status_link, &pservice->running);\r
 889 \r
 890         list_del_init(&reg->session_link);\r
 891         list_add_tail(&reg->session_link, &reg->session->running);\r
 892 }\r
 893 \r
 894 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 895 {\r
 896         int i;\r
 897         u32 *dst = (u32 *)&reg->reg[0];\r
 898         for (i = 0; i < count; i++)\r
 899                 *dst++ = *src++;\r
 900 }\r
 901 \r
 902 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 903 {\r
 904         int irq_reg = -1;\r
 905         list_del_init(&reg->status_link);\r
 906         list_add_tail(&reg->status_link, &pservice->done);\r
 907 \r
 908         list_del_init(&reg->session_link);\r
 909         list_add_tail(&reg->session_link, &reg->session->done);\r
 910 \r
 911         switch (reg->type) {\r
 912         case VPU_ENC : {\r
 913                 pservice->reg_codec = NULL;\r
 914                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 915                 irq_reg = ENC_INTERRUPT_REGISTER;\r
 916                 break;\r
 917         }\r
 918         case VPU_DEC : {\r
 919                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
 920                 pservice->reg_codec = NULL;\r
 921                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, reg_len);\r
 922                 irq_reg = DEC_INTERRUPT_REGISTER;\r
 923                 break;\r
 924         }\r
 925         case VPU_PP : {\r
 926                 pservice->reg_pproc = NULL;\r
 927                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 928                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 929                 break;\r
 930         }\r
 931         case VPU_DEC_PP : {\r
 932                 pservice->reg_codec = NULL;\r
 933                 pservice->reg_pproc = NULL;\r
 934                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 935                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 936                 break;\r
 937         }\r
 938         default : {\r
 939                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 940                 break;\r
 941         }\r
 942         }\r
 943 \r
 944         if (irq_reg != -1) {\r
 945                 reg->reg[irq_reg] = pservice->irq_status;\r
 946         }\r
 947 \r
 948         atomic_sub(1, &reg->session->task_running);\r
 949         atomic_sub(1, &pservice->total_running);\r
 950         wake_up(&reg->session->wait);\r
 951 }\r
 952 \r
 953 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 954 {\r
 955         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 956         if (curr == reg->freq) {\r
 957                 return ;\r
 958         }\r
 959         atomic_set(&pservice->freq_status, reg->freq);\r
 960         switch (reg->freq) {\r
 961         case VPU_FREQ_200M : {\r
 962                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 963                 //printk("default: 200M\n");\r
 964         } break;\r
 965         case VPU_FREQ_266M : {\r
 966                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 967                 //printk("default: 266M\n");\r
 968         } break;\r
 969         case VPU_FREQ_300M : {\r
 970                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 971                 //printk("default: 300M\n");\r
 972         } break;\r
 973         case VPU_FREQ_400M : {\r
 974                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 975                 //printk("default: 400M\n");\r
 976         } break;\r
 977         case VPU_FREQ_500M : {\r
 978                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);\r
 979         } break;\r
 980         case VPU_FREQ_600M : {\r
 981                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);\r
 982         } break;\r
 983         default : {\r
 984                 if (soc_is_rk2928g()) {\r
 985                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 986                 } else {\r
 987                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 988                 }\r
 989                 //printk("default: 300M\n");\r
 990         } break;\r
 991         }\r
 992 }\r
 993 \r
 994 #if HEVC_SIM_ENABLE\r
 995 static void simulate_start(struct vpu_service_info *pservice);\r
 996 #endif\r
 997 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 998 {\r
 999         int i;\r
1000         u32 *src = (u32 *)&reg->reg[0];\r
1001         atomic_add(1, &pservice->total_running);\r
1002         atomic_add(1, &reg->session->task_running);\r
1003         if (pservice->auto_freq) {\r
1004                 vpu_service_set_freq(pservice, reg);\r
1005         }\r
1006         switch (reg->type) {\r
1007         case VPU_ENC : {\r
1008                 int enc_count = pservice->hw_info->enc_reg_num;\r
1009                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
1010 \r
1011                 pservice->reg_codec = reg;\r
1012 \r
1013                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
1014 \r
1015                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
1016                         dst[i] = src[i];\r
1017 \r
1018                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
1019                         dst[i] = src[i];\r
1020 \r
1021                 dsb();\r
1022 \r
1023                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
1024                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
1025 \r
1026 #if VPU_SERVICE_SHOW_TIME\r
1027                 do_gettimeofday(&enc_start);\r
1028 #endif\r
1029 \r
1030         } break;\r
1031         case VPU_DEC : {\r
1032                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1033 \r
1034                 pservice->reg_codec = reg;\r
1035 \r
1036                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1037                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
1038                                 dst[i] = src[i];\r
1039                 } else {\r
1040                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
1041                                 dst[i] = src[i];\r
1042                         }\r
1043                 }\r
1044 \r
1045                 dsb();\r
1046 \r
1047                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
1048                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
1049                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
1050                 } else {\r
1051                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
1052                 }\r
1053 \r
1054                 dsb();\r
1055                 dmb();\r
1056 \r
1057 #if VPU_SERVICE_SHOW_TIME\r
1058                 do_gettimeofday(&dec_start);\r
1059 #endif\r
1060 \r
1061         } break;\r
1062         case VPU_PP : {\r
1063                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
1064                 pservice->reg_pproc = reg;\r
1065 \r
1066                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1067 \r
1068                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
1069                         dst[i] = src[i];\r
1070 \r
1071                 dsb();\r
1072 \r
1073                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
1074 \r
1075 #if VPU_SERVICE_SHOW_TIME\r
1076                 do_gettimeofday(&pp_start);\r
1077 #endif\r
1078 \r
1079         } break;\r
1080         case VPU_DEC_PP : {\r
1081                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
1082                 pservice->reg_codec = reg;\r
1083                 pservice->reg_pproc = reg;\r
1084 \r
1085                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
1086                         dst[i] = src[i];\r
1087 \r
1088                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
1089                 dsb();\r
1090 \r
1091                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
1092                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
1093                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
1094 \r
1095 #if VPU_SERVICE_SHOW_TIME\r
1096                 do_gettimeofday(&dec_start);\r
1097 #endif\r
1098 \r
1099         } break;\r
1100         default : {\r
1101                 pr_err("error: unsupport session type %d", reg->type);\r
1102                 atomic_sub(1, &pservice->total_running);\r
1103                 atomic_sub(1, &reg->session->task_running);\r
1104                 break;\r
1105         }\r
1106         }\r
1107 \r
1108 #if HEVC_SIM_ENABLE\r
1109         if (pservice->hw_info->hw_id == HEVC_ID) {\r
1110                 simulate_start(pservice);\r
1111         }\r
1112 #endif\r
1113 }\r
1114 \r
1115 static void try_set_reg(struct vpu_service_info *pservice)\r
1116 {\r
1117         // first get reg from reg list\r
1118         if (!list_empty(&pservice->waiting)) {\r
1119                 int can_set = 0;\r
1120                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
1121 \r
1122                 vpu_service_power_on(pservice);\r
1123 \r
1124                 switch (reg->type) {\r
1125                 case VPU_ENC : {\r
1126                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
1127                                 can_set = 1;\r
1128                 } break;\r
1129                 case VPU_DEC : {\r
1130                         if (NULL == pservice->reg_codec)\r
1131                                 can_set = 1;\r
1132                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
1133                                 can_set = 0;\r
1134                         }\r
1135                 } break;\r
1136                 case VPU_PP : {\r
1137                         if (NULL == pservice->reg_codec) {\r
1138                                 if (NULL == pservice->reg_pproc)\r
1139                                         can_set = 1;\r
1140                         } else {\r
1141                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
1142                                         can_set = 1;\r
1143                                 // can not charge frequency when vpu is working\r
1144                                 if (pservice->auto_freq) {\r
1145                                         can_set = 0;\r
1146                                 }\r
1147                         }\r
1148                 } break;\r
1149                 case VPU_DEC_PP : {\r
1150                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
1151                                 can_set = 1;\r
1152                         } break;\r
1153                 default : {\r
1154                         printk("undefined reg type %d\n", reg->type);\r
1155                 } break;\r
1156                 }\r
1157                 if (can_set) {\r
1158                         reg_from_wait_to_run(pservice, reg);\r
1159                         reg_copy_to_hw(pservice, reg);\r
1160                 }\r
1161         }\r
1162 }\r
1163 \r
1164 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
1165 {\r
1166         int ret = 0;\r
1167         switch (reg->type) {\r
1168         case VPU_ENC : {\r
1169                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
1170                         ret = -EFAULT;\r
1171                 break;\r
1172         }\r
1173         case VPU_DEC : {\r
1174                 int reg_len = pservice->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;\r
1175                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))\r
1176                         ret = -EFAULT;\r
1177                 break;\r
1178         }\r
1179         case VPU_PP : {\r
1180                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
1181                         ret = -EFAULT;\r
1182                 break;\r
1183         }\r
1184         case VPU_DEC_PP : {\r
1185                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
1186                         ret = -EFAULT;\r
1187                 break;\r
1188         }\r
1189         default : {\r
1190                 ret = -EFAULT;\r
1191                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
1192                 break;\r
1193         }\r
1194         }\r
1195         reg_deinit(pservice, reg);\r
1196         return ret;\r
1197 }\r
1198 \r
1199 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
1200 {\r
1201     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
1202         vpu_session *session = (vpu_session *)filp->private_data;\r
1203         if (NULL == session) {\r
1204                 return -EINVAL;\r
1205         }\r
1206 \r
1207         switch (cmd) {\r
1208         case VPU_IOC_SET_CLIENT_TYPE : {\r
1209                 session->type = (VPU_CLIENT_TYPE)arg;\r
1210                 break;\r
1211         }\r
1212         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
1213                 vpu_request req;\r
1214                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1215                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1216                         return -EFAULT;\r
1217                 } else {\r
1218                         if (VPU_ENC != session->type) {\r
1219                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1220                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1221                                         return -EFAULT;\r
1222                                 }\r
1223                         } else {\r
1224                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1225                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1226                                         return -EFAULT;\r
1227                                 }\r
1228                         }\r
1229                 }\r
1230 \r
1231                 break;\r
1232         }\r
1233         case VPU_IOC_SET_REG : {\r
1234                 vpu_request req;\r
1235                 vpu_reg *reg;\r
1236                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1237                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1238                         return -EFAULT;\r
1239                 }\r
1240                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1241                 if (NULL == reg) {\r
1242                         return -EFAULT;\r
1243                 } else {\r
1244                         mutex_lock(&pservice->lock);\r
1245                         try_set_reg(pservice);\r
1246                         mutex_unlock(&pservice->lock);\r
1247                 }\r
1248 \r
1249                 break;\r
1250         }\r
1251         case VPU_IOC_GET_REG : {\r
1252                 vpu_request req;\r
1253                 vpu_reg *reg;\r
1254                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1255                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1256                         return -EFAULT;\r
1257                 } else {\r
1258                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1259                         if (!list_empty(&session->done)) {\r
1260                                 if (ret < 0) {\r
1261                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1262                                 }\r
1263                                 ret = 0;\r
1264                         } else {\r
1265                                 if (unlikely(ret < 0)) {\r
1266                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1267                                 } else if (0 == ret) {\r
1268                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1269                                         ret = -ETIMEDOUT;\r
1270                                 }\r
1271                         }\r
1272                         if (ret < 0) {\r
1273                                 int task_running = atomic_read(&session->task_running);\r
1274                                 mutex_lock(&pservice->lock);\r
1275                                 vpu_service_dump(pservice);\r
1276                                 if (task_running) {\r
1277                                         atomic_set(&session->task_running, 0);\r
1278                                         atomic_sub(task_running, &pservice->total_running);\r
1279                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1280                                         vpu_reset(pservice);\r
1281                                         printk("done\n");\r
1282                                 }\r
1283                                 vpu_service_session_clear(pservice, session);\r
1284                                 mutex_unlock(&pservice->lock);\r
1285                                 return ret;\r
1286                         }\r
1287                 }\r
1288                 mutex_lock(&pservice->lock);\r
1289                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1290                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1291                 mutex_unlock(&pservice->lock);\r
1292                 break;\r
1293         }\r
1294         case VPU_IOC_PROBE_IOMMU_STATUS: {\r
1295                 int iommu_enable = 0;\r
1296 \r
1297 #if defined(CONFIG_VCODEC_MMU)                \r
1298                 iommu_enable = pservice->mmu_dev ? 1 : 0; \r
1299 #endif                \r
1300 \r
1301                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {\r
1302                         pr_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");\r
1303                         return -EFAULT;\r
1304                 }\r
1305                 break;\r
1306         }\r
1307         default : {\r
1308                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1309                 break;\r
1310         }\r
1311         }\r
1312 \r
1313         return 0;\r
1314 }\r
1315 \r
1316 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1317 {\r
1318         int ret = -EINVAL, i = 0;\r
1319         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1320         u32 enc_id = *tmp;\r
1321 \r
1322 #if HEVC_SIM_ENABLE\r
1323         /// temporary, hevc driver test.\r
1324         if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1325                 p->hw_info = &vpu_hw_set[2];\r
1326                 return 0;\r
1327         }\r
1328 #endif\r
1329 \r
1330         enc_id = (enc_id >> 16) & 0xFFFF;\r
1331         pr_info("checking hw id %x\n", enc_id);\r
1332         p->hw_info = NULL;\r
1333         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1334                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1335                         p->hw_info = &vpu_hw_set[i];\r
1336                         ret = 0;\r
1337                         break;\r
1338                 }\r
1339         }\r
1340         iounmap((void *)tmp);\r
1341         return ret;\r
1342 }\r
1343 \r
1344 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1345 {\r
1346         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1347         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1348         if (NULL == session) {\r
1349                 pr_err("error: unable to allocate memory for vpu_session.");\r
1350                 return -ENOMEM;\r
1351         }\r
1352 \r
1353         session->type   = VPU_TYPE_BUTT;\r
1354         session->pid    = current->pid;\r
1355         INIT_LIST_HEAD(&session->waiting);\r
1356         INIT_LIST_HEAD(&session->running);\r
1357         INIT_LIST_HEAD(&session->done);\r
1358         INIT_LIST_HEAD(&session->list_session);\r
1359         init_waitqueue_head(&session->wait);\r
1360         atomic_set(&session->task_running, 0);\r
1361         mutex_lock(&pservice->lock);\r
1362         list_add_tail(&session->list_session, &pservice->session);\r
1363         filp->private_data = (void *)session;\r
1364         mutex_unlock(&pservice->lock);\r
1365 \r
1366         pr_debug("dev opened\n");\r
1367         return nonseekable_open(inode, filp);\r
1368 }\r
1369 \r
1370 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1371 {\r
1372         struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1373         int task_running;\r
1374         vpu_session *session = (vpu_session *)filp->private_data;\r
1375         if (NULL == session)\r
1376                 return -EINVAL;\r
1377 \r
1378         task_running = atomic_read(&session->task_running);\r
1379         if (task_running) {\r
1380                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1381                 msleep(50);\r
1382         }\r
1383         wake_up(&session->wait);\r
1384 \r
1385         mutex_lock(&pservice->lock);\r
1386         /* remove this filp from the asynchronusly notified filp's */\r
1387         list_del_init(&session->list_session);\r
1388         vpu_service_session_clear(pservice, session);\r
1389         kfree(session);\r
1390         filp->private_data = NULL;\r
1391         mutex_unlock(&pservice->lock);\r
1392 \r
1393         pr_debug("dev closed\n");\r
1394         return 0;\r
1395 }\r
1396 \r
1397 static const struct file_operations vpu_service_fops = {\r
1398         .unlocked_ioctl = vpu_service_ioctl,\r
1399         .open           = vpu_service_open,\r
1400         .release        = vpu_service_release,\r
1401         //.fasync       = vpu_service_fasync,\r
1402 };\r
1403 \r
1404 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1405 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1406 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1407 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1408 static void get_hw_info(struct vpu_service_info *pservice);\r
1409 \r
1410 #if HEVC_SIM_ENABLE\r
1411 static void simulate_work(struct work_struct *work_s)\r
1412 {\r
1413     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1414     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1415     vpu_device *dev = &pservice->dec_dev;\r
1416 \r
1417     if (!list_empty(&pservice->running)) {\r
1418         atomic_add(1, &dev->irq_count_codec);\r
1419         vdpu_isr(0, (void*)pservice);\r
1420     } else {\r
1421         //simulate_start(pservice);\r
1422         pr_err("empty running queue\n");\r
1423     }\r
1424 }\r
1425 \r
1426 static void simulate_init(struct vpu_service_info *pservice)\r
1427 {\r
1428     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1429 }\r
1430 \r
1431 static void simulate_start(struct vpu_service_info *pservice)\r
1432 {\r
1433     cancel_delayed_work_sync(&pservice->power_off_work);\r
1434     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1435 }\r
1436 #endif\r
1437 \r
1438 #if HEVC_TEST_ENABLE\r
1439 static int hevc_test_case0(vpu_service_info *pservice);\r
1440 #endif\r
1441 #if defined(CONFIG_ION_ROCKCHIP)\r
1442 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1443 #endif\r
1444 static int vcodec_probe(struct platform_device *pdev)\r
1445 {\r
1446     int ret = 0;\r
1447     struct resource *res = NULL;\r
1448     struct device *dev = &pdev->dev;\r
1449     void __iomem *regs = NULL;\r
1450     struct device_node *np = pdev->dev.of_node;\r
1451     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1452     char *prop = (char*)dev_name(dev);\r
1453 #if defined(CONFIG_VCODEC_MMU)\r
1454     char mmu_dev_dts_name[40];\r
1455 #endif\r
1456 \r
1457     pr_info("probe device %s\n", dev_name(dev));\r
1458 \r
1459     of_property_read_string(np, "name", (const char**)&prop);\r
1460     dev_set_name(dev, prop);\r
1461 \r
1462     if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1463         pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1464     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1465         pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1466     } else {\r
1467         dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1468         return -1;\r
1469     }\r
1470 \r
1471     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1472     INIT_LIST_HEAD(&pservice->waiting);\r
1473     INIT_LIST_HEAD(&pservice->running);\r
1474     INIT_LIST_HEAD(&pservice->done);\r
1475     INIT_LIST_HEAD(&pservice->session);\r
1476     mutex_init(&pservice->lock);\r
1477     pservice->reg_codec = NULL;\r
1478     pservice->reg_pproc = NULL;\r
1479     atomic_set(&pservice->total_running, 0);\r
1480     pservice->enabled = false;\r
1481 #if defined(CONFIG_VCODEC_MMU)    \r
1482     pservice->mmu_dev = NULL;\r
1483 #endif    \r
1484     pservice->dev = dev;\r
1485 \r
1486     if (0 > vpu_get_clk(pservice)) {\r
1487         goto err;\r
1488     }\r
1489 \r
1490     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1491 \r
1492     vpu_service_power_on(pservice);\r
1493     \r
1494     mdelay(1);\r
1495 \r
1496     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1497 \r
1498     regs = devm_ioremap_resource(pservice->dev, res);\r
1499     if (IS_ERR(regs)) {\r
1500         ret = PTR_ERR(regs);\r
1501         goto err;\r
1502     }\r
1503 \r
1504     ret = vpu_service_check_hw(pservice, res->start);\r
1505     if (ret < 0) {\r
1506         pr_err("error: hw info check faild\n");\r
1507         goto err;\r
1508     }\r
1509 \r
1510     /// define regs address.\r
1511     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1512     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1513 \r
1514     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1515 \r
1516     pservice->reg_size   = pservice->dec_dev.iosize;\r
1517 \r
1518     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1519         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1520         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1521 \r
1522         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1523 \r
1524         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1525 \r
1526         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1527         if (pservice->irq_enc < 0) {\r
1528             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1529             ret = -ENXIO;\r
1530             goto err;\r
1531         }\r
1532 \r
1533         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1534         if (ret) {\r
1535             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1536             goto err;\r
1537         }\r
1538     }\r
1539 \r
1540     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1541     if (pservice->irq_dec < 0) {\r
1542         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1543         ret = -ENXIO;\r
1544         goto err;\r
1545     }\r
1546 \r
1547     /* get the IRQ line */\r
1548     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1549     if (ret) {\r
1550         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1551         goto err;\r
1552     }\r
1553 \r
1554     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1555     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1556     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1557     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1558 \r
1559     /// create device\r
1560     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1561     if (ret) {\r
1562         dev_err(dev, "alloc dev_t failed\n");\r
1563         goto err;\r
1564     }\r
1565 \r
1566     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1567 \r
1568     pservice->cdev.owner = THIS_MODULE;\r
1569     pservice->cdev.ops = &vpu_service_fops;\r
1570 \r
1571     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1572 \r
1573     if (ret) {\r
1574         dev_err(dev, "add dev_t failed\n");\r
1575         goto err;\r
1576     }\r
1577 \r
1578     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1579 \r
1580     if (IS_ERR(pservice->cls)) {\r
1581         ret = PTR_ERR(pservice->cls);\r
1582         dev_err(dev, "class_create err:%d\n", ret);\r
1583         goto err;\r
1584     }\r
1585 \r
1586     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1587 \r
1588     platform_set_drvdata(pdev, pservice);\r
1589 \r
1590     get_hw_info(pservice);\r
1591 \r
1592 \r
1593 #ifdef CONFIG_DEBUG_FS\r
1594     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1595     \r
1596     if (pservice->debugfs_dir == NULL) {\r
1597         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1598     }\r
1599 \r
1600     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1601                     pservice->debugfs_dir, pservice,\r
1602                     &debug_vcodec_fops);\r
1603 #endif\r
1604 \r
1605 #if defined(CONFIG_VCODEC_MMU)\r
1606     pservice->ion_client = rockchip_ion_client_create("vpu");\r
1607     if (IS_ERR(pservice->ion_client)) {\r
1608         dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1609         return PTR_ERR(pservice->ion_client);\r
1610     } else {\r
1611         dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1612     }\r
1613     \r
1614     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1615         sprintf(mmu_dev_dts_name, "iommu,hevc_mmu");\r
1616     } else {\r
1617         sprintf(mmu_dev_dts_name, "iommu,vpu_mmu");\r
1618     }\r
1619     \r
1620     pservice->mmu_dev = rockchip_get_sysmmu_device_by_compatible(mmu_dev_dts_name);\r
1621     \r
1622     if (pservice->mmu_dev) {\r
1623         platform_set_sysmmu(pservice->mmu_dev, pservice->dev);\r
1624         iovmm_activate(pservice->dev);\r
1625     }\r
1626 #endif\r
1627 \r
1628     vpu_service_power_off(pservice);\r
1629     pr_info("init success\n");\r
1630 \r
1631 #if HEVC_SIM_ENABLE\r
1632     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1633         simulate_init(pservice);\r
1634     }\r
1635 #endif\r
1636 \r
1637 #if HEVC_TEST_ENABLE\r
1638     hevc_test_case0(pservice);\r
1639 #endif\r
1640 \r
1641     return 0;\r
1642 \r
1643 err:\r
1644     pr_info("init failed\n");\r
1645     vpu_service_power_off(pservice);\r
1646     vpu_put_clk(pservice);\r
1647     wake_lock_destroy(&pservice->wake_lock);\r
1648 \r
1649     if (res) {\r
1650         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1651     }\r
1652 \r
1653     if (pservice->irq_enc > 0) {\r
1654         free_irq(pservice->irq_enc, (void *)pservice);\r
1655     }\r
1656 \r
1657     if (pservice->irq_dec > 0) {\r
1658         free_irq(pservice->irq_dec, (void *)pservice);\r
1659     }\r
1660 \r
1661     if (pservice->child_dev) {\r
1662         device_destroy(pservice->cls, pservice->dev_t);\r
1663         cdev_del(&pservice->cdev);\r
1664         unregister_chrdev_region(pservice->dev_t, 1);\r
1665     }\r
1666 \r
1667     if (pservice->cls) {\r
1668         class_destroy(pservice->cls);\r
1669     }\r
1670 \r
1671     return ret;\r
1672 }\r
1673 \r
1674 static int vcodec_remove(struct platform_device *pdev)\r
1675 {\r
1676     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1677     struct resource *res;\r
1678 \r
1679     device_destroy(pservice->cls, pservice->dev_t);\r
1680     class_destroy(pservice->cls);\r
1681     cdev_del(&pservice->cdev);\r
1682     unregister_chrdev_region(pservice->dev_t, 1);\r
1683 \r
1684     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1685     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1686     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1687     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1688     vpu_put_clk(pservice);\r
1689     wake_lock_destroy(&pservice->wake_lock);\r
1690     \r
1691 #ifdef CONFIG_DEBUG_FS\r
1692     if (pservice->debugfs_file_regs) {\r
1693         debugfs_remove(pservice->debugfs_file_regs);\r
1694     }\r
1695 \r
1696     if (pservice->debugfs_dir) {\r
1697         debugfs_remove(pservice->debugfs_dir);\r
1698     }\r
1699 #endif\r
1700 \r
1701     return 0;\r
1702 }\r
1703 \r
1704 #if defined(CONFIG_OF)\r
1705 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1706     {.compatible = "vpu_service",},\r
1707     {.compatible = "rockchip,hevc_service",},\r
1708     {},\r
1709 };\r
1710 #endif\r
1711 \r
1712 static struct platform_driver vcodec_driver = {\r
1713     .probe     = vcodec_probe,\r
1714     .remove        = vcodec_remove,\r
1715     .driver = {\r
1716         .name = "vcodec",\r
1717         .owner = THIS_MODULE,\r
1718 #if defined(CONFIG_OF)\r
1719         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1720 #endif\r
1721     },\r
1722 };\r
1723 \r
1724 static void get_hw_info(struct vpu_service_info *pservice)\r
1725 {\r
1726     VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1727     VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1728 \r
1729     if (pservice->dev_id == VCODEC_DEVICE_ID_VPU) {             \r
1730         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1731         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1732     \r
1733         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1734         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1735         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1736             dec->jpegSupport = JPEG_PROGRESSIVE;\r
1737         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1738         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1739         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1740         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1741         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1742         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1743     \r
1744         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1745             dec->maxDecPicWidth = configReg & 0x07FFU;\r
1746         } else {\r
1747             dec->maxDecPicWidth = 4096;\r
1748         }\r
1749     \r
1750         /* 2nd Config register */\r
1751         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1752         if (dec->refBufSupport) {\r
1753             if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1754                 dec->refBufSupport |= 2;\r
1755             if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1756                 dec->refBufSupport |= 4;\r
1757         }\r
1758         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1759         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1760         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1761         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1762     \r
1763         /* JPEG xtensions */\r
1764         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1765             dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1766         } else {\r
1767             dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1768         }\r
1769     \r
1770         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1771             dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1772         } else {\r
1773             dec->rvSupport = RV_NOT_SUPPORTED;\r
1774         }\r
1775     \r
1776         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1777     \r
1778         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1779             dec->refBufSupport |= 8; /* enable HW support for offset */\r
1780         }\r
1781     \r
1782         /// invalidate fuse register value in rk319x vpu and following.\r
1783         if (!soc_is_rk3190() && !soc_is_rk3288()) {\r
1784             VPUHwFuseStatus_t hwFuseSts;\r
1785             /* Decoder fuse configuration */\r
1786             u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1787     \r
1788             hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1789             hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1790             hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1791             hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1792             hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1793             hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1794             hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1795             hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1796             hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1797             hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1798             hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1799             hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1800             hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1801             hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1802     \r
1803             /* check max. decoder output width */\r
1804     \r
1805             if (fuseReg & 0x8000U)\r
1806                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1807             else if (fuseReg & 0x4000U)\r
1808                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1809             else if (fuseReg & 0x2000U)\r
1810                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1811             else if (fuseReg & 0x1000U)\r
1812                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1813             else    /* remove warning */\r
1814                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1815     \r
1816             hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1817     \r
1818             /* Pp configuration */\r
1819             configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1820     \r
1821             if ((configReg >> DWL_PP_E) & 0x01U) {\r
1822                 dec->ppSupport = 1;\r
1823                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1824                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1825                 dec->ppConfig = configReg;\r
1826             } else {\r
1827                 dec->ppSupport = 0;\r
1828                 dec->maxPpOutPicWidth = 0;\r
1829                 dec->ppConfig = 0;\r
1830             }\r
1831     \r
1832             /* check the HW versio */\r
1833             if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))     {\r
1834                 /* Pp configuration */\r
1835                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1836     \r
1837                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1838                     /* Pp fuse configuration */\r
1839                     u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1840     \r
1841                     if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1842                         hwFuseSts.ppSupportFuse = 1;\r
1843                         /* check max. pp output width */\r
1844                         if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1845                         else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1846                         else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1847                         else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1848                         else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1849                         hwFuseSts.ppConfigFuse = fuseRegPp;\r
1850                     } else {\r
1851                         hwFuseSts.ppSupportFuse = 0;\r
1852                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1853                         hwFuseSts.ppConfigFuse = 0;\r
1854                     }\r
1855                 } else {\r
1856                     hwFuseSts.ppSupportFuse = 0;\r
1857                     hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1858                     hwFuseSts.ppConfigFuse = 0;\r
1859                 }\r
1860     \r
1861                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1862                     dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1863                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1864                     dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1865                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1866                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1867                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1868                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1869                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1870                     dec->jpegSupport = JPEG_BASELINE;\r
1871                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1872                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1873                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1874                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1875                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1876                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1877     \r
1878                 /* check the pp config vs fuse status */\r
1879                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1880                     u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1881                     u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1882                     u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1883                     u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1884     \r
1885                     if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1886                     if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1887                 }\r
1888                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1889                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1890                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1891                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1892                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1893             }\r
1894         }\r
1895     \r
1896         configReg = pservice->enc_dev.hwregs[63];\r
1897         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1898         enc->h264Enabled = (configReg >> 27) & 1;\r
1899         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1900         enc->jpegEnabled = (configReg >> 25) & 1;\r
1901         enc->vsEnabled = (configReg >> 24) & 1;\r
1902         enc->rgbEnabled = (configReg >> 28) & 1;\r
1903         //enc->busType = (configReg >> 20) & 15;\r
1904         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1905         //enc->busWidth = (configReg >> 12) & 15;\r
1906         enc->reg_size = pservice->reg_size;\r
1907         enc->reserv[0] = enc->reserv[1] = 0;\r
1908     \r
1909         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();\r
1910         if (pservice->auto_freq) {\r
1911             pr_info("vpu_service set to auto frequency mode\n");\r
1912             atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1913         }\r
1914         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1915         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1916     } else {\r
1917         // disable frequency switch in hevc.\r
1918         pservice->auto_freq = false;\r
1919     }\r
1920 }\r
1921 \r
1922 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1923 {\r
1924     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1925     vpu_device *dev = &pservice->dec_dev;\r
1926     u32 raw_status;\r
1927     u32 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1928 \r
1929         pr_debug("dec_irq\n");\r
1930 \r
1931         if (irq_status & DEC_INTERRUPT_BIT) {\r
1932                 pr_debug("dec_isr dec %x\n", irq_status);\r
1933                 if ((irq_status & 0x40001) == 0x40001)\r
1934                 {\r
1935                         do {\r
1936                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1937                         } while ((irq_status & 0x40001) == 0x40001);\r
1938                 }\r
1939 \r
1940                 /* clear dec IRQ */\r
1941         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1942             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1943         } else {\r
1944             /*writel(irq_status \r
1945               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1946                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1947 \r
1948             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1949         }\r
1950                 atomic_add(1, &dev->irq_count_codec);\r
1951         }\r
1952 \r
1953     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1954         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1955         if (irq_status & PP_INTERRUPT_BIT) {\r
1956             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1957             /* clear pp IRQ */\r
1958             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1959             atomic_add(1, &dev->irq_count_pp);\r
1960         }\r
1961     }\r
1962 \r
1963     pservice->irq_status = raw_status;\r
1964 \r
1965         return IRQ_WAKE_THREAD;\r
1966 }\r
1967 \r
1968 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1969 {\r
1970     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1971     vpu_device *dev = &pservice->dec_dev;\r
1972 \r
1973         mutex_lock(&pservice->lock);\r
1974         if (atomic_read(&dev->irq_count_codec)) {\r
1975 #if VPU_SERVICE_SHOW_TIME\r
1976                 do_gettimeofday(&dec_end);\r
1977                 pr_info("dec task: %ld ms\n",\r
1978                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1979                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1980 #endif\r
1981                 atomic_sub(1, &dev->irq_count_codec);\r
1982                 if (NULL == pservice->reg_codec) {\r
1983                         pr_err("error: dec isr with no task waiting\n");\r
1984                 } else {\r
1985                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1986                 }\r
1987         }\r
1988 \r
1989         if (atomic_read(&dev->irq_count_pp)) {\r
1990 \r
1991 #if VPU_SERVICE_SHOW_TIME\r
1992                 do_gettimeofday(&pp_end);\r
1993                 printk("pp  task: %ld ms\n",\r
1994                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1995                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1996 #endif\r
1997 \r
1998                 atomic_sub(1, &dev->irq_count_pp);\r
1999                 if (NULL == pservice->reg_pproc) {\r
2000                         pr_err("error: pp isr with no task waiting\n");\r
2001                 } else {\r
2002                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
2003                 }\r
2004         }\r
2005         try_set_reg(pservice);\r
2006         mutex_unlock(&pservice->lock);\r
2007         return IRQ_HANDLED;\r
2008 }\r
2009 \r
2010 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
2011 {\r
2012         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2013     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2014     vpu_device *dev = &pservice->enc_dev;\r
2015         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2016 \r
2017         pr_debug("vepu_irq irq status %x\n", irq_status);\r
2018 \r
2019 #if VPU_SERVICE_SHOW_TIME\r
2020         do_gettimeofday(&enc_end);\r
2021         pr_info("enc task: %ld ms\n",\r
2022                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
2023                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
2024 #endif\r
2025     \r
2026         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
2027                 /* clear enc IRQ */\r
2028                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
2029                 atomic_add(1, &dev->irq_count_codec);\r
2030         }\r
2031     \r
2032     pservice->irq_status = irq_status;\r
2033 \r
2034         return IRQ_WAKE_THREAD;\r
2035 }\r
2036 \r
2037 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
2038 {\r
2039         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
2040     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
2041     vpu_device *dev = &pservice->enc_dev;\r
2042 \r
2043         mutex_lock(&pservice->lock);\r
2044         if (atomic_read(&dev->irq_count_codec)) {\r
2045                 atomic_sub(1, &dev->irq_count_codec);\r
2046                 if (NULL == pservice->reg_codec) {\r
2047                         pr_err("error: enc isr with no task waiting\n");\r
2048                 } else {\r
2049                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
2050                 }\r
2051         }\r
2052         try_set_reg(pservice);\r
2053         mutex_unlock(&pservice->lock);\r
2054         return IRQ_HANDLED;\r
2055 }\r
2056 \r
2057 static int __init vcodec_service_init(void)\r
2058 {\r
2059     int ret;\r
2060 \r
2061     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
2062         pr_err("Platform device register failed (%d).\n", ret);\r
2063         return ret;\r
2064     }\r
2065 \r
2066 #ifdef CONFIG_DEBUG_FS\r
2067     vcodec_debugfs_init();\r
2068 #endif\r
2069 \r
2070     return ret;\r
2071 }\r
2072 \r
2073 static void __exit vcodec_service_exit(void)\r
2074 {\r
2075 #ifdef CONFIG_DEBUG_FS\r
2076     vcodec_debugfs_exit();\r
2077 #endif\r
2078 \r
2079         platform_driver_unregister(&vcodec_driver);\r
2080 }\r
2081 \r
2082 module_init(vcodec_service_init);\r
2083 module_exit(vcodec_service_exit);\r
2084 \r
2085 #ifdef CONFIG_DEBUG_FS\r
2086 #include <linux/seq_file.h>\r
2087 \r
2088 static int vcodec_debugfs_init()\r
2089 {\r
2090     parent = debugfs_create_dir("vcodec", NULL);\r
2091     if (!parent)\r
2092         return -1;\r
2093 \r
2094     return 0;\r
2095 }\r
2096 \r
2097 static void vcodec_debugfs_exit()\r
2098 {\r
2099     debugfs_remove(parent);\r
2100 }\r
2101 \r
2102 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
2103 {\r
2104     return debugfs_create_dir(dirname, parent);\r
2105 }\r
2106 \r
2107 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
2108 {\r
2109         struct vpu_service_info *pservice = s->private;\r
2110     unsigned int i, n;\r
2111         vpu_reg *reg, *reg_tmp;\r
2112         vpu_session *session, *session_tmp;\r
2113 \r
2114         mutex_lock(&pservice->lock);\r
2115         vpu_service_power_on(pservice);\r
2116     if (pservice->hw_info->hw_id != HEVC_ID) {\r
2117         seq_printf(s, "\nENC Registers:\n");\r
2118         n = pservice->enc_dev.iosize >> 2;\r
2119         for (i = 0; i < n; i++) {\r
2120             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
2121         }\r
2122     }\r
2123         seq_printf(s, "\nDEC Registers:\n");\r
2124         n = pservice->dec_dev.iosize >> 2;\r
2125         for (i = 0; i < n; i++) {\r
2126                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2127         }\r
2128 \r
2129         seq_printf(s, "\nvpu service status:\n");\r
2130         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
2131                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
2132                 //seq_printf(s, "waiting reg set %d\n");\r
2133                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
2134                         seq_printf(s, "waiting register set\n");\r
2135                 }\r
2136                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
2137                         seq_printf(s, "running register set\n");\r
2138                 }\r
2139                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
2140                         seq_printf(s, "done    register set\n");\r
2141                 }\r
2142         }\r
2143         mutex_unlock(&pservice->lock);\r
2144 \r
2145     return 0;\r
2146 }\r
2147 \r
2148 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
2149 {\r
2150         return single_open(file, debug_vcodec_show, inode->i_private);\r
2151 }\r
2152 \r
2153 #endif\r
2154 \r
2155 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
2156 #include "hevc_test_inc/pps_00.h"\r
2157 #include "hevc_test_inc/register_00.h"\r
2158 #include "hevc_test_inc/rps_00.h"\r
2159 #include "hevc_test_inc/scaling_list_00.h"\r
2160 #include "hevc_test_inc/stream_00.h"\r
2161 \r
2162 #include "hevc_test_inc/pps_01.h"\r
2163 #include "hevc_test_inc/register_01.h"\r
2164 #include "hevc_test_inc/rps_01.h"\r
2165 #include "hevc_test_inc/scaling_list_01.h"\r
2166 #include "hevc_test_inc/stream_01.h"\r
2167 \r
2168 #include "hevc_test_inc/cabac.h"\r
2169 \r
2170 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
2171 \r
2172 static struct ion_client *ion_client = NULL;\r
2173 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
2174 {\r
2175         int size = (len+15) & (~15);\r
2176     struct ion_handle *handle;\r
2177         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2178 \r
2179     if (ion_client == NULL) {\r
2180         ion_client = rockchip_ion_client_create("vcodec");\r
2181     }\r
2182 \r
2183     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2184 \r
2185     ptr = ion_map_kernel(ion_client, handle);\r
2186 \r
2187     ion_phys(ion_client, handle, phy, &size);\r
2188 \r
2189         memcpy(ptr, tbl, len);\r
2190 \r
2191         return ptr;\r
2192 }\r
2193 \r
2194 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
2195 {\r
2196         int size = (len+15) & (~15);\r
2197     struct ion_handle *handle;\r
2198         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
2199 \r
2200     if (ion_client == NULL) {\r
2201         ion_client = rockchip_ion_client_create("vcodec");\r
2202     }\r
2203 \r
2204     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
2205 \r
2206     ptr = ion_map_kernel(ion_client, handle);\r
2207 \r
2208     ion_phys(ion_client, handle, phy, &size);\r
2209 \r
2210         return ptr;\r
2211 }\r
2212 \r
2213 #define TEST_CNT    2\r
2214 static int hevc_test_case0(vpu_service_info *pservice)\r
2215 {\r
2216     vpu_session session;\r
2217     vpu_reg *reg; \r
2218     unsigned long size = 272;//sizeof(register_00); // registers array length\r
2219     int testidx = 0;\r
2220     int ret = 0;\r
2221 \r
2222     u8 *pps_tbl[TEST_CNT];\r
2223     u8 *register_tbl[TEST_CNT];\r
2224     u8 *rps_tbl[TEST_CNT];\r
2225     u8 *scaling_list_tbl[TEST_CNT];\r
2226     u8 *stream_tbl[TEST_CNT];\r
2227 \r
2228         int stream_size[2];\r
2229         int pps_size[2];\r
2230         int rps_size[2];\r
2231         int scl_size[2];\r
2232         int cabac_size[2];\r
2233         \r
2234     u32 phy_pps;\r
2235     u32 phy_rps;\r
2236     u32 phy_scl;\r
2237     u32 phy_str;\r
2238     u32 phy_yuv;\r
2239     u32 phy_ref;\r
2240     u32 phy_cabac;\r
2241 \r
2242         volatile u8 *stream_buf;\r
2243         volatile u8 *pps_buf;\r
2244         volatile u8 *rps_buf;\r
2245         volatile u8 *scl_buf;\r
2246         volatile u8 *yuv_buf;\r
2247         volatile u8 *cabac_buf;\r
2248         volatile u8 *ref_buf;\r
2249 \r
2250     u8 *pps;\r
2251     u8 *yuv[2];\r
2252     int i;\r
2253     \r
2254     pps_tbl[0] = pps_00;\r
2255     pps_tbl[1] = pps_01;\r
2256 \r
2257     register_tbl[0] = register_00;\r
2258     register_tbl[1] = register_01;\r
2259     \r
2260     rps_tbl[0] = rps_00;\r
2261     rps_tbl[1] = rps_01;\r
2262     \r
2263     scaling_list_tbl[0] = scaling_list_00;\r
2264     scaling_list_tbl[1] = scaling_list_01;\r
2265 \r
2266     stream_tbl[0] = stream_00;\r
2267     stream_tbl[1] = stream_01;\r
2268 \r
2269     stream_size[0] = sizeof(stream_00);\r
2270     stream_size[1] = sizeof(stream_01);\r
2271 \r
2272         pps_size[0] = sizeof(pps_00);\r
2273         pps_size[1] = sizeof(pps_01);\r
2274 \r
2275         rps_size[0] = sizeof(rps_00);\r
2276         rps_size[1] = sizeof(rps_01);\r
2277 \r
2278         scl_size[0] = sizeof(scaling_list_00);\r
2279         scl_size[1] = sizeof(scaling_list_01);\r
2280         \r
2281         cabac_size[0] = sizeof(Cabac_table);\r
2282         cabac_size[1] = sizeof(Cabac_table);\r
2283 \r
2284     // create session\r
2285     session.pid = current->pid;\r
2286     session.type = VPU_DEC;\r
2287     INIT_LIST_HEAD(&session.waiting);\r
2288         INIT_LIST_HEAD(&session.running);\r
2289         INIT_LIST_HEAD(&session.done);\r
2290         INIT_LIST_HEAD(&session.list_session);\r
2291         init_waitqueue_head(&session.wait);\r
2292         atomic_set(&session.task_running, 0);\r
2293         list_add_tail(&session.list_session, &pservice->session);\r
2294 \r
2295     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2296     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2297 \r
2298         while (testidx < TEST_CNT) {\r
2299         \r
2300         // create registers\r
2301         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2302         if (NULL == reg) {\r
2303             pr_err("error: kmalloc fail in reg_init\n");\r
2304             return -1;\r
2305         }\r
2306 \r
2307 \r
2308         if (size > pservice->reg_size) {\r
2309             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2310             size = pservice->reg_size;\r
2311         }\r
2312         reg->session = &session;\r
2313         reg->type = session.type;\r
2314         reg->size = size;\r
2315         reg->freq = VPU_FREQ_DEFAULT;\r
2316         reg->reg = (unsigned long *)&reg[1];\r
2317         INIT_LIST_HEAD(&reg->session_link);\r
2318         INIT_LIST_HEAD(&reg->status_link);\r
2319 \r
2320         // TODO: stuff registers\r
2321         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2322 \r
2323                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2324                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2325                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2326                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2327                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2328 \r
2329                 pps = pps_buf;\r
2330 \r
2331         // TODO: replace reigster address\r
2332 \r
2333         for (i=0; i<64; i++) {\r
2334             u32 scaling_offset;\r
2335             u32 tmp;\r
2336 \r
2337             scaling_offset = (u32)pps[i*80+74];\r
2338             scaling_offset += (u32)pps[i*80+75] << 8;\r
2339             scaling_offset += (u32)pps[i*80+76] << 16;\r
2340             scaling_offset += (u32)pps[i*80+77] << 24;\r
2341 \r
2342             tmp = phy_scl + scaling_offset;\r
2343 \r
2344             pps[i*80+74] = tmp & 0xff;\r
2345             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2346             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2347             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2348         }\r
2349 \r
2350         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2351 \r
2352         reg->reg[1] = 0x21;\r
2353         reg->reg[4] = phy_str;\r
2354         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2355         reg->reg[6] = phy_cabac;\r
2356         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2357         reg->reg[42] = phy_pps;\r
2358         reg->reg[43] = phy_rps;\r
2359         for (i = 10; i <= 24; i++) {\r
2360             reg->reg[i] = phy_yuv;\r
2361         }\r
2362 \r
2363         mutex_lock(&pservice->lock);\r
2364         list_add_tail(&reg->status_link, &pservice->waiting);\r
2365         list_add_tail(&reg->session_link, &session.waiting);\r
2366         mutex_unlock(&pservice->lock);\r
2367 \r
2368         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2369 \r
2370         // stuff hardware\r
2371         try_set_reg(pservice);\r
2372 \r
2373         // wait for result\r
2374         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2375         if (!list_empty(&session.done)) {\r
2376             if (ret < 0) {\r
2377                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2378             }\r
2379             ret = 0;\r
2380         } else {\r
2381             if (unlikely(ret < 0)) {\r
2382                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2383             } else if (0 == ret) {\r
2384                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2385                 ret = -ETIMEDOUT;\r
2386             }\r
2387         }\r
2388         if (ret < 0) {\r
2389             int task_running = atomic_read(&session.task_running);\r
2390             int n;\r
2391             mutex_lock(&pservice->lock);\r
2392             vpu_service_dump(pservice);\r
2393             if (task_running) {\r
2394                 atomic_set(&session.task_running, 0);\r
2395                 atomic_sub(task_running, &pservice->total_running);\r
2396                 printk("%d task is running but not return, reset hardware...", task_running);\r
2397                 vpu_reset(pservice);\r
2398                 printk("done\n");\r
2399             }\r
2400             vpu_service_session_clear(pservice, &session);\r
2401             mutex_unlock(&pservice->lock);\r
2402 \r
2403             printk("\nDEC Registers:\n");\r
2404                 n = pservice->dec_dev.iosize >> 2;\r
2405                 for (i=0; i<n; i++) {\r
2406                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2407                 }\r
2408 \r
2409             pr_err("test index %d failed\n", testidx);\r
2410             break;\r
2411         } else {\r
2412             pr_info("test index %d success\n", testidx);\r
2413 \r
2414             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2415 \r
2416             for (i=0; i<68; i++) {\r
2417                 if (i % 4 == 0) {\r
2418                     printk("%02d: ", i);\r
2419                 }\r
2420                 printk("%08x ", reg->reg[i]);\r
2421                 if ((i+1) % 4 == 0) {\r
2422                     printk("\n");\r
2423                 }\r
2424             }\r
2425 \r
2426             testidx++;\r
2427         }\r
2428 \r
2429         reg_deinit(pservice, reg);\r
2430     }\r
2431 \r
2432     return 0;\r
2433 }\r
2434 \r
2435 #endif\r
2436 \r