2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/clk.h>
20 #include <linux/compat.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/miscdevice.h>
31 #include <linux/poll.h>
32 #include <linux/platform_device.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/wakelock.h>
36 #include <linux/cdev.h>
38 #include <linux/of_platform.h>
39 #include <linux/of_irq.h>
40 #include <linux/rockchip/cpu.h>
41 #include <linux/rockchip/cru.h>
42 #ifdef CONFIG_MFD_SYSCON
43 #include <linux/regmap.h>
45 #include <linux/mfd/syscon.h>
47 #include <asm/cacheflush.h>
48 #include <linux/uaccess.h>
49 #include <linux/rockchip/grf.h>
51 #if defined(CONFIG_ION_ROCKCHIP)
52 #include <linux/rockchip_ion.h>
55 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
56 #define CONFIG_VCODEC_MMU
59 #ifdef CONFIG_VCODEC_MMU
60 #include <linux/rockchip-iovmm.h>
61 #include <linux/dma-buf.h>
64 #ifdef CONFIG_DEBUG_FS
65 #include <linux/debugfs.h>
68 #if defined(CONFIG_ARCH_RK319X)
72 #include "vcodec_service.h"
76 * +------+-------------------+
78 * +------+-------------------+
79 * 0~23 bit is for different information type
80 * 24~31 bit is for information print format
83 #define DEBUG_POWER 0x00000001
84 #define DEBUG_CLOCK 0x00000002
85 #define DEBUG_IRQ_STATUS 0x00000004
86 #define DEBUG_IOMMU 0x00000008
87 #define DEBUG_IOCTL 0x00000010
88 #define DEBUG_FUNCTION 0x00000020
89 #define DEBUG_REGISTER 0x00000040
90 #define DEBUG_EXTRA_INFO 0x00000080
91 #define DEBUG_TIMING 0x00000100
93 #define PRINT_FUNCTION 0x80000000
94 #define PRINT_LINE 0x40000000
97 module_param(debug, int, S_IRUGO | S_IWUSR);
98 MODULE_PARM_DESC(debug,
99 "Debug level - higher value produces more verbose messages");
101 #define HEVC_TEST_ENABLE 0
102 #define VCODEC_CLOCK_ENABLE 1
105 VPU_DEC_ID_9190 = 0x6731,
106 VPU_ID_8270 = 0x8270,
107 VPU_ID_4831 = 0x4831,
114 VPU_TYPE_COMBO_NOENC,
119 VPU_DEC_TYPE_9190 = 0,
120 VPU_ENC_TYPE_8270 = 0x100,
124 typedef enum VPU_FREQ {
137 unsigned long hw_addr;
138 unsigned long enc_offset;
139 unsigned long enc_reg_num;
140 unsigned long enc_io_size;
141 unsigned long dec_offset;
142 unsigned long dec_reg_num;
143 unsigned long dec_io_size;
146 struct extra_info_elem {
151 #define EXTRA_INFO_MAGIC 0x4C4A46
153 struct extra_info_for_iommu {
156 struct extra_info_elem elem[20];
159 #define MHZ (1000*1000)
161 #define REG_NUM_9190_DEC (60)
162 #define REG_NUM_9190_PP (41)
163 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
165 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
167 #define REG_NUM_ENC_8270 (96)
168 #define REG_SIZE_ENC_8270 (0x200)
169 #define REG_NUM_ENC_4831 (164)
170 #define REG_SIZE_ENC_4831 (0x400)
172 #define REG_NUM_HEVC_DEC (68)
174 #define SIZE_REG(reg) ((reg)*4)
176 static VPU_HW_INFO_E vpu_hw_set[] = {
178 .hw_id = VPU_ID_8270,
181 .enc_reg_num = REG_NUM_ENC_8270,
182 .enc_io_size = REG_NUM_ENC_8270 * 4,
183 .dec_offset = REG_SIZE_ENC_8270,
184 .dec_reg_num = REG_NUM_9190_DEC_PP,
185 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
188 .hw_id = VPU_ID_4831,
191 .enc_reg_num = REG_NUM_ENC_4831,
192 .enc_io_size = REG_NUM_ENC_4831 * 4,
193 .dec_offset = REG_SIZE_ENC_4831,
194 .dec_reg_num = REG_NUM_9190_DEC_PP,
195 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
201 .dec_reg_num = REG_NUM_HEVC_DEC,
202 .dec_io_size = REG_NUM_HEVC_DEC * 4,
205 .hw_id = VPU_DEC_ID_9190,
211 .dec_reg_num = REG_NUM_9190_DEC_PP,
212 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
217 #define BIT(x) (1<<(x))
220 // interrupt and error status register
221 #define DEC_INTERRUPT_REGISTER 1
222 #define DEC_INTERRUPT_BIT BIT(8)
223 #define DEC_READY_BIT BIT(12)
224 #define DEC_BUS_ERROR_BIT BIT(13)
225 #define DEC_BUFFER_EMPTY_BIT BIT(14)
226 #define DEC_ASO_ERROR_BIT BIT(15)
227 #define DEC_STREAM_ERROR_BIT BIT(16)
228 #define DEC_SLICE_DONE_BIT BIT(17)
229 #define DEC_TIMEOUT_BIT BIT(18)
230 #define DEC_ERR_MASK DEC_BUS_ERROR_BIT \
231 |DEC_BUFFER_EMPTY_BIT \
232 |DEC_STREAM_ERROR_BIT \
235 #define PP_INTERRUPT_REGISTER 60
236 #define PP_INTERRUPT_BIT BIT(8)
237 #define PP_READY_BIT BIT(12)
238 #define PP_BUS_ERROR_BIT BIT(13)
239 #define PP_ERR_MASK PP_BUS_ERROR_BIT
241 #define ENC_INTERRUPT_REGISTER 1
242 #define ENC_INTERRUPT_BIT BIT(0)
243 #define ENC_READY_BIT BIT(2)
244 #define ENC_BUS_ERROR_BIT BIT(3)
245 #define ENC_BUFFER_FULL_BIT BIT(5)
246 #define ENC_TIMEOUT_BIT BIT(6)
247 #define ENC_ERR_MASK ENC_BUS_ERROR_BIT \
248 |ENC_BUFFER_FULL_BIT \
251 #define HEVC_INTERRUPT_REGISTER 1
252 #define HEVC_DEC_INT_RAW_BIT BIT(9)
253 #define HEVC_DEC_BUS_ERROR_BIT BIT(13)
254 #define HEVC_DEC_STR_ERROR_BIT BIT(14)
255 #define HEVC_DEC_TIMEOUT_BIT BIT(15)
256 #define HEVC_DEC_BUFFER_EMPTY_BIT BIT(16)
257 #define HEVC_DEC_COLMV_ERROR_BIT BIT(17)
258 #define HEVC_DEC_ERR_MASK HEVC_DEC_BUS_ERROR_BIT \
259 |HEVC_DEC_STR_ERROR_BIT \
260 |HEVC_DEC_TIMEOUT_BIT \
261 |HEVC_DEC_BUFFER_EMPTY_BIT \
262 |HEVC_DEC_COLMV_ERROR_BIT
265 // gating configuration set
266 #define VPU_REG_EN_ENC 14
267 #define VPU_REG_ENC_GATE 2
268 #define VPU_REG_ENC_GATE_BIT (1<<4)
270 #define VPU_REG_EN_DEC 1
271 #define VPU_REG_DEC_GATE 2
272 #define VPU_REG_DEC_GATE_BIT (1<<10)
273 #define VPU_REG_EN_PP 0
274 #define VPU_REG_PP_GATE 1
275 #define VPU_REG_PP_GATE_BIT (1<<8)
276 #define VPU_REG_EN_DEC_PP 1
277 #define VPU_REG_DEC_PP_GATE 61
278 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
282 #define vpu_debug_func(type, fmt, args...) \
284 if (unlikely(debug & type)) { \
285 pr_info("%s:%d: " fmt, \
286 __func__, __LINE__, ##args); \
289 #define vpu_debug(type, fmt, args...) \
291 if (unlikely(debug & type)) { \
292 pr_info(fmt, ##args); \
296 #define vpu_debug_func(level, fmt, args...)
297 #define vpu_debug(level, fmt, args...)
300 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
301 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
303 #define vpu_err(fmt, args...) \
304 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
306 #if defined(CONFIG_VCODEC_MMU)
307 static u8 addr_tbl_vpu_h264dec[] = {
308 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
309 25, 26, 27, 28, 29, 40, 41
312 static u8 addr_tbl_vpu_vp8dec[] = {
313 10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
316 static u8 addr_tbl_vpu_vp6dec[] = {
317 12, 13, 14, 18, 27, 40
320 static u8 addr_tbl_vpu_vc1dec[] = {
321 12, 13, 14, 15, 16, 17, 27, 41
324 static u8 addr_tbl_vpu_jpegdec[] = {
328 static u8 addr_tbl_vpu_defaultdec[] = {
329 12, 13, 14, 15, 16, 17, 40, 41
332 static u8 addr_tbl_vpu_enc[] = {
333 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
336 static u8 addr_tbl_hevc_dec[] = {
337 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
338 21, 22, 23, 24, 42, 43
363 * struct for process session which connect to vpu
365 * @author ChenHengming (2011-5-3)
367 typedef struct vpu_session {
368 enum VPU_CLIENT_TYPE type;
369 /* a linked list of data so we can access them for debugging */
370 struct list_head list_session;
371 /* a linked list of register data waiting for process */
372 struct list_head waiting;
373 /* a linked list of register data in processing */
374 struct list_head running;
375 /* a linked list of register data processed */
376 struct list_head done;
377 wait_queue_head_t wait;
379 atomic_t task_running;
383 * struct for process register set
385 * @author ChenHengming (2011-5-4)
387 typedef struct vpu_reg {
388 enum VPU_CLIENT_TYPE type;
390 vpu_session *session;
391 struct vpu_subdev_data *data;
392 struct list_head session_link; /* link to vpu service session */
393 struct list_head status_link; /* link to register set list */
395 #if defined(CONFIG_VCODEC_MMU)
396 struct list_head mem_region_list;
401 typedef struct vpu_device {
402 atomic_t irq_count_codec;
403 atomic_t irq_count_pp;
404 unsigned long iobaseaddr;
406 volatile u32 *hwregs;
409 enum vcodec_device_id {
410 VCODEC_DEVICE_ID_VPU,
411 VCODEC_DEVICE_ID_HEVC,
412 VCODEC_DEVICE_ID_COMBO
415 enum VCODEC_RUNNING_MODE {
416 VCODEC_RUNNING_MODE_NONE = -1,
417 VCODEC_RUNNING_MODE_VPU,
418 VCODEC_RUNNING_MODE_HEVC,
421 struct vcodec_mem_region {
422 struct list_head srv_lnk;
423 struct list_head reg_lnk;
424 struct list_head session_lnk;
425 unsigned long iova; /* virtual address for iommu */
428 struct ion_handle *hdl;
432 MMU_ACTIVATED = BIT(0)
435 struct vpu_subdev_data {
439 struct device *child_dev;
443 struct vpu_service_info *pservice;
446 enum VCODEC_RUNNING_MODE mode;
447 struct list_head lnk_service;
453 VPU_HW_INFO_E *hw_info;
458 #ifdef CONFIG_DEBUG_FS
459 struct dentry *debugfs_dir;
460 struct dentry *debugfs_file_regs;
463 #if defined(CONFIG_VCODEC_MMU)
464 struct device *mmu_dev;
468 typedef struct vpu_service_info {
469 struct wake_lock wake_lock;
470 struct delayed_work power_off_work;
472 struct list_head waiting; /* link to link_reg in struct vpu_reg */
473 struct list_head running; /* link to link_reg in struct vpu_reg */
474 struct list_head done; /* link to link_reg in struct vpu_reg */
475 struct list_head session; /* link to list_session in struct vpu_session */
476 atomic_t total_running;
478 atomic_t power_on_cnt;
479 atomic_t power_off_cnt;
483 struct vpu_dec_config dec_config;
484 struct vpu_enc_config enc_config;
488 atomic_t freq_status;
490 struct clk *aclk_vcodec;
491 struct clk *hclk_vcodec;
492 struct clk *clk_core;
493 struct clk *clk_cabac;
494 struct clk *pd_video;
499 #if defined(CONFIG_VCODEC_MMU)
500 struct ion_client *ion_client;
501 struct list_head mem_region_list;
504 enum vcodec_device_id dev_id;
506 enum VCODEC_RUNNING_MODE curr_mode;
509 struct delayed_work simulate_work;
515 #ifdef CONFIG_MFD_SYSCON
516 struct regmap *grf_base;
523 struct list_head subdev_list;
526 struct vcodec_combo {
527 struct vpu_service_info *vpu_srv;
528 struct vpu_service_info *hevc_srv;
529 struct list_head waiting;
530 struct list_head running;
531 struct mutex run_lock;
533 enum vcodec_device_id current_hw_mode;
541 struct compat_vpu_request {
546 /* debugfs root directory for all device (vpu, hevc).*/
547 static struct dentry *parent;
549 #ifdef CONFIG_DEBUG_FS
550 static int vcodec_debugfs_init(void);
551 static void vcodec_debugfs_exit(void);
552 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
553 static int debug_vcodec_open(struct inode *inode, struct file *file);
555 static const struct file_operations debug_vcodec_fops = {
556 .open = debug_vcodec_open,
559 .release = single_release,
563 #define VDPU_SOFT_RESET_REG 101
564 #define VDPU_CLEAN_CACHE_REG 516
565 #define VEPU_CLEAN_CACHE_REG 772
566 #define HEVC_CLEAN_CACHE_REG 260
568 #define VPU_REG_ENABLE(base, reg) do { \
572 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
573 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
574 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
575 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
577 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
578 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
582 struct timeval start;
595 task_info tasks[TASK_TYPE_BUTT] = {
598 .error_mask = ENC_ERR_MASK
602 .error_mask = DEC_ERR_MASK
606 .error_mask = PP_ERR_MASK
610 .error_mask = HEVC_DEC_ERR_MASK
614 static void time_record(task_info *task, int is_end)
616 if (unlikely(debug & DEBUG_TIMING)) {
617 do_gettimeofday((is_end)?(&task->end):(&task->start));
621 static void time_diff(task_info *task)
623 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
624 (task->end.tv_sec - task->start.tv_sec) * 1000 +
625 (task->end.tv_usec - task->start.tv_usec) / 1000);
628 static void vcodec_enter_mode(struct vpu_subdev_data *data)
632 struct vpu_service_info *pservice = data->pservice;
633 struct vpu_subdev_data *subdata, *n;
634 if (pservice->subcnt < 2) {
635 #if defined(CONFIG_VCODEC_MMU)
636 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
637 set_bit(MMU_ACTIVATED, &data->state);
638 if (atomic_read(&pservice->enabled))
639 rockchip_iovmm_activate(data->dev);
641 BUG_ON(!atomic_read(&pservice->enabled));
647 if (pservice->curr_mode == data->mode)
650 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
651 #if defined(CONFIG_VCODEC_MMU)
652 list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
653 if (data != subdata && subdata->mmu_dev &&
654 test_bit(MMU_ACTIVATED, &subdata->state)) {
655 clear_bit(MMU_ACTIVATED, &subdata->state);
656 rockchip_iovmm_deactivate(subdata->dev);
660 bits = 1 << pservice->mode_bit;
661 #ifdef CONFIG_MFD_SYSCON
662 regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
664 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
665 regmap_write(pservice->grf_base, pservice->mode_ctrl,
666 raw | bits | (bits << 16));
668 regmap_write(pservice->grf_base, pservice->mode_ctrl,
669 (raw & (~bits)) | (bits << 16));
671 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
672 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
673 writel_relaxed(raw | bits | (bits << 16),
674 pservice->grf_base + pservice->mode_ctrl / 4);
676 writel_relaxed((raw & (~bits)) | (bits << 16),
677 pservice->grf_base + pservice->mode_ctrl / 4);
679 #if defined(CONFIG_VCODEC_MMU)
680 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
681 set_bit(MMU_ACTIVATED, &data->state);
682 if (atomic_read(&pservice->enabled))
683 rockchip_iovmm_activate(data->dev);
685 BUG_ON(!atomic_read(&pservice->enabled));
688 pservice->prev_mode = pservice->curr_mode;
689 pservice->curr_mode = data->mode;
692 static void vcodec_exit_mode(struct vpu_subdev_data *data)
694 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
695 clear_bit(MMU_ACTIVATED, &data->state);
696 rockchip_iovmm_deactivate(data->dev);
697 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
701 static int vpu_get_clk(struct vpu_service_info *pservice)
703 #if VCODEC_CLOCK_ENABLE
704 switch (pservice->dev_id) {
705 case VCODEC_DEVICE_ID_HEVC:
706 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
707 if (IS_ERR(pservice->pd_video)) {
708 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
711 case VCODEC_DEVICE_ID_COMBO:
712 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
713 if (IS_ERR(pservice->clk_cabac)) {
714 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
715 pservice->clk_cabac = NULL;
717 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
718 if (IS_ERR(pservice->clk_core)) {
719 dev_err(pservice->dev, "failed on clk_get clk_core\n");
722 case VCODEC_DEVICE_ID_VPU:
723 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
724 if (IS_ERR(pservice->aclk_vcodec)) {
725 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
729 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
730 if (IS_ERR(pservice->hclk_vcodec)) {
731 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
734 if (pservice->pd_video == NULL) {
735 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
736 if (IS_ERR(pservice->pd_video)) {
737 pservice->pd_video = NULL;
738 dev_info(pservice->dev, "do not have pd_video\n");
752 static void vpu_put_clk(struct vpu_service_info *pservice)
754 #if VCODEC_CLOCK_ENABLE
755 if (pservice->pd_video)
756 devm_clk_put(pservice->dev, pservice->pd_video);
757 if (pservice->aclk_vcodec)
758 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
759 if (pservice->hclk_vcodec)
760 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
761 if (pservice->clk_core)
762 devm_clk_put(pservice->dev, pservice->clk_core);
763 if (pservice->clk_cabac)
764 devm_clk_put(pservice->dev, pservice->clk_cabac);
768 static void vpu_reset(struct vpu_subdev_data *data)
770 struct vpu_service_info *pservice = data->pservice;
771 pr_info("%s: resetting...", dev_name(pservice->dev));
773 #if defined(CONFIG_ARCH_RK29)
774 clk_disable(aclk_ddr_vepu);
775 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
776 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
777 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
778 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
780 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
781 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
782 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
783 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
784 clk_enable(aclk_ddr_vepu);
785 #elif defined(CONFIG_ARCH_RK30)
786 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
787 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
788 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
789 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
790 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
792 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
793 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
794 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
795 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
796 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
798 pservice->reg_codec = NULL;
799 pservice->reg_pproc = NULL;
800 pservice->reg_resev = NULL;
802 #if defined(CONFIG_VCODEC_MMU)
803 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
804 clear_bit(MMU_ACTIVATED, &data->state);
805 if (atomic_read(&pservice->enabled))
806 rockchip_iovmm_deactivate(data->dev);
808 BUG_ON(!atomic_read(&pservice->enabled));
813 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
814 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
817 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
818 reg_deinit(data, reg);
820 list_for_each_entry_safe(reg, n, &session->running, session_link) {
821 reg_deinit(data, reg);
823 list_for_each_entry_safe(reg, n, &session->done, session_link) {
824 reg_deinit(data, reg);
828 static void vpu_service_dump(struct vpu_service_info *pservice)
832 static void vpu_service_power_off(struct vpu_service_info *pservice)
835 struct vpu_subdev_data *data = NULL, *n;
836 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
840 total_running = atomic_read(&pservice->total_running);
842 pr_alert("alert: power off when %d task running!!\n", total_running);
844 pr_alert("alert: delay 50 ms for running task\n");
845 vpu_service_dump(pservice);
848 pr_info("%s: power off...", dev_name(pservice->dev));
850 #if defined(CONFIG_VCODEC_MMU)
851 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
852 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
853 clear_bit(MMU_ACTIVATED, &data->state);
854 rockchip_iovmm_deactivate(data->dev);
857 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
860 #if VCODEC_CLOCK_ENABLE
861 if (pservice->pd_video)
862 clk_disable_unprepare(pservice->pd_video);
863 if (pservice->hclk_vcodec)
864 clk_disable_unprepare(pservice->hclk_vcodec);
865 if (pservice->aclk_vcodec)
866 clk_disable_unprepare(pservice->aclk_vcodec);
867 if (pservice->clk_core)
868 clk_disable_unprepare(pservice->clk_core);
869 if (pservice->clk_cabac)
870 clk_disable_unprepare(pservice->clk_cabac);
873 atomic_add(1, &pservice->power_off_cnt);
874 wake_unlock(&pservice->wake_lock);
878 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
880 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
883 static void vpu_power_off_work(struct work_struct *work_s)
885 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
886 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
888 if (mutex_trylock(&pservice->lock)) {
889 vpu_service_power_off(pservice);
890 mutex_unlock(&pservice->lock);
892 /* Come back later if the device is busy... */
893 vpu_queue_power_off_work(pservice);
897 static void vpu_service_power_on(struct vpu_service_info *pservice)
901 ktime_t now = ktime_get();
902 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
903 cancel_delayed_work_sync(&pservice->power_off_work);
904 vpu_queue_power_off_work(pservice);
907 ret = atomic_add_unless(&pservice->enabled, 1, 1);
911 pr_info("%s: power on\n", dev_name(pservice->dev));
913 #define BIT_VCODEC_CLK_SEL (1<<10)
915 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
916 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
917 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
919 #if VCODEC_CLOCK_ENABLE
920 if (pservice->aclk_vcodec)
921 clk_prepare_enable(pservice->aclk_vcodec);
922 if (pservice->hclk_vcodec)
923 clk_prepare_enable(pservice->hclk_vcodec);
924 if (pservice->clk_core)
925 clk_prepare_enable(pservice->clk_core);
926 if (pservice->clk_cabac)
927 clk_prepare_enable(pservice->clk_cabac);
928 if (pservice->pd_video)
929 clk_prepare_enable(pservice->pd_video);
933 atomic_add(1, &pservice->power_on_cnt);
934 wake_lock(&pservice->wake_lock);
937 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
939 u32 type = (reg->reg[3] & 0xF0000000) >> 28;
940 return ((type == 8) || (type == 4));
943 static inline bool reg_check_interlace(vpu_reg *reg)
945 u32 type = (reg->reg[3] & (1 << 23));
949 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
951 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
955 static inline int reg_probe_width(vpu_reg *reg)
957 int width_in_mb = reg->reg[4] >> 23;
958 return width_in_mb * 16;
961 #if defined(CONFIG_VCODEC_MMU)
962 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
964 struct vpu_service_info *pservice = data->pservice;
965 struct ion_handle *hdl;
967 struct vcodec_mem_region *mem_region;
969 hdl = ion_import_dma_buf(pservice->ion_client, fd);
971 vpu_err("import dma-buf from fd %d failed\n", fd);
974 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
976 if (mem_region == NULL) {
977 vpu_err("allocate memory for iommu memory region failed\n");
978 ion_free(pservice->ion_client, hdl);
982 mem_region->hdl = hdl;
983 ret = ion_map_iommu(data->dev, pservice->ion_client,
984 mem_region->hdl, &mem_region->iova, &mem_region->len);
987 vpu_err("ion map iommu failed\n");
989 ion_free(pservice->ion_client, hdl);
992 INIT_LIST_HEAD(&mem_region->reg_lnk);
993 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
994 return mem_region->iova;
997 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
998 int size, vpu_reg *reg,
999 struct extra_info_for_iommu *ext_inf)
1001 struct vpu_service_info *pservice = data->pservice;
1006 if (tbl == NULL || size <= 0) {
1007 dev_err(pservice->dev, "input arguments invalidate\n");
1011 for (i = 0; i < size; i++) {
1012 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1014 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1015 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1016 /* special for vpu dec num 41 regitster */
1017 offset = reg->reg[tbl[i]] >> 10 << 4;
1019 offset = reg->reg[tbl[i]] >> 10;
1022 struct ion_handle *hdl;
1024 struct vcodec_mem_region *mem_region;
1026 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1028 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1029 return PTR_ERR(hdl);
1032 if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1035 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1036 for (i=0; i<64; i++) {
1040 scaling_offset = (u32)pps[i*80+74];
1041 scaling_offset += (u32)pps[i*80+75] << 8;
1042 scaling_offset += (u32)pps[i*80+76] << 16;
1043 scaling_offset += (u32)pps[i*80+77] << 24;
1044 scaling_fd = scaling_offset&0x3ff;
1045 scaling_offset = scaling_offset >> 10;
1046 if(scaling_fd > 0) {
1047 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1048 tmp += scaling_offset;
1049 pps[i*80+74] = tmp & 0xff;
1050 pps[i*80+75] = (tmp >> 8) & 0xff;
1051 pps[i*80+76] = (tmp >> 16) & 0xff;
1052 pps[i*80+77] = (tmp >> 24) & 0xff;
1057 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1059 if (mem_region == NULL) {
1060 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1061 ion_free(pservice->ion_client, hdl);
1065 mem_region->hdl = hdl;
1066 mem_region->reg_idx = tbl[i];
1067 ret = ion_map_iommu(data->dev,
1068 pservice->ion_client,
1074 dev_err(pservice->dev, "ion map iommu failed\n");
1076 ion_free(pservice->ion_client, hdl);
1079 reg->reg[tbl[i]] = mem_region->iova + offset;
1080 INIT_LIST_HEAD(&mem_region->reg_lnk);
1081 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1085 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1086 for (i=0; i<ext_inf->cnt; i++) {
1087 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1088 ext_inf->elem[i].index,
1089 ext_inf->elem[i].offset);
1090 reg->reg[ext_inf->elem[i].index] +=
1091 ext_inf->elem[i].offset;
1098 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1100 struct extra_info_for_iommu *ext_inf)
1106 hw_id = data->hw_info->hw_id;
1108 if (hw_id == HEVC_ID) {
1109 tbl = addr_tbl_hevc_dec;
1110 size = sizeof(addr_tbl_hevc_dec);
1112 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1113 switch (reg_check_fmt(reg)) {
1114 case VPU_DEC_FMT_H264:
1116 tbl = addr_tbl_vpu_h264dec;
1117 size = sizeof(addr_tbl_vpu_h264dec);
1120 case VPU_DEC_FMT_VP8:
1121 case VPU_DEC_FMT_VP7:
1123 tbl = addr_tbl_vpu_vp8dec;
1124 size = sizeof(addr_tbl_vpu_vp8dec);
1128 case VPU_DEC_FMT_VP6:
1130 tbl = addr_tbl_vpu_vp6dec;
1131 size = sizeof(addr_tbl_vpu_vp6dec);
1134 case VPU_DEC_FMT_VC1:
1136 tbl = addr_tbl_vpu_vc1dec;
1137 size = sizeof(addr_tbl_vpu_vc1dec);
1141 case VPU_DEC_FMT_JPEG:
1143 tbl = addr_tbl_vpu_jpegdec;
1144 size = sizeof(addr_tbl_vpu_jpegdec);
1148 tbl = addr_tbl_vpu_defaultdec;
1149 size = sizeof(addr_tbl_vpu_defaultdec);
1152 } else if (reg->type == VPU_ENC) {
1153 tbl = addr_tbl_vpu_enc;
1154 size = sizeof(addr_tbl_vpu_enc);
1159 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1166 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1167 vpu_session *session, void __user *src, u32 size)
1169 struct vpu_service_info *pservice = data->pservice;
1171 struct extra_info_for_iommu extra_info;
1172 vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1177 vpu_err("error: kmalloc fail in reg_init\n");
1181 if (size > data->reg_size) {
1182 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1183 size, data->reg_size);*/
1184 extra_size = size - data->reg_size;
1185 size = data->reg_size;
1187 reg->session = session;
1189 reg->type = session->type;
1191 reg->freq = VPU_FREQ_DEFAULT;
1192 reg->reg = (u32 *)®[1];
1193 INIT_LIST_HEAD(®->session_link);
1194 INIT_LIST_HEAD(®->status_link);
1196 #if defined(CONFIG_VCODEC_MMU)
1198 INIT_LIST_HEAD(®->mem_region_list);
1201 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1202 vpu_err("error: copy_from_user failed in reg_init\n");
1207 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1208 vpu_err("error: copy_from_user failed in reg_init\n");
1213 #if defined(CONFIG_VCODEC_MMU)
1214 if (data->mmu_dev &&
1215 0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1216 vpu_err("error: translate reg address failed\n");
1222 mutex_lock(&pservice->lock);
1223 list_add_tail(®->status_link, &pservice->waiting);
1224 list_add_tail(®->session_link, &session->waiting);
1225 mutex_unlock(&pservice->lock);
1227 if (pservice->auto_freq) {
1228 if (!soc_is_rk2928g()) {
1229 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1230 if (reg_check_rmvb_wmv(reg)) {
1231 reg->freq = VPU_FREQ_200M;
1232 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1233 if (reg_probe_width(reg) > 3200) {
1234 /*raise frequency for 4k avc.*/
1235 reg->freq = VPU_FREQ_500M;
1238 if (reg_check_interlace(reg)) {
1239 reg->freq = VPU_FREQ_400M;
1243 if (reg->type == VPU_PP) {
1244 reg->freq = VPU_FREQ_400M;
1252 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1254 struct vpu_service_info *pservice = data->pservice;
1255 #if defined(CONFIG_VCODEC_MMU)
1256 struct vcodec_mem_region *mem_region = NULL, *n;
1259 list_del_init(®->session_link);
1260 list_del_init(®->status_link);
1261 if (reg == pservice->reg_codec)
1262 pservice->reg_codec = NULL;
1263 if (reg == pservice->reg_pproc)
1264 pservice->reg_pproc = NULL;
1266 #if defined(CONFIG_VCODEC_MMU)
1267 /* release memory region attach to this registers table. */
1268 if (data->mmu_dev) {
1269 list_for_each_entry_safe(mem_region, n,
1270 ®->mem_region_list, reg_lnk) {
1271 /* do not unmap iommu manually,
1272 unmap will proccess when memory release */
1273 /*vcodec_enter_mode(data);
1274 ion_unmap_iommu(data->dev,
1275 pservice->ion_client,
1277 vcodec_exit_mode();*/
1278 ion_free(pservice->ion_client, mem_region->hdl);
1279 list_del_init(&mem_region->reg_lnk);
1288 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1291 list_del_init(®->status_link);
1292 list_add_tail(®->status_link, &pservice->running);
1294 list_del_init(®->session_link);
1295 list_add_tail(®->session_link, ®->session->running);
1299 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1302 u32 *dst = (u32 *)®->reg[0];
1304 for (i = 0; i < count; i++)
1309 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1312 struct vpu_service_info *pservice = data->pservice;
1317 list_del_init(®->status_link);
1318 list_add_tail(®->status_link, &pservice->done);
1320 list_del_init(®->session_link);
1321 list_add_tail(®->session_link, ®->session->done);
1323 /*vcodec_enter_mode(data);*/
1324 switch (reg->type) {
1326 pservice->reg_codec = NULL;
1327 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1328 irq_reg = ENC_INTERRUPT_REGISTER;
1332 int reg_len = REG_NUM_9190_DEC;
1333 pservice->reg_codec = NULL;
1334 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1335 irq_reg = DEC_INTERRUPT_REGISTER;
1339 pservice->reg_pproc = NULL;
1340 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1341 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1345 pservice->reg_codec = NULL;
1346 pservice->reg_pproc = NULL;
1347 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1348 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1352 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1356 vcodec_exit_mode(data);
1359 reg->reg[irq_reg] = pservice->irq_status;
1361 atomic_sub(1, ®->session->task_running);
1362 atomic_sub(1, &pservice->total_running);
1363 wake_up(®->session->wait);
1368 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1370 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1371 if (curr == reg->freq)
1373 atomic_set(&pservice->freq_status, reg->freq);
1374 switch (reg->freq) {
1375 case VPU_FREQ_200M : {
1376 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1378 case VPU_FREQ_266M : {
1379 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1381 case VPU_FREQ_300M : {
1382 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1384 case VPU_FREQ_400M : {
1385 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1387 case VPU_FREQ_500M : {
1388 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1390 case VPU_FREQ_600M : {
1391 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1394 if (soc_is_rk2928g())
1395 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1397 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1402 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1404 struct vpu_service_info *pservice = data->pservice;
1406 u32 *src = (u32 *)®->reg[0];
1409 atomic_add(1, &pservice->total_running);
1410 atomic_add(1, ®->session->task_running);
1411 if (pservice->auto_freq)
1412 vpu_service_set_freq(pservice, reg);
1414 vcodec_enter_mode(data);
1416 switch (reg->type) {
1418 int enc_count = data->hw_info->enc_reg_num;
1419 u32 *dst = (u32 *)data->enc_dev.hwregs;
1421 pservice->reg_codec = reg;
1423 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1425 for (i = 0; i < VPU_REG_EN_ENC; i++)
1428 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1431 VEPU_CLEAN_CACHE(dst);
1435 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1436 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1438 time_record(&tasks[TASK_VPU_ENC], 0);
1441 u32 *dst = (u32 *)data->dec_dev.hwregs;
1443 pservice->reg_codec = reg;
1445 if (data->hw_info->hw_id != HEVC_ID) {
1446 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1448 VDPU_CLEAN_CACHE(dst);
1450 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1452 HEVC_CLEAN_CACHE(dst);
1457 if (data->hw_info->hw_id != HEVC_ID) {
1458 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1459 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1461 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1466 time_record(&tasks[TASK_VPU_DEC], 0);
1469 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1470 pservice->reg_pproc = reg;
1472 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1474 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1479 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1481 time_record(&tasks[TASK_VPU_PP], 0);
1484 u32 *dst = (u32 *)data->dec_dev.hwregs;
1485 pservice->reg_codec = reg;
1486 pservice->reg_pproc = reg;
1488 VDPU_SOFT_RESET(dst);
1489 VDPU_CLEAN_CACHE(dst);
1491 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1494 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1497 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1498 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1499 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1501 time_record(&tasks[TASK_VPU_DEC], 0);
1504 vpu_err("error: unsupport session type %d", reg->type);
1505 atomic_sub(1, &pservice->total_running);
1506 atomic_sub(1, ®->session->task_running);
1510 /*vcodec_exit_mode(data);*/
1514 static void try_set_reg(struct vpu_subdev_data *data)
1516 struct vpu_service_info *pservice = data->pservice;
1518 if (!list_empty(&pservice->waiting)) {
1520 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1522 vpu_service_power_on(pservice);
1524 switch (reg->type) {
1526 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1530 if (NULL == pservice->reg_codec)
1532 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1536 if (NULL == pservice->reg_codec) {
1537 if (NULL == pservice->reg_pproc)
1540 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1542 /* can not charge frequency when vpu is working */
1543 if (pservice->auto_freq)
1548 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1552 printk("undefined reg type %d\n", reg->type);
1556 reg_from_wait_to_run(pservice, reg);
1557 reg_copy_to_hw(reg->data, reg);
1563 static int return_reg(struct vpu_subdev_data *data,
1564 vpu_reg *reg, u32 __user *dst)
1568 switch (reg->type) {
1570 if (copy_to_user(dst, ®->reg[0], data->hw_info->enc_io_size))
1575 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1576 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1581 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1586 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1592 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1596 reg_deinit(data, reg);
1601 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1604 struct vpu_subdev_data *data =
1605 container_of(filp->f_dentry->d_inode->i_cdev,
1606 struct vpu_subdev_data, cdev);
1607 struct vpu_service_info *pservice = data->pservice;
1608 vpu_session *session = (vpu_session *)filp->private_data;
1610 if (NULL == session)
1614 case VPU_IOC_SET_CLIENT_TYPE : {
1615 session->type = (enum VPU_CLIENT_TYPE)arg;
1616 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1619 case VPU_IOC_GET_HW_FUSE_STATUS : {
1620 struct vpu_request req;
1621 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1622 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1623 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1626 if (VPU_ENC != session->type) {
1627 if (copy_to_user((void __user *)req.req,
1628 &pservice->dec_config,
1629 sizeof(struct vpu_dec_config))) {
1630 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1635 if (copy_to_user((void __user *)req.req,
1636 &pservice->enc_config,
1637 sizeof(struct vpu_enc_config ))) {
1638 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1647 case VPU_IOC_SET_REG : {
1648 struct vpu_request req;
1650 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1651 if (copy_from_user(&req, (void __user *)arg,
1652 sizeof(struct vpu_request))) {
1653 vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1656 reg = reg_init(data, session,
1657 (void __user *)req.req, req.size);
1661 mutex_lock(&pservice->lock);
1663 mutex_unlock(&pservice->lock);
1668 case VPU_IOC_GET_REG : {
1669 struct vpu_request req;
1671 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1672 if (copy_from_user(&req, (void __user *)arg,
1673 sizeof(struct vpu_request))) {
1674 vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1677 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1678 if (!list_empty(&session->done)) {
1680 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1684 if (unlikely(ret < 0)) {
1685 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1686 } else if (0 == ret) {
1687 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1692 int task_running = atomic_read(&session->task_running);
1693 mutex_lock(&pservice->lock);
1694 vpu_service_dump(pservice);
1696 atomic_set(&session->task_running, 0);
1697 atomic_sub(task_running, &pservice->total_running);
1698 printk("%d task is running but not return, reset hardware...", task_running);
1702 vpu_service_session_clear(data, session);
1703 mutex_unlock(&pservice->lock);
1707 mutex_lock(&pservice->lock);
1708 reg = list_entry(session->done.next, vpu_reg, session_link);
1709 return_reg(data, reg, (u32 __user *)req.req);
1710 mutex_unlock(&pservice->lock);
1713 case VPU_IOC_PROBE_IOMMU_STATUS: {
1714 int iommu_enable = 0;
1716 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1718 #if defined(CONFIG_VCODEC_MMU)
1719 iommu_enable = data->mmu_dev ? 1 : 0;
1722 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1723 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1729 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1737 #ifdef CONFIG_COMPAT
1738 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1741 struct vpu_subdev_data *data =
1742 container_of(filp->f_dentry->d_inode->i_cdev,
1743 struct vpu_subdev_data, cdev);
1744 struct vpu_service_info *pservice = data->pservice;
1745 vpu_session *session = (vpu_session *)filp->private_data;
1747 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1748 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1749 if (NULL == session)
1753 case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1754 session->type = (enum VPU_CLIENT_TYPE)arg;
1755 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1758 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1759 struct compat_vpu_request req;
1760 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1761 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1762 sizeof(struct compat_vpu_request))) {
1763 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1764 " copy_from_user failed\n");
1767 if (VPU_ENC != session->type) {
1768 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1769 &pservice->dec_config,
1770 sizeof(struct vpu_dec_config))) {
1771 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1772 "copy_to_user failed type %d\n",
1777 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1778 &pservice->enc_config,
1779 sizeof(struct vpu_enc_config ))) {
1780 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1781 " copy_to_user failed type %d\n",
1790 case COMPAT_VPU_IOC_SET_REG : {
1791 struct compat_vpu_request req;
1793 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1794 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1795 sizeof(struct compat_vpu_request))) {
1796 vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1799 reg = reg_init(data, session,
1800 compat_ptr((compat_uptr_t)req.req), req.size);
1804 mutex_lock(&pservice->lock);
1806 mutex_unlock(&pservice->lock);
1811 case COMPAT_VPU_IOC_GET_REG : {
1812 struct compat_vpu_request req;
1814 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1815 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1816 sizeof(struct compat_vpu_request))) {
1817 vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1820 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1821 if (!list_empty(&session->done)) {
1823 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1827 if (unlikely(ret < 0)) {
1828 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1829 } else if (0 == ret) {
1830 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1835 int task_running = atomic_read(&session->task_running);
1836 mutex_lock(&pservice->lock);
1837 vpu_service_dump(pservice);
1839 atomic_set(&session->task_running, 0);
1840 atomic_sub(task_running, &pservice->total_running);
1841 printk("%d task is running but not return, reset hardware...", task_running);
1845 vpu_service_session_clear(data, session);
1846 mutex_unlock(&pservice->lock);
1850 mutex_lock(&pservice->lock);
1851 reg = list_entry(session->done.next, vpu_reg, session_link);
1852 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1853 mutex_unlock(&pservice->lock);
1856 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1857 int iommu_enable = 0;
1859 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1860 #if defined(CONFIG_VCODEC_MMU)
1861 iommu_enable = data->mmu_dev ? 1 : 0;
1864 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1865 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1871 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1880 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1882 int ret = -EINVAL, i = 0;
1883 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1886 enc_id = (enc_id >> 16) & 0xFFFF;
1887 pr_info("checking hw id %x\n", enc_id);
1888 data->hw_info = NULL;
1889 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1890 if (enc_id == vpu_hw_set[i].hw_id) {
1891 data->hw_info = &vpu_hw_set[i];
1896 iounmap((void *)tmp);
1900 static int vpu_service_open(struct inode *inode, struct file *filp)
1902 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1903 struct vpu_service_info *pservice = data->pservice;
1904 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1908 if (NULL == session) {
1909 vpu_err("error: unable to allocate memory for vpu_session.");
1913 session->type = VPU_TYPE_BUTT;
1914 session->pid = current->pid;
1915 INIT_LIST_HEAD(&session->waiting);
1916 INIT_LIST_HEAD(&session->running);
1917 INIT_LIST_HEAD(&session->done);
1918 INIT_LIST_HEAD(&session->list_session);
1919 init_waitqueue_head(&session->wait);
1920 atomic_set(&session->task_running, 0);
1921 mutex_lock(&pservice->lock);
1922 list_add_tail(&session->list_session, &pservice->session);
1923 filp->private_data = (void *)session;
1924 mutex_unlock(&pservice->lock);
1926 pr_debug("dev opened\n");
1928 return nonseekable_open(inode, filp);
1931 static int vpu_service_release(struct inode *inode, struct file *filp)
1933 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1934 struct vpu_service_info *pservice = data->pservice;
1936 vpu_session *session = (vpu_session *)filp->private_data;
1938 if (NULL == session)
1941 task_running = atomic_read(&session->task_running);
1943 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1946 wake_up(&session->wait);
1948 mutex_lock(&pservice->lock);
1949 /* remove this filp from the asynchronusly notified filp's */
1950 list_del_init(&session->list_session);
1951 vpu_service_session_clear(data, session);
1953 filp->private_data = NULL;
1954 mutex_unlock(&pservice->lock);
1956 pr_debug("dev closed\n");
1961 static const struct file_operations vpu_service_fops = {
1962 .unlocked_ioctl = vpu_service_ioctl,
1963 .open = vpu_service_open,
1964 .release = vpu_service_release,
1965 #ifdef CONFIG_COMPAT
1966 .compat_ioctl = compat_vpu_service_ioctl,
1970 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1971 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1972 static irqreturn_t vepu_irq(int irq, void *dev_id);
1973 static irqreturn_t vepu_isr(int irq, void *dev_id);
1974 static void get_hw_info(struct vpu_subdev_data *data);
1976 #ifdef CONFIG_VCODEC_MMU
1977 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1979 struct device_node *dn = NULL;
1980 struct platform_device *pd = NULL;
1981 struct device *ret = NULL ;
1983 dn = of_find_compatible_node(NULL,NULL,compt);
1985 printk("can't find device node %s \r\n",compt);
1989 pd = of_find_device_by_node(dn);
1991 printk("can't find platform device in device node %s\n",compt);
1999 #ifdef CONFIG_IOMMU_API
2000 static inline void platform_set_sysmmu(struct device *iommu,
2003 dev->archdata.iommu = iommu;
2006 static inline void platform_set_sysmmu(struct device *iommu,
2012 int vcodec_sysmmu_fault_hdl(struct device *dev,
2013 enum rk_iommu_inttype itype,
2014 unsigned long pgtable_base,
2015 unsigned long fault_addr, unsigned int status)
2017 struct platform_device *pdev;
2018 struct vpu_subdev_data *data;
2019 struct vpu_service_info *pservice;
2023 pdev = container_of(dev, struct platform_device, dev);
2025 data = platform_get_drvdata(pdev);
2026 pservice = data->pservice;
2028 if (pservice->reg_codec) {
2029 struct vcodec_mem_region *mem, *n;
2031 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2032 list_for_each_entry_safe(mem, n,
2033 &pservice->reg_codec->mem_region_list,
2035 vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2036 mem->reg_idx, i, (u32)mem->iova, mem->len);
2040 pr_alert("vcodec, page fault occur, reset hw\n");
2041 pservice->reg_codec->reg[101] = 1;
2049 #if HEVC_TEST_ENABLE
2050 static int hevc_test_case0(vpu_service_info *pservice);
2052 #if defined(CONFIG_ION_ROCKCHIP)
2053 extern struct ion_client *rockchip_ion_client_create(const char * name);
2056 static int vcodec_subdev_probe(struct platform_device *pdev,
2057 struct vpu_service_info *pservice)
2060 struct resource *res = NULL;
2062 struct device *dev = &pdev->dev;
2063 char *name = (char*)dev_name(dev);
2064 struct device_node *np = pdev->dev.of_node;
2065 struct vpu_subdev_data *data =
2066 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2067 #if defined(CONFIG_VCODEC_MMU)
2069 char mmu_dev_dts_name[40];
2070 of_property_read_u32(np, "iommu_enabled", &iommu_en);
2072 pr_info("probe device %s\n", dev_name(dev));
2074 data->pservice = pservice;
2077 of_property_read_string(np, "name", (const char**)&name);
2078 of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2079 /*dev_set_name(dev, name);*/
2081 if (pservice->reg_base == 0) {
2082 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2083 data->regs = devm_ioremap_resource(dev, res);
2084 if (IS_ERR(data->regs)) {
2085 ret = PTR_ERR(data->regs);
2088 ioaddr = res->start;
2090 data->regs = pservice->reg_base;
2091 ioaddr = pservice->ioaddr;
2094 clear_bit(MMU_ACTIVATED, &data->state);
2095 vcodec_enter_mode(data);
2096 ret = vpu_service_check_hw(data, ioaddr);
2098 vpu_err("error: hw info check faild\n");
2102 data->dec_dev.iosize = data->hw_info->dec_io_size;
2103 data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2104 data->reg_size = data->dec_dev.iosize;
2106 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2107 data->enc_dev.iosize = data->hw_info->enc_io_size;
2108 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2109 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2112 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2113 if (data->irq_enc > 0) {
2114 ret = devm_request_threaded_irq(dev,
2115 data->irq_enc, vepu_irq, vepu_isr,
2116 IRQF_SHARED, dev_name(dev),
2120 "error: can't request vepu irq %d\n",
2125 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2126 if (data->irq_dec > 0) {
2127 ret = devm_request_threaded_irq(dev,
2128 data->irq_dec, vdpu_irq, vdpu_isr,
2129 IRQF_SHARED, dev_name(dev),
2133 "error: can't request vdpu irq %d\n",
2138 atomic_set(&data->dec_dev.irq_count_codec, 0);
2139 atomic_set(&data->dec_dev.irq_count_pp, 0);
2140 atomic_set(&data->enc_dev.irq_count_codec, 0);
2141 atomic_set(&data->enc_dev.irq_count_pp, 0);
2142 #if defined(CONFIG_VCODEC_MMU)
2144 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2145 sprintf(mmu_dev_dts_name,
2146 HEVC_IOMMU_COMPATIBLE_NAME);
2148 sprintf(mmu_dev_dts_name,
2149 VPU_IOMMU_COMPATIBLE_NAME);
2152 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2155 platform_set_sysmmu(data->mmu_dev, dev);
2157 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2160 vcodec_exit_mode(data);
2161 /* create device node */
2162 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2164 dev_err(dev, "alloc dev_t failed\n");
2168 cdev_init(&data->cdev, &vpu_service_fops);
2170 data->cdev.owner = THIS_MODULE;
2171 data->cdev.ops = &vpu_service_fops;
2173 ret = cdev_add(&data->cdev, data->dev_t, 1);
2176 dev_err(dev, "add dev_t failed\n");
2180 data->cls = class_create(THIS_MODULE, name);
2182 if (IS_ERR(data->cls)) {
2183 ret = PTR_ERR(data->cls);
2184 dev_err(dev, "class_create err:%d\n", ret);
2188 data->child_dev = device_create(data->cls, dev,
2189 data->dev_t, NULL, name);
2193 platform_set_drvdata(pdev, data);
2195 INIT_LIST_HEAD(&data->lnk_service);
2196 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2198 #ifdef CONFIG_DEBUG_FS
2200 vcodec_debugfs_create_device_dir((char*)name, parent);
2201 if (data->debugfs_dir == NULL)
2202 vpu_err("create debugfs dir %s failed\n", name);
2204 data->debugfs_file_regs =
2205 debugfs_create_file("regs", 0664,
2206 data->debugfs_dir, data,
2207 &debug_vcodec_fops);
2211 if (data->irq_enc > 0)
2212 free_irq(data->irq_enc, (void *)data);
2213 if (data->irq_dec > 0)
2214 free_irq(data->irq_dec, (void *)data);
2216 if (data->child_dev) {
2217 device_destroy(data->cls, data->dev_t);
2218 cdev_del(&data->cdev);
2219 unregister_chrdev_region(data->dev_t, 1);
2223 class_destroy(data->cls);
2227 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2229 device_destroy(data->cls, data->dev_t);
2230 class_destroy(data->cls);
2231 cdev_del(&data->cdev);
2232 unregister_chrdev_region(data->dev_t, 1);
2234 free_irq(data->irq_enc, (void *)&data);
2235 free_irq(data->irq_dec, (void *)&data);
2237 #ifdef CONFIG_DEBUG_FS
2238 debugfs_remove(data->debugfs_file_regs);
2239 debugfs_remove(data->debugfs_dir);
2243 static void vcodec_read_property(struct device_node *np,
2244 struct vpu_service_info *pservice)
2246 pservice->mode_bit = 0;
2247 pservice->mode_ctrl = 0;
2248 pservice->subcnt = 0;
2250 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2252 if (pservice->subcnt > 1) {
2253 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2254 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2256 #ifdef CONFIG_MFD_SYSCON
2257 pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2259 pservice->grf_base = (u32*)RK_GRF_VIRT;
2261 if (IS_ERR(pservice->grf_base)) {
2263 pservice->grf_base = RK_GRF_VIRT;
2265 vpu_err("can't find vpu grf property\n");
2269 of_property_read_string(np, "name", (const char**)&pservice->name);
2272 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2274 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2275 pservice->curr_mode = -1;
2277 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2278 INIT_LIST_HEAD(&pservice->waiting);
2279 INIT_LIST_HEAD(&pservice->running);
2280 mutex_init(&pservice->lock);
2282 INIT_LIST_HEAD(&pservice->done);
2283 INIT_LIST_HEAD(&pservice->session);
2284 INIT_LIST_HEAD(&pservice->subdev_list);
2286 pservice->reg_pproc = NULL;
2287 atomic_set(&pservice->total_running, 0);
2288 atomic_set(&pservice->enabled, 0);
2289 atomic_set(&pservice->power_on_cnt, 0);
2290 atomic_set(&pservice->power_off_cnt, 0);
2292 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2294 pservice->ion_client = rockchip_ion_client_create("vpu");
2295 if (IS_ERR(pservice->ion_client)) {
2296 vpu_err("failed to create ion client for vcodec ret %ld\n",
2297 PTR_ERR(pservice->ion_client));
2299 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2303 static int vcodec_probe(struct platform_device *pdev)
2307 struct resource *res = NULL;
2308 struct device *dev = &pdev->dev;
2309 struct device_node *np = pdev->dev.of_node;
2310 struct vpu_service_info *pservice =
2311 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2313 pr_info("probe device %s\n", dev_name(dev));
2315 vcodec_read_property(np, pservice);
2316 vcodec_init_drvdata(pservice);
2318 if (strncmp(pservice->name, "hevc_service", 12) == 0)
2319 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2320 else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2321 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2323 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2325 pservice->dev = dev;
2327 if (0 > vpu_get_clk(pservice))
2330 vpu_service_power_on(pservice);
2332 if (of_property_read_bool(np, "reg")) {
2333 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2335 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2336 if (IS_ERR(pservice->reg_base)) {
2337 vpu_err("ioremap registers base failed\n");
2338 ret = PTR_ERR(pservice->reg_base);
2341 pservice->ioaddr = res->start;
2343 pservice->reg_base = 0;
2346 if (of_property_read_bool(np, "subcnt")) {
2347 for (i = 0; i<pservice->subcnt; i++) {
2348 struct device_node *sub_np;
2349 struct platform_device *sub_pdev;
2350 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2351 sub_pdev = of_find_device_by_node(sub_np);
2353 vcodec_subdev_probe(sub_pdev, pservice);
2356 vcodec_subdev_probe(pdev, pservice);
2358 platform_set_drvdata(pdev, pservice);
2360 vpu_service_power_off(pservice);
2362 pr_info("init success\n");
2367 pr_info("init failed\n");
2368 vpu_service_power_off(pservice);
2369 vpu_put_clk(pservice);
2370 wake_lock_destroy(&pservice->wake_lock);
2373 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2378 static int vcodec_remove(struct platform_device *pdev)
2380 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2381 struct resource *res;
2382 struct vpu_subdev_data *data, *n;
2384 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2385 vcodec_subdev_remove(data);
2388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2389 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2390 vpu_put_clk(pservice);
2391 wake_lock_destroy(&pservice->wake_lock);
2396 #if defined(CONFIG_OF)
2397 static const struct of_device_id vcodec_service_dt_ids[] = {
2398 {.compatible = "vpu_service",},
2399 {.compatible = "rockchip,hevc_service",},
2400 {.compatible = "rockchip,vpu_combo",},
2405 static struct platform_driver vcodec_driver = {
2406 .probe = vcodec_probe,
2407 .remove = vcodec_remove,
2410 .owner = THIS_MODULE,
2411 #if defined(CONFIG_OF)
2412 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2417 static void get_hw_info(struct vpu_subdev_data *data)
2419 struct vpu_service_info *pservice = data->pservice;
2420 struct vpu_dec_config *dec = &pservice->dec_config;
2421 struct vpu_enc_config *enc = &pservice->enc_config;
2422 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2423 u32 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2424 u32 asicID = data->dec_dev.hwregs[0];
2426 dec->h264_support = (configReg >> DWL_H264_E) & 0x3U;
2427 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2428 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2429 dec->jpegSupport = JPEG_PROGRESSIVE;
2430 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2431 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2432 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2433 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2434 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2435 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2437 dec->maxDecPicWidth = 4096;
2439 /* 2nd Config register */
2440 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2441 if (dec->refBufSupport) {
2442 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2443 dec->refBufSupport |= 2;
2444 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2445 dec->refBufSupport |= 4;
2447 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2448 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2449 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2450 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2452 /* JPEG xtensions */
2453 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2454 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2456 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2458 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2459 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2461 dec->rvSupport = RV_NOT_SUPPORTED;
2462 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2464 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2465 dec->refBufSupport |= 8; /* enable HW support for offset */
2467 if (!cpu_is_rk3036()) {
2468 configReg = data->enc_dev.hwregs[63];
2469 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2470 enc->h264Enabled = (configReg >> 27) & 1;
2471 enc->mpeg4Enabled = (configReg >> 26) & 1;
2472 enc->jpegEnabled = (configReg >> 25) & 1;
2473 enc->vsEnabled = (configReg >> 24) & 1;
2474 enc->rgbEnabled = (configReg >> 28) & 1;
2475 enc->reg_size = data->reg_size;
2476 enc->reserv[0] = enc->reserv[1] = 0;
2478 pservice->auto_freq = true;
2479 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2480 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2482 pservice->bug_dec_addr = cpu_is_rk30xx();
2484 if (cpu_is_rk3036() || cpu_is_rk312x())
2485 dec->maxDecPicWidth = 1920;
2487 dec->maxDecPicWidth = 4096;
2488 /* disable frequency switch in hevc.*/
2489 pservice->auto_freq = false;
2493 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2495 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2496 struct vpu_service_info *pservice = data->pservice;
2497 vpu_device *dev = &data->dec_dev;
2501 /*vcodec_enter_mode(data);*/
2503 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2505 if (irq_status & DEC_INTERRUPT_BIT) {
2506 time_record(&tasks[TASK_VPU_DEC], 1);
2507 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", irq_status);
2508 if ((irq_status & 0x40001) == 0x40001) {
2512 DEC_INTERRUPT_REGISTER);
2513 } while ((irq_status & 0x40001) == 0x40001);
2516 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2517 atomic_add(1, &dev->irq_count_codec);
2518 time_diff(&tasks[TASK_VPU_DEC]);
2521 if (data->hw_info->hw_id != HEVC_ID) {
2522 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2523 if (irq_status & PP_INTERRUPT_BIT) {
2524 time_record(&tasks[TASK_VPU_PP], 1);
2525 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", irq_status);
2527 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2528 atomic_add(1, &dev->irq_count_pp);
2529 time_diff(&tasks[TASK_VPU_PP]);
2533 pservice->irq_status = raw_status;
2535 /*vcodec_exit_mode(pservice);*/
2537 if (atomic_read(&dev->irq_count_pp) ||
2538 atomic_read(&dev->irq_count_codec))
2539 return IRQ_WAKE_THREAD;
2544 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2546 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2547 struct vpu_service_info *pservice = data->pservice;
2548 vpu_device *dev = &data->dec_dev;
2550 mutex_lock(&pservice->lock);
2551 if (atomic_read(&dev->irq_count_codec)) {
2552 atomic_sub(1, &dev->irq_count_codec);
2553 if (NULL == pservice->reg_codec) {
2554 vpu_err("error: dec isr with no task waiting\n");
2556 reg_from_run_to_done(data, pservice->reg_codec);
2557 /* avoid vpu timeout and can't recover problem */
2558 VDPU_SOFT_RESET(data->regs);
2562 if (atomic_read(&dev->irq_count_pp)) {
2563 atomic_sub(1, &dev->irq_count_pp);
2564 if (NULL == pservice->reg_pproc) {
2565 vpu_err("error: pp isr with no task waiting\n");
2567 reg_from_run_to_done(data, pservice->reg_pproc);
2571 mutex_unlock(&pservice->lock);
2575 static irqreturn_t vepu_irq(int irq, void *dev_id)
2577 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2578 struct vpu_service_info *pservice = data->pservice;
2579 vpu_device *dev = &data->enc_dev;
2582 /*vcodec_enter_mode(data);*/
2583 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2585 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2587 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2588 time_record(&tasks[TASK_VPU_ENC], 1);
2590 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2591 atomic_add(1, &dev->irq_count_codec);
2592 time_diff(&tasks[TASK_VPU_ENC]);
2595 pservice->irq_status = irq_status;
2597 /*vcodec_exit_mode(pservice);*/
2599 if (atomic_read(&dev->irq_count_codec))
2600 return IRQ_WAKE_THREAD;
2605 static irqreturn_t vepu_isr(int irq, void *dev_id)
2607 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2608 struct vpu_service_info *pservice = data->pservice;
2609 vpu_device *dev = &data->enc_dev;
2611 mutex_lock(&pservice->lock);
2612 if (atomic_read(&dev->irq_count_codec)) {
2613 atomic_sub(1, &dev->irq_count_codec);
2614 if (NULL == pservice->reg_codec) {
2615 vpu_err("error: enc isr with no task waiting\n");
2617 reg_from_run_to_done(data, pservice->reg_codec);
2621 mutex_unlock(&pservice->lock);
2625 static int __init vcodec_service_init(void)
2629 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2630 vpu_err("Platform device register failed (%d).\n", ret);
2634 #ifdef CONFIG_DEBUG_FS
2635 vcodec_debugfs_init();
2641 static void __exit vcodec_service_exit(void)
2643 #ifdef CONFIG_DEBUG_FS
2644 vcodec_debugfs_exit();
2647 platform_driver_unregister(&vcodec_driver);
2650 module_init(vcodec_service_init);
2651 module_exit(vcodec_service_exit);
2653 #ifdef CONFIG_DEBUG_FS
2654 #include <linux/seq_file.h>
2656 static int vcodec_debugfs_init()
2658 parent = debugfs_create_dir("vcodec", NULL);
2665 static void vcodec_debugfs_exit()
2667 debugfs_remove(parent);
2670 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2672 return debugfs_create_dir(dirname, parent);
2675 static int debug_vcodec_show(struct seq_file *s, void *unused)
2677 struct vpu_subdev_data *data = s->private;
2678 struct vpu_service_info *pservice = data->pservice;
2680 vpu_reg *reg, *reg_tmp;
2681 vpu_session *session, *session_tmp;
2683 mutex_lock(&pservice->lock);
2684 vpu_service_power_on(pservice);
2685 if (data->hw_info->hw_id != HEVC_ID) {
2686 seq_printf(s, "\nENC Registers:\n");
2687 n = data->enc_dev.iosize >> 2;
2688 for (i = 0; i < n; i++)
2689 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2691 seq_printf(s, "\nDEC Registers:\n");
2692 n = data->dec_dev.iosize >> 2;
2693 for (i = 0; i < n; i++)
2694 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2696 seq_printf(s, "\nvpu service status:\n");
2697 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2698 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2699 /*seq_printf(s, "waiting reg set %d\n");*/
2700 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2701 seq_printf(s, "waiting register set\n");
2703 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2704 seq_printf(s, "running register set\n");
2706 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2707 seq_printf(s, "done register set\n");
2711 seq_printf(s, "\npower counter: on %d off %d\n",
2712 atomic_read(&pservice->power_on_cnt),
2713 atomic_read(&pservice->power_off_cnt));
2714 mutex_unlock(&pservice->lock);
2715 vpu_service_power_off(pservice);
2720 static int debug_vcodec_open(struct inode *inode, struct file *file)
2722 return single_open(file, debug_vcodec_show, inode->i_private);
2727 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2728 #include "hevc_test_inc/pps_00.h"
2729 #include "hevc_test_inc/register_00.h"
2730 #include "hevc_test_inc/rps_00.h"
2731 #include "hevc_test_inc/scaling_list_00.h"
2732 #include "hevc_test_inc/stream_00.h"
2734 #include "hevc_test_inc/pps_01.h"
2735 #include "hevc_test_inc/register_01.h"
2736 #include "hevc_test_inc/rps_01.h"
2737 #include "hevc_test_inc/scaling_list_01.h"
2738 #include "hevc_test_inc/stream_01.h"
2740 #include "hevc_test_inc/cabac.h"
2742 extern struct ion_client *rockchip_ion_client_create(const char * name);
2744 static struct ion_client *ion_client = NULL;
2745 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2747 int size = (len+15) & (~15);
2748 struct ion_handle *handle;
2751 if (ion_client == NULL)
2752 ion_client = rockchip_ion_client_create("vcodec");
2754 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2756 ptr = ion_map_kernel(ion_client, handle);
2758 ion_phys(ion_client, handle, phy, &size);
2760 memcpy(ptr, tbl, len);
2765 u8* get_align_ptr_no_copy(int len, u32 *phy)
2767 int size = (len+15) & (~15);
2768 struct ion_handle *handle;
2771 if (ion_client == NULL)
2772 ion_client = rockchip_ion_client_create("vcodec");
2774 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2776 ptr = ion_map_kernel(ion_client, handle);
2778 ion_phys(ion_client, handle, phy, &size);
2784 static int hevc_test_case0(vpu_service_info *pservice)
2786 vpu_session session;
2788 unsigned long size = 272;
2791 u8 *pps_tbl[TEST_CNT];
2792 u8 *register_tbl[TEST_CNT];
2793 u8 *rps_tbl[TEST_CNT];
2794 u8 *scaling_list_tbl[TEST_CNT];
2795 u8 *stream_tbl[TEST_CNT];
2811 volatile u8 *stream_buf;
2812 volatile u8 *pps_buf;
2813 volatile u8 *rps_buf;
2814 volatile u8 *scl_buf;
2815 volatile u8 *yuv_buf;
2816 volatile u8 *cabac_buf;
2817 volatile u8 *ref_buf;
2823 pps_tbl[0] = pps_00;
2824 pps_tbl[1] = pps_01;
2826 register_tbl[0] = register_00;
2827 register_tbl[1] = register_01;
2829 rps_tbl[0] = rps_00;
2830 rps_tbl[1] = rps_01;
2832 scaling_list_tbl[0] = scaling_list_00;
2833 scaling_list_tbl[1] = scaling_list_01;
2835 stream_tbl[0] = stream_00;
2836 stream_tbl[1] = stream_01;
2838 stream_size[0] = sizeof(stream_00);
2839 stream_size[1] = sizeof(stream_01);
2841 pps_size[0] = sizeof(pps_00);
2842 pps_size[1] = sizeof(pps_01);
2844 rps_size[0] = sizeof(rps_00);
2845 rps_size[1] = sizeof(rps_01);
2847 scl_size[0] = sizeof(scaling_list_00);
2848 scl_size[1] = sizeof(scaling_list_01);
2850 cabac_size[0] = sizeof(Cabac_table);
2851 cabac_size[1] = sizeof(Cabac_table);
2853 /* create session */
2854 session.pid = current->pid;
2855 session.type = VPU_DEC;
2856 INIT_LIST_HEAD(&session.waiting);
2857 INIT_LIST_HEAD(&session.running);
2858 INIT_LIST_HEAD(&session.done);
2859 INIT_LIST_HEAD(&session.list_session);
2860 init_waitqueue_head(&session.wait);
2861 atomic_set(&session.task_running, 0);
2862 list_add_tail(&session.list_session, &pservice->session);
2864 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2865 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2867 while (testidx < TEST_CNT) {
2868 /* create registers */
2869 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2871 vpu_err("error: kmalloc fail in reg_init\n");
2875 if (size > pservice->reg_size) {
2876 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2877 size = pservice->reg_size;
2879 reg->session = &session;
2880 reg->type = session.type;
2882 reg->freq = VPU_FREQ_DEFAULT;
2883 reg->reg = (unsigned long *)®[1];
2884 INIT_LIST_HEAD(®->session_link);
2885 INIT_LIST_HEAD(®->status_link);
2887 /* TODO: stuff registers */
2888 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2890 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2891 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2892 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2893 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2894 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2898 /* TODO: replace reigster address */
2899 for (i=0; i<64; i++) {
2903 scaling_offset = (u32)pps[i*80+74];
2904 scaling_offset += (u32)pps[i*80+75] << 8;
2905 scaling_offset += (u32)pps[i*80+76] << 16;
2906 scaling_offset += (u32)pps[i*80+77] << 24;
2908 tmp = phy_scl + scaling_offset;
2910 pps[i*80+74] = tmp & 0xff;
2911 pps[i*80+75] = (tmp >> 8) & 0xff;
2912 pps[i*80+76] = (tmp >> 16) & 0xff;
2913 pps[i*80+77] = (tmp >> 24) & 0xff;
2916 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2917 __func__, __LINE__, phy_str, phy_pps, phy_rps);
2920 reg->reg[4] = phy_str;
2921 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2922 reg->reg[6] = phy_cabac;
2923 reg->reg[7] = testidx?phy_ref:phy_yuv;
2924 reg->reg[42] = phy_pps;
2925 reg->reg[43] = phy_rps;
2926 for (i = 10; i <= 24; i++)
2927 reg->reg[i] = phy_yuv;
2929 mutex_lock(pservice->lock);
2930 list_add_tail(®->status_link, &pservice->waiting);
2931 list_add_tail(®->session_link, &session.waiting);
2932 mutex_unlock(pservice->lock);
2934 /* stuff hardware */
2937 /* wait for result */
2938 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2939 if (!list_empty(&session.done)) {
2941 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2944 if (unlikely(ret < 0)) {
2945 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2946 } else if (0 == ret) {
2947 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2952 int task_running = atomic_read(&session.task_running);
2954 mutex_lock(pservice->lock);
2955 vpu_service_dump(pservice);
2957 atomic_set(&session.task_running, 0);
2958 atomic_sub(task_running, &pservice->total_running);
2959 printk("%d task is running but not return, reset hardware...", task_running);
2963 vpu_service_session_clear(pservice, &session);
2964 mutex_unlock(pservice->lock);
2966 printk("\nDEC Registers:\n");
2967 n = data->dec_dev.iosize >> 2;
2969 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2971 vpu_err("test index %d failed\n", testidx);
2974 vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
2976 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2978 for (i=0; i<68; i++) {
2980 printk("%02d: ", i);
2981 printk("%08x ", reg->reg[i]);
2989 reg_deinit(data, reg);