arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #ifdef CONFIG_DEBUG_FS\r
  43 #include <linux/debugfs.h>\r
  44 #endif\r
  45 \r
  46 #if defined(CONFIG_ARCH_RK319X)\r
  47 #include <mach/grf.h>\r
  48 #endif\r
  49 \r
  50 #include "vcodec_service.h"\r
  51 \r
  52 #define HEVC_TEST_ENABLE    0\r
  53 #define HEVC_SIM_ENABLE         0\r
  54 \r
  55 typedef enum {\r
  56         VPU_DEC_ID_9190         = 0x6731,\r
  57         VPU_ID_8270             = 0x8270,\r
  58         VPU_ID_4831             = 0x4831,\r
  59     HEVC_ID         = 0x6867,\r
  60 } VPU_HW_ID;\r
  61 \r
  62 typedef enum {\r
  63         VPU_DEC_TYPE_9190       = 0,\r
  64         VPU_ENC_TYPE_8270       = 0x100,\r
  65         VPU_ENC_TYPE_4831       ,\r
  66 } VPU_HW_TYPE_E;\r
  67 \r
  68 typedef enum VPU_FREQ {\r
  69         VPU_FREQ_200M,\r
  70         VPU_FREQ_266M,\r
  71         VPU_FREQ_300M,\r
  72         VPU_FREQ_400M,\r
  73         VPU_FREQ_DEFAULT,\r
  74         VPU_FREQ_BUT,\r
  75 } VPU_FREQ;\r
  76 \r
  77 typedef struct {\r
  78         VPU_HW_ID               hw_id;\r
  79         unsigned long           hw_addr;\r
  80         unsigned long           enc_offset;\r
  81         unsigned long           enc_reg_num;\r
  82         unsigned long           enc_io_size;\r
  83         unsigned long           dec_offset;\r
  84         unsigned long           dec_reg_num;\r
  85         unsigned long           dec_io_size;\r
  86 } VPU_HW_INFO_E;\r
  87 \r
  88 #define VPU_SERVICE_SHOW_TIME                   0\r
  89 \r
  90 #if VPU_SERVICE_SHOW_TIME\r
  91 static struct timeval enc_start, enc_end;\r
  92 static struct timeval dec_start, dec_end;\r
  93 static struct timeval pp_start,  pp_end;\r
  94 #endif\r
  95 \r
  96 #define MHZ                                     (1000*1000)\r
  97 \r
  98 #if 0\r
  99 #if defined(CONFIG_ARCH_RK319X)\r
 100 #define VCODEC_PHYS             RK319X_VCODEC_PHYS\r
 101 #else\r
 102 #define VCODEC_PHYS                             (0x10104000)\r
 103 #endif\r
 104 #endif\r
 105 \r
 106 #define REG_NUM_9190_DEC                        (60)\r
 107 #define REG_NUM_9190_PP                         (41)\r
 108 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 109 \r
 110 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 111 \r
 112 #define REG_NUM_ENC_8270                        (96)\r
 113 #define REG_SIZE_ENC_8270                       (0x200)\r
 114 #define REG_NUM_ENC_4831                        (164)\r
 115 #define REG_SIZE_ENC_4831                       (0x400)\r
 116 \r
 117 #define REG_NUM_HEVC_DEC            (68)\r
 118 \r
 119 #define SIZE_REG(reg)                           ((reg)*4)\r
 120 \r
 121 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 122         [0] = {\r
 123                 .hw_id          = VPU_ID_8270,\r
 124                 .hw_addr        = 0,\r
 125                 .enc_offset     = 0x0,\r
 126                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 127                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 128                 .dec_offset     = REG_SIZE_ENC_8270,\r
 129                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 130                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 131         },\r
 132         [1] = {\r
 133                 .hw_id          = VPU_ID_4831,\r
 134                 .hw_addr        = 0,\r
 135                 .enc_offset     = 0x0,\r
 136                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 137                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 138                 .dec_offset     = REG_SIZE_ENC_4831,\r
 139                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 140                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 141         },\r
 142     [2] = {\r
 143         .hw_id      = HEVC_ID,\r
 144         .hw_addr    = 0,\r
 145         .dec_offset = 0x0,\r
 146         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 147         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 148     },\r
 149 };\r
 150 \r
 151 \r
 152 #define DEC_INTERRUPT_REGISTER                  1\r
 153 #define PP_INTERRUPT_REGISTER                   60\r
 154 #define ENC_INTERRUPT_REGISTER                  1\r
 155 \r
 156 #define DEC_INTERRUPT_BIT                       0x100\r
 157 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 158 #define PP_INTERRUPT_BIT                        0x100\r
 159 #define ENC_INTERRUPT_BIT                       0x1\r
 160 \r
 161 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 162 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 163 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 164 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 165 \r
 166 #define VPU_REG_EN_ENC                          14\r
 167 #define VPU_REG_ENC_GATE                        2\r
 168 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 169 \r
 170 #define VPU_REG_EN_DEC                          1\r
 171 #define VPU_REG_DEC_GATE                        2\r
 172 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 173 #define VPU_REG_EN_PP                           0\r
 174 #define VPU_REG_PP_GATE                         1\r
 175 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 176 #define VPU_REG_EN_DEC_PP                       1\r
 177 #define VPU_REG_DEC_PP_GATE                     61\r
 178 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 179 \r
 180 /**\r
 181  * struct for process session which connect to vpu\r
 182  *\r
 183  * @author ChenHengming (2011-5-3)\r
 184  */\r
 185 typedef struct vpu_session {\r
 186         VPU_CLIENT_TYPE         type;\r
 187         /* a linked list of data so we can access them for debugging */\r
 188         struct list_head        list_session;\r
 189         /* a linked list of register data waiting for process */\r
 190         struct list_head        waiting;\r
 191         /* a linked list of register data in processing */\r
 192         struct list_head        running;\r
 193         /* a linked list of register data processed */\r
 194         struct list_head        done;\r
 195         wait_queue_head_t       wait;\r
 196         pid_t                   pid;\r
 197         atomic_t                task_running;\r
 198 } vpu_session;\r
 199 \r
 200 /**\r
 201  * struct for process register set\r
 202  *\r
 203  * @author ChenHengming (2011-5-4)\r
 204  */\r
 205 typedef struct vpu_reg {\r
 206         VPU_CLIENT_TYPE         type;\r
 207         VPU_FREQ                freq;\r
 208         vpu_session             *session;\r
 209         struct list_head        session_link;           /* link to vpu service session */\r
 210         struct list_head        status_link;            /* link to register set list */\r
 211         unsigned long           size;\r
 212         unsigned long           *reg;\r
 213 } vpu_reg;\r
 214 \r
 215 typedef struct vpu_device {\r
 216         atomic_t                irq_count_codec;\r
 217         atomic_t                irq_count_pp;\r
 218         unsigned long           iobaseaddr;\r
 219         unsigned int            iosize;\r
 220         volatile u32            *hwregs;\r
 221 } vpu_device;\r
 222 \r
 223 typedef struct vpu_service_info {\r
 224         struct wake_lock        wake_lock;\r
 225         struct delayed_work     power_off_work;\r
 226         struct mutex            lock;\r
 227         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 228         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 229         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 230         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 231         atomic_t                total_running;\r
 232         bool                    enabled;\r
 233         vpu_reg                 *reg_codec;\r
 234         vpu_reg                 *reg_pproc;\r
 235         vpu_reg                 *reg_resev;\r
 236         VPUHwDecConfig_t        dec_config;\r
 237         VPUHwEncConfig_t        enc_config;\r
 238         VPU_HW_INFO_E           *hw_info;\r
 239         unsigned long           reg_size;\r
 240         bool                    auto_freq;\r
 241         bool                    bug_dec_addr;\r
 242         atomic_t                freq_status;\r
 243 \r
 244     struct clk *aclk_vcodec;\r
 245     struct clk *hclk_vcodec;\r
 246 \r
 247     int irq_dec;\r
 248     int irq_enc;\r
 249 \r
 250     vpu_device enc_dev;\r
 251     vpu_device dec_dev;\r
 252 \r
 253     struct device   *dev;\r
 254 \r
 255     struct cdev     cdev;\r
 256     dev_t           dev_t;\r
 257     struct class    *cls;\r
 258     struct device   *child_dev;\r
 259 \r
 260     struct dentry   *debugfs_dir;\r
 261     struct dentry   *debugfs_file_regs;\r
 262 \r
 263     u32 irq_status;\r
 264 \r
 265     struct delayed_work simulate_work;\r
 266 } vpu_service_info;\r
 267 \r
 268 typedef struct vpu_request\r
 269 {\r
 270         unsigned long   *req;\r
 271         unsigned long   size;\r
 272 } vpu_request;\r
 273 \r
 274 /// global variable\r
 275 //static struct clk *pd_video;\r
 276 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 277 \r
 278 #ifdef CONFIG_DEBUG_FS\r
 279 static int vcodec_debugfs_init(void);\r
 280 static void vcodec_debugfs_exit(void);\r
 281 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 282 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 283 \r
 284 static const struct file_operations debug_vcodec_fops = {\r
 285         .open = debug_vcodec_open,\r
 286         .read = seq_read,\r
 287         .llseek = seq_lseek,\r
 288         .release = single_release,\r
 289 };\r
 290 #endif\r
 291 \r
 292 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 293 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 294 \r
 295 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(5)\r
 296 \r
 297 static void vpu_get_clk(struct vpu_service_info *pservice)\r
 298 {\r
 299         /*pd_video      = clk_get(NULL, "pd_video");\r
 300         if (IS_ERR(pd_video)) {\r
 301                 pr_err("failed on clk_get pd_video\n");\r
 302         }*/\r
 303         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 304         if (IS_ERR(pservice->aclk_vcodec)) {\r
 305                 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 306         }\r
 307         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 308         if (IS_ERR(pservice->hclk_vcodec)) {\r
 309                 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 310         }\r
 311 }\r
 312 \r
 313 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 314 {\r
 315     //clk_put(pd_video);\r
 316 \r
 317     if (pservice->aclk_vcodec) {\r
 318         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 319     }\r
 320 \r
 321     if (pservice->hclk_vcodec) {\r
 322         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 323     }\r
 324 }\r
 325 \r
 326 static void vpu_reset(struct vpu_service_info *pservice)\r
 327 {\r
 328 #if defined(CONFIG_ARCH_RK29)\r
 329         clk_disable(aclk_ddr_vepu);\r
 330         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 331         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 332         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 333         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 334         mdelay(10);\r
 335         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 336         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 337         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 338         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 339         clk_enable(aclk_ddr_vepu);\r
 340 #elif defined(CONFIG_ARCH_RK30)\r
 341         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 342         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 343         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 344         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 345         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 346         mdelay(1);\r
 347         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 348         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 349         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 350         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 351         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 352 #endif\r
 353         pservice->reg_codec = NULL;\r
 354         pservice->reg_pproc = NULL;\r
 355         pservice->reg_resev = NULL;\r
 356 }\r
 357 \r
 358 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 359 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 360 {\r
 361         vpu_reg *reg, *n;\r
 362         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 363                 reg_deinit(pservice, reg);\r
 364         }\r
 365         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 366                 reg_deinit(pservice, reg);\r
 367         }\r
 368         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 369                 reg_deinit(pservice, reg);\r
 370         }\r
 371 }\r
 372 \r
 373 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 374 {\r
 375         int running;\r
 376         vpu_reg *reg, *reg_tmp;\r
 377         vpu_session *session, *session_tmp;\r
 378 \r
 379         running = atomic_read(&pservice->total_running);\r
 380         printk("total_running %d\n", running);\r
 381 \r
 382         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 383         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 384         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 385 \r
 386         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 387                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 388                 running = atomic_read(&session->task_running);\r
 389                 printk("task_running %d\n", running);\r
 390                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 391                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 392                 }\r
 393                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 394                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 395                 }\r
 396                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 397                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 398                 }\r
 399         }\r
 400 }\r
 401 \r
 402 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 403 {\r
 404         int total_running;\r
 405         if (!pservice->enabled) {\r
 406                 return;\r
 407         }\r
 408 \r
 409         pservice->enabled = false;\r
 410         total_running = atomic_read(&pservice->total_running);\r
 411         if (total_running) {\r
 412                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 413                 mdelay(50);\r
 414                 pr_alert("alert: delay 50 ms for running task\n");\r
 415                 vpu_service_dump(pservice);\r
 416         }\r
 417 \r
 418         printk("vpu: power off...");\r
 419 #ifdef CONFIG_ARCH_RK29\r
 420         pmu_set_power_domain(PD_VCODEC, false);\r
 421 #else\r
 422         //clk_disable(pd_video);\r
 423 #endif\r
 424         udelay(10);\r
 425         //clk_disable(hclk_cpu_vcodec);\r
 426         //clk_disable(aclk_ddr_vepu);\r
 427 #if 0\r
 428         clk_disable_unprepare(pservice->hclk_vcodec);\r
 429         clk_disable_unprepare(pservice->aclk_vcodec);\r
 430 #endif\r
 431         wake_unlock(&pservice->wake_lock);\r
 432         printk("done\n");\r
 433 }\r
 434 \r
 435 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 436 {\r
 437         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 438 }\r
 439 \r
 440 static void vpu_power_off_work(struct work_struct *work_s)\r
 441 {\r
 442     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 443     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 444 \r
 445         if (mutex_trylock(&pservice->lock)) {\r
 446                 vpu_service_power_off(pservice);\r
 447                 mutex_unlock(&pservice->lock);\r
 448         } else {\r
 449                 /* Come back later if the device is busy... */\r
 450                 vpu_queue_power_off_work(pservice);\r
 451         }\r
 452 }\r
 453 \r
 454 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 455 {\r
 456         static ktime_t last;\r
 457         ktime_t now = ktime_get();\r
 458         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 459                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 460                 vpu_queue_power_off_work(pservice);\r
 461                 last = now;\r
 462         }\r
 463         if (pservice->enabled)\r
 464                 return ;\r
 465 \r
 466         pservice->enabled = true;\r
 467         printk("vpu: power on\n");\r
 468 \r
 469 #if 0\r
 470     clk_prepare_enable(pservice->aclk_vcodec);\r
 471         clk_prepare_enable(pservice->hclk_vcodec);\r
 472 #endif\r
 473         //clk_prepare_enable(hclk_cpu_vcodec);\r
 474 #if defined(CONFIG_ARCH_RK319X)\r
 475     /// select aclk_vepu as vcodec clock source. \r
 476     #define BIT_VCODEC_SEL  (1<<7)\r
 477     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 478 #endif\r
 479         udelay(10);\r
 480 #ifdef CONFIG_ARCH_RK29\r
 481         pmu_set_power_domain(PD_VCODEC, true);\r
 482 #else\r
 483         //clk_enable(pd_video);\r
 484 #endif\r
 485         udelay(10);\r
 486         //clk_enable(aclk_ddr_vepu);\r
 487         wake_lock(&pservice->wake_lock);\r
 488 }\r
 489 \r
 490 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 491 {\r
 492         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 493         return ((type == 8) || (type == 4));\r
 494 }\r
 495 \r
 496 static inline bool reg_check_interlace(vpu_reg *reg)\r
 497 {\r
 498         unsigned long type = (reg->reg[3] & (1 << 23));\r
 499         return (type > 0);\r
 500 }\r
 501 \r
 502 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 503 {\r
 504         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 505         if (NULL == reg) {\r
 506                 pr_err("error: kmalloc fail in reg_init\n");\r
 507                 return NULL;\r
 508         }\r
 509 \r
 510         if (size > pservice->reg_size) {\r
 511                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 512                 size = pservice->reg_size;\r
 513         }\r
 514         reg->session = session;\r
 515         reg->type = session->type;\r
 516         reg->size = size;\r
 517         reg->freq = VPU_FREQ_DEFAULT;\r
 518         reg->reg = (unsigned long *)&reg[1];\r
 519         INIT_LIST_HEAD(&reg->session_link);\r
 520         INIT_LIST_HEAD(&reg->status_link);\r
 521 \r
 522         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 523                 pr_err("error: copy_from_user failed in reg_init\n");\r
 524                 kfree(reg);\r
 525                 return NULL;\r
 526         }\r
 527 \r
 528         mutex_lock(&pservice->lock);\r
 529         list_add_tail(&reg->status_link, &pservice->waiting);\r
 530         list_add_tail(&reg->session_link, &session->waiting);\r
 531         mutex_unlock(&pservice->lock);\r
 532 \r
 533         if (pservice->auto_freq) {\r
 534                 if (!soc_is_rk2928g()) {\r
 535                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 536                                 if (reg_check_rmvb_wmv(reg)) {\r
 537                                         reg->freq = VPU_FREQ_200M;\r
 538                                 } else {\r
 539                                         if (reg_check_interlace(reg)) {\r
 540                                                 reg->freq = VPU_FREQ_400M;\r
 541                                         }\r
 542                                 }\r
 543                         }\r
 544                         if (reg->type == VPU_PP) {\r
 545                                 reg->freq = VPU_FREQ_400M;\r
 546                         }\r
 547                 }\r
 548         }\r
 549 \r
 550         return reg;\r
 551 }\r
 552 \r
 553 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 554 {\r
 555         list_del_init(&reg->session_link);\r
 556         list_del_init(&reg->status_link);\r
 557         if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 558         if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 559         kfree(reg);\r
 560 }\r
 561 \r
 562 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 563 {\r
 564         list_del_init(&reg->status_link);\r
 565         list_add_tail(&reg->status_link, &pservice->running);\r
 566 \r
 567         list_del_init(&reg->session_link);\r
 568         list_add_tail(&reg->session_link, &reg->session->running);\r
 569 }\r
 570 \r
 571 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 572 {\r
 573         int i;\r
 574         u32 *dst = (u32 *)&reg->reg[0];\r
 575         for (i = 0; i < count; i++)\r
 576                 *dst++ = *src++;\r
 577 }\r
 578 \r
 579 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 580 {\r
 581     int irq_reg = -1;\r
 582         list_del_init(&reg->status_link);\r
 583         list_add_tail(&reg->status_link, &pservice->done);\r
 584 \r
 585         list_del_init(&reg->session_link);\r
 586         list_add_tail(&reg->session_link, &reg->session->done);\r
 587 \r
 588         switch (reg->type) {\r
 589         case VPU_ENC : {\r
 590                 pservice->reg_codec = NULL;\r
 591                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 592         irq_reg = ENC_INTERRUPT_REGISTER;\r
 593                 break;\r
 594         }\r
 595         case VPU_DEC : {\r
 596                 pservice->reg_codec = NULL;\r
 597                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC);\r
 598         irq_reg = DEC_INTERRUPT_REGISTER;\r
 599                 break;\r
 600         }\r
 601         case VPU_PP : {\r
 602                 pservice->reg_pproc = NULL;\r
 603                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 604                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 605                 break;\r
 606         }\r
 607         case VPU_DEC_PP : {\r
 608                 pservice->reg_codec = NULL;\r
 609                 pservice->reg_pproc = NULL;\r
 610                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 611                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 612                 break;\r
 613         }\r
 614         default : {\r
 615                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 616                 break;\r
 617         }\r
 618         }\r
 619 \r
 620     if (irq_reg != -1) {\r
 621         reg->reg[irq_reg] = pservice->irq_status;\r
 622     }\r
 623 \r
 624         atomic_sub(1, &reg->session->task_running);\r
 625         atomic_sub(1, &pservice->total_running);\r
 626         wake_up(&reg->session->wait);\r
 627 }\r
 628 \r
 629 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 630 {\r
 631         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 632         if (curr == reg->freq) {\r
 633                 return ;\r
 634         }\r
 635         atomic_set(&pservice->freq_status, reg->freq);\r
 636         switch (reg->freq) {\r
 637         case VPU_FREQ_200M : {\r
 638                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 639                 //printk("default: 200M\n");\r
 640         } break;\r
 641         case VPU_FREQ_266M : {\r
 642                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 643                 //printk("default: 266M\n");\r
 644         } break;\r
 645         case VPU_FREQ_300M : {\r
 646                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 647                 //printk("default: 300M\n");\r
 648         } break;\r
 649         case VPU_FREQ_400M : {\r
 650                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 651                 //printk("default: 400M\n");\r
 652         } break;\r
 653         default : {\r
 654                 if (soc_is_rk2928g()) {\r
 655                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 656                 } else {\r
 657                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 658                 }\r
 659                 //printk("default: 300M\n");\r
 660         } break;\r
 661         }\r
 662 }\r
 663 \r
 664 #if HEVC_SIM_ENABLE\r
 665 static void simulate_start(struct vpu_service_info *pservice);\r
 666 #endif\r
 667 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 668 {\r
 669         int i;\r
 670         u32 *src = (u32 *)&reg->reg[0];\r
 671         atomic_add(1, &pservice->total_running);\r
 672         atomic_add(1, &reg->session->task_running);\r
 673         if (pservice->auto_freq) {\r
 674                 vpu_service_set_freq(pservice, reg);\r
 675         }\r
 676         switch (reg->type) {\r
 677         case VPU_ENC : {\r
 678                 int enc_count = pservice->hw_info->enc_reg_num;\r
 679                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 680 #if 0\r
 681                 if (pservice->bug_dec_addr) {\r
 682 #if !defined(CONFIG_ARCH_RK319X)\r
 683                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 684 #endif\r
 685                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 686                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 687 #if !defined(CONFIG_ARCH_RK319X)\r
 688                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 689 #endif\r
 690                 }\r
 691 #endif\r
 692                 pservice->reg_codec = reg;\r
 693 \r
 694                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 695 \r
 696                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 697                         dst[i] = src[i];\r
 698 \r
 699                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 700                         dst[i] = src[i];\r
 701 \r
 702                 dsb();\r
 703 \r
 704                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 705                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 706 \r
 707 #if VPU_SERVICE_SHOW_TIME\r
 708                 do_gettimeofday(&enc_start);\r
 709 #endif\r
 710 \r
 711         } break;\r
 712         case VPU_DEC : {\r
 713                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 714                 pservice->reg_codec = reg;\r
 715 \r
 716                 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 717                         dst[i] = src[i];\r
 718 \r
 719                 dsb();\r
 720 \r
 721                 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 722                 dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 723 \r
 724 #if VPU_SERVICE_SHOW_TIME\r
 725                 do_gettimeofday(&dec_start);\r
 726 #endif\r
 727 \r
 728         } break;\r
 729         case VPU_PP : {\r
 730                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 731                 pservice->reg_pproc = reg;\r
 732 \r
 733                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 734 \r
 735                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
 736                         dst[i] = src[i];\r
 737 \r
 738                 dsb();\r
 739 \r
 740                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
 741 \r
 742 #if VPU_SERVICE_SHOW_TIME\r
 743                 do_gettimeofday(&pp_start);\r
 744 #endif\r
 745 \r
 746         } break;\r
 747         case VPU_DEC_PP : {\r
 748                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 749                 pservice->reg_codec = reg;\r
 750                 pservice->reg_pproc = reg;\r
 751 \r
 752                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
 753                         dst[i] = src[i];\r
 754 \r
 755                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
 756                 dsb();\r
 757 \r
 758                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 759                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
 760                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
 761 \r
 762 #if VPU_SERVICE_SHOW_TIME\r
 763                 do_gettimeofday(&dec_start);\r
 764 #endif\r
 765 \r
 766         } break;\r
 767         default : {\r
 768                 pr_err("error: unsupport session type %d", reg->type);\r
 769                 atomic_sub(1, &pservice->total_running);\r
 770                 atomic_sub(1, &reg->session->task_running);\r
 771                 break;\r
 772         }\r
 773         }\r
 774 \r
 775 #if HEVC_SIM_ENABLE\r
 776     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 777         simulate_start(pservice);\r
 778     }\r
 779 #endif\r
 780 }\r
 781 \r
 782 static void try_set_reg(struct vpu_service_info *pservice)\r
 783 {\r
 784         // first get reg from reg list\r
 785         if (!list_empty(&pservice->waiting)) {\r
 786                 int can_set = 0;\r
 787                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
 788 \r
 789                 vpu_service_power_on(pservice);\r
 790 \r
 791                 switch (reg->type) {\r
 792                 case VPU_ENC : {\r
 793                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
 794                                 can_set = 1;\r
 795                 } break;\r
 796                 case VPU_DEC : {\r
 797                         if (NULL == pservice->reg_codec)\r
 798                                 can_set = 1;\r
 799                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
 800                                 can_set = 0;\r
 801                         }\r
 802                 } break;\r
 803                 case VPU_PP : {\r
 804                         if (NULL == pservice->reg_codec) {\r
 805                                 if (NULL == pservice->reg_pproc)\r
 806                                         can_set = 1;\r
 807                         } else {\r
 808                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
 809                                         can_set = 1;\r
 810                                 // can not charge frequency when vpu is working\r
 811                                 if (pservice->auto_freq) {\r
 812                                         can_set = 0;\r
 813                                 }\r
 814                         }\r
 815                 } break;\r
 816                 case VPU_DEC_PP : {\r
 817                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
 818                                 can_set = 1;\r
 819                         } break;\r
 820                 default : {\r
 821                         printk("undefined reg type %d\n", reg->type);\r
 822                 } break;\r
 823                 }\r
 824                 if (can_set) {\r
 825                         reg_from_wait_to_run(pservice, reg);\r
 826                         reg_copy_to_hw(pservice, reg);\r
 827                 }\r
 828         }\r
 829 }\r
 830 \r
 831 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
 832 {\r
 833         int ret = 0;\r
 834         switch (reg->type) {\r
 835         case VPU_ENC : {\r
 836                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
 837                         ret = -EFAULT;\r
 838                 break;\r
 839         }\r
 840         case VPU_DEC : {\r
 841                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC)))\r
 842                         ret = -EFAULT;\r
 843                 break;\r
 844         }\r
 845         case VPU_PP : {\r
 846                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
 847                         ret = -EFAULT;\r
 848                 break;\r
 849         }\r
 850         case VPU_DEC_PP : {\r
 851                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
 852                         ret = -EFAULT;\r
 853                 break;\r
 854         }\r
 855         default : {\r
 856                 ret = -EFAULT;\r
 857                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
 858                 break;\r
 859         }\r
 860         }\r
 861         reg_deinit(pservice, reg);\r
 862         return ret;\r
 863 }\r
 864 \r
 865 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
 866 {\r
 867     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
 868         vpu_session *session = (vpu_session *)filp->private_data;\r
 869         if (NULL == session) {\r
 870                 return -EINVAL;\r
 871         }\r
 872 \r
 873         switch (cmd) {\r
 874         case VPU_IOC_SET_CLIENT_TYPE : {\r
 875                 session->type = (VPU_CLIENT_TYPE)arg;\r
 876                 break;\r
 877         }\r
 878         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
 879                 vpu_request req;\r
 880                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
 881                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
 882                         return -EFAULT;\r
 883                 } else {\r
 884                         if (VPU_ENC != session->type) {\r
 885                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
 886                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
 887                                         return -EFAULT;\r
 888                                 }\r
 889                         } else {\r
 890                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
 891                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
 892                                         return -EFAULT;\r
 893                                 }\r
 894                         }\r
 895                 }\r
 896 \r
 897                 break;\r
 898         }\r
 899         case VPU_IOC_SET_REG : {\r
 900                 vpu_request req;\r
 901                 vpu_reg *reg;\r
 902                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
 903                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
 904                         return -EFAULT;\r
 905                 }\r
 906                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
 907                 if (NULL == reg) {\r
 908                         return -EFAULT;\r
 909                 } else {\r
 910                         mutex_lock(&pservice->lock);\r
 911                         try_set_reg(pservice);\r
 912                         mutex_unlock(&pservice->lock);\r
 913                 }\r
 914 \r
 915                 break;\r
 916         }\r
 917         case VPU_IOC_GET_REG : {\r
 918                 vpu_request req;\r
 919                 vpu_reg *reg;\r
 920                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
 921                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
 922                         return -EFAULT;\r
 923                 } else {\r
 924                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
 925                         if (!list_empty(&session->done)) {\r
 926                                 if (ret < 0) {\r
 927                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
 928                                 }\r
 929                                 ret = 0;\r
 930                         } else {\r
 931                                 if (unlikely(ret < 0)) {\r
 932                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
 933                                 } else if (0 == ret) {\r
 934                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
 935                                         ret = -ETIMEDOUT;\r
 936                                 }\r
 937                         }\r
 938                         if (ret < 0) {\r
 939                                 int task_running = atomic_read(&session->task_running);\r
 940                                 mutex_lock(&pservice->lock);\r
 941                                 vpu_service_dump(pservice);\r
 942                                 if (task_running) {\r
 943                                         atomic_set(&session->task_running, 0);\r
 944                                         atomic_sub(task_running, &pservice->total_running);\r
 945                                         printk("%d task is running but not return, reset hardware...", task_running);\r
 946                                         vpu_reset(pservice);\r
 947                                         printk("done\n");\r
 948                                 }\r
 949                                 vpu_service_session_clear(pservice, session);\r
 950                                 mutex_unlock(&pservice->lock);\r
 951                                 return ret;\r
 952                         }\r
 953                 }\r
 954                 mutex_lock(&pservice->lock);\r
 955                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
 956                 return_reg(pservice, reg, (u32 __user *)req.req);\r
 957                 mutex_unlock(&pservice->lock);\r
 958                 break;\r
 959         }\r
 960         default : {\r
 961                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
 962                 break;\r
 963         }\r
 964         }\r
 965 \r
 966         return 0;\r
 967 }\r
 968 \r
 969 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
 970 {\r
 971         int ret = -EINVAL, i = 0;\r
 972         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
 973         u32 enc_id = *tmp;\r
 974 \r
 975 #if 0\r
 976     /// temporary, hevc driver test.\r
 977     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
 978         p->hw_info = &vpu_hw_set[2];\r
 979         return 0;\r
 980     }\r
 981 #endif\r
 982 \r
 983         enc_id = (enc_id >> 16) & 0xFFFF;\r
 984         pr_info("checking hw id %x\n", enc_id);\r
 985     p->hw_info = NULL;\r
 986         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
 987                 if (enc_id == vpu_hw_set[i].hw_id) {\r
 988                         p->hw_info = &vpu_hw_set[i];\r
 989                         ret = 0;\r
 990                         break;\r
 991                 }\r
 992         }\r
 993         iounmap((void *)tmp);\r
 994         return ret;\r
 995 }\r
 996 \r
 997 static int vpu_service_open(struct inode *inode, struct file *filp)\r
 998 {\r
 999     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1000         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1001         if (NULL == session) {\r
1002                 pr_err("error: unable to allocate memory for vpu_session.");\r
1003                 return -ENOMEM;\r
1004         }\r
1005 \r
1006         session->type   = VPU_TYPE_BUTT;\r
1007         session->pid    = current->pid;\r
1008         INIT_LIST_HEAD(&session->waiting);\r
1009         INIT_LIST_HEAD(&session->running);\r
1010         INIT_LIST_HEAD(&session->done);\r
1011         INIT_LIST_HEAD(&session->list_session);\r
1012         init_waitqueue_head(&session->wait);\r
1013         atomic_set(&session->task_running, 0);\r
1014         mutex_lock(&pservice->lock);\r
1015         list_add_tail(&session->list_session, &pservice->session);\r
1016         filp->private_data = (void *)session;\r
1017         mutex_unlock(&pservice->lock);\r
1018 \r
1019         pr_debug("dev opened\n");\r
1020         return nonseekable_open(inode, filp);\r
1021 }\r
1022 \r
1023 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1024 {\r
1025     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1026         int task_running;\r
1027         vpu_session *session = (vpu_session *)filp->private_data;\r
1028         if (NULL == session)\r
1029                 return -EINVAL;\r
1030 \r
1031         task_running = atomic_read(&session->task_running);\r
1032         if (task_running) {\r
1033                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1034                 msleep(50);\r
1035         }\r
1036         wake_up(&session->wait);\r
1037 \r
1038         mutex_lock(&pservice->lock);\r
1039         /* remove this filp from the asynchronusly notified filp's */\r
1040         list_del_init(&session->list_session);\r
1041         vpu_service_session_clear(pservice, session);\r
1042         kfree(session);\r
1043         filp->private_data = NULL;\r
1044         mutex_unlock(&pservice->lock);\r
1045 \r
1046     pr_debug("dev closed\n");\r
1047         return 0;\r
1048 }\r
1049 \r
1050 static const struct file_operations vpu_service_fops = {\r
1051         .unlocked_ioctl = vpu_service_ioctl,\r
1052         .open           = vpu_service_open,\r
1053         .release        = vpu_service_release,\r
1054         //.fasync       = vpu_service_fasync,\r
1055 };\r
1056 \r
1057 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1058 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1059 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1060 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1061 static void get_hw_info(struct vpu_service_info *pservice);\r
1062 \r
1063 #if HEVC_SIM_ENABLE\r
1064 static void simulate_work(struct work_struct *work_s)\r
1065 {\r
1066     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1067     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1068     vpu_device *dev = &pservice->dec_dev;\r
1069 \r
1070     if (!list_empty(&pservice->running)) {\r
1071         atomic_add(1, &dev->irq_count_codec);\r
1072         vdpu_isr(0, (void*)pservice);\r
1073     } else {\r
1074         //simulate_start(pservice);\r
1075         pr_err("empty running queue\n");\r
1076     }\r
1077 }\r
1078 \r
1079 static void simulate_init(struct vpu_service_info *pservice)\r
1080 {\r
1081     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1082 }\r
1083 \r
1084 static void simulate_start(struct vpu_service_info *pservice)\r
1085 {\r
1086     cancel_delayed_work_sync(&pservice->power_off_work);\r
1087     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1088 }\r
1089 #endif\r
1090 \r
1091 #if HEVC_TEST_ENABLE\r
1092 static int hevc_test_case0(vpu_service_info *pservice);\r
1093 #endif\r
1094 static int vcodec_probe(struct platform_device *pdev)\r
1095 {\r
1096     int ret = 0;\r
1097     struct resource *res = NULL;\r
1098     struct device *dev = &pdev->dev;\r
1099     void __iomem *regs = NULL;\r
1100     struct device_node *np = pdev->dev.of_node;\r
1101     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1102     char *prop = (char*)dev_name(dev);\r
1103 \r
1104     pr_info("probe device %s\n", dev_name(dev));\r
1105 \r
1106     of_property_read_string(np, "name", (const char**)&prop);\r
1107     dev_set_name(dev, prop);\r
1108 \r
1109     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1110     INIT_LIST_HEAD(&pservice->waiting);\r
1111     INIT_LIST_HEAD(&pservice->running);\r
1112     INIT_LIST_HEAD(&pservice->done);\r
1113     INIT_LIST_HEAD(&pservice->session);\r
1114     mutex_init(&pservice->lock);\r
1115     pservice->reg_codec = NULL;\r
1116     pservice->reg_pproc = NULL;\r
1117     atomic_set(&pservice->total_running, 0);\r
1118     pservice->enabled = false;\r
1119 \r
1120     pservice->dev = dev;\r
1121 \r
1122     vpu_get_clk(pservice);\r
1123 \r
1124     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1125 \r
1126     vpu_service_power_on(pservice);\r
1127 \r
1128     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1129 \r
1130     regs = devm_ioremap_resource(pservice->dev, res);\r
1131     if (IS_ERR(regs)) {\r
1132         ret = PTR_ERR(regs);\r
1133         goto err;\r
1134     }\r
1135 \r
1136     ret = vpu_service_check_hw(pservice, res->start);\r
1137     if (ret < 0) {\r
1138         pr_err("error: hw info check faild\n");\r
1139         goto err;\r
1140     }\r
1141 \r
1142     /// define regs address.\r
1143     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1144     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1145 \r
1146     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1147 \r
1148     pservice->reg_size   = pservice->dec_dev.iosize;\r
1149 \r
1150     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1151         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1152         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1153 \r
1154         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1155 \r
1156         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1157 \r
1158         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1159         if (pservice->irq_enc < 0) {\r
1160             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1161             ret = -ENXIO;\r
1162             goto err;\r
1163         }\r
1164 \r
1165         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1166         if (ret) {\r
1167             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1168             goto err;\r
1169         }\r
1170     }\r
1171 \r
1172     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1173     if (pservice->irq_dec < 0) {\r
1174         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1175         ret = -ENXIO;\r
1176         goto err;\r
1177     }\r
1178 \r
1179     /* get the IRQ line */\r
1180     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1181     if (ret) {\r
1182         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1183         goto err;\r
1184     }\r
1185 \r
1186     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1187     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1188     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1189     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1190 \r
1191     /// create device\r
1192     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1193     if (ret) {\r
1194         dev_err(dev, "alloc dev_t failed\n");\r
1195         goto err;\r
1196     }\r
1197 \r
1198     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1199 \r
1200     pservice->cdev.owner = THIS_MODULE;\r
1201     pservice->cdev.ops = &vpu_service_fops;\r
1202 \r
1203     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1204 \r
1205     if (ret) {\r
1206         dev_err(dev, "add dev_t failed\n");\r
1207         goto err;\r
1208     }\r
1209 \r
1210     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1211 \r
1212     if (IS_ERR(pservice->cls)) {\r
1213         ret = PTR_ERR(pservice->cls);\r
1214         dev_err(dev, "class_create err:%d\n", ret);\r
1215         goto err;\r
1216     }\r
1217 \r
1218     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1219 \r
1220     platform_set_drvdata(pdev, pservice);\r
1221 \r
1222     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1223         get_hw_info(pservice);\r
1224     }\r
1225 \r
1226 #ifdef CONFIG_DEBUG_FS\r
1227     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1228     \r
1229     if (pservice->debugfs_dir == NULL) {\r
1230         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1231     }\r
1232 \r
1233     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1234                     pservice->debugfs_dir, pservice,\r
1235                     &debug_vcodec_fops);\r
1236 #endif\r
1237 \r
1238     vpu_service_power_off(pservice);\r
1239     pr_info("init success\n");\r
1240 \r
1241 #if HEVC_SIM_ENABLE\r
1242     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1243         simulate_init(pservice);\r
1244     }\r
1245 #endif\r
1246 \r
1247 #if HEVC_TEST_ENABLE\r
1248     hevc_test_case0(pservice);\r
1249 #endif\r
1250 \r
1251     return 0;\r
1252 \r
1253 err:\r
1254     pr_info("init failed\n");\r
1255     vpu_service_power_off(pservice);\r
1256     vpu_put_clk(pservice);\r
1257     wake_lock_destroy(&pservice->wake_lock);\r
1258 \r
1259     if (res) {\r
1260         if (regs) {\r
1261             devm_ioremap_release(&pdev->dev, res);\r
1262         }\r
1263         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1264     }\r
1265 \r
1266     if (pservice->irq_enc > 0) {\r
1267         free_irq(pservice->irq_enc, (void *)pservice);\r
1268     }\r
1269 \r
1270     if (pservice->irq_dec > 0) {\r
1271         free_irq(pservice->irq_dec, (void *)pservice);\r
1272     }\r
1273 \r
1274     if (pservice->child_dev) {\r
1275         device_destroy(pservice->cls, pservice->dev_t);\r
1276         cdev_del(&pservice->cdev);\r
1277         unregister_chrdev_region(pservice->dev_t, 1);\r
1278     }\r
1279 \r
1280     if (pservice->cls) {\r
1281         class_destroy(pservice->cls);\r
1282     }\r
1283 \r
1284     return ret;\r
1285 }\r
1286 \r
1287 static int vcodec_remove(struct platform_device *pdev)\r
1288 {\r
1289     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1290     struct resource *res;\r
1291 \r
1292     device_destroy(pservice->cls, pservice->dev_t);\r
1293     class_destroy(pservice->cls);\r
1294     cdev_del(&pservice->cdev);\r
1295     unregister_chrdev_region(pservice->dev_t, 1);\r
1296 \r
1297     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1298     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1299     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1300     devm_ioremap_release(&pdev->dev, res);\r
1301     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1302     vpu_put_clk(pservice);\r
1303     wake_lock_destroy(&pservice->wake_lock);\r
1304     \r
1305 #ifdef CONFIG_DEBUG_FS\r
1306     if (pservice->debugfs_file_regs) {\r
1307         debugfs_remove(pservice->debugfs_file_regs);\r
1308     }\r
1309 \r
1310     if (pservice->debugfs_dir) {\r
1311         debugfs_remove(pservice->debugfs_dir);\r
1312     }\r
1313 #endif\r
1314 \r
1315     return 0;\r
1316 }\r
1317 \r
1318 #if defined(CONFIG_OF)\r
1319 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1320         //{.compatible = "vpu_service",},\r
1321         {.compatible = "rockchip,hevc_service",},\r
1322     {},\r
1323 };\r
1324 #endif\r
1325 \r
1326 static struct platform_driver vcodec_driver = {\r
1327         .probe     = vcodec_probe,\r
1328     .remove        = vcodec_remove,\r
1329     .driver = {\r
1330         .name = "vcodec",\r
1331         .owner = THIS_MODULE,\r
1332 #if defined(CONFIG_OF)\r
1333         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1334 #endif\r
1335         },\r
1336 };\r
1337 \r
1338 static void get_hw_info(struct vpu_service_info *pservice)\r
1339 {\r
1340         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1341         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1342         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1343         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1344 \r
1345         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1346         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1347         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1348                 dec->jpegSupport = JPEG_PROGRESSIVE;\r
1349         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1350         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1351         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1352         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1353         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1354         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1355 #if !defined(CONFIG_ARCH_RK319X)\r
1356     /// invalidate max decode picture width value in rk319x vpu\r
1357         dec->maxDecPicWidth = configReg & 0x07FFU;\r
1358 #else\r
1359     dec->maxDecPicWidth = 3840;\r
1360 #endif\r
1361 \r
1362         /* 2nd Config register */\r
1363         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1364         if (dec->refBufSupport) {\r
1365                 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1366                         dec->refBufSupport |= 2;\r
1367                 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1368                         dec->refBufSupport |= 4;\r
1369         }\r
1370         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1371         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1372         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1373         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1374 \r
1375         /* JPEG xtensions */\r
1376         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1377                 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1378         } else {\r
1379                 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1380         }\r
1381 \r
1382         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1383                 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1384         } else {\r
1385                 dec->rvSupport = RV_NOT_SUPPORTED;\r
1386         }\r
1387 \r
1388         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1389 \r
1390         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1391                 dec->refBufSupport |= 8; /* enable HW support for offset */\r
1392         }\r
1393 \r
1394 #if !defined(CONFIG_ARCH_RK319X)\r
1395     /// invalidate fuse register value in rk319x vpu\r
1396         {\r
1397         VPUHwFuseStatus_t hwFuseSts;\r
1398         /* Decoder fuse configuration */\r
1399         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1400 \r
1401         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1402         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1403         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1404         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1405         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1406         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1407         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1408         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1409         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1410         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1411         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1412         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1413         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1414         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1415 \r
1416         /* check max. decoder output width */\r
1417 \r
1418         if (fuseReg & 0x8000U)\r
1419                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1420         else if (fuseReg & 0x4000U)\r
1421                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1422         else if (fuseReg & 0x2000U)\r
1423                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1424         else if (fuseReg & 0x1000U)\r
1425                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1426         else    /* remove warning */\r
1427                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1428 \r
1429         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1430 \r
1431         /* Pp configuration */\r
1432         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1433 \r
1434         if ((configReg >> DWL_PP_E) & 0x01U) {\r
1435                 dec->ppSupport = 1;\r
1436                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1437                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1438                 dec->ppConfig = configReg;\r
1439         } else {\r
1440                 dec->ppSupport = 0;\r
1441                 dec->maxPpOutPicWidth = 0;\r
1442                 dec->ppConfig = 0;\r
1443         }\r
1444 \r
1445         /* check the HW versio */\r
1446         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1447                 /* Pp configuration */\r
1448                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1449 \r
1450                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1451                         /* Pp fuse configuration */\r
1452                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1453 \r
1454                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1455                                 hwFuseSts.ppSupportFuse = 1;\r
1456                                 /* check max. pp output width */\r
1457                                 if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1458                                 else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1459                                 else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1460                                 else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1461                                 else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1462                                 hwFuseSts.ppConfigFuse = fuseRegPp;\r
1463                         } else {\r
1464                                 hwFuseSts.ppSupportFuse = 0;\r
1465                                 hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1466                                 hwFuseSts.ppConfigFuse = 0;\r
1467                         }\r
1468                 } else {\r
1469                         hwFuseSts.ppSupportFuse = 0;\r
1470                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1471                         hwFuseSts.ppConfigFuse = 0;\r
1472                 }\r
1473 \r
1474                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1475                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1476                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1477                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1478                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1479                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1480                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1481                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1482                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1483                         dec->jpegSupport = JPEG_BASELINE;\r
1484                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1485                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1486                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1487                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1488                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1489                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1490 \r
1491                 /* check the pp config vs fuse status */\r
1492                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1493                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1494                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1495                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1496                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1497 \r
1498                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1499                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1500                 }\r
1501                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1502                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1503                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1504                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1505                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1506         }\r
1507         }\r
1508 #endif\r
1509         configReg = pservice->enc_dev.hwregs[63];\r
1510         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1511         enc->h264Enabled = (configReg >> 27) & 1;\r
1512         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1513         enc->jpegEnabled = (configReg >> 25) & 1;\r
1514         enc->vsEnabled = (configReg >> 24) & 1;\r
1515         enc->rgbEnabled = (configReg >> 28) & 1;\r
1516         //enc->busType = (configReg >> 20) & 15;\r
1517         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1518         //enc->busWidth = (configReg >> 12) & 15;\r
1519         enc->reg_size = pservice->reg_size;\r
1520         enc->reserv[0] = enc->reserv[1] = 0;\r
1521 \r
1522         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();\r
1523         if (pservice->auto_freq) {\r
1524                 printk("vpu_service set to auto frequency mode\n");\r
1525                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1526         }\r
1527         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1528         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1529 }\r
1530 \r
1531 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1532 {\r
1533     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1534     vpu_device *dev = &pservice->dec_dev;\r
1535         u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1536 \r
1537         pr_debug("dec_irq\n");\r
1538 \r
1539         if (irq_status & DEC_INTERRUPT_BIT) {\r
1540                 pr_debug("dec_isr dec %x\n", irq_status);\r
1541                 if ((irq_status & 0x40001) == 0x40001)\r
1542                 {\r
1543                         do {\r
1544                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1545                         } while ((irq_status & 0x40001) == 0x40001);\r
1546                 }\r
1547 \r
1548                 /* clear dec IRQ */\r
1549         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1550             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1551         } else {\r
1552             /*writel(irq_status \r
1553               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1554                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1555 \r
1556             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1557         }\r
1558                 atomic_add(1, &dev->irq_count_codec);\r
1559         }\r
1560 \r
1561     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1562         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1563         if (irq_status & PP_INTERRUPT_BIT) {\r
1564             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1565             /* clear pp IRQ */\r
1566             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1567             atomic_add(1, &dev->irq_count_pp);\r
1568         }\r
1569     }\r
1570 \r
1571     pservice->irq_status = irq_status;\r
1572 \r
1573         return IRQ_WAKE_THREAD;\r
1574 }\r
1575 \r
1576 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1577 {\r
1578     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1579     vpu_device *dev = &pservice->dec_dev;\r
1580 \r
1581         mutex_lock(&pservice->lock);\r
1582         if (atomic_read(&dev->irq_count_codec)) {\r
1583 #if VPU_SERVICE_SHOW_TIME\r
1584                 do_gettimeofday(&dec_end);\r
1585                 pr_info("dec task: %ld ms\n",\r
1586                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1587                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1588 #endif\r
1589                 atomic_sub(1, &dev->irq_count_codec);\r
1590                 if (NULL == pservice->reg_codec) {\r
1591                         pr_err("error: dec isr with no task waiting\n");\r
1592                 } else {\r
1593                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1594                 }\r
1595         }\r
1596 \r
1597         if (atomic_read(&dev->irq_count_pp)) {\r
1598 \r
1599 #if VPU_SERVICE_SHOW_TIME\r
1600                 do_gettimeofday(&pp_end);\r
1601                 printk("pp  task: %ld ms\n",\r
1602                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1603                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1604 #endif\r
1605 \r
1606                 atomic_sub(1, &dev->irq_count_pp);\r
1607                 if (NULL == pservice->reg_pproc) {\r
1608                         pr_err("error: pp isr with no task waiting\n");\r
1609                 } else {\r
1610                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1611                 }\r
1612         }\r
1613         try_set_reg(pservice);\r
1614         mutex_unlock(&pservice->lock);\r
1615         return IRQ_HANDLED;\r
1616 }\r
1617 \r
1618 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1619 {\r
1620         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1621     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1622     vpu_device *dev = &pservice->enc_dev;\r
1623         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1624 \r
1625         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1626 \r
1627 #if VPU_SERVICE_SHOW_TIME\r
1628         do_gettimeofday(&enc_end);\r
1629         pr_info("enc task: %ld ms\n",\r
1630                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1631                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1632 #endif\r
1633 \r
1634         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1635                 /* clear enc IRQ */\r
1636                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1637                 atomic_add(1, &dev->irq_count_codec);\r
1638         }\r
1639 \r
1640         return IRQ_WAKE_THREAD;\r
1641 }\r
1642 \r
1643 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1644 {\r
1645         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1646     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1647     vpu_device *dev = &pservice->enc_dev;\r
1648 \r
1649         mutex_lock(&pservice->lock);\r
1650         if (atomic_read(&dev->irq_count_codec)) {\r
1651                 atomic_sub(1, &dev->irq_count_codec);\r
1652                 if (NULL == pservice->reg_codec) {\r
1653                         pr_err("error: enc isr with no task waiting\n");\r
1654                 } else {\r
1655                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1656                 }\r
1657         }\r
1658         try_set_reg(pservice);\r
1659         mutex_unlock(&pservice->lock);\r
1660         return IRQ_HANDLED;\r
1661 }\r
1662 \r
1663 static int __init vcodec_service_init(void)\r
1664 {\r
1665     int ret;\r
1666 \r
1667     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1668         pr_err("Platform device register failed (%d).\n", ret);\r
1669         return ret;\r
1670     }\r
1671 \r
1672 #ifdef CONFIG_DEBUG_FS\r
1673     vcodec_debugfs_init();\r
1674 #endif\r
1675 \r
1676     return ret;\r
1677 }\r
1678 \r
1679 static void __exit vcodec_service_exit(void)\r
1680 {\r
1681 #ifdef CONFIG_DEBUG_FS\r
1682     vcodec_debugfs_exit();\r
1683 #endif\r
1684 \r
1685         platform_driver_unregister(&vcodec_driver);\r
1686 }\r
1687 \r
1688 module_init(vcodec_service_init);\r
1689 module_exit(vcodec_service_exit);\r
1690 \r
1691 #ifdef CONFIG_DEBUG_FS\r
1692 #include <linux/seq_file.h>\r
1693 \r
1694 static int vcodec_debugfs_init()\r
1695 {\r
1696     parent = debugfs_create_dir("vcodec", NULL);\r
1697     if (!parent)\r
1698         return -1;\r
1699 \r
1700     return 0;\r
1701 }\r
1702 \r
1703 static void vcodec_debugfs_exit()\r
1704 {\r
1705     debugfs_remove(parent);\r
1706 }\r
1707 \r
1708 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
1709 {\r
1710     return debugfs_create_dir(dirname, parent);\r
1711 }\r
1712 \r
1713 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
1714 {\r
1715         struct vpu_service_info *pservice = s->private;\r
1716     unsigned int i, n;\r
1717         vpu_reg *reg, *reg_tmp;\r
1718         vpu_session *session, *session_tmp;\r
1719 \r
1720         mutex_lock(&pservice->lock);\r
1721         vpu_service_power_on(pservice);\r
1722     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1723         seq_printf(s, "\nENC Registers:\n");\r
1724         n = pservice->enc_dev.iosize >> 2;\r
1725         for (i = 0; i < n; i++) {\r
1726             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
1727         }\r
1728     }\r
1729         seq_printf(s, "\nDEC Registers:\n");\r
1730         n = pservice->dec_dev.iosize >> 2;\r
1731         for (i = 0; i < n; i++) {\r
1732                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
1733         }\r
1734 \r
1735         seq_printf(s, "\nvpu service status:\n");\r
1736         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
1737                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
1738                 //seq_printf(s, "waiting reg set %d\n");\r
1739                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
1740                         seq_printf(s, "waiting register set\n");\r
1741                 }\r
1742                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
1743                         seq_printf(s, "running register set\n");\r
1744                 }\r
1745                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
1746                         seq_printf(s, "done    register set\n");\r
1747                 }\r
1748         }\r
1749         mutex_unlock(&pservice->lock);\r
1750 \r
1751     return 0;\r
1752 }\r
1753 \r
1754 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
1755 {\r
1756         return single_open(file, debug_vcodec_show, inode->i_private);\r
1757 }\r
1758 \r
1759 #endif\r
1760 \r
1761 #if HEVC_TEST_ENABLE\r
1762 #include "hevc_test_inc/pps_00.h"\r
1763 #include "hevc_test_inc/register_00.h"\r
1764 #include "hevc_test_inc/rps_00.h"\r
1765 #include "hevc_test_inc/scaling_list_00.h"\r
1766 #include "hevc_test_inc/stream_00.h"\r
1767 \r
1768 #include "hevc_test_inc/pps_01.h"\r
1769 #include "hevc_test_inc/register_01.h"\r
1770 #include "hevc_test_inc/rps_01.h"\r
1771 #include "hevc_test_inc/scaling_list_01.h"\r
1772 #include "hevc_test_inc/stream_01.h"\r
1773 \r
1774 #include "hevc_test_inc/cabac.h"\r
1775 \r
1776 #define TEST_CNT    2\r
1777 static int hevc_test_case0(vpu_service_info *pservice)\r
1778 {\r
1779     vpu_session session;\r
1780     vpu_reg *reg; \r
1781     unsigned long size = sizeof(register_00); // registers array length\r
1782     int testidx = 0;\r
1783     int ret = 0;\r
1784 \r
1785     u8 *pps_tbl[TEST_CNT];\r
1786     u8 *register_tbl[TEST_CNT];\r
1787     u8 *rps_tbl[TEST_CNT];\r
1788     u8 *scaling_list_tbl[TEST_CNT];\r
1789     u8 *stream_tbl[TEST_CNT];\r
1790 \r
1791     int stream_size[2];\r
1792 \r
1793     u32 phy_pps;\r
1794     u32 phy_rps;\r
1795     u32 phy_scl;\r
1796     u32 phy_str;\r
1797     u32 phy_yuv;\r
1798     u32 phy_cabac;\r
1799 \r
1800     u8 *pps;\r
1801     u8 *yuv;\r
1802     int i;\r
1803     \r
1804     pps_tbl[0] = pps_00;\r
1805     pps_tbl[1] = pps_01;\r
1806 \r
1807     register_tbl[0] = register_00;\r
1808     register_tbl[1] = register_01;\r
1809     \r
1810     rps_tbl[0] = rps_00;\r
1811     rps_tbl[1] = rps_01;\r
1812     \r
1813     scaling_list_tbl[0] = scaling_list_00;\r
1814     scaling_list_tbl[1] = scaling_list_01;\r
1815 \r
1816     stream_tbl[0] = stream_00;\r
1817     stream_tbl[1] = stream_01;\r
1818 \r
1819     stream_size[0] = sizeof(stream_00);\r
1820     stream_size[1] = sizeof(stream_01);\r
1821 \r
1822     // create session\r
1823     session.pid = current->pid;\r
1824     session.type = VPU_DEC;\r
1825     INIT_LIST_HEAD(&session.waiting);\r
1826         INIT_LIST_HEAD(&session.running);\r
1827         INIT_LIST_HEAD(&session.done);\r
1828         INIT_LIST_HEAD(&session.list_session);\r
1829         init_waitqueue_head(&session.wait);\r
1830         atomic_set(&session.task_running, 0);\r
1831         list_add_tail(&session.list_session, &pservice->session);\r
1832 \r
1833     while (testidx < TEST_CNT) {\r
1834         // create registers\r
1835         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
1836         if (NULL == reg) {\r
1837             pr_err("error: kmalloc fail in reg_init\n");\r
1838             return -1;\r
1839         }\r
1840 \r
1841         if (size > pservice->reg_size) {\r
1842             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
1843             size = pservice->reg_size;\r
1844         }\r
1845         reg->session = &session;\r
1846         reg->type = session.type;\r
1847         reg->size = size;\r
1848         reg->freq = VPU_FREQ_DEFAULT;\r
1849         reg->reg = (unsigned long *)&reg[1];\r
1850         INIT_LIST_HEAD(&reg->session_link);\r
1851         INIT_LIST_HEAD(&reg->status_link);\r
1852 \r
1853         pps = kmalloc(sizeof(pps_00), GFP_KERNEL);\r
1854         yuv = kzalloc(256*256*3/2, GFP_KERNEL);\r
1855         memcpy(pps, pps_tbl[testidx], sizeof(pps_00));\r
1856 \r
1857         // TODO: stuff registers\r
1858         memcpy(&reg->reg[0], register_tbl[testidx], sizeof(register_00));\r
1859 \r
1860         // TODO: replace reigster address\r
1861         phy_pps = virt_to_phys(pps);\r
1862         phy_rps = virt_to_phys(rps_tbl[testidx]);\r
1863         phy_scl = virt_to_phys(scaling_list_tbl[testidx]);\r
1864         phy_str = virt_to_phys(stream_tbl[testidx]);\r
1865         phy_yuv = virt_to_phys(yuv);\r
1866         phy_cabac = virt_to_phys(Cabac_table);\r
1867 \r
1868         for (i=0; i<64; i++) {\r
1869             u32 scaling_offset;\r
1870             u32 tmp;\r
1871 \r
1872             scaling_offset = (u32)pps[i*80+74];\r
1873             scaling_offset += (u32)pps[i*80+75] << 8;\r
1874             scaling_offset += (u32)pps[i*80+76] << 16;\r
1875             scaling_offset += (u32)pps[i*80+77] << 24;\r
1876 \r
1877             tmp = phy_scl + scaling_offset;\r
1878 \r
1879             pps[i*80+74] = tmp & 0xff;\r
1880             pps[i*80+75] = (tmp >> 8) & 0xff;\r
1881             pps[i*80+76] = (tmp >> 16) & 0xff;\r
1882             pps[i*80+77] = (tmp >> 24) & 0xff;\r
1883         }\r
1884 \r
1885         dmac_flush_range(&pps[0], &pps[sizeof(pps_00) - 1]);\r
1886         outer_flush_range(phy_pps, phy_pps + sizeof(pps_00) - 1);\r
1887 \r
1888         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
1889 \r
1890         reg->reg[4] = phy_str;\r
1891         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
1892         reg->reg[6] = phy_cabac;\r
1893         reg->reg[7] = phy_yuv;\r
1894         reg->reg[42] = phy_pps;\r
1895         reg->reg[43] = phy_rps;\r
1896 \r
1897         mutex_lock(&pservice->lock);\r
1898         list_add_tail(&reg->status_link, &pservice->waiting);\r
1899         list_add_tail(&reg->session_link, &session.waiting);\r
1900         mutex_unlock(&pservice->lock);\r
1901 \r
1902         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
1903 \r
1904         // stuff hardware\r
1905         try_set_reg(pservice);\r
1906 \r
1907         // wait for result\r
1908         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
1909         if (!list_empty(&session.done)) {\r
1910             if (ret < 0) {\r
1911                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
1912             }\r
1913             ret = 0;\r
1914         } else {\r
1915             if (unlikely(ret < 0)) {\r
1916                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
1917             } else if (0 == ret) {\r
1918                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
1919                 ret = -ETIMEDOUT;\r
1920             }\r
1921         }\r
1922         if (ret < 0) {\r
1923             int task_running = atomic_read(&session.task_running);\r
1924             int n;\r
1925             mutex_lock(&pservice->lock);\r
1926             vpu_service_dump(pservice);\r
1927             if (task_running) {\r
1928                 atomic_set(&session.task_running, 0);\r
1929                 atomic_sub(task_running, &pservice->total_running);\r
1930                 printk("%d task is running but not return, reset hardware...", task_running);\r
1931                 vpu_reset(pservice);\r
1932                 printk("done\n");\r
1933             }\r
1934             vpu_service_session_clear(pservice, &session);\r
1935             mutex_unlock(&pservice->lock);\r
1936 \r
1937             printk("\nDEC Registers:\n");\r
1938                 n = pservice->dec_dev.iosize >> 2;\r
1939                 for (i=0; i<n; i++) {\r
1940                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
1941                 }\r
1942 \r
1943             pr_err("test index %d failed\n", testidx);\r
1944             kfree(pps);\r
1945             kfree(yuv);\r
1946             break;\r
1947         } else {\r
1948             pr_info("test index %d success\n", testidx);\r
1949 \r
1950             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
1951 \r
1952             for (i=0; i<68; i++) {\r
1953                 if (i % 4 == 0) {\r
1954                     printk("%02d: ", i);\r
1955                 }\r
1956                 printk("%08x ", reg->reg[i]);\r
1957                 if ((i+1) % 4 == 0) {\r
1958                     printk("\n");\r
1959                 }\r
1960             }\r
1961 \r
1962             testidx++;\r
1963         }\r
1964 \r
1965         reg_deinit(pservice, reg);\r
1966         kfree(pps);\r
1967         kfree(yuv);\r
1968     }\r
1969 \r
1970     return 0;\r
1971 }\r
1972 \r
1973 #endif\r
1974 \r