arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/clk.h>
  20 #include <linux/compat.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/fs.h>
  28 #include <linux/ioport.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/mm.h>
  31 #include <linux/poll.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35 #include <linux/wakelock.h>
  36 #include <linux/cdev.h>
  37 #include <linux/of.h>
  38 #include <linux/of_platform.h>
  39 #include <linux/of_irq.h>
  40 #include <linux/rockchip/cpu.h>
  41 #include <linux/rockchip/cru.h>
  42 #ifdef CONFIG_MFD_SYSCON
  43 #include <linux/regmap.h>
  44 #endif
  45 #include <linux/mfd/syscon.h>
  46
  47 #include <asm/cacheflush.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/rockchip/grf.h>
  50
  51 #if defined(CONFIG_ION_ROCKCHIP)
  52 #include <linux/rockchip_ion.h>
  53 #endif
  54
  55 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  56 #define CONFIG_VCODEC_MMU
  57 #endif
  58
  59 #ifdef CONFIG_VCODEC_MMU
  60 #include <linux/rockchip-iovmm.h>
  61 #include <linux/dma-buf.h>
  62 #endif
  63
  64 #ifdef CONFIG_DEBUG_FS
  65 #include <linux/debugfs.h>
  66 #endif
  67
  68 #if defined(CONFIG_ARCH_RK319X)
  69 #include <mach/grf.h>
  70 #endif
  71
  72 #include "vcodec_service.h"
  73
  74 /*
  75  * debug flag usage:
  76  * +------+-------------------+
  77  * | 8bit |      24bit        |
  78  * +------+-------------------+
  79  *  0~23 bit is for different information type
  80  * 24~31 bit is for information print format
  81  */
  82
  83 #define DEBUG_POWER                             0x00000001
  84 #define DEBUG_CLOCK                             0x00000002
  85 #define DEBUG_IRQ_STATUS                        0x00000004
  86 #define DEBUG_IOMMU                             0x00000008
  87 #define DEBUG_IOCTL                             0x00000010
  88 #define DEBUG_FUNCTION                          0x00000020
  89 #define DEBUG_REGISTER                          0x00000040
  90 #define DEBUG_EXTRA_INFO                        0x00000080
  91 #define DEBUG_TIMING                            0x00000100
  92
  93 #define PRINT_FUNCTION                          0x80000000
  94 #define PRINT_LINE                              0x40000000
  95
  96 static int debug;
  97 module_param(debug, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(debug,
  99                  "Debug level - higher value produces more verbose messages");
 100
 101 #define HEVC_TEST_ENABLE        0
 102 #define VCODEC_CLOCK_ENABLE     1
 103
 104 typedef enum {
 105         VPU_DEC_ID_9190         = 0x6731,
 106         VPU_ID_8270             = 0x8270,
 107         VPU_ID_4831             = 0x4831,
 108         HEVC_ID                 = 0x6867,
 109 } VPU_HW_ID;
 110
 111 enum VPU_HW_SPEC {
 112         VPU_TYPE_VPU,
 113         VPU_TYPE_HEVC,
 114         VPU_TYPE_COMBO_NOENC,
 115         VPU_TYPE_COMBO
 116 };
 117
 118 typedef enum {
 119         VPU_DEC_TYPE_9190       = 0,
 120         VPU_ENC_TYPE_8270       = 0x100,
 121         VPU_ENC_TYPE_4831       ,
 122 } VPU_HW_TYPE_E;
 123
 124 typedef enum VPU_FREQ {
 125         VPU_FREQ_200M,
 126         VPU_FREQ_266M,
 127         VPU_FREQ_300M,
 128         VPU_FREQ_400M,
 129         VPU_FREQ_500M,
 130         VPU_FREQ_600M,
 131         VPU_FREQ_DEFAULT,
 132         VPU_FREQ_BUT,
 133 } VPU_FREQ;
 134
 135 typedef struct {
 136         VPU_HW_ID               hw_id;
 137         unsigned long           hw_addr;
 138         unsigned long           enc_offset;
 139         unsigned long           enc_reg_num;
 140         unsigned long           enc_io_size;
 141         unsigned long           dec_offset;
 142         unsigned long           dec_reg_num;
 143         unsigned long           dec_io_size;
 144 } VPU_HW_INFO_E;
 145
 146 struct extra_info_elem {
 147         u32 index;
 148         u32 offset;
 149 };
 150
 151 #define EXTRA_INFO_MAGIC        0x4C4A46
 152
 153 struct extra_info_for_iommu {
 154         u32 magic;
 155         u32 cnt;
 156         struct extra_info_elem elem[20];
 157 };
 158
 159 #define VPU_SERVICE_SHOW_TIME                   0
 160
 161 #if VPU_SERVICE_SHOW_TIME
 162 static struct timeval enc_start, enc_end;
 163 static struct timeval dec_start, dec_end;
 164 static struct timeval pp_start,  pp_end;
 165 #endif
 166
 167 #define MHZ                                     (1000*1000)
 168
 169 #define REG_NUM_9190_DEC                        (60)
 170 #define REG_NUM_9190_PP                         (41)
 171 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 172
 173 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 174
 175 #define REG_NUM_ENC_8270                        (96)
 176 #define REG_SIZE_ENC_8270                       (0x200)
 177 #define REG_NUM_ENC_4831                        (164)
 178 #define REG_SIZE_ENC_4831                       (0x400)
 179
 180 #define REG_NUM_HEVC_DEC                        (68)
 181
 182 #define SIZE_REG(reg)                           ((reg)*4)
 183
 184 static VPU_HW_INFO_E vpu_hw_set[] = {
 185         [0] = {
 186                 .hw_id          = VPU_ID_8270,
 187                 .hw_addr        = 0,
 188                 .enc_offset     = 0x0,
 189                 .enc_reg_num    = REG_NUM_ENC_8270,
 190                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 191                 .dec_offset     = REG_SIZE_ENC_8270,
 192                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 193                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 194         },
 195         [1] = {
 196                 .hw_id          = VPU_ID_4831,
 197                 .hw_addr        = 0,
 198                 .enc_offset     = 0x0,
 199                 .enc_reg_num    = REG_NUM_ENC_4831,
 200                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 201                 .dec_offset     = REG_SIZE_ENC_4831,
 202                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 203                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 204         },
 205         [2] = {
 206                 .hw_id          = HEVC_ID,
 207                 .hw_addr        = 0,
 208                 .dec_offset     = 0x0,
 209                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 210                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 211         },
 212         [3] = {
 213                 .hw_id          = VPU_DEC_ID_9190,
 214                 .hw_addr        = 0,
 215                 .enc_offset     = 0x0,
 216                 .enc_reg_num    = 0,
 217                 .enc_io_size    = 0,
 218                 .dec_offset     = 0,
 219                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 220                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 221         },
 222 };
 223
 224
 225 #define DEC_INTERRUPT_REGISTER                  1
 226 #define PP_INTERRUPT_REGISTER                   60
 227 #define ENC_INTERRUPT_REGISTER                  1
 228
 229 #define DEC_INTERRUPT_BIT                       0x100
 230 #define DEC_BUFFER_EMPTY_BIT                    0x4000
 231 #define PP_INTERRUPT_BIT                        0x100
 232 #define ENC_INTERRUPT_BIT                       0x1
 233
 234 #define HEVC_DEC_INT_RAW_BIT                    0x200
 235 #define HEVC_DEC_STR_ERROR_BIT                  0x4000
 236 #define HEVC_DEC_BUS_ERROR_BIT                  0x2000
 237 #define HEVC_DEC_BUFFER_EMPTY_BIT               0x10000
 238
 239 #define VPU_REG_EN_ENC                          14
 240 #define VPU_REG_ENC_GATE                        2
 241 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 242
 243 #define VPU_REG_EN_DEC                          1
 244 #define VPU_REG_DEC_GATE                        2
 245 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 246 #define VPU_REG_EN_PP                           0
 247 #define VPU_REG_PP_GATE                         1
 248 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 249 #define VPU_REG_EN_DEC_PP                       1
 250 #define VPU_REG_DEC_PP_GATE                     61
 251 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 252
 253 #define DEBUG
 254 #ifdef DEBUG
 255 #define vpu_debug_func(type, fmt, args...)                      \
 256         do {                                                    \
 257                 if (unlikely(debug & type)) {                   \
 258                         pr_info("%s:%d: " fmt,                  \
 259                                  __func__, __LINE__, ##args);   \
 260                 }                                               \
 261         } while (0)
 262 #define vpu_debug(type, fmt, args...)                           \
 263         do {                                                    \
 264                 if (unlikely(debug & type)) {                   \
 265                         pr_info(fmt, ##args);                   \
 266                 }                                               \
 267         } while (0)
 268 #else
 269 #define vpu_debug_func(level, fmt, args...)
 270 #define vpu_debug(level, fmt, args...)
 271 #endif
 272
 273 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
 274 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
 275
 276 #define vpu_err(fmt, args...)                           \
 277                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 278
 279 #if defined(CONFIG_VCODEC_MMU)
 280 static u8 addr_tbl_vpu_h264dec[] = {
 281         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 282         25, 26, 27, 28, 29, 40, 41
 283 };
 284
 285 static u8 addr_tbl_vpu_vp8dec[] = {
 286         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 287 };
 288
 289 static u8 addr_tbl_vpu_vp6dec[] = {
 290         12, 13, 14, 18, 27, 40
 291 };
 292
 293 static u8 addr_tbl_vpu_vc1dec[] = {
 294         12, 13, 14, 15, 16, 17, 27, 41
 295 };
 296
 297 static u8 addr_tbl_vpu_jpegdec[] = {
 298         12, 40, 66, 67
 299 };
 300
 301 static u8 addr_tbl_vpu_defaultdec[] = {
 302         12, 13, 14, 15, 16, 17, 40, 41
 303 };
 304
 305 static u8 addr_tbl_vpu_enc[] = {
 306         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 307 };
 308
 309 static u8 addr_tbl_hevc_dec[] = {
 310         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 311         21, 22, 23, 24, 42, 43
 312 };
 313 #endif
 314
 315 enum VPU_DEC_FMT {
 316         VPU_DEC_FMT_H264,
 317         VPU_DEC_FMT_MPEG4,
 318         VPU_DEC_FMT_H263,
 319         VPU_DEC_FMT_JPEG,
 320         VPU_DEC_FMT_VC1,
 321         VPU_DEC_FMT_MPEG2,
 322         VPU_DEC_FMT_MPEG1,
 323         VPU_DEC_FMT_VP6,
 324         VPU_DEC_FMT_RV,
 325         VPU_DEC_FMT_VP7,
 326         VPU_DEC_FMT_VP8,
 327         VPU_DEC_FMT_AVS,
 328         VPU_DEC_FMT_SVC,
 329         VPU_DEC_FMT_VC2,
 330         VPU_DEC_FMT_MVC,
 331         VPU_DEC_FMT_THEORA,
 332         VPU_DEC_FMT_RES
 333 };
 334
 335 /**
 336  * struct for process session which connect to vpu
 337  *
 338  * @author ChenHengming (2011-5-3)
 339  */
 340 typedef struct vpu_session {
 341         enum VPU_CLIENT_TYPE type;
 342         /* a linked list of data so we can access them for debugging */
 343         struct list_head list_session;
 344         /* a linked list of register data waiting for process */
 345         struct list_head waiting;
 346         /* a linked list of register data in processing */
 347         struct list_head running;
 348         /* a linked list of register data processed */
 349         struct list_head done;
 350         wait_queue_head_t wait;
 351         pid_t pid;
 352         atomic_t task_running;
 353 } vpu_session;
 354
 355 /**
 356  * struct for process register set
 357  *
 358  * @author ChenHengming (2011-5-4)
 359  */
 360 typedef struct vpu_reg {
 361         enum VPU_CLIENT_TYPE type;
 362         VPU_FREQ freq;
 363         vpu_session *session;
 364         struct vpu_subdev_data *data;
 365         struct list_head session_link;          /* link to vpu service session */
 366         struct list_head status_link;           /* link to register set list */
 367         unsigned long size;
 368 #if defined(CONFIG_VCODEC_MMU)
 369         struct list_head mem_region_list;
 370 #endif
 371         u32 *reg;
 372 } vpu_reg;
 373
 374 typedef struct vpu_device {
 375         atomic_t                irq_count_codec;
 376         atomic_t                irq_count_pp;
 377         unsigned long           iobaseaddr;
 378         unsigned int            iosize;
 379         volatile u32            *hwregs;
 380 } vpu_device;
 381
 382 enum vcodec_device_id {
 383         VCODEC_DEVICE_ID_VPU,
 384         VCODEC_DEVICE_ID_HEVC,
 385         VCODEC_DEVICE_ID_COMBO
 386 };
 387
 388 enum VCODEC_RUNNING_MODE {
 389         VCODEC_RUNNING_MODE_NONE = -1,
 390         VCODEC_RUNNING_MODE_VPU,
 391         VCODEC_RUNNING_MODE_HEVC,
 392 };
 393
 394 struct vcodec_mem_region {
 395         struct list_head srv_lnk;
 396         struct list_head reg_lnk;
 397         struct list_head session_lnk;
 398         unsigned long iova;     /* virtual address for iommu */
 399         unsigned long len;
 400         u32 reg_idx;
 401         struct ion_handle *hdl;
 402 };
 403
 404 enum vpu_ctx_state {
 405         MMU_ACTIVATED   = BIT(0)
 406 };
 407
 408 struct vpu_subdev_data {
 409         struct cdev cdev;
 410         dev_t dev_t;
 411         struct class *cls;
 412         struct device *child_dev;
 413
 414         int irq_enc;
 415         int irq_dec;
 416         struct vpu_service_info *pservice;
 417
 418         u32 *regs;
 419         enum VCODEC_RUNNING_MODE mode;
 420         struct list_head lnk_service;
 421
 422         struct device *dev;
 423
 424         vpu_device enc_dev;
 425         vpu_device dec_dev;
 426         VPU_HW_INFO_E *hw_info;
 427
 428         u32 reg_size;
 429         unsigned long state;
 430
 431 #ifdef CONFIG_DEBUG_FS
 432         struct dentry *debugfs_dir;
 433         struct dentry *debugfs_file_regs;
 434 #endif
 435
 436 #if defined(CONFIG_VCODEC_MMU)
 437         struct device *mmu_dev;
 438 #endif
 439 };
 440
 441 typedef struct vpu_service_info {
 442         struct wake_lock wake_lock;
 443         struct delayed_work power_off_work;
 444         struct mutex lock;
 445         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 446         struct list_head running;               /* link to link_reg in struct vpu_reg */
 447         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 448         struct list_head session;               /* link to list_session in struct vpu_session */
 449         atomic_t total_running;
 450         atomic_t enabled;
 451         atomic_t power_on_cnt;
 452         atomic_t power_off_cnt;
 453         vpu_reg *reg_codec;
 454         vpu_reg *reg_pproc;
 455         vpu_reg *reg_resev;
 456         struct vpu_dec_config dec_config;
 457         struct vpu_enc_config enc_config;
 458
 459         bool auto_freq;
 460         bool bug_dec_addr;
 461         atomic_t freq_status;
 462
 463         struct clk *aclk_vcodec;
 464         struct clk *hclk_vcodec;
 465         struct clk *clk_core;
 466         struct clk *clk_cabac;
 467         struct clk *pd_video;
 468
 469         struct device *dev;
 470
 471         u32 irq_status;
 472 #if defined(CONFIG_VCODEC_MMU)
 473         struct ion_client *ion_client;
 474         struct list_head mem_region_list;
 475 #endif
 476
 477         enum vcodec_device_id dev_id;
 478
 479         enum VCODEC_RUNNING_MODE curr_mode;
 480         u32 prev_mode;
 481
 482         struct delayed_work simulate_work;
 483
 484         u32 mode_bit;
 485         u32 mode_ctrl;
 486         u32 *reg_base;
 487         u32 ioaddr;
 488 #ifdef CONFIG_MFD_SYSCON
 489         struct regmap *grf_base;
 490 #else
 491         u32 *grf_base;
 492 #endif
 493         char *name;
 494
 495         u32 subcnt;
 496         struct list_head subdev_list;
 497 } vpu_service_info;
 498
 499 struct vcodec_combo {
 500         struct vpu_service_info *vpu_srv;
 501         struct vpu_service_info *hevc_srv;
 502         struct list_head waiting;
 503         struct list_head running;
 504         struct mutex run_lock;
 505         vpu_reg *reg_codec;
 506         enum vcodec_device_id current_hw_mode;
 507 };
 508
 509 struct vpu_request {
 510         u32 *req;
 511         u32 size;
 512 };
 513
 514 struct compat_vpu_request {
 515         compat_uptr_t req;
 516         u32 size;
 517 };
 518
 519 /* debugfs root directory for all device (vpu, hevc).*/
 520 static struct dentry *parent;
 521
 522 #ifdef CONFIG_DEBUG_FS
 523 static int vcodec_debugfs_init(void);
 524 static void vcodec_debugfs_exit(void);
 525 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 526 static int debug_vcodec_open(struct inode *inode, struct file *file);
 527
 528 static const struct file_operations debug_vcodec_fops = {
 529         .open = debug_vcodec_open,
 530         .read = seq_read,
 531         .llseek = seq_lseek,
 532         .release = single_release,
 533 };
 534 #endif
 535
 536 #define VDPU_SOFT_RESET_REG     101
 537 #define VDPU_CLEAN_CACHE_REG    516
 538 #define VEPU_CLEAN_CACHE_REG    772
 539 #define HEVC_CLEAN_CACHE_REG    260
 540
 541 #define VPU_REG_ENABLE(base, reg)       do { \
 542                                                 base[reg] = 1; \
 543                                         } while (0)
 544
 545 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 546 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 547 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 548 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 549
 550 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 551 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 552
 553 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 554 {
 555         int bits;
 556         u32 raw = 0;
 557         struct vpu_service_info *pservice = data->pservice;
 558         struct vpu_subdev_data *subdata, *n;
 559         if (pservice->subcnt < 2) {
 560 #if defined(CONFIG_VCODEC_MMU)
 561                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 562                         set_bit(MMU_ACTIVATED, &data->state);
 563                         if (atomic_read(&pservice->enabled))
 564                                 rockchip_iovmm_activate(data->dev);
 565                         else
 566                                 BUG_ON(!atomic_read(&pservice->enabled));
 567                 }
 568 #endif
 569                 return;
 570         }
 571
 572         if (pservice->curr_mode == data->mode)
 573                 return;
 574
 575         vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
 576 #if defined(CONFIG_VCODEC_MMU)
 577         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 578                 if (data != subdata && subdata->mmu_dev &&
 579                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 580                         clear_bit(MMU_ACTIVATED, &subdata->state);
 581                         rockchip_iovmm_deactivate(subdata->dev);
 582                 }
 583         }
 584 #endif
 585         bits = 1 << pservice->mode_bit;
 586 #ifdef CONFIG_MFD_SYSCON
 587         regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
 588
 589         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 590                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 591                         raw | bits | (bits << 16));
 592         else
 593                 regmap_write(pservice->grf_base, pservice->mode_ctrl,
 594                         (raw & (~bits)) | (bits << 16));
 595 #else
 596         raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 597         if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 598                 writel_relaxed(raw | bits | (bits << 16),
 599                         pservice->grf_base + pservice->mode_ctrl / 4);
 600         else
 601                 writel_relaxed((raw & (~bits)) | (bits << 16),
 602                         pservice->grf_base + pservice->mode_ctrl / 4);
 603 #endif
 604 #if defined(CONFIG_VCODEC_MMU)
 605         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 606                 set_bit(MMU_ACTIVATED, &data->state);
 607                 if (atomic_read(&pservice->enabled))
 608                         rockchip_iovmm_activate(data->dev);
 609                 else
 610                         BUG_ON(!atomic_read(&pservice->enabled));
 611         }
 612 #endif
 613         pservice->prev_mode = pservice->curr_mode;
 614         pservice->curr_mode = data->mode;
 615 }
 616
 617 static void vcodec_exit_mode(struct vpu_subdev_data *data)
 618 {
 619         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 620                 clear_bit(MMU_ACTIVATED, &data->state);
 621                 rockchip_iovmm_deactivate(data->dev);
 622                 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 623         }
 624 }
 625
 626 static int vpu_get_clk(struct vpu_service_info *pservice)
 627 {
 628 #if VCODEC_CLOCK_ENABLE
 629         switch (pservice->dev_id) {
 630         case VCODEC_DEVICE_ID_HEVC:
 631                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 632                 if (IS_ERR(pservice->pd_video)) {
 633                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 634                         return -1;
 635                 }
 636         case VCODEC_DEVICE_ID_COMBO:
 637                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 638                 if (IS_ERR(pservice->clk_cabac)) {
 639                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 640                         pservice->clk_cabac = NULL;
 641                 }
 642                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 643                 if (IS_ERR(pservice->clk_core)) {
 644                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 645                         return -1;
 646                 }
 647         case VCODEC_DEVICE_ID_VPU:
 648                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 649                 if (IS_ERR(pservice->aclk_vcodec)) {
 650                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 651                         return -1;
 652                 }
 653
 654                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 655                 if (IS_ERR(pservice->hclk_vcodec)) {
 656                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 657                         return -1;
 658                 }
 659                 if (pservice->pd_video == NULL) {
 660                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 661                         if (IS_ERR(pservice->pd_video)) {
 662                                 pservice->pd_video = NULL;
 663                                 dev_info(pservice->dev, "do not have pd_video\n");
 664                         }
 665                 }
 666                 break;
 667         default:
 668                 ;
 669         }
 670
 671         return 0;
 672 #else
 673         return 0;
 674 #endif
 675 }
 676
 677 static void vpu_put_clk(struct vpu_service_info *pservice)
 678 {
 679 #if VCODEC_CLOCK_ENABLE
 680         if (pservice->pd_video)
 681                 devm_clk_put(pservice->dev, pservice->pd_video);
 682         if (pservice->aclk_vcodec)
 683                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 684         if (pservice->hclk_vcodec)
 685                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 686         if (pservice->clk_core)
 687                 devm_clk_put(pservice->dev, pservice->clk_core);
 688         if (pservice->clk_cabac)
 689                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 690 #endif
 691 }
 692
 693 static void vpu_reset(struct vpu_subdev_data *data)
 694 {
 695         struct vpu_service_info *pservice = data->pservice;
 696         pr_info("%s: resetting...", dev_name(pservice->dev));
 697
 698 #if defined(CONFIG_ARCH_RK29)
 699         clk_disable(aclk_ddr_vepu);
 700         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 701         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 702         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 703         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 704         mdelay(10);
 705         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 706         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 707         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 708         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 709         clk_enable(aclk_ddr_vepu);
 710 #elif defined(CONFIG_ARCH_RK30)
 711         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 712         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 713         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 714         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 715         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 716         mdelay(1);
 717         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 718         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 719         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 720         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 721         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 722 #endif
 723         pservice->reg_codec = NULL;
 724         pservice->reg_pproc = NULL;
 725         pservice->reg_resev = NULL;
 726
 727 #if defined(CONFIG_VCODEC_MMU)
 728         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 729                 clear_bit(MMU_ACTIVATED, &data->state);
 730                 if (atomic_read(&pservice->enabled))
 731                         rockchip_iovmm_deactivate(data->dev);
 732                 else
 733                         BUG_ON(!atomic_read(&pservice->enabled));
 734         }
 735 #endif
 736 }
 737
 738 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 739 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 740 {
 741         vpu_reg *reg, *n;
 742         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 743                 reg_deinit(data, reg);
 744         }
 745         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 746                 reg_deinit(data, reg);
 747         }
 748         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 749                 reg_deinit(data, reg);
 750         }
 751 }
 752
 753 static void vpu_service_dump(struct vpu_service_info *pservice)
 754 {
 755 }
 756
 757 static void vpu_service_power_off(struct vpu_service_info *pservice)
 758 {
 759         int total_running;
 760         struct vpu_subdev_data *data = NULL, *n;
 761         int ret = atomic_add_unless(&pservice->enabled, -1, 0);
 762         if (!ret)
 763                 return;
 764
 765         total_running = atomic_read(&pservice->total_running);
 766         if (total_running) {
 767                 pr_alert("alert: power off when %d task running!!\n", total_running);
 768                 mdelay(50);
 769                 pr_alert("alert: delay 50 ms for running task\n");
 770                 vpu_service_dump(pservice);
 771         }
 772
 773         pr_info("%s: power off...", dev_name(pservice->dev));
 774         udelay(10);
 775 #if defined(CONFIG_VCODEC_MMU)
 776         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 777                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 778                         clear_bit(MMU_ACTIVATED, &data->state);
 779                         rockchip_iovmm_deactivate(data->dev);
 780                 }
 781         }
 782         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 783 #endif
 784
 785 #if VCODEC_CLOCK_ENABLE
 786         if (pservice->pd_video)
 787                 clk_disable_unprepare(pservice->pd_video);
 788         if (pservice->hclk_vcodec)
 789                 clk_disable_unprepare(pservice->hclk_vcodec);
 790         if (pservice->aclk_vcodec)
 791                 clk_disable_unprepare(pservice->aclk_vcodec);
 792         if (pservice->clk_core)
 793                 clk_disable_unprepare(pservice->clk_core);
 794         if (pservice->clk_cabac)
 795                 clk_disable_unprepare(pservice->clk_cabac);
 796 #endif
 797
 798         atomic_add(1, &pservice->power_off_cnt);
 799         wake_unlock(&pservice->wake_lock);
 800         pr_info("done\n");
 801 }
 802
 803 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 804 {
 805         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 806 }
 807
 808 static void vpu_power_off_work(struct work_struct *work_s)
 809 {
 810         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 811         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 812
 813         if (mutex_trylock(&pservice->lock)) {
 814                 vpu_service_power_off(pservice);
 815                 mutex_unlock(&pservice->lock);
 816         } else {
 817                 /* Come back later if the device is busy... */
 818                 vpu_queue_power_off_work(pservice);
 819         }
 820 }
 821
 822 static void vpu_service_power_on(struct vpu_service_info *pservice)
 823 {
 824         int ret;
 825         static ktime_t last;
 826         ktime_t now = ktime_get();
 827         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 828                 cancel_delayed_work_sync(&pservice->power_off_work);
 829                 vpu_queue_power_off_work(pservice);
 830                 last = now;
 831         }
 832         ret = atomic_add_unless(&pservice->enabled, 1, 1);
 833         if (!ret)
 834                 return ;
 835
 836         pr_info("%s: power on\n", dev_name(pservice->dev));
 837
 838 #define BIT_VCODEC_CLK_SEL      (1<<10)
 839         if (cpu_is_rk312x())
 840                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 841                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 842                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 843
 844 #if VCODEC_CLOCK_ENABLE
 845         if (pservice->aclk_vcodec)
 846                 clk_prepare_enable(pservice->aclk_vcodec);
 847         if (pservice->hclk_vcodec)
 848                 clk_prepare_enable(pservice->hclk_vcodec);
 849         if (pservice->clk_core)
 850                 clk_prepare_enable(pservice->clk_core);
 851         if (pservice->clk_cabac)
 852                 clk_prepare_enable(pservice->clk_cabac);
 853         if (pservice->pd_video)
 854                 clk_prepare_enable(pservice->pd_video);
 855 #endif
 856
 857         udelay(10);
 858         atomic_add(1, &pservice->power_on_cnt);
 859         wake_lock(&pservice->wake_lock);
 860 }
 861
 862 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 863 {
 864         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 865         return ((type == 8) || (type == 4));
 866 }
 867
 868 static inline bool reg_check_interlace(vpu_reg *reg)
 869 {
 870         u32 type = (reg->reg[3] & (1 << 23));
 871         return (type > 0);
 872 }
 873
 874 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
 875 {
 876         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
 877         return type;
 878 }
 879
 880 static inline int reg_probe_width(vpu_reg *reg)
 881 {
 882         int width_in_mb = reg->reg[4] >> 23;
 883         return width_in_mb * 16;
 884 }
 885
 886 #if defined(CONFIG_VCODEC_MMU)
 887 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
 888 {
 889         struct vpu_service_info *pservice = data->pservice;
 890         struct ion_handle *hdl;
 891         int ret = 0;
 892         struct vcodec_mem_region *mem_region;
 893
 894         hdl = ion_import_dma_buf(pservice->ion_client, fd);
 895         if (IS_ERR(hdl)) {
 896                 vpu_err("import dma-buf from fd %d failed\n", fd);
 897                 return PTR_ERR(hdl);
 898         }
 899         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 900
 901         if (mem_region == NULL) {
 902                 vpu_err("allocate memory for iommu memory region failed\n");
 903                 ion_free(pservice->ion_client, hdl);
 904                 return -1;
 905         }
 906
 907         mem_region->hdl = hdl;
 908         ret = ion_map_iommu(data->dev, pservice->ion_client,
 909                 mem_region->hdl, &mem_region->iova, &mem_region->len);
 910
 911         if (ret < 0) {
 912                 vpu_err("ion map iommu failed\n");
 913                 kfree(mem_region);
 914                 ion_free(pservice->ion_client, hdl);
 915                 return ret;
 916         }
 917         INIT_LIST_HEAD(&mem_region->reg_lnk);
 918         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
 919         return mem_region->iova;
 920 }
 921
 922 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
 923                                 int size, vpu_reg *reg,
 924                                 struct extra_info_for_iommu *ext_inf)
 925 {
 926         struct vpu_service_info *pservice = data->pservice;
 927         int i;
 928         int usr_fd = 0;
 929         int offset = 0;
 930
 931         if (tbl == NULL || size <= 0) {
 932                 dev_err(pservice->dev, "input arguments invalidate\n");
 933                 return -1;
 934         }
 935
 936         for (i = 0; i < size; i++) {
 937                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
 938
 939                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
 940                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
 941                         /* special for vpu dec num 41 regitster */
 942                         offset = reg->reg[tbl[i]] >> 10 << 4;
 943                 else
 944                         offset = reg->reg[tbl[i]] >> 10;
 945
 946                 if (usr_fd != 0) {
 947                         struct ion_handle *hdl;
 948                         int ret = 0;
 949                         struct vcodec_mem_region *mem_region;
 950
 951                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
 952                         if (IS_ERR(hdl)) {
 953                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
 954                                 return PTR_ERR(hdl);
 955                         }
 956
 957                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
 958                                 int i = 0;
 959                                 char *pps;
 960                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
 961                                 for (i=0; i<64; i++) {
 962                                         u32 scaling_offset;
 963                                         u32 tmp;
 964                                         int scaling_fd= 0;
 965                                         scaling_offset = (u32)pps[i*80+74];
 966                                         scaling_offset += (u32)pps[i*80+75] << 8;
 967                                         scaling_offset += (u32)pps[i*80+76] << 16;
 968                                         scaling_offset += (u32)pps[i*80+77] << 24;
 969                                         scaling_fd = scaling_offset&0x3ff;
 970                                         scaling_offset = scaling_offset >> 10;
 971                                         if(scaling_fd > 0) {
 972                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
 973                                                 tmp += scaling_offset;
 974                                                 pps[i*80+74] = tmp & 0xff;
 975                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
 976                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
 977                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
 978                                         }
 979                                 }
 980                         }
 981
 982                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
 983
 984                         if (mem_region == NULL) {
 985                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
 986                                 ion_free(pservice->ion_client, hdl);
 987                                 return -1;
 988                         }
 989
 990                         mem_region->hdl = hdl;
 991                         mem_region->reg_idx = tbl[i];
 992                         ret = ion_map_iommu(data->dev,
 993                                             pservice->ion_client,
 994                                             mem_region->hdl,
 995                                             &mem_region->iova,
 996                                             &mem_region->len);
 997
 998                         if (ret < 0) {
 999                                 dev_err(pservice->dev, "ion map iommu failed\n");
1000                                 kfree(mem_region);
1001                                 ion_free(pservice->ion_client, hdl);
1002                                 return ret;
1003                         }
1004                         reg->reg[tbl[i]] = mem_region->iova + offset;
1005                         INIT_LIST_HEAD(&mem_region->reg_lnk);
1006                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1007                 }
1008         }
1009
1010         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1011                 for (i=0; i<ext_inf->cnt; i++) {
1012                         vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1013                                   ext_inf->elem[i].index,
1014                                   ext_inf->elem[i].offset);
1015                         reg->reg[ext_inf->elem[i].index] +=
1016                                 ext_inf->elem[i].offset;
1017                 }
1018         }
1019
1020         return 0;
1021 }
1022
1023 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1024                                         vpu_reg *reg,
1025                                         struct extra_info_for_iommu *ext_inf)
1026 {
1027         VPU_HW_ID hw_id;
1028         u8 *tbl;
1029         int size = 0;
1030
1031         hw_id = data->hw_info->hw_id;
1032
1033         if (hw_id == HEVC_ID) {
1034                 tbl = addr_tbl_hevc_dec;
1035                 size = sizeof(addr_tbl_hevc_dec);
1036         } else {
1037                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1038                         switch (reg_check_fmt(reg)) {
1039                         case VPU_DEC_FMT_H264:
1040                                 {
1041                                         tbl = addr_tbl_vpu_h264dec;
1042                                         size = sizeof(addr_tbl_vpu_h264dec);
1043                                         break;
1044                                 }
1045                         case VPU_DEC_FMT_VP8:
1046                         case VPU_DEC_FMT_VP7:
1047                                 {
1048                                         tbl = addr_tbl_vpu_vp8dec;
1049                                         size = sizeof(addr_tbl_vpu_vp8dec);
1050                                         break;
1051                                 }
1052
1053                         case VPU_DEC_FMT_VP6:
1054                                 {
1055                                         tbl = addr_tbl_vpu_vp6dec;
1056                                         size = sizeof(addr_tbl_vpu_vp6dec);
1057                                         break;
1058                                 }
1059                         case VPU_DEC_FMT_VC1:
1060                                 {
1061                                         tbl = addr_tbl_vpu_vc1dec;
1062                                         size = sizeof(addr_tbl_vpu_vc1dec);
1063                                         break;
1064                                 }
1065
1066                         case VPU_DEC_FMT_JPEG:
1067                                 {
1068                                         tbl = addr_tbl_vpu_jpegdec;
1069                                         size = sizeof(addr_tbl_vpu_jpegdec);
1070                                         break;
1071                                 }
1072                         default:
1073                                 tbl = addr_tbl_vpu_defaultdec;
1074                                 size = sizeof(addr_tbl_vpu_defaultdec);
1075                                 break;
1076                         }
1077                 } else if (reg->type == VPU_ENC) {
1078                         tbl = addr_tbl_vpu_enc;
1079                         size = sizeof(addr_tbl_vpu_enc);
1080                 }
1081         }
1082
1083         if (size != 0) {
1084                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1085         } else {
1086                 return -1;
1087         }
1088 }
1089 #endif
1090
1091 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1092         vpu_session *session, void __user *src, u32 size)
1093 {
1094         struct vpu_service_info *pservice = data->pservice;
1095         int extra_size = 0;
1096         struct extra_info_for_iommu extra_info;
1097         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1098
1099         vpu_debug_enter();
1100
1101         if (NULL == reg) {
1102                 vpu_err("error: kmalloc fail in reg_init\n");
1103                 return NULL;
1104         }
1105
1106         if (size > data->reg_size) {
1107                 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1108                   size, data->reg_size);*/
1109                 extra_size = size - data->reg_size;
1110                 size = data->reg_size;
1111         }
1112         reg->session = session;
1113         reg->data = data;
1114         reg->type = session->type;
1115         reg->size = size;
1116         reg->freq = VPU_FREQ_DEFAULT;
1117         reg->reg = (u32 *)&reg[1];
1118         INIT_LIST_HEAD(&reg->session_link);
1119         INIT_LIST_HEAD(&reg->status_link);
1120
1121 #if defined(CONFIG_VCODEC_MMU)
1122         if (data->mmu_dev)
1123                 INIT_LIST_HEAD(&reg->mem_region_list);
1124 #endif
1125
1126         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1127                 vpu_err("error: copy_from_user failed in reg_init\n");
1128                 kfree(reg);
1129                 return NULL;
1130         }
1131
1132         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1133                 vpu_err("error: copy_from_user failed in reg_init\n");
1134                 kfree(reg);
1135                 return NULL;
1136         }
1137
1138 #if defined(CONFIG_VCODEC_MMU)
1139         if (data->mmu_dev &&
1140             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1141                 vpu_err("error: translate reg address failed\n");
1142                 kfree(reg);
1143                 return NULL;
1144         }
1145 #endif
1146
1147         mutex_lock(&pservice->lock);
1148         list_add_tail(&reg->status_link, &pservice->waiting);
1149         list_add_tail(&reg->session_link, &session->waiting);
1150         mutex_unlock(&pservice->lock);
1151
1152         if (pservice->auto_freq) {
1153                 if (!soc_is_rk2928g()) {
1154                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1155                                 if (reg_check_rmvb_wmv(reg)) {
1156                                         reg->freq = VPU_FREQ_200M;
1157                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1158                                         if (reg_probe_width(reg) > 3200) {
1159                                                 /*raise frequency for 4k avc.*/
1160                                                 reg->freq = VPU_FREQ_500M;
1161                                         }
1162                                 } else {
1163                                         if (reg_check_interlace(reg)) {
1164                                                 reg->freq = VPU_FREQ_400M;
1165                                         }
1166                                 }
1167                         }
1168                         if (reg->type == VPU_PP) {
1169                                 reg->freq = VPU_FREQ_400M;
1170                         }
1171                 }
1172         }
1173         vpu_debug_leave();
1174         return reg;
1175 }
1176
1177 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1178 {
1179         struct vpu_service_info *pservice = data->pservice;
1180 #if defined(CONFIG_VCODEC_MMU)
1181         struct vcodec_mem_region *mem_region = NULL, *n;
1182 #endif
1183
1184         list_del_init(&reg->session_link);
1185         list_del_init(&reg->status_link);
1186         if (reg == pservice->reg_codec)
1187                 pservice->reg_codec = NULL;
1188         if (reg == pservice->reg_pproc)
1189                 pservice->reg_pproc = NULL;
1190
1191 #if defined(CONFIG_VCODEC_MMU)
1192         /* release memory region attach to this registers table. */
1193         if (data->mmu_dev) {
1194                 list_for_each_entry_safe(mem_region, n,
1195                         &reg->mem_region_list, reg_lnk) {
1196                         /* do not unmap iommu manually,
1197                            unmap will proccess when memory release */
1198                         /*vcodec_enter_mode(data);
1199                         ion_unmap_iommu(data->dev,
1200                                         pservice->ion_client,
1201                                         mem_region->hdl);
1202                         vcodec_exit_mode();*/
1203                         ion_free(pservice->ion_client, mem_region->hdl);
1204                         list_del_init(&mem_region->reg_lnk);
1205                         kfree(mem_region);
1206                 }
1207         }
1208 #endif
1209
1210         kfree(reg);
1211 }
1212
1213 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1214 {
1215         vpu_debug_enter();
1216         list_del_init(&reg->status_link);
1217         list_add_tail(&reg->status_link, &pservice->running);
1218
1219         list_del_init(&reg->session_link);
1220         list_add_tail(&reg->session_link, &reg->session->running);
1221         vpu_debug_leave();
1222 }
1223
1224 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1225 {
1226         int i;
1227         u32 *dst = (u32 *)&reg->reg[0];
1228         vpu_debug_enter();
1229         for (i = 0; i < count; i++)
1230                 *dst++ = *src++;
1231         vpu_debug_leave();
1232 }
1233
1234 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1235         vpu_reg *reg)
1236 {
1237         struct vpu_service_info *pservice = data->pservice;
1238         int irq_reg = -1;
1239
1240         vpu_debug_enter();
1241
1242         list_del_init(&reg->status_link);
1243         list_add_tail(&reg->status_link, &pservice->done);
1244
1245         list_del_init(&reg->session_link);
1246         list_add_tail(&reg->session_link, &reg->session->done);
1247
1248         /*vcodec_enter_mode(data);*/
1249         switch (reg->type) {
1250         case VPU_ENC : {
1251                 pservice->reg_codec = NULL;
1252                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1253                 irq_reg = ENC_INTERRUPT_REGISTER;
1254                 break;
1255         }
1256         case VPU_DEC : {
1257                 int reg_len = REG_NUM_9190_DEC;
1258                 pservice->reg_codec = NULL;
1259                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1260                 irq_reg = DEC_INTERRUPT_REGISTER;
1261                 break;
1262         }
1263         case VPU_PP : {
1264                 pservice->reg_pproc = NULL;
1265                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1266                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1267                 break;
1268         }
1269         case VPU_DEC_PP : {
1270                 pservice->reg_codec = NULL;
1271                 pservice->reg_pproc = NULL;
1272                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1273                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1274                 break;
1275         }
1276         default : {
1277                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1278                 break;
1279         }
1280         }
1281         vcodec_exit_mode(data);
1282
1283         if (irq_reg != -1)
1284                 reg->reg[irq_reg] = pservice->irq_status;
1285
1286         atomic_sub(1, &reg->session->task_running);
1287         atomic_sub(1, &pservice->total_running);
1288         wake_up(&reg->session->wait);
1289
1290         vpu_debug_leave();
1291 }
1292
1293 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1294 {
1295         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1296         if (curr == reg->freq)
1297                 return;
1298         atomic_set(&pservice->freq_status, reg->freq);
1299         switch (reg->freq) {
1300         case VPU_FREQ_200M : {
1301                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1302         } break;
1303         case VPU_FREQ_266M : {
1304                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1305         } break;
1306         case VPU_FREQ_300M : {
1307                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1308         } break;
1309         case VPU_FREQ_400M : {
1310                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1311         } break;
1312         case VPU_FREQ_500M : {
1313                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1314         } break;
1315         case VPU_FREQ_600M : {
1316                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1317         } break;
1318         default : {
1319                 if (soc_is_rk2928g())
1320                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1321                 else
1322                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1323         } break;
1324         }
1325 }
1326
1327 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1328 {
1329         struct vpu_service_info *pservice = data->pservice;
1330         int i;
1331         u32 *src = (u32 *)&reg->reg[0];
1332         vpu_debug_enter();
1333
1334         atomic_add(1, &pservice->total_running);
1335         atomic_add(1, &reg->session->task_running);
1336         if (pservice->auto_freq)
1337                 vpu_service_set_freq(pservice, reg);
1338
1339         vcodec_enter_mode(data);
1340
1341         switch (reg->type) {
1342         case VPU_ENC : {
1343                 int enc_count = data->hw_info->enc_reg_num;
1344                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1345
1346                 pservice->reg_codec = reg;
1347
1348                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1349
1350                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1351                         dst[i] = src[i];
1352
1353                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1354                         dst[i] = src[i];
1355
1356                 VEPU_CLEAN_CACHE(dst);
1357
1358                 dsb(sy);
1359
1360                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1361                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1362
1363 #if VPU_SERVICE_SHOW_TIME
1364                 do_gettimeofday(&enc_start);
1365 #endif
1366
1367         } break;
1368         case VPU_DEC : {
1369                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1370
1371                 pservice->reg_codec = reg;
1372
1373                 if (data->hw_info->hw_id != HEVC_ID) {
1374                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1375                                 dst[i] = src[i];
1376                         VDPU_CLEAN_CACHE(dst);
1377                 } else {
1378                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1379                                 dst[i] = src[i];
1380                         HEVC_CLEAN_CACHE(dst);
1381                 }
1382
1383                 dsb(sy);
1384
1385                 if (data->hw_info->hw_id != HEVC_ID) {
1386                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1387                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1388                 } else {
1389                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1390                 }
1391                 dsb(sy);
1392                 dmb(sy);
1393 #if VPU_SERVICE_SHOW_TIME
1394                 do_gettimeofday(&dec_start);
1395 #endif
1396         } break;
1397         case VPU_PP : {
1398                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1399                 pservice->reg_pproc = reg;
1400
1401                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1402
1403                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1404                         dst[i] = src[i];
1405
1406                 dsb(sy);
1407
1408                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1409 #if VPU_SERVICE_SHOW_TIME
1410                 do_gettimeofday(&pp_start);
1411 #endif
1412
1413         } break;
1414         case VPU_DEC_PP : {
1415                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1416                 pservice->reg_codec = reg;
1417                 pservice->reg_pproc = reg;
1418
1419                 VDPU_SOFT_RESET(dst);
1420                 VDPU_CLEAN_CACHE(dst);
1421
1422                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1423                         dst[i] = src[i];
1424
1425                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1426                 dsb(sy);
1427
1428                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1429                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1430                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1431 #if VPU_SERVICE_SHOW_TIME
1432                 do_gettimeofday(&dec_start);
1433 #endif
1434         } break;
1435         default : {
1436                 vpu_err("error: unsupport session type %d", reg->type);
1437                 atomic_sub(1, &pservice->total_running);
1438                 atomic_sub(1, &reg->session->task_running);
1439                 break;
1440         }
1441         }
1442
1443         /*vcodec_exit_mode(data);*/
1444         vpu_debug_leave();
1445 }
1446
1447 static void try_set_reg(struct vpu_subdev_data *data)
1448 {
1449         struct vpu_service_info *pservice = data->pservice;
1450         vpu_debug_enter();
1451         if (!list_empty(&pservice->waiting)) {
1452                 int can_set = 0;
1453                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1454
1455                 vpu_service_power_on(pservice);
1456
1457                 switch (reg->type) {
1458                 case VPU_ENC : {
1459                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))
1460                                 can_set = 1;
1461                 } break;
1462                 case VPU_DEC : {
1463                         if (NULL == pservice->reg_codec)
1464                                 can_set = 1;
1465                         if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1466                                 can_set = 0;
1467                 } break;
1468                 case VPU_PP : {
1469                         if (NULL == pservice->reg_codec) {
1470                                 if (NULL == pservice->reg_pproc)
1471                                         can_set = 1;
1472                         } else {
1473                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1474                                         can_set = 1;
1475                                 /* can not charge frequency when vpu is working */
1476                                 if (pservice->auto_freq)
1477                                         can_set = 0;
1478                         }
1479                 } break;
1480                 case VPU_DEC_PP : {
1481                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1482                                 can_set = 1;
1483                         } break;
1484                 default : {
1485                         printk("undefined reg type %d\n", reg->type);
1486                 } break;
1487                 }
1488                 if (can_set) {
1489                         reg_from_wait_to_run(pservice, reg);
1490                         reg_copy_to_hw(reg->data, reg);
1491                 }
1492         }
1493         vpu_debug_leave();
1494 }
1495
1496 static int return_reg(struct vpu_subdev_data *data,
1497         vpu_reg *reg, u32 __user *dst)
1498 {
1499         int ret = 0;
1500         vpu_debug_enter();
1501         switch (reg->type) {
1502         case VPU_ENC : {
1503                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1504                         ret = -EFAULT;
1505                 break;
1506         }
1507         case VPU_DEC : {
1508                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1509                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1510                         ret = -EFAULT;
1511                 break;
1512         }
1513         case VPU_PP : {
1514                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1515                         ret = -EFAULT;
1516                 break;
1517         }
1518         case VPU_DEC_PP : {
1519                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1520                         ret = -EFAULT;
1521                 break;
1522         }
1523         default : {
1524                 ret = -EFAULT;
1525                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1526                 break;
1527         }
1528         }
1529         reg_deinit(data, reg);
1530         vpu_debug_leave();
1531         return ret;
1532 }
1533
1534 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1535         unsigned long arg)
1536 {
1537         struct vpu_subdev_data *data =
1538                 container_of(filp->f_dentry->d_inode->i_cdev,
1539                         struct vpu_subdev_data, cdev);
1540         struct vpu_service_info *pservice = data->pservice;
1541         vpu_session *session = (vpu_session *)filp->private_data;
1542         vpu_debug_enter();
1543         if (NULL == session)
1544                 return -EINVAL;
1545
1546         switch (cmd) {
1547         case VPU_IOC_SET_CLIENT_TYPE : {
1548                 session->type = (enum VPU_CLIENT_TYPE)arg;
1549                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1550                 break;
1551         }
1552         case VPU_IOC_GET_HW_FUSE_STATUS : {
1553                 struct vpu_request req;
1554                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1555                 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1556                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1557                         return -EFAULT;
1558                 } else {
1559                         if (VPU_ENC != session->type) {
1560                                 if (copy_to_user((void __user *)req.req,
1561                                         &pservice->dec_config,
1562                                         sizeof(struct vpu_dec_config))) {
1563                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1564                                                 session->type);
1565                                         return -EFAULT;
1566                                 }
1567                         } else {
1568                                 if (copy_to_user((void __user *)req.req,
1569                                         &pservice->enc_config,
1570                                         sizeof(struct vpu_enc_config ))) {
1571                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1572                                                 session->type);
1573                                         return -EFAULT;
1574                                 }
1575                         }
1576                 }
1577
1578                 break;
1579         }
1580         case VPU_IOC_SET_REG : {
1581                 struct vpu_request req;
1582                 vpu_reg *reg;
1583                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1584                 if (copy_from_user(&req, (void __user *)arg,
1585                         sizeof(struct vpu_request))) {
1586                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1587                         return -EFAULT;
1588                 }
1589                 reg = reg_init(data, session,
1590                         (void __user *)req.req, req.size);
1591                 if (NULL == reg) {
1592                         return -EFAULT;
1593                 } else {
1594                         mutex_lock(&pservice->lock);
1595                         try_set_reg(data);
1596                         mutex_unlock(&pservice->lock);
1597                 }
1598
1599                 break;
1600         }
1601         case VPU_IOC_GET_REG : {
1602                 struct vpu_request req;
1603                 vpu_reg *reg;
1604                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1605                 if (copy_from_user(&req, (void __user *)arg,
1606                         sizeof(struct vpu_request))) {
1607                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1608                         return -EFAULT;
1609                 } else {
1610                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1611                         if (!list_empty(&session->done)) {
1612                                 if (ret < 0) {
1613                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1614                                 }
1615                                 ret = 0;
1616                         } else {
1617                                 if (unlikely(ret < 0)) {
1618                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1619                                 } else if (0 == ret) {
1620                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1621                                         ret = -ETIMEDOUT;
1622                                 }
1623                         }
1624                         if (ret < 0) {
1625                                 int task_running = atomic_read(&session->task_running);
1626                                 mutex_lock(&pservice->lock);
1627                                 vpu_service_dump(pservice);
1628                                 if (task_running) {
1629                                         atomic_set(&session->task_running, 0);
1630                                         atomic_sub(task_running, &pservice->total_running);
1631                                         printk("%d task is running but not return, reset hardware...", task_running);
1632                                         vpu_reset(data);
1633                                         printk("done\n");
1634                                 }
1635                                 vpu_service_session_clear(data, session);
1636                                 mutex_unlock(&pservice->lock);
1637                                 return ret;
1638                         }
1639                 }
1640                 mutex_lock(&pservice->lock);
1641                 reg = list_entry(session->done.next, vpu_reg, session_link);
1642                 return_reg(data, reg, (u32 __user *)req.req);
1643                 mutex_unlock(&pservice->lock);
1644                 break;
1645         }
1646         case VPU_IOC_PROBE_IOMMU_STATUS: {
1647                 int iommu_enable = 0;
1648
1649                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1650
1651 #if defined(CONFIG_VCODEC_MMU)
1652                 iommu_enable = data->mmu_dev ? 1 : 0;
1653 #endif
1654
1655                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1656                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1657                         return -EFAULT;
1658                 }
1659                 break;
1660         }
1661         default : {
1662                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1663                 break;
1664         }
1665         }
1666         vpu_debug_leave();
1667         return 0;
1668 }
1669
1670 #ifdef CONFIG_COMPAT
1671 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1672         unsigned long arg)
1673 {
1674         struct vpu_subdev_data *data =
1675                 container_of(filp->f_dentry->d_inode->i_cdev,
1676                         struct vpu_subdev_data, cdev);
1677         struct vpu_service_info *pservice = data->pservice;
1678         vpu_session *session = (vpu_session *)filp->private_data;
1679         vpu_debug_enter();
1680         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1681                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1682         if (NULL == session)
1683                 return -EINVAL;
1684
1685         switch (cmd) {
1686         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1687                 session->type = (enum VPU_CLIENT_TYPE)arg;
1688                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1689                 break;
1690         }
1691         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1692                 struct compat_vpu_request req;
1693                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1694                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1695                                    sizeof(struct compat_vpu_request))) {
1696                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1697                                 " copy_from_user failed\n");
1698                         return -EFAULT;
1699                 } else {
1700                         if (VPU_ENC != session->type) {
1701                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1702                                                  &pservice->dec_config,
1703                                                  sizeof(struct vpu_dec_config))) {
1704                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1705                                                 "copy_to_user failed type %d\n",
1706                                                 session->type);
1707                                         return -EFAULT;
1708                                 }
1709                         } else {
1710                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1711                                                  &pservice->enc_config,
1712                                                  sizeof(struct vpu_enc_config ))) {
1713                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1714                                                 " copy_to_user failed type %d\n",
1715                                                 session->type);
1716                                         return -EFAULT;
1717                                 }
1718                         }
1719                 }
1720
1721                 break;
1722         }
1723         case COMPAT_VPU_IOC_SET_REG : {
1724                 struct compat_vpu_request req;
1725                 vpu_reg *reg;
1726                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1727                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1728                                    sizeof(struct compat_vpu_request))) {
1729                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1730                         return -EFAULT;
1731                 }
1732                 reg = reg_init(data, session,
1733                                compat_ptr((compat_uptr_t)req.req), req.size);
1734                 if (NULL == reg) {
1735                         return -EFAULT;
1736                 } else {
1737                         mutex_lock(&pservice->lock);
1738                         try_set_reg(data);
1739                         mutex_unlock(&pservice->lock);
1740                 }
1741
1742                 break;
1743         }
1744         case COMPAT_VPU_IOC_GET_REG : {
1745                 struct compat_vpu_request req;
1746                 vpu_reg *reg;
1747                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1748                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1749                                    sizeof(struct compat_vpu_request))) {
1750                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1751                         return -EFAULT;
1752                 } else {
1753                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1754                         if (!list_empty(&session->done)) {
1755                                 if (ret < 0) {
1756                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1757                                 }
1758                                 ret = 0;
1759                         } else {
1760                                 if (unlikely(ret < 0)) {
1761                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1762                                 } else if (0 == ret) {
1763                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1764                                         ret = -ETIMEDOUT;
1765                                 }
1766                         }
1767                         if (ret < 0) {
1768                                 int task_running = atomic_read(&session->task_running);
1769                                 mutex_lock(&pservice->lock);
1770                                 vpu_service_dump(pservice);
1771                                 if (task_running) {
1772                                         atomic_set(&session->task_running, 0);
1773                                         atomic_sub(task_running, &pservice->total_running);
1774                                         printk("%d task is running but not return, reset hardware...", task_running);
1775                                         vpu_reset(data);
1776                                         printk("done\n");
1777                                 }
1778                                 vpu_service_session_clear(data, session);
1779                                 mutex_unlock(&pservice->lock);
1780                                 return ret;
1781                         }
1782                 }
1783                 mutex_lock(&pservice->lock);
1784                 reg = list_entry(session->done.next, vpu_reg, session_link);
1785                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1786                 mutex_unlock(&pservice->lock);
1787                 break;
1788         }
1789         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1790                 int iommu_enable = 0;
1791
1792                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1793 #if defined(CONFIG_VCODEC_MMU)
1794                 iommu_enable = data->mmu_dev ? 1 : 0;
1795 #endif
1796
1797                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1798                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1799                         return -EFAULT;
1800                 }
1801                 break;
1802         }
1803         default : {
1804                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1805                 break;
1806         }
1807         }
1808         vpu_debug_leave();
1809         return 0;
1810 }
1811 #endif
1812
1813 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1814 {
1815         int ret = -EINVAL, i = 0;
1816         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1817         u32 enc_id = *tmp;
1818
1819         enc_id = (enc_id >> 16) & 0xFFFF;
1820         pr_info("checking hw id %x\n", enc_id);
1821         data->hw_info = NULL;
1822         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1823                 if (enc_id == vpu_hw_set[i].hw_id) {
1824                         data->hw_info = &vpu_hw_set[i];
1825                         ret = 0;
1826                         break;
1827                 }
1828         }
1829         iounmap((void *)tmp);
1830         return ret;
1831 }
1832
1833 static int vpu_service_open(struct inode *inode, struct file *filp)
1834 {
1835         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1836         struct vpu_service_info *pservice = data->pservice;
1837         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1838
1839         vpu_debug_enter();
1840
1841         if (NULL == session) {
1842                 vpu_err("error: unable to allocate memory for vpu_session.");
1843                 return -ENOMEM;
1844         }
1845
1846         session->type   = VPU_TYPE_BUTT;
1847         session->pid    = current->pid;
1848         INIT_LIST_HEAD(&session->waiting);
1849         INIT_LIST_HEAD(&session->running);
1850         INIT_LIST_HEAD(&session->done);
1851         INIT_LIST_HEAD(&session->list_session);
1852         init_waitqueue_head(&session->wait);
1853         atomic_set(&session->task_running, 0);
1854         mutex_lock(&pservice->lock);
1855         list_add_tail(&session->list_session, &pservice->session);
1856         filp->private_data = (void *)session;
1857         mutex_unlock(&pservice->lock);
1858
1859         pr_debug("dev opened\n");
1860         vpu_debug_leave();
1861         return nonseekable_open(inode, filp);
1862 }
1863
1864 static int vpu_service_release(struct inode *inode, struct file *filp)
1865 {
1866         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1867         struct vpu_service_info *pservice = data->pservice;
1868         int task_running;
1869         vpu_session *session = (vpu_session *)filp->private_data;
1870         vpu_debug_enter();
1871         if (NULL == session)
1872                 return -EINVAL;
1873
1874         task_running = atomic_read(&session->task_running);
1875         if (task_running) {
1876                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1877                 msleep(50);
1878         }
1879         wake_up(&session->wait);
1880
1881         mutex_lock(&pservice->lock);
1882         /* remove this filp from the asynchronusly notified filp's */
1883         list_del_init(&session->list_session);
1884         vpu_service_session_clear(data, session);
1885         kfree(session);
1886         filp->private_data = NULL;
1887         mutex_unlock(&pservice->lock);
1888
1889         pr_debug("dev closed\n");
1890         vpu_debug_leave();
1891         return 0;
1892 }
1893
1894 static const struct file_operations vpu_service_fops = {
1895         .unlocked_ioctl = vpu_service_ioctl,
1896         .open           = vpu_service_open,
1897         .release        = vpu_service_release,
1898 #ifdef CONFIG_COMPAT
1899         .compat_ioctl   = compat_vpu_service_ioctl,
1900 #endif
1901 };
1902
1903 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1904 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1905 static irqreturn_t vepu_irq(int irq, void *dev_id);
1906 static irqreturn_t vepu_isr(int irq, void *dev_id);
1907 static void get_hw_info(struct vpu_subdev_data *data);
1908
1909 #ifdef CONFIG_VCODEC_MMU
1910 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1911 {
1912         struct device_node *dn = NULL;
1913         struct platform_device *pd = NULL;
1914         struct device *ret = NULL ;
1915
1916         dn = of_find_compatible_node(NULL,NULL,compt);
1917         if(!dn) {
1918                 printk("can't find device node %s \r\n",compt);
1919                 return NULL;
1920         }
1921
1922         pd = of_find_device_by_node(dn);
1923         if(!pd) {
1924                 printk("can't find platform device in device node %s\n",compt);
1925                 return  NULL;
1926         }
1927         ret = &pd->dev;
1928
1929         return ret;
1930
1931 }
1932 #ifdef CONFIG_IOMMU_API
1933 static inline void platform_set_sysmmu(struct device *iommu,
1934         struct device *dev)
1935 {
1936         dev->archdata.iommu = iommu;
1937 }
1938 #else
1939 static inline void platform_set_sysmmu(struct device *iommu,
1940         struct device *dev)
1941 {
1942 }
1943 #endif
1944
1945 int vcodec_sysmmu_fault_hdl(struct device *dev,
1946                                 enum rk_iommu_inttype itype,
1947                                 unsigned long pgtable_base,
1948                                 unsigned long fault_addr, unsigned int status)
1949 {
1950         struct platform_device *pdev;
1951         struct vpu_subdev_data *data;
1952         struct vpu_service_info *pservice;
1953
1954         vpu_debug_enter();
1955
1956         pdev = container_of(dev, struct platform_device, dev);
1957
1958         data = platform_get_drvdata(pdev);
1959         pservice = data->pservice;
1960
1961         if (pservice->reg_codec) {
1962                 struct vcodec_mem_region *mem, *n;
1963                 int i = 0;
1964                 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1965                 list_for_each_entry_safe(mem, n,
1966                                          &pservice->reg_codec->mem_region_list,
1967                                          reg_lnk) {
1968                         vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1969                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
1970                         i++;
1971                 }
1972
1973                 pr_alert("vcodec, page fault occur, reset hw\n");
1974                 pservice->reg_codec->reg[101] = 1;
1975                 vpu_reset(data);
1976         }
1977
1978         return 0;
1979 }
1980 #endif
1981
1982 #if HEVC_TEST_ENABLE
1983 static int hevc_test_case0(vpu_service_info *pservice);
1984 #endif
1985 #if defined(CONFIG_ION_ROCKCHIP)
1986 extern struct ion_client *rockchip_ion_client_create(const char * name);
1987 #endif
1988
1989 static int vcodec_subdev_probe(struct platform_device *pdev,
1990         struct vpu_service_info *pservice)
1991 {
1992         int ret = 0;
1993         struct resource *res = NULL;
1994         u32 ioaddr = 0;
1995         struct device *dev = &pdev->dev;
1996         char *name = (char*)dev_name(dev);
1997         struct device_node *np = pdev->dev.of_node;
1998         struct vpu_subdev_data *data =
1999                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2000 #if defined(CONFIG_VCODEC_MMU)
2001         u32 iommu_en = 0;
2002         char mmu_dev_dts_name[40];
2003         of_property_read_u32(np, "iommu_enabled", &iommu_en);
2004 #endif
2005         pr_info("probe device %s\n", dev_name(dev));
2006
2007         data->pservice = pservice;
2008         data->dev = dev;
2009
2010         of_property_read_string(np, "name", (const char**)&name);
2011         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2012         /*dev_set_name(dev, name);*/
2013
2014         if (pservice->reg_base == 0) {
2015                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2016                 data->regs = devm_ioremap_resource(dev, res);
2017                 if (IS_ERR(data->regs)) {
2018                         ret = PTR_ERR(data->regs);
2019                         goto err;
2020                 }
2021                 ioaddr = res->start;
2022         } else {
2023                 data->regs = pservice->reg_base;
2024                 ioaddr = pservice->ioaddr;
2025         }
2026
2027         clear_bit(MMU_ACTIVATED, &data->state);
2028         vcodec_enter_mode(data);
2029         ret = vpu_service_check_hw(data, ioaddr);
2030         if (ret < 0) {
2031                 vpu_err("error: hw info check faild\n");
2032                 goto err;
2033         }
2034
2035         data->dec_dev.iosize = data->hw_info->dec_io_size;
2036         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2037         data->reg_size = data->dec_dev.iosize;
2038
2039         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2040                 data->enc_dev.iosize = data->hw_info->enc_io_size;
2041                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2042                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2043         }
2044
2045         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2046         if (data->irq_enc > 0) {
2047                 ret = devm_request_threaded_irq(dev,
2048                         data->irq_enc, vepu_irq, vepu_isr,
2049                         IRQF_SHARED, dev_name(dev),
2050                         (void *)data);
2051                 if (ret) {
2052                         dev_err(dev,
2053                                 "error: can't request vepu irq %d\n",
2054                                 data->irq_enc);
2055                         goto err;
2056                 }
2057         }
2058         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2059         if (data->irq_dec > 0) {
2060                 ret = devm_request_threaded_irq(dev,
2061                         data->irq_dec, vdpu_irq, vdpu_isr,
2062                         IRQF_SHARED, dev_name(dev),
2063                         (void *)data);
2064                 if (ret) {
2065                         dev_err(dev,
2066                                 "error: can't request vdpu irq %d\n",
2067                                 data->irq_dec);
2068                         goto err;
2069                 }
2070         }
2071         atomic_set(&data->dec_dev.irq_count_codec, 0);
2072         atomic_set(&data->dec_dev.irq_count_pp, 0);
2073         atomic_set(&data->enc_dev.irq_count_codec, 0);
2074         atomic_set(&data->enc_dev.irq_count_pp, 0);
2075 #if defined(CONFIG_VCODEC_MMU)
2076         if (iommu_en) {
2077                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2078                         sprintf(mmu_dev_dts_name,
2079                                 HEVC_IOMMU_COMPATIBLE_NAME);
2080                 else
2081                         sprintf(mmu_dev_dts_name,
2082                                 VPU_IOMMU_COMPATIBLE_NAME);
2083
2084                 data->mmu_dev =
2085                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2086
2087                 if (data->mmu_dev)
2088                         platform_set_sysmmu(data->mmu_dev, dev);
2089
2090                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2091         }
2092 #endif
2093         vcodec_exit_mode(data);
2094         /* create device node */
2095         ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2096         if (ret) {
2097                 dev_err(dev, "alloc dev_t failed\n");
2098                 goto err;
2099         }
2100
2101         cdev_init(&data->cdev, &vpu_service_fops);
2102
2103         data->cdev.owner = THIS_MODULE;
2104         data->cdev.ops = &vpu_service_fops;
2105
2106         ret = cdev_add(&data->cdev, data->dev_t, 1);
2107
2108         if (ret) {
2109                 dev_err(dev, "add dev_t failed\n");
2110                 goto err;
2111         }
2112
2113         data->cls = class_create(THIS_MODULE, name);
2114
2115         if (IS_ERR(data->cls)) {
2116                 ret = PTR_ERR(data->cls);
2117                 dev_err(dev, "class_create err:%d\n", ret);
2118                 goto err;
2119         }
2120
2121         data->child_dev = device_create(data->cls, dev,
2122                 data->dev_t, NULL, name);
2123
2124         get_hw_info(data);
2125
2126         platform_set_drvdata(pdev, data);
2127
2128         INIT_LIST_HEAD(&data->lnk_service);
2129         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2130
2131 #ifdef CONFIG_DEBUG_FS
2132         data->debugfs_dir =
2133                 vcodec_debugfs_create_device_dir((char*)name, parent);
2134         if (data->debugfs_dir == NULL)
2135                 vpu_err("create debugfs dir %s failed\n", name);
2136
2137         data->debugfs_file_regs =
2138                 debugfs_create_file("regs", 0664,
2139                                     data->debugfs_dir, data,
2140                                     &debug_vcodec_fops);
2141 #endif
2142         return 0;
2143 err:
2144         if (data->irq_enc > 0)
2145                 free_irq(data->irq_enc, (void *)data);
2146         if (data->irq_dec > 0)
2147                 free_irq(data->irq_dec, (void *)data);
2148
2149         if (data->child_dev) {
2150                 device_destroy(data->cls, data->dev_t);
2151                 cdev_del(&data->cdev);
2152                 unregister_chrdev_region(data->dev_t, 1);
2153         }
2154
2155         if (data->cls)
2156                 class_destroy(data->cls);
2157         return -1;
2158 }
2159
2160 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2161 {
2162         device_destroy(data->cls, data->dev_t);
2163         class_destroy(data->cls);
2164         cdev_del(&data->cdev);
2165         unregister_chrdev_region(data->dev_t, 1);
2166
2167         free_irq(data->irq_enc, (void *)&data);
2168         free_irq(data->irq_dec, (void *)&data);
2169
2170 #ifdef CONFIG_DEBUG_FS
2171         debugfs_remove(data->debugfs_file_regs);
2172         debugfs_remove(data->debugfs_dir);
2173 #endif
2174 }
2175
2176 static void vcodec_read_property(struct device_node *np,
2177         struct vpu_service_info *pservice)
2178 {
2179         pservice->mode_bit = 0;
2180         pservice->mode_ctrl = 0;
2181         pservice->subcnt = 0;
2182
2183         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2184
2185         if (pservice->subcnt > 1) {
2186                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2187                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2188         }
2189 #ifdef CONFIG_MFD_SYSCON
2190         pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2191 #else
2192         pservice->grf_base = (u32*)RK_GRF_VIRT;
2193 #endif
2194         if (IS_ERR(pservice->grf_base)) {
2195 #ifdef CONFIG_ARM
2196                 pservice->grf_base = RK_GRF_VIRT;
2197 #else
2198                 vpu_err("can't find vpu grf property\n");
2199                 return;
2200 #endif
2201         }
2202         of_property_read_string(np, "name", (const char**)&pservice->name);
2203 }
2204
2205 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2206 {
2207         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2208         pservice->curr_mode = -1;
2209
2210         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2211         INIT_LIST_HEAD(&pservice->waiting);
2212         INIT_LIST_HEAD(&pservice->running);
2213         mutex_init(&pservice->lock);
2214
2215         INIT_LIST_HEAD(&pservice->done);
2216         INIT_LIST_HEAD(&pservice->session);
2217         INIT_LIST_HEAD(&pservice->subdev_list);
2218
2219         pservice->reg_pproc     = NULL;
2220         atomic_set(&pservice->total_running, 0);
2221         atomic_set(&pservice->enabled,       0);
2222         atomic_set(&pservice->power_on_cnt,  0);
2223         atomic_set(&pservice->power_off_cnt, 0);
2224
2225         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2226
2227         pservice->ion_client = rockchip_ion_client_create("vpu");
2228         if (IS_ERR(pservice->ion_client)) {
2229                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2230                         PTR_ERR(pservice->ion_client));
2231         } else {
2232                 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2233         }
2234 }
2235
2236 static int vcodec_probe(struct platform_device *pdev)
2237 {
2238         int i;
2239         int ret = 0;
2240         struct resource *res = NULL;
2241         struct device *dev = &pdev->dev;
2242         struct device_node *np = pdev->dev.of_node;
2243         struct vpu_service_info *pservice =
2244                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2245
2246         pr_info("probe device %s\n", dev_name(dev));
2247
2248         vcodec_read_property(np, pservice);
2249         vcodec_init_drvdata(pservice);
2250
2251         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2252                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2253         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2254                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2255         else
2256                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2257
2258         pservice->dev = dev;
2259
2260         if (0 > vpu_get_clk(pservice))
2261                 goto err;
2262
2263         vpu_service_power_on(pservice);
2264
2265         if (of_property_read_bool(np, "reg")) {
2266                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2267
2268                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2269                 if (IS_ERR(pservice->reg_base)) {
2270                         vpu_err("ioremap registers base failed\n");
2271                         ret = PTR_ERR(pservice->reg_base);
2272                         goto err;
2273                 }
2274                 pservice->ioaddr = res->start;
2275         } else {
2276                 pservice->reg_base = 0;
2277         }
2278
2279         if (of_property_read_bool(np, "subcnt")) {
2280                 for (i = 0; i<pservice->subcnt; i++) {
2281                         struct device_node *sub_np;
2282                         struct platform_device *sub_pdev;
2283                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2284                         sub_pdev = of_find_device_by_node(sub_np);
2285
2286                         vcodec_subdev_probe(sub_pdev, pservice);
2287                 }
2288         } else {
2289                 vcodec_subdev_probe(pdev, pservice);
2290         }
2291         platform_set_drvdata(pdev, pservice);
2292
2293         vpu_service_power_off(pservice);
2294
2295         pr_info("init success\n");
2296
2297         return 0;
2298
2299 err:
2300         pr_info("init failed\n");
2301         vpu_service_power_off(pservice);
2302         vpu_put_clk(pservice);
2303         wake_lock_destroy(&pservice->wake_lock);
2304
2305         if (res)
2306                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2307
2308         return ret;
2309 }
2310
2311 static int vcodec_remove(struct platform_device *pdev)
2312 {
2313         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2314         struct resource *res;
2315         struct vpu_subdev_data *data, *n;
2316
2317         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2318                 vcodec_subdev_remove(data);
2319         }
2320
2321         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2322         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2323         vpu_put_clk(pservice);
2324         wake_lock_destroy(&pservice->wake_lock);
2325
2326         return 0;
2327 }
2328
2329 #if defined(CONFIG_OF)
2330 static const struct of_device_id vcodec_service_dt_ids[] = {
2331         {.compatible = "vpu_service",},
2332         {.compatible = "rockchip,hevc_service",},
2333         {.compatible = "rockchip,vpu_combo",},
2334         {},
2335 };
2336 #endif
2337
2338 static struct platform_driver vcodec_driver = {
2339         .probe = vcodec_probe,
2340         .remove = vcodec_remove,
2341         .driver = {
2342                 .name = "vcodec",
2343                 .owner = THIS_MODULE,
2344 #if defined(CONFIG_OF)
2345                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2346 #endif
2347         },
2348 };
2349
2350 static void get_hw_info(struct vpu_subdev_data *data)
2351 {
2352         struct vpu_service_info *pservice = data->pservice;
2353         struct vpu_dec_config *dec = &pservice->dec_config;
2354         struct vpu_enc_config *enc = &pservice->enc_config;
2355         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2356                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2357                 u32 asicID      = data->dec_dev.hwregs[0];
2358
2359                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2360                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2361                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2362                         dec->jpegSupport = JPEG_PROGRESSIVE;
2363                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2364                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2365                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2366                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2367                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2368                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2369
2370                 dec->maxDecPicWidth = 4096;
2371
2372                 /* 2nd Config register */
2373                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2374                 if (dec->refBufSupport) {
2375                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2376                                 dec->refBufSupport |= 2;
2377                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2378                                 dec->refBufSupport |= 4;
2379                 }
2380                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2381                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2382                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2383                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2384
2385                 /* JPEG xtensions */
2386                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2387                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2388                 else
2389                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2390
2391                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2392                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2393                 else
2394                         dec->rvSupport = RV_NOT_SUPPORTED;
2395                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2396
2397                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2398                         dec->refBufSupport |= 8; /* enable HW support for offset */
2399
2400                 if (!cpu_is_rk3036()) {
2401                         configReg = data->enc_dev.hwregs[63];
2402                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2403                         enc->h264Enabled = (configReg >> 27) & 1;
2404                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2405                         enc->jpegEnabled = (configReg >> 25) & 1;
2406                         enc->vsEnabled = (configReg >> 24) & 1;
2407                         enc->rgbEnabled = (configReg >> 28) & 1;
2408                         enc->reg_size = data->reg_size;
2409                         enc->reserv[0] = enc->reserv[1] = 0;
2410                 }
2411                 pservice->auto_freq = true;
2412                 vpu_debug(3, "vpu_service set to auto frequency mode\n");
2413                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2414
2415                 pservice->bug_dec_addr = cpu_is_rk30xx();
2416         } else {
2417                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2418                         dec->maxDecPicWidth = 1920;
2419                 else
2420                         dec->maxDecPicWidth = 4096;
2421                 /* disable frequency switch in hevc.*/
2422                 pservice->auto_freq = false;
2423         }
2424 }
2425
2426 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2427 {
2428         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2429         struct vpu_service_info *pservice = data->pservice;
2430         vpu_device *dev = &data->dec_dev;
2431         u32 raw_status;
2432         u32 irq_status;
2433
2434         /*vcodec_enter_mode(data);*/
2435
2436         irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2437
2438         if (irq_status & DEC_INTERRUPT_BIT) {
2439                 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", irq_status);
2440                 if ((irq_status & 0x40001) == 0x40001) {
2441                         do {
2442                                 irq_status =
2443                                         readl(dev->hwregs +
2444                                                 DEC_INTERRUPT_REGISTER);
2445                         } while ((irq_status & 0x40001) == 0x40001);
2446                 }
2447
2448                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2449                 atomic_add(1, &dev->irq_count_codec);
2450         }
2451
2452         if (data->hw_info->hw_id != HEVC_ID) {
2453                 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2454                 if (irq_status & PP_INTERRUPT_BIT) {
2455                         vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", irq_status);
2456                         /* clear pp IRQ */
2457                         writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2458                         atomic_add(1, &dev->irq_count_pp);
2459                 }
2460         }
2461
2462         pservice->irq_status = raw_status;
2463
2464         /*vcodec_exit_mode(pservice);*/
2465
2466         if (atomic_read(&dev->irq_count_pp) ||
2467             atomic_read(&dev->irq_count_codec))
2468                 return IRQ_WAKE_THREAD;
2469         else
2470                 return IRQ_NONE;
2471 }
2472
2473 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2474 {
2475         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2476         struct vpu_service_info *pservice = data->pservice;
2477         vpu_device *dev = &data->dec_dev;
2478
2479         mutex_lock(&pservice->lock);
2480         if (atomic_read(&dev->irq_count_codec)) {
2481 #if VPU_SERVICE_SHOW_TIME
2482                 do_gettimeofday(&dec_end);
2483                 vpu_debug(3, "dec task: %ld ms\n",
2484                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +
2485                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2486 #endif
2487                 atomic_sub(1, &dev->irq_count_codec);
2488                 if (NULL == pservice->reg_codec) {
2489                         vpu_err("error: dec isr with no task waiting\n");
2490                 } else {
2491                         reg_from_run_to_done(data, pservice->reg_codec);
2492                         /* avoid vpu timeout and can't recover problem */
2493                         VDPU_SOFT_RESET(data->regs);
2494                 }
2495         }
2496
2497         if (atomic_read(&dev->irq_count_pp)) {
2498 #if VPU_SERVICE_SHOW_TIME
2499                 do_gettimeofday(&pp_end);
2500                 printk("pp  task: %ld ms\n",
2501                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +
2502                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2503 #endif
2504                 atomic_sub(1, &dev->irq_count_pp);
2505                 if (NULL == pservice->reg_pproc) {
2506                         vpu_err("error: pp isr with no task waiting\n");
2507                 } else {
2508                         reg_from_run_to_done(data, pservice->reg_pproc);
2509                 }
2510         }
2511         try_set_reg(data);
2512         mutex_unlock(&pservice->lock);
2513         return IRQ_HANDLED;
2514 }
2515
2516 static irqreturn_t vepu_irq(int irq, void *dev_id)
2517 {
2518         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2519         struct vpu_service_info *pservice = data->pservice;
2520         vpu_device *dev = &data->enc_dev;
2521         u32 irq_status;
2522
2523         /*vcodec_enter_mode(data);*/
2524         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2525
2526         vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2527
2528 #if VPU_SERVICE_SHOW_TIME
2529         do_gettimeofday(&enc_end);
2530         vpu_debug(3, "enc task: %ld ms\n",
2531                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +
2532                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2533 #endif
2534         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2535                 /* clear enc IRQ */
2536                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2537                 atomic_add(1, &dev->irq_count_codec);
2538         }
2539
2540         pservice->irq_status = irq_status;
2541
2542         /*vcodec_exit_mode(pservice);*/
2543
2544         if (atomic_read(&dev->irq_count_codec))
2545                 return IRQ_WAKE_THREAD;
2546         else
2547                 return IRQ_NONE;
2548 }
2549
2550 static irqreturn_t vepu_isr(int irq, void *dev_id)
2551 {
2552         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2553         struct vpu_service_info *pservice = data->pservice;
2554         vpu_device *dev = &data->enc_dev;
2555
2556         mutex_lock(&pservice->lock);
2557         if (atomic_read(&dev->irq_count_codec)) {
2558                 atomic_sub(1, &dev->irq_count_codec);
2559                 if (NULL == pservice->reg_codec) {
2560                         vpu_err("error: enc isr with no task waiting\n");
2561                 } else {
2562                         reg_from_run_to_done(data, pservice->reg_codec);
2563                 }
2564         }
2565         try_set_reg(data);
2566         mutex_unlock(&pservice->lock);
2567         return IRQ_HANDLED;
2568 }
2569
2570 static int __init vcodec_service_init(void)
2571 {
2572         int ret;
2573
2574         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2575                 vpu_err("Platform device register failed (%d).\n", ret);
2576                 return ret;
2577         }
2578
2579 #ifdef CONFIG_DEBUG_FS
2580         vcodec_debugfs_init();
2581 #endif
2582
2583         return ret;
2584 }
2585
2586 static void __exit vcodec_service_exit(void)
2587 {
2588 #ifdef CONFIG_DEBUG_FS
2589         vcodec_debugfs_exit();
2590 #endif
2591
2592         platform_driver_unregister(&vcodec_driver);
2593 }
2594
2595 module_init(vcodec_service_init);
2596 module_exit(vcodec_service_exit);
2597
2598 #ifdef CONFIG_DEBUG_FS
2599 #include <linux/seq_file.h>
2600
2601 static int vcodec_debugfs_init()
2602 {
2603         parent = debugfs_create_dir("vcodec", NULL);
2604         if (!parent)
2605                 return -1;
2606
2607         return 0;
2608 }
2609
2610 static void vcodec_debugfs_exit()
2611 {
2612         debugfs_remove(parent);
2613 }
2614
2615 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2616 {
2617         return debugfs_create_dir(dirname, parent);
2618 }
2619
2620 static int debug_vcodec_show(struct seq_file *s, void *unused)
2621 {
2622         struct vpu_subdev_data *data = s->private;
2623         struct vpu_service_info *pservice = data->pservice;
2624         unsigned int i, n;
2625         vpu_reg *reg, *reg_tmp;
2626         vpu_session *session, *session_tmp;
2627
2628         mutex_lock(&pservice->lock);
2629         vpu_service_power_on(pservice);
2630         if (data->hw_info->hw_id != HEVC_ID) {
2631                 seq_printf(s, "\nENC Registers:\n");
2632                 n = data->enc_dev.iosize >> 2;
2633                 for (i = 0; i < n; i++)
2634                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2635         }
2636         seq_printf(s, "\nDEC Registers:\n");
2637         n = data->dec_dev.iosize >> 2;
2638         for (i = 0; i < n; i++)
2639                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2640
2641         seq_printf(s, "\nvpu service status:\n");
2642         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2643                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2644                 /*seq_printf(s, "waiting reg set %d\n");*/
2645                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2646                         seq_printf(s, "waiting register set\n");
2647                 }
2648                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2649                         seq_printf(s, "running register set\n");
2650                 }
2651                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2652                         seq_printf(s, "done    register set\n");
2653                 }
2654         }
2655
2656         seq_printf(s, "\npower counter: on %d off %d\n",
2657                         atomic_read(&pservice->power_on_cnt),
2658                         atomic_read(&pservice->power_off_cnt));
2659         mutex_unlock(&pservice->lock);
2660         vpu_service_power_off(pservice);
2661
2662         return 0;
2663 }
2664
2665 static int debug_vcodec_open(struct inode *inode, struct file *file)
2666 {
2667         return single_open(file, debug_vcodec_show, inode->i_private);
2668 }
2669
2670 #endif
2671
2672 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2673 #include "hevc_test_inc/pps_00.h"
2674 #include "hevc_test_inc/register_00.h"
2675 #include "hevc_test_inc/rps_00.h"
2676 #include "hevc_test_inc/scaling_list_00.h"
2677 #include "hevc_test_inc/stream_00.h"
2678
2679 #include "hevc_test_inc/pps_01.h"
2680 #include "hevc_test_inc/register_01.h"
2681 #include "hevc_test_inc/rps_01.h"
2682 #include "hevc_test_inc/scaling_list_01.h"
2683 #include "hevc_test_inc/stream_01.h"
2684
2685 #include "hevc_test_inc/cabac.h"
2686
2687 extern struct ion_client *rockchip_ion_client_create(const char * name);
2688
2689 static struct ion_client *ion_client = NULL;
2690 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2691 {
2692         int size = (len+15) & (~15);
2693         struct ion_handle *handle;
2694         u8 *ptr;
2695
2696         if (ion_client == NULL)
2697                 ion_client = rockchip_ion_client_create("vcodec");
2698
2699         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2700
2701         ptr = ion_map_kernel(ion_client, handle);
2702
2703         ion_phys(ion_client, handle, phy, &size);
2704
2705         memcpy(ptr, tbl, len);
2706
2707         return ptr;
2708 }
2709
2710 u8* get_align_ptr_no_copy(int len, u32 *phy)
2711 {
2712         int size = (len+15) & (~15);
2713         struct ion_handle *handle;
2714         u8 *ptr;
2715
2716         if (ion_client == NULL)
2717                 ion_client = rockchip_ion_client_create("vcodec");
2718
2719         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2720
2721         ptr = ion_map_kernel(ion_client, handle);
2722
2723         ion_phys(ion_client, handle, phy, &size);
2724
2725         return ptr;
2726 }
2727
2728 #define TEST_CNT    2
2729 static int hevc_test_case0(vpu_service_info *pservice)
2730 {
2731         vpu_session session;
2732         vpu_reg *reg;
2733         unsigned long size = 272;
2734         int testidx = 0;
2735         int ret = 0;
2736         u8 *pps_tbl[TEST_CNT];
2737         u8 *register_tbl[TEST_CNT];
2738         u8 *rps_tbl[TEST_CNT];
2739         u8 *scaling_list_tbl[TEST_CNT];
2740         u8 *stream_tbl[TEST_CNT];
2741
2742         int stream_size[2];
2743         int pps_size[2];
2744         int rps_size[2];
2745         int scl_size[2];
2746         int cabac_size[2];
2747
2748         u32 phy_pps;
2749         u32 phy_rps;
2750         u32 phy_scl;
2751         u32 phy_str;
2752         u32 phy_yuv;
2753         u32 phy_ref;
2754         u32 phy_cabac;
2755
2756         volatile u8 *stream_buf;
2757         volatile u8 *pps_buf;
2758         volatile u8 *rps_buf;
2759         volatile u8 *scl_buf;
2760         volatile u8 *yuv_buf;
2761         volatile u8 *cabac_buf;
2762         volatile u8 *ref_buf;
2763
2764         u8 *pps;
2765         u8 *yuv[2];
2766         int i;
2767
2768         pps_tbl[0] = pps_00;
2769         pps_tbl[1] = pps_01;
2770
2771         register_tbl[0] = register_00;
2772         register_tbl[1] = register_01;
2773
2774         rps_tbl[0] = rps_00;
2775         rps_tbl[1] = rps_01;
2776
2777         scaling_list_tbl[0] = scaling_list_00;
2778         scaling_list_tbl[1] = scaling_list_01;
2779
2780         stream_tbl[0] = stream_00;
2781         stream_tbl[1] = stream_01;
2782
2783         stream_size[0] = sizeof(stream_00);
2784         stream_size[1] = sizeof(stream_01);
2785
2786         pps_size[0] = sizeof(pps_00);
2787         pps_size[1] = sizeof(pps_01);
2788
2789         rps_size[0] = sizeof(rps_00);
2790         rps_size[1] = sizeof(rps_01);
2791
2792         scl_size[0] = sizeof(scaling_list_00);
2793         scl_size[1] = sizeof(scaling_list_01);
2794
2795         cabac_size[0] = sizeof(Cabac_table);
2796         cabac_size[1] = sizeof(Cabac_table);
2797
2798         /* create session */
2799         session.pid = current->pid;
2800         session.type = VPU_DEC;
2801         INIT_LIST_HEAD(&session.waiting);
2802         INIT_LIST_HEAD(&session.running);
2803         INIT_LIST_HEAD(&session.done);
2804         INIT_LIST_HEAD(&session.list_session);
2805         init_waitqueue_head(&session.wait);
2806         atomic_set(&session.task_running, 0);
2807         list_add_tail(&session.list_session, &pservice->session);
2808
2809         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2810         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2811
2812         while (testidx < TEST_CNT) {
2813                 /* create registers */
2814                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2815                 if (NULL == reg) {
2816                         vpu_err("error: kmalloc fail in reg_init\n");
2817                         return -1;
2818                 }
2819
2820                 if (size > pservice->reg_size) {
2821                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2822                         size = pservice->reg_size;
2823                 }
2824                 reg->session = &session;
2825                 reg->type = session.type;
2826                 reg->size = size;
2827                 reg->freq = VPU_FREQ_DEFAULT;
2828                 reg->reg = (unsigned long *)&reg[1];
2829                 INIT_LIST_HEAD(&reg->session_link);
2830                 INIT_LIST_HEAD(&reg->status_link);
2831
2832                 /* TODO: stuff registers */
2833                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2834
2835                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2836                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2837                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2838                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2839                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2840
2841                 pps = pps_buf;
2842
2843                 /* TODO: replace reigster address */
2844                 for (i=0; i<64; i++) {
2845                         u32 scaling_offset;
2846                         u32 tmp;
2847
2848                         scaling_offset = (u32)pps[i*80+74];
2849                         scaling_offset += (u32)pps[i*80+75] << 8;
2850                         scaling_offset += (u32)pps[i*80+76] << 16;
2851                         scaling_offset += (u32)pps[i*80+77] << 24;
2852
2853                         tmp = phy_scl + scaling_offset;
2854
2855                         pps[i*80+74] = tmp & 0xff;
2856                         pps[i*80+75] = (tmp >> 8) & 0xff;
2857                         pps[i*80+76] = (tmp >> 16) & 0xff;
2858                         pps[i*80+77] = (tmp >> 24) & 0xff;
2859                 }
2860
2861                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2862                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
2863
2864                 reg->reg[1] = 0x21;
2865                 reg->reg[4] = phy_str;
2866                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2867                 reg->reg[6] = phy_cabac;
2868                 reg->reg[7] = testidx?phy_ref:phy_yuv;
2869                 reg->reg[42] = phy_pps;
2870                 reg->reg[43] = phy_rps;
2871                 for (i = 10; i <= 24; i++)
2872                         reg->reg[i] = phy_yuv;
2873
2874                 mutex_lock(pservice->lock);
2875                 list_add_tail(&reg->status_link, &pservice->waiting);
2876                 list_add_tail(&reg->session_link, &session.waiting);
2877                 mutex_unlock(pservice->lock);
2878
2879                 /* stuff hardware */
2880                 try_set_reg(data);
2881
2882                 /* wait for result */
2883                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2884                 if (!list_empty(&session.done)) {
2885                         if (ret < 0)
2886                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2887                         ret = 0;
2888                 } else {
2889                         if (unlikely(ret < 0)) {
2890                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2891                         } else if (0 == ret) {
2892                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2893                                 ret = -ETIMEDOUT;
2894                         }
2895                 }
2896                 if (ret < 0) {
2897                         int task_running = atomic_read(&session.task_running);
2898                         int n;
2899                         mutex_lock(pservice->lock);
2900                         vpu_service_dump(pservice);
2901                         if (task_running) {
2902                                 atomic_set(&session.task_running, 0);
2903                                 atomic_sub(task_running, &pservice->total_running);
2904                                 printk("%d task is running but not return, reset hardware...", task_running);
2905                                 vpu_reset(data);
2906                                 printk("done\n");
2907                         }
2908                         vpu_service_session_clear(pservice, &session);
2909                         mutex_unlock(pservice->lock);
2910
2911                         printk("\nDEC Registers:\n");
2912                         n = data->dec_dev.iosize >> 2;
2913                         for (i=0; i<n; i++)
2914                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2915
2916                         vpu_err("test index %d failed\n", testidx);
2917                         break;
2918                 } else {
2919                         vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
2920
2921                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2922
2923                         for (i=0; i<68; i++) {
2924                                 if (i % 4 == 0)
2925                                         printk("%02d: ", i);
2926                                 printk("%08x ", reg->reg[i]);
2927                                 if ((i+1) % 4 == 0)
2928                                         printk("\n");
2929                         }
2930
2931                         testidx++;
2932                 }
2933
2934                 reg_deinit(data, reg);
2935         }
2936
2937         return 0;
2938 }
2939
2940 #endif
2941