2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/miscdevice.h>
28 #include <linux/poll.h>
29 #include <linux/platform_device.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/wakelock.h>
33 #include <linux/cdev.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_irq.h>
37 #include <linux/rockchip/cpu.h>
38 #include <linux/rockchip/cru.h>
39 #ifdef CONFIG_MFD_SYSCON
40 #include <linux/regmap.h>
42 #include <linux/mfd/syscon.h>
44 #include <asm/cacheflush.h>
45 #include <linux/uaccess.h>
46 #include <linux/rockchip/grf.h>
48 #if defined(CONFIG_ION_ROCKCHIP)
49 #include <linux/rockchip_ion.h>
52 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
53 #define CONFIG_VCODEC_MMU
56 #ifdef CONFIG_VCODEC_MMU
57 #include <linux/rockchip-iovmm.h>
58 #include <linux/dma-buf.h>
61 #ifdef CONFIG_DEBUG_FS
62 #include <linux/debugfs.h>
65 #if defined(CONFIG_ARCH_RK319X)
69 #include "vcodec_service.h"
72 module_param(debug, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(debug,
74 "Debug level - higher value produces more verbose messages");
76 #define HEVC_TEST_ENABLE 0
77 #define VCODEC_CLOCK_ENABLE 1
80 VPU_DEC_ID_9190 = 0x6731,
94 VPU_DEC_TYPE_9190 = 0,
95 VPU_ENC_TYPE_8270 = 0x100,
99 typedef enum VPU_FREQ {
112 unsigned long hw_addr;
113 unsigned long enc_offset;
114 unsigned long enc_reg_num;
115 unsigned long enc_io_size;
116 unsigned long dec_offset;
117 unsigned long dec_reg_num;
118 unsigned long dec_io_size;
121 struct extra_info_elem {
126 #define EXTRA_INFO_MAGIC 0x4C4A46
128 struct extra_info_for_iommu {
131 struct extra_info_elem elem[20];
134 #define VPU_SERVICE_SHOW_TIME 0
136 #if VPU_SERVICE_SHOW_TIME
137 static struct timeval enc_start, enc_end;
138 static struct timeval dec_start, dec_end;
139 static struct timeval pp_start, pp_end;
142 #define MHZ (1000*1000)
144 #define REG_NUM_9190_DEC (60)
145 #define REG_NUM_9190_PP (41)
146 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
148 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
150 #define REG_NUM_ENC_8270 (96)
151 #define REG_SIZE_ENC_8270 (0x200)
152 #define REG_NUM_ENC_4831 (164)
153 #define REG_SIZE_ENC_4831 (0x400)
155 #define REG_NUM_HEVC_DEC (68)
157 #define SIZE_REG(reg) ((reg)*4)
159 static VPU_HW_INFO_E vpu_hw_set[] = {
161 .hw_id = VPU_ID_8270,
164 .enc_reg_num = REG_NUM_ENC_8270,
165 .enc_io_size = REG_NUM_ENC_8270 * 4,
166 .dec_offset = REG_SIZE_ENC_8270,
167 .dec_reg_num = REG_NUM_9190_DEC_PP,
168 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
171 .hw_id = VPU_ID_4831,
174 .enc_reg_num = REG_NUM_ENC_4831,
175 .enc_io_size = REG_NUM_ENC_4831 * 4,
176 .dec_offset = REG_SIZE_ENC_4831,
177 .dec_reg_num = REG_NUM_9190_DEC_PP,
178 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
184 .dec_reg_num = REG_NUM_HEVC_DEC,
185 .dec_io_size = REG_NUM_HEVC_DEC * 4,
188 .hw_id = VPU_DEC_ID_9190,
194 .dec_reg_num = REG_NUM_9190_DEC_PP,
195 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
200 #define DEC_INTERRUPT_REGISTER 1
201 #define PP_INTERRUPT_REGISTER 60
202 #define ENC_INTERRUPT_REGISTER 1
204 #define DEC_INTERRUPT_BIT 0x100
205 #define DEC_BUFFER_EMPTY_BIT 0x4000
206 #define PP_INTERRUPT_BIT 0x100
207 #define ENC_INTERRUPT_BIT 0x1
209 #define HEVC_DEC_INT_RAW_BIT 0x200
210 #define HEVC_DEC_STR_ERROR_BIT 0x4000
211 #define HEVC_DEC_BUS_ERROR_BIT 0x2000
212 #define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000
214 #define VPU_REG_EN_ENC 14
215 #define VPU_REG_ENC_GATE 2
216 #define VPU_REG_ENC_GATE_BIT (1<<4)
218 #define VPU_REG_EN_DEC 1
219 #define VPU_REG_DEC_GATE 2
220 #define VPU_REG_DEC_GATE_BIT (1<<10)
221 #define VPU_REG_EN_PP 0
222 #define VPU_REG_PP_GATE 1
223 #define VPU_REG_PP_GATE_BIT (1<<8)
224 #define VPU_REG_EN_DEC_PP 1
225 #define VPU_REG_DEC_PP_GATE 61
226 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
230 #define vpu_debug(level, fmt, args...) \
232 if (debug >= level) \
233 pr_info("%s:%d: " fmt, \
234 __func__, __LINE__, ##args); \
237 #define vpu_debug(level, fmt, args...)
240 #define vpu_debug_enter() vpu_debug(4, "enter\n")
241 #define vpu_debug_leave() vpu_debug(4, "leave\n")
243 #define vpu_err(fmt, args...) \
244 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
246 #if defined(CONFIG_VCODEC_MMU)
247 static u8 addr_tbl_vpu_h264dec[] = {
248 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
249 25, 26, 27, 28, 29, 40, 41
252 static u8 addr_tbl_vpu_vp8dec[] = {
253 10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
256 static u8 addr_tbl_vpu_vp6dec[] = {
257 12, 13, 14, 18, 27, 40
260 static u8 addr_tbl_vpu_vc1dec[] = {
261 12, 13, 14, 15, 16, 17, 27, 41
264 static u8 addr_tbl_vpu_jpegdec[] = {
268 static u8 addr_tbl_vpu_defaultdec[] = {
269 12, 13, 14, 15, 16, 17, 40, 41
272 static u8 addr_tbl_vpu_enc[] = {
273 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
276 static u8 addr_tbl_hevc_dec[] = {
277 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
278 21, 22, 23, 24, 42, 43
303 * struct for process session which connect to vpu
305 * @author ChenHengming (2011-5-3)
307 typedef struct vpu_session {
308 enum VPU_CLIENT_TYPE type;
309 /* a linked list of data so we can access them for debugging */
310 struct list_head list_session;
311 /* a linked list of register data waiting for process */
312 struct list_head waiting;
313 /* a linked list of register data in processing */
314 struct list_head running;
315 /* a linked list of register data processed */
316 struct list_head done;
317 wait_queue_head_t wait;
319 atomic_t task_running;
323 * struct for process register set
325 * @author ChenHengming (2011-5-4)
327 typedef struct vpu_reg {
328 enum VPU_CLIENT_TYPE type;
330 vpu_session *session;
331 struct list_head session_link; /* link to vpu service session */
332 struct list_head status_link; /* link to register set list */
334 #if defined(CONFIG_VCODEC_MMU)
335 struct list_head mem_region_list;
340 typedef struct vpu_device {
341 atomic_t irq_count_codec;
342 atomic_t irq_count_pp;
343 unsigned long iobaseaddr;
345 volatile u32 *hwregs;
348 enum vcodec_device_id {
349 VCODEC_DEVICE_ID_VPU,
350 VCODEC_DEVICE_ID_HEVC,
351 VCODEC_DEVICE_ID_COMBO
354 enum VCODEC_RUNNING_MODE {
355 VCODEC_RUNNING_MODE_NONE = -1,
356 VCODEC_RUNNING_MODE_VPU,
357 VCODEC_RUNNING_MODE_HEVC,
360 struct vcodec_mem_region {
361 struct list_head srv_lnk;
362 struct list_head reg_lnk;
363 struct list_head session_lnk;
364 unsigned long iova; /* virtual address for iommu */
367 struct ion_handle *hdl;
371 MMU_ACTIVATED = BIT(0)
374 struct vpu_subdev_data {
378 struct device *child_dev;
382 struct vpu_service_info *pservice;
385 enum VCODEC_RUNNING_MODE mode;
386 struct list_head lnk_service;
392 VPU_HW_INFO_E *hw_info;
397 #ifdef CONFIG_DEBUG_FS
398 struct dentry *debugfs_dir;
399 struct dentry *debugfs_file_regs;
402 #if defined(CONFIG_VCODEC_MMU)
403 struct device *mmu_dev;
407 typedef struct vpu_service_info {
408 struct wake_lock wake_lock;
409 struct delayed_work power_off_work;
411 struct list_head waiting; /* link to link_reg in struct vpu_reg */
412 struct list_head running; /* link to link_reg in struct vpu_reg */
413 struct list_head done; /* link to link_reg in struct vpu_reg */
414 struct list_head session; /* link to list_session in struct vpu_session */
415 atomic_t total_running;
420 struct vpu_dec_config dec_config;
421 struct vpu_enc_config enc_config;
425 atomic_t freq_status;
427 struct clk *aclk_vcodec;
428 struct clk *hclk_vcodec;
429 struct clk *clk_core;
430 struct clk *clk_cabac;
431 struct clk *pd_video;
436 #if defined(CONFIG_VCODEC_MMU)
437 struct ion_client *ion_client;
438 struct list_head mem_region_list;
441 enum vcodec_device_id dev_id;
443 enum VCODEC_RUNNING_MODE curr_mode;
446 struct delayed_work simulate_work;
452 #ifdef CONFIG_MFD_SYSCON
453 struct regmap *grf_base;
460 struct list_head subdev_list;
463 struct vcodec_combo {
464 struct vpu_service_info *vpu_srv;
465 struct vpu_service_info *hevc_srv;
466 struct list_head waiting;
467 struct list_head running;
468 struct mutex run_lock;
470 enum vcodec_device_id current_hw_mode;
473 typedef struct vpu_request {
478 /* debugfs root directory for all device (vpu, hevc).*/
479 static struct dentry *parent;
481 #ifdef CONFIG_DEBUG_FS
482 static int vcodec_debugfs_init(void);
483 static void vcodec_debugfs_exit(void);
484 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
485 static int debug_vcodec_open(struct inode *inode, struct file *file);
487 static const struct file_operations debug_vcodec_fops = {
488 .open = debug_vcodec_open,
491 .release = single_release,
495 #define VDPU_SOFT_RESET_REG 101
496 #define VDPU_CLEAN_CACHE_REG 516
497 #define VEPU_CLEAN_CACHE_REG 772
498 #define HEVC_CLEAN_CACHE_REG 260
500 #define VPU_REG_ENABLE(base, reg) do { \
504 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
505 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
506 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
507 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
509 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
510 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
512 static void vcodec_enter_mode(struct vpu_subdev_data *data)
516 struct vpu_service_info *pservice = data->pservice;
517 struct vpu_subdev_data *subdata, *n;
518 if (pservice->subcnt < 2) {
519 #if defined(CONFIG_VCODEC_MMU)
520 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
521 set_bit(MMU_ACTIVATED, &data->state);
522 BUG_ON(!pservice->enabled);
523 if (pservice->enabled)
524 rockchip_iovmm_activate(data->dev);
530 if (pservice->curr_mode == data->mode)
533 vpu_debug(3, "vcodec enter mode %d\n", data->mode);
534 #if defined(CONFIG_VCODEC_MMU)
535 list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
536 if (data != subdata && subdata->mmu_dev &&
537 test_bit(MMU_ACTIVATED, &subdata->state)) {
538 clear_bit(MMU_ACTIVATED, &subdata->state);
539 rockchip_iovmm_deactivate(subdata->dev);
543 bits = 1 << pservice->mode_bit;
544 #ifdef CONFIG_MFD_SYSCON
545 regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
547 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
548 regmap_write(pservice->grf_base, pservice->mode_ctrl,
549 raw | bits | (bits << 16));
551 regmap_write(pservice->grf_base, pservice->mode_ctrl,
552 (raw & (~bits)) | (bits << 16));
554 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
555 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
556 writel_relaxed(raw | bits | (bits << 16),
557 pservice->grf_base + pservice->mode_ctrl / 4);
559 writel_relaxed((raw & (~bits)) | (bits << 16),
560 pservice->grf_base + pservice->mode_ctrl / 4);
562 #if defined(CONFIG_VCODEC_MMU)
563 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
564 set_bit(MMU_ACTIVATED, &data->state);
565 BUG_ON(!pservice->enabled);
566 if (pservice->enabled)
567 rockchip_iovmm_activate(data->dev);
570 pservice->prev_mode = pservice->curr_mode;
571 pservice->curr_mode = data->mode;
574 static void vcodec_exit_mode(struct vpu_service_info *pservice)
579 static int vpu_get_clk(struct vpu_service_info *pservice)
581 #if VCODEC_CLOCK_ENABLE
582 switch (pservice->dev_id) {
583 case VCODEC_DEVICE_ID_HEVC:
584 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
585 if (IS_ERR(pservice->pd_video)) {
586 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
589 case VCODEC_DEVICE_ID_COMBO:
590 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
591 if (IS_ERR(pservice->clk_cabac)) {
592 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
593 pservice->clk_cabac = NULL;
595 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
596 if (IS_ERR(pservice->clk_core)) {
597 dev_err(pservice->dev, "failed on clk_get clk_core\n");
600 case VCODEC_DEVICE_ID_VPU:
601 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
602 if (IS_ERR(pservice->aclk_vcodec)) {
603 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
607 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
608 if (IS_ERR(pservice->hclk_vcodec)) {
609 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
612 if (pservice->pd_video == NULL) {
613 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
614 if (IS_ERR(pservice->pd_video))
615 pservice->pd_video = NULL;
628 static void vpu_put_clk(struct vpu_service_info *pservice)
630 #if VCODEC_CLOCK_ENABLE
631 if (pservice->pd_video)
632 devm_clk_put(pservice->dev, pservice->pd_video);
633 if (pservice->aclk_vcodec)
634 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
635 if (pservice->hclk_vcodec)
636 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
637 if (pservice->clk_core)
638 devm_clk_put(pservice->dev, pservice->clk_core);
639 if (pservice->clk_cabac)
640 devm_clk_put(pservice->dev, pservice->clk_cabac);
644 static void vpu_reset(struct vpu_subdev_data *data)
646 struct vpu_service_info *pservice = data->pservice;
647 #if defined(CONFIG_ARCH_RK29)
648 clk_disable(aclk_ddr_vepu);
649 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
650 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
651 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
652 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
654 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
655 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
656 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
657 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
658 clk_enable(aclk_ddr_vepu);
659 #elif defined(CONFIG_ARCH_RK30)
660 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
661 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
662 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
663 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
664 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
666 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
667 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
668 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
669 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
670 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
672 pservice->reg_codec = NULL;
673 pservice->reg_pproc = NULL;
674 pservice->reg_resev = NULL;
676 #if defined(CONFIG_VCODEC_MMU)
677 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
678 clear_bit(MMU_ACTIVATED, &data->state);
679 BUG_ON(!pservice->enabled);
680 if (pservice->enabled)
681 rockchip_iovmm_deactivate(data->dev);
686 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
687 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
690 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
691 reg_deinit(data, reg);
693 list_for_each_entry_safe(reg, n, &session->running, session_link) {
694 reg_deinit(data, reg);
696 list_for_each_entry_safe(reg, n, &session->done, session_link) {
697 reg_deinit(data, reg);
701 static void vpu_service_dump(struct vpu_service_info *pservice)
705 static void vpu_service_power_off(struct vpu_service_info *pservice)
708 struct vpu_subdev_data *data = NULL, *n;
709 if (!pservice->enabled)
712 pservice->enabled = false;
713 total_running = atomic_read(&pservice->total_running);
715 pr_alert("alert: power off when %d task running!!\n", total_running);
717 pr_alert("alert: delay 50 ms for running task\n");
718 vpu_service_dump(pservice);
721 pr_info("%s: power off...", dev_name(pservice->dev));
723 #if defined(CONFIG_VCODEC_MMU)
724 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
725 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
726 clear_bit(MMU_ACTIVATED, &data->state);
727 rockchip_iovmm_deactivate(data->dev);
730 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
733 #if VCODEC_CLOCK_ENABLE
734 if (pservice->pd_video)
735 clk_disable_unprepare(pservice->pd_video);
736 if (pservice->hclk_vcodec)
737 clk_disable_unprepare(pservice->hclk_vcodec);
738 if (pservice->aclk_vcodec)
739 clk_disable_unprepare(pservice->aclk_vcodec);
740 if (pservice->clk_core)
741 clk_disable_unprepare(pservice->clk_core);
742 if (pservice->clk_cabac)
743 clk_disable_unprepare(pservice->clk_cabac);
746 wake_unlock(&pservice->wake_lock);
750 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
752 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
755 static void vpu_power_off_work(struct work_struct *work_s)
757 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
758 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
760 if (mutex_trylock(&pservice->lock)) {
761 vpu_service_power_off(pservice);
762 mutex_unlock(&pservice->lock);
764 /* Come back later if the device is busy... */
765 vpu_queue_power_off_work(pservice);
769 static void vpu_service_power_on(struct vpu_service_info *pservice)
772 ktime_t now = ktime_get();
773 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
774 cancel_delayed_work_sync(&pservice->power_off_work);
775 vpu_queue_power_off_work(pservice);
778 if (pservice->enabled)
781 pservice->enabled = true;
782 pr_info("%s: power on\n", dev_name(pservice->dev));
784 #define BIT_VCODEC_CLK_SEL (1<<10)
786 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
787 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
788 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
790 #if VCODEC_CLOCK_ENABLE
791 if (pservice->aclk_vcodec)
792 clk_prepare_enable(pservice->aclk_vcodec);
793 if (pservice->hclk_vcodec)
794 clk_prepare_enable(pservice->hclk_vcodec);
795 if (pservice->clk_core)
796 clk_prepare_enable(pservice->clk_core);
797 if (pservice->clk_cabac)
798 clk_prepare_enable(pservice->clk_cabac);
799 if (pservice->pd_video)
800 clk_prepare_enable(pservice->pd_video);
804 wake_lock(&pservice->wake_lock);
807 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
809 u32 type = (reg->reg[3] & 0xF0000000) >> 28;
810 return ((type == 8) || (type == 4));
813 static inline bool reg_check_interlace(vpu_reg *reg)
815 u32 type = (reg->reg[3] & (1 << 23));
819 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
821 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
825 static inline int reg_probe_width(vpu_reg *reg)
827 int width_in_mb = reg->reg[4] >> 23;
828 return width_in_mb * 16;
831 #if defined(CONFIG_VCODEC_MMU)
832 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
834 struct vpu_service_info *pservice = data->pservice;
835 struct ion_handle *hdl;
837 struct vcodec_mem_region *mem_region;
839 hdl = ion_import_dma_buf(pservice->ion_client, fd);
841 vpu_err("import dma-buf from fd %d failed\n", fd);
844 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
846 if (mem_region == NULL) {
847 vpu_err("allocate memory for iommu memory region failed\n");
848 ion_free(pservice->ion_client, hdl);
852 mem_region->hdl = hdl;
853 vcodec_enter_mode(data);
854 ret = ion_map_iommu(data->dev, pservice->ion_client,
855 mem_region->hdl, &mem_region->iova, &mem_region->len);
856 vcodec_exit_mode(pservice);
859 vpu_err("ion map iommu failed\n");
861 ion_free(pservice->ion_client, hdl);
864 INIT_LIST_HEAD(&mem_region->reg_lnk);
865 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
866 return mem_region->iova;
869 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
870 int size, vpu_reg *reg,
871 struct extra_info_for_iommu *ext_inf)
873 struct vpu_service_info *pservice = data->pservice;
878 if (tbl == NULL || size <= 0) {
879 dev_err(pservice->dev, "input arguments invalidate\n");
883 vpu_service_power_on(pservice);
885 for (i = 0; i < size; i++) {
886 usr_fd = reg->reg[tbl[i]] & 0x3FF;
888 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
889 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
890 /* special for vpu dec num 41 regitster */
891 offset = reg->reg[tbl[i]] >> 10 << 4;
893 offset = reg->reg[tbl[i]] >> 10;
896 struct ion_handle *hdl;
898 struct vcodec_mem_region *mem_region;
900 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
902 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
906 if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
909 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
910 for (i=0; i<64; i++) {
914 scaling_offset = (u32)pps[i*80+74];
915 scaling_offset += (u32)pps[i*80+75] << 8;
916 scaling_offset += (u32)pps[i*80+76] << 16;
917 scaling_offset += (u32)pps[i*80+77] << 24;
918 scaling_fd = scaling_offset&0x3ff;
919 scaling_offset = scaling_offset >> 10;
921 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
922 tmp += scaling_offset;
923 pps[i*80+74] = tmp & 0xff;
924 pps[i*80+75] = (tmp >> 8) & 0xff;
925 pps[i*80+76] = (tmp >> 16) & 0xff;
926 pps[i*80+77] = (tmp >> 24) & 0xff;
931 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
933 if (mem_region == NULL) {
934 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
935 ion_free(pservice->ion_client, hdl);
939 mem_region->hdl = hdl;
940 mem_region->reg_idx = tbl[i];
941 vcodec_enter_mode(data);
942 ret = ion_map_iommu(data->dev,
943 pservice->ion_client,
947 vcodec_exit_mode(pservice);
950 dev_err(pservice->dev, "ion map iommu failed\n");
952 ion_free(pservice->ion_client, hdl);
955 reg->reg[tbl[i]] = mem_region->iova + offset;
956 INIT_LIST_HEAD(&mem_region->reg_lnk);
957 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
961 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
962 for (i=0; i<ext_inf->cnt; i++) {
963 vpu_debug(3, "reg[%d] + offset %d\n",
964 ext_inf->elem[i].index,
965 ext_inf->elem[i].offset);
966 reg->reg[ext_inf->elem[i].index] +=
967 ext_inf->elem[i].offset;
974 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
976 struct extra_info_for_iommu *ext_inf)
982 hw_id = data->hw_info->hw_id;
984 if (hw_id == HEVC_ID) {
985 tbl = addr_tbl_hevc_dec;
986 size = sizeof(addr_tbl_hevc_dec);
988 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
989 switch (reg_check_fmt(reg)) {
990 case VPU_DEC_FMT_H264:
992 tbl = addr_tbl_vpu_h264dec;
993 size = sizeof(addr_tbl_vpu_h264dec);
996 case VPU_DEC_FMT_VP8:
997 case VPU_DEC_FMT_VP7:
999 tbl = addr_tbl_vpu_vp8dec;
1000 size = sizeof(addr_tbl_vpu_vp8dec);
1004 case VPU_DEC_FMT_VP6:
1006 tbl = addr_tbl_vpu_vp6dec;
1007 size = sizeof(addr_tbl_vpu_vp6dec);
1010 case VPU_DEC_FMT_VC1:
1012 tbl = addr_tbl_vpu_vc1dec;
1013 size = sizeof(addr_tbl_vpu_vc1dec);
1017 case VPU_DEC_FMT_JPEG:
1019 tbl = addr_tbl_vpu_jpegdec;
1020 size = sizeof(addr_tbl_vpu_jpegdec);
1024 tbl = addr_tbl_vpu_defaultdec;
1025 size = sizeof(addr_tbl_vpu_defaultdec);
1028 } else if (reg->type == VPU_ENC) {
1029 tbl = addr_tbl_vpu_enc;
1030 size = sizeof(addr_tbl_vpu_enc);
1035 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1042 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1043 vpu_session *session, void __user *src, u32 size)
1045 struct vpu_service_info *pservice = data->pservice;
1047 struct extra_info_for_iommu extra_info;
1048 vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1053 vpu_err("error: kmalloc fail in reg_init\n");
1057 if (size > data->reg_size) {
1058 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1059 size, pservice->reg_size);
1060 size = pservice->reg_size;*/
1061 extra_size = size - data->reg_size;
1062 size = data->reg_size;
1064 reg->session = session;
1065 reg->type = session->type;
1067 reg->freq = VPU_FREQ_DEFAULT;
1068 reg->reg = (u32 *)®[1];
1069 INIT_LIST_HEAD(®->session_link);
1070 INIT_LIST_HEAD(®->status_link);
1072 #if defined(CONFIG_VCODEC_MMU)
1074 INIT_LIST_HEAD(®->mem_region_list);
1077 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1078 vpu_err("error: copy_from_user failed in reg_init\n");
1083 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1084 vpu_err("error: copy_from_user failed in reg_init\n");
1089 #if defined(CONFIG_VCODEC_MMU)
1090 if (data->mmu_dev &&
1091 0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1092 vpu_err("error: translate reg address failed\n");
1098 mutex_lock(&pservice->lock);
1099 list_add_tail(®->status_link, &pservice->waiting);
1100 list_add_tail(®->session_link, &session->waiting);
1101 mutex_unlock(&pservice->lock);
1103 if (pservice->auto_freq) {
1104 if (!soc_is_rk2928g()) {
1105 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1106 if (reg_check_rmvb_wmv(reg)) {
1107 reg->freq = VPU_FREQ_200M;
1108 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1109 if (reg_probe_width(reg) > 3200) {
1110 // raise frequency for 4k avc.
1111 reg->freq = VPU_FREQ_500M;
1114 if (reg_check_interlace(reg)) {
1115 reg->freq = VPU_FREQ_400M;
1119 if (reg->type == VPU_PP) {
1120 reg->freq = VPU_FREQ_400M;
1128 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1130 struct vpu_service_info *pservice = data->pservice;
1131 #if defined(CONFIG_VCODEC_MMU)
1132 struct vcodec_mem_region *mem_region = NULL, *n;
1135 list_del_init(®->session_link);
1136 list_del_init(®->status_link);
1137 if (reg == pservice->reg_codec)
1138 pservice->reg_codec = NULL;
1139 if (reg == pservice->reg_pproc)
1140 pservice->reg_pproc = NULL;
1142 #if defined(CONFIG_VCODEC_MMU)
1143 /* release memory region attach to this registers table. */
1144 if (data->mmu_dev) {
1145 list_for_each_entry_safe(mem_region, n,
1146 ®->mem_region_list, reg_lnk) {
1147 /* do not unmap iommu manually,
1148 unmap will proccess when memory release */
1149 /*vcodec_enter_mode(data);
1150 ion_unmap_iommu(data->dev,
1151 pservice->ion_client,
1153 vcodec_exit_mode();*/
1154 ion_free(pservice->ion_client, mem_region->hdl);
1155 list_del_init(&mem_region->reg_lnk);
1164 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1167 list_del_init(®->status_link);
1168 list_add_tail(®->status_link, &pservice->running);
1170 list_del_init(®->session_link);
1171 list_add_tail(®->session_link, ®->session->running);
1175 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1178 u32 *dst = (u32 *)®->reg[0];
1180 for (i = 0; i < count; i++)
1185 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1188 struct vpu_service_info *pservice = data->pservice;
1193 list_del_init(®->status_link);
1194 list_add_tail(®->status_link, &pservice->done);
1196 list_del_init(®->session_link);
1197 list_add_tail(®->session_link, ®->session->done);
1199 vcodec_enter_mode(data);
1200 switch (reg->type) {
1202 pservice->reg_codec = NULL;
1203 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1204 irq_reg = ENC_INTERRUPT_REGISTER;
1208 int reg_len = REG_NUM_9190_DEC;
1209 pservice->reg_codec = NULL;
1210 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1211 irq_reg = DEC_INTERRUPT_REGISTER;
1215 pservice->reg_pproc = NULL;
1216 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1217 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1221 pservice->reg_codec = NULL;
1222 pservice->reg_pproc = NULL;
1223 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1224 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1228 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1232 vcodec_exit_mode(pservice);
1235 reg->reg[irq_reg] = pservice->irq_status;
1237 atomic_sub(1, ®->session->task_running);
1238 atomic_sub(1, &pservice->total_running);
1239 wake_up(®->session->wait);
1244 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1246 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1247 if (curr == reg->freq)
1249 atomic_set(&pservice->freq_status, reg->freq);
1250 switch (reg->freq) {
1251 case VPU_FREQ_200M : {
1252 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1254 case VPU_FREQ_266M : {
1255 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1257 case VPU_FREQ_300M : {
1258 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1260 case VPU_FREQ_400M : {
1261 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1263 case VPU_FREQ_500M : {
1264 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1266 case VPU_FREQ_600M : {
1267 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1270 if (soc_is_rk2928g())
1271 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1273 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1278 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1280 struct vpu_service_info *pservice = data->pservice;
1282 u32 *src = (u32 *)®->reg[0];
1285 atomic_add(1, &pservice->total_running);
1286 atomic_add(1, ®->session->task_running);
1287 if (pservice->auto_freq)
1288 vpu_service_set_freq(pservice, reg);
1290 vcodec_enter_mode(data);
1292 switch (reg->type) {
1294 int enc_count = data->hw_info->enc_reg_num;
1295 u32 *dst = (u32 *)data->enc_dev.hwregs;
1297 pservice->reg_codec = reg;
1299 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1301 for (i = 0; i < VPU_REG_EN_ENC; i++)
1304 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1307 VEPU_CLEAN_CACHE(dst);
1311 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1312 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1314 #if VPU_SERVICE_SHOW_TIME
1315 do_gettimeofday(&enc_start);
1320 u32 *dst = (u32 *)data->dec_dev.hwregs;
1322 pservice->reg_codec = reg;
1324 if (data->hw_info->hw_id != HEVC_ID) {
1325 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1327 VDPU_CLEAN_CACHE(dst);
1329 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1331 HEVC_CLEAN_CACHE(dst);
1336 if (data->hw_info->hw_id != HEVC_ID) {
1337 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1338 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1340 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1344 #if VPU_SERVICE_SHOW_TIME
1345 do_gettimeofday(&dec_start);
1349 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1350 pservice->reg_pproc = reg;
1352 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1354 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1359 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1360 #if VPU_SERVICE_SHOW_TIME
1361 do_gettimeofday(&pp_start);
1366 u32 *dst = (u32 *)data->dec_dev.hwregs;
1367 pservice->reg_codec = reg;
1368 pservice->reg_pproc = reg;
1370 VDPU_SOFT_RESET(dst);
1371 VDPU_CLEAN_CACHE(dst);
1373 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1376 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1379 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1380 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1381 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1382 #if VPU_SERVICE_SHOW_TIME
1383 do_gettimeofday(&dec_start);
1387 vpu_err("error: unsupport session type %d", reg->type);
1388 atomic_sub(1, &pservice->total_running);
1389 atomic_sub(1, ®->session->task_running);
1394 vcodec_exit_mode(pservice);
1398 static void try_set_reg(struct vpu_subdev_data *data)
1400 struct vpu_service_info *pservice = data->pservice;
1402 if (!list_empty(&pservice->waiting)) {
1404 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1406 vpu_service_power_on(pservice);
1408 switch (reg->type) {
1410 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1414 if (NULL == pservice->reg_codec)
1416 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1420 if (NULL == pservice->reg_codec) {
1421 if (NULL == pservice->reg_pproc)
1424 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1426 /* can not charge frequency when vpu is working */
1427 if (pservice->auto_freq)
1432 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1436 printk("undefined reg type %d\n", reg->type);
1440 reg_from_wait_to_run(pservice, reg);
1441 reg_copy_to_hw(data, reg);
1447 static int return_reg(struct vpu_subdev_data *data,
1448 vpu_reg *reg, u32 __user *dst)
1452 switch (reg->type) {
1454 if (copy_to_user(dst, ®->reg[0], data->hw_info->enc_io_size))
1459 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1460 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1465 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1470 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1476 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1480 reg_deinit(data, reg);
1485 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1488 struct vpu_subdev_data *data =
1489 container_of(filp->f_dentry->d_inode->i_cdev,
1490 struct vpu_subdev_data, cdev);
1491 struct vpu_service_info *pservice = data->pservice;
1492 vpu_session *session = (vpu_session *)filp->private_data;
1494 vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, (u32)VPU_IOC_SET_CLIENT_TYPE);
1495 if (NULL == session)
1499 case VPU_IOC_SET_CLIENT_TYPE : {
1500 session->type = (enum VPU_CLIENT_TYPE)arg;
1503 case VPU_IOC_GET_HW_FUSE_STATUS : {
1505 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1506 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1509 if (VPU_ENC != session->type) {
1510 if (copy_to_user((void __user *)req.req,
1511 &pservice->dec_config,
1512 sizeof(struct vpu_dec_config))) {
1513 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1518 if (copy_to_user((void __user *)req.req,
1519 &pservice->enc_config,
1520 sizeof(struct vpu_enc_config ))) {
1521 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1530 case VPU_IOC_SET_REG : {
1533 if (copy_from_user(&req, (void __user *)arg,
1534 sizeof(vpu_request))) {
1535 vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1538 reg = reg_init(data, session,
1539 (void __user *)req.req, req.size);
1543 mutex_lock(&pservice->lock);
1545 mutex_unlock(&pservice->lock);
1550 case VPU_IOC_GET_REG : {
1553 if (copy_from_user(&req, (void __user *)arg,
1554 sizeof(vpu_request))) {
1555 vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1558 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1559 if (!list_empty(&session->done)) {
1561 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1565 if (unlikely(ret < 0)) {
1566 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1567 } else if (0 == ret) {
1568 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1573 int task_running = atomic_read(&session->task_running);
1574 mutex_lock(&pservice->lock);
1575 vpu_service_dump(pservice);
1577 atomic_set(&session->task_running, 0);
1578 atomic_sub(task_running, &pservice->total_running);
1579 printk("%d task is running but not return, reset hardware...", task_running);
1583 vpu_service_session_clear(data, session);
1584 mutex_unlock(&pservice->lock);
1588 mutex_lock(&pservice->lock);
1589 reg = list_entry(session->done.next, vpu_reg, session_link);
1590 return_reg(data, reg, (u32 __user *)req.req);
1591 mutex_unlock(&pservice->lock);
1594 case VPU_IOC_PROBE_IOMMU_STATUS: {
1595 int iommu_enable = 0;
1597 #if defined(CONFIG_VCODEC_MMU)
1598 iommu_enable = data->mmu_dev ? 1 : 0;
1601 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1602 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1608 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1616 #ifdef CONFIG_COMPAT
1617 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1620 struct vpu_subdev_data *data =
1621 container_of(filp->f_dentry->d_inode->i_cdev,
1622 struct vpu_subdev_data, cdev);
1623 struct vpu_service_info *pservice = data->pservice;
1624 vpu_session *session = (vpu_session *)filp->private_data;
1626 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1627 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1628 if (NULL == session)
1632 case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1633 session->type = (enum VPU_CLIENT_TYPE)arg;
1636 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1638 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1639 sizeof(vpu_request))) {
1640 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1641 " copy_from_user failed\n");
1644 if (VPU_ENC != session->type) {
1645 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1646 &pservice->dec_config,
1647 sizeof(struct vpu_dec_config))) {
1648 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1649 "copy_to_user failed type %d\n",
1654 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1655 &pservice->enc_config,
1656 sizeof(struct vpu_enc_config ))) {
1657 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1658 " copy_to_user failed type %d\n",
1667 case COMPAT_VPU_IOC_SET_REG : {
1670 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1671 sizeof(vpu_request))) {
1672 vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1675 reg = reg_init(data, session,
1676 compat_ptr((compat_uptr_t)req.req), req.size);
1680 mutex_lock(&pservice->lock);
1682 mutex_unlock(&pservice->lock);
1687 case COMPAT_VPU_IOC_GET_REG : {
1690 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1691 sizeof(vpu_request))) {
1692 vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1695 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1696 if (!list_empty(&session->done)) {
1698 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1702 if (unlikely(ret < 0)) {
1703 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1704 } else if (0 == ret) {
1705 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1710 int task_running = atomic_read(&session->task_running);
1711 mutex_lock(&pservice->lock);
1712 vpu_service_dump(pservice);
1714 atomic_set(&session->task_running, 0);
1715 atomic_sub(task_running, &pservice->total_running);
1716 printk("%d task is running but not return, reset hardware...", task_running);
1720 vpu_service_session_clear(data, session);
1721 mutex_unlock(&pservice->lock);
1725 mutex_lock(&pservice->lock);
1726 reg = list_entry(session->done.next, vpu_reg, session_link);
1727 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1728 mutex_unlock(&pservice->lock);
1731 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1732 int iommu_enable = 0;
1734 #if defined(CONFIG_VCODEC_MMU)
1735 iommu_enable = data->mmu_dev ? 1 : 0;
1738 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1739 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1745 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1754 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1756 int ret = -EINVAL, i = 0;
1757 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1760 enc_id = (enc_id >> 16) & 0xFFFF;
1761 pr_info("checking hw id %x\n", enc_id);
1762 data->hw_info = NULL;
1763 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1764 if (enc_id == vpu_hw_set[i].hw_id) {
1765 data->hw_info = &vpu_hw_set[i];
1770 iounmap((void *)tmp);
1774 static int vpu_service_open(struct inode *inode, struct file *filp)
1776 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1777 struct vpu_service_info *pservice = data->pservice;
1778 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1782 if (NULL == session) {
1783 vpu_err("error: unable to allocate memory for vpu_session.");
1787 session->type = VPU_TYPE_BUTT;
1788 session->pid = current->pid;
1789 INIT_LIST_HEAD(&session->waiting);
1790 INIT_LIST_HEAD(&session->running);
1791 INIT_LIST_HEAD(&session->done);
1792 INIT_LIST_HEAD(&session->list_session);
1793 init_waitqueue_head(&session->wait);
1794 atomic_set(&session->task_running, 0);
1795 mutex_lock(&pservice->lock);
1796 list_add_tail(&session->list_session, &pservice->session);
1797 filp->private_data = (void *)session;
1798 mutex_unlock(&pservice->lock);
1800 pr_debug("dev opened\n");
1802 return nonseekable_open(inode, filp);
1805 static int vpu_service_release(struct inode *inode, struct file *filp)
1807 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1808 struct vpu_service_info *pservice = data->pservice;
1810 vpu_session *session = (vpu_session *)filp->private_data;
1812 if (NULL == session)
1815 task_running = atomic_read(&session->task_running);
1817 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1820 wake_up(&session->wait);
1822 mutex_lock(&pservice->lock);
1823 /* remove this filp from the asynchronusly notified filp's */
1824 list_del_init(&session->list_session);
1825 vpu_service_session_clear(data, session);
1827 filp->private_data = NULL;
1828 mutex_unlock(&pservice->lock);
1830 pr_debug("dev closed\n");
1835 static const struct file_operations vpu_service_fops = {
1836 .unlocked_ioctl = vpu_service_ioctl,
1837 .open = vpu_service_open,
1838 .release = vpu_service_release,
1839 #ifdef CONFIG_COMPAT
1840 .compat_ioctl = compat_vpu_service_ioctl,
1842 //.fasync = vpu_service_fasync,
1845 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1846 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1847 static irqreturn_t vepu_irq(int irq, void *dev_id);
1848 static irqreturn_t vepu_isr(int irq, void *dev_id);
1849 static void get_hw_info(struct vpu_subdev_data *data);
1851 #ifdef CONFIG_VCODEC_MMU
1852 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1854 struct device_node *dn = NULL;
1855 struct platform_device *pd = NULL;
1856 struct device *ret = NULL ;
1858 dn = of_find_compatible_node(NULL,NULL,compt);
1860 printk("can't find device node %s \r\n",compt);
1864 pd = of_find_device_by_node(dn);
1866 printk("can't find platform device in device node %s\n",compt);
1874 #ifdef CONFIG_IOMMU_API
1875 static inline void platform_set_sysmmu(struct device *iommu,
1878 dev->archdata.iommu = iommu;
1881 static inline void platform_set_sysmmu(struct device *iommu,
1887 int vcodec_sysmmu_fault_hdl(struct device *dev,
1888 enum rk_iommu_inttype itype,
1889 unsigned long pgtable_base,
1890 unsigned long fault_addr, unsigned int status)
1892 struct platform_device *pdev;
1893 struct vpu_subdev_data *data;
1894 struct vpu_service_info *pservice;
1898 pdev = container_of(dev, struct platform_device, dev);
1900 data = platform_get_drvdata(pdev);
1901 pservice = data->pservice;
1903 if (pservice->reg_codec) {
1904 struct vcodec_mem_region *mem, *n;
1906 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1907 list_for_each_entry_safe(mem, n,
1908 &pservice->reg_codec->mem_region_list,
1910 vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1911 mem->reg_idx, i, (u32)mem->iova, mem->len);
1915 pr_alert("vcodec, page fault occur, reset hw\n");
1916 pservice->reg_codec->reg[101] = 1;
1924 #if HEVC_TEST_ENABLE
1925 static int hevc_test_case0(vpu_service_info *pservice);
1927 #if defined(CONFIG_ION_ROCKCHIP)
1928 extern struct ion_client *rockchip_ion_client_create(const char * name);
1931 static int vcodec_subdev_probe(struct platform_device *pdev,
1932 struct vpu_service_info *pservice)
1935 struct resource *res = NULL;
1937 struct device *dev = &pdev->dev;
1938 char *name = (char*)dev_name(dev);
1939 struct device_node *np = pdev->dev.of_node;
1940 struct vpu_subdev_data *data =
1941 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1942 #if defined(CONFIG_VCODEC_MMU)
1944 char mmu_dev_dts_name[40];
1945 of_property_read_u32(np, "iommu_enabled", &iommu_en);
1947 pr_info("probe device %s\n", dev_name(dev));
1949 data->pservice = pservice;
1952 of_property_read_string(np, "name", (const char**)&name);
1953 of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
1954 dev_set_name(dev, name);
1956 if (pservice->reg_base == 0) {
1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1958 data->regs = devm_ioremap_resource(dev, res);
1959 if (IS_ERR(data->regs)) {
1960 ret = PTR_ERR(data->regs);
1963 ioaddr = res->start;
1965 data->regs = pservice->reg_base;
1966 ioaddr = pservice->ioaddr;
1969 clear_bit(MMU_ACTIVATED, &data->state);
1970 vcodec_enter_mode(data);
1971 ret = vpu_service_check_hw(data, ioaddr);
1973 vpu_err("error: hw info check faild\n");
1977 data->dec_dev.iosize = data->hw_info->dec_io_size;
1978 data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1979 data->reg_size = data->dec_dev.iosize;
1981 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1982 data->enc_dev.iosize = data->hw_info->enc_io_size;
1983 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1984 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1987 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1988 if (data->irq_enc > 0) {
1989 ret = devm_request_threaded_irq(dev,
1990 data->irq_enc, vepu_irq, vepu_isr,
1991 IRQF_SHARED, dev_name(dev),
1995 "error: can't request vepu irq %d\n",
2000 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2001 if (data->irq_dec > 0) {
2002 ret = devm_request_threaded_irq(dev,
2003 data->irq_dec, vdpu_irq, vdpu_isr,
2004 IRQF_SHARED, dev_name(dev),
2008 "error: can't request vdpu irq %d\n",
2013 atomic_set(&data->dec_dev.irq_count_codec, 0);
2014 atomic_set(&data->dec_dev.irq_count_pp, 0);
2015 atomic_set(&data->enc_dev.irq_count_codec, 0);
2016 atomic_set(&data->enc_dev.irq_count_pp, 0);
2017 #if defined(CONFIG_VCODEC_MMU)
2019 vcodec_enter_mode(data);
2020 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2021 sprintf(mmu_dev_dts_name,
2022 HEVC_IOMMU_COMPATIBLE_NAME);
2024 sprintf(mmu_dev_dts_name,
2025 VPU_IOMMU_COMPATIBLE_NAME);
2028 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2031 platform_set_sysmmu(data->mmu_dev, dev);
2033 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2036 /* create device node */
2037 ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
2039 dev_err(dev, "alloc dev_t failed\n");
2043 cdev_init(&data->cdev, &vpu_service_fops);
2045 data->cdev.owner = THIS_MODULE;
2046 data->cdev.ops = &vpu_service_fops;
2048 ret = cdev_add(&data->cdev, data->dev_t, 1);
2051 dev_err(dev, "add dev_t failed\n");
2055 data->cls = class_create(THIS_MODULE, dev_name(dev));
2057 if (IS_ERR(data->cls)) {
2058 ret = PTR_ERR(data->cls);
2059 dev_err(dev, "class_create err:%d\n", ret);
2063 data->child_dev = device_create(data->cls, dev,
2064 data->dev_t, NULL, dev_name(dev));
2068 platform_set_drvdata(pdev, data);
2070 INIT_LIST_HEAD(&data->lnk_service);
2071 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2073 #ifdef CONFIG_DEBUG_FS
2075 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2076 if (data->debugfs_dir == NULL)
2077 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2079 data->debugfs_file_regs =
2080 debugfs_create_file("regs", 0664,
2081 data->debugfs_dir, data,
2082 &debug_vcodec_fops);
2086 if (data->irq_enc > 0)
2087 free_irq(data->irq_enc, (void *)data);
2088 if (data->irq_dec > 0)
2089 free_irq(data->irq_dec, (void *)data);
2091 if (data->child_dev) {
2092 device_destroy(data->cls, data->dev_t);
2093 cdev_del(&data->cdev);
2094 unregister_chrdev_region(data->dev_t, 1);
2098 class_destroy(data->cls);
2102 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2104 device_destroy(data->cls, data->dev_t);
2105 class_destroy(data->cls);
2106 cdev_del(&data->cdev);
2107 unregister_chrdev_region(data->dev_t, 1);
2109 free_irq(data->irq_enc, (void *)&data);
2110 free_irq(data->irq_dec, (void *)&data);
2112 #ifdef CONFIG_DEBUG_FS
2113 debugfs_remove(data->debugfs_file_regs);
2114 debugfs_remove(data->debugfs_dir);
2118 static void vcodec_read_property(struct device_node *np,
2119 struct vpu_service_info *pservice)
2121 pservice->mode_bit = 0;
2122 pservice->mode_ctrl = 0;
2123 pservice->subcnt = 0;
2125 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2127 if (pservice->subcnt > 1) {
2128 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2129 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2131 #ifdef CONFIG_MFD_SYSCON
2132 pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2134 pservice->grf_base = (u32*)RK_GRF_VIRT;
2136 if (IS_ERR(pservice->grf_base)) {
2137 vpu_err("can't find vpu grf property\n");
2140 of_property_read_string(np, "name", (const char**)&pservice->name);
2143 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2145 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2146 pservice->curr_mode = -1;
2148 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2149 INIT_LIST_HEAD(&pservice->waiting);
2150 INIT_LIST_HEAD(&pservice->running);
2151 mutex_init(&pservice->lock);
2153 INIT_LIST_HEAD(&pservice->done);
2154 INIT_LIST_HEAD(&pservice->session);
2155 INIT_LIST_HEAD(&pservice->subdev_list);
2157 pservice->reg_pproc = NULL;
2158 atomic_set(&pservice->total_running, 0);
2159 pservice->enabled = false;
2161 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2163 pservice->ion_client = rockchip_ion_client_create("vpu");
2164 if (IS_ERR(pservice->ion_client)) {
2165 vpu_err("failed to create ion client for vcodec ret %ld\n",
2166 PTR_ERR(pservice->ion_client));
2168 vpu_debug(3, "vcodec ion client create success!\n");
2172 static int vcodec_probe(struct platform_device *pdev)
2176 struct resource *res = NULL;
2177 struct device *dev = &pdev->dev;
2178 struct device_node *np = pdev->dev.of_node;
2179 struct vpu_service_info *pservice =
2180 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2182 pr_info("probe device %s\n", dev_name(dev));
2184 vcodec_read_property(np, pservice);
2185 vcodec_init_drvdata(pservice);
2187 if (strncmp(pservice->name, "hevc_service", 12) == 0)
2188 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2189 else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2190 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2192 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2194 pservice->dev = dev;
2196 if (0 > vpu_get_clk(pservice))
2199 vpu_service_power_on(pservice);
2201 if (of_property_read_bool(np, "reg")) {
2202 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2204 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2205 if (IS_ERR(pservice->reg_base)) {
2206 vpu_err("ioremap registers base failed\n");
2207 ret = PTR_ERR(pservice->reg_base);
2210 pservice->ioaddr = res->start;
2212 pservice->reg_base = 0;
2215 if (of_property_read_bool(np, "subcnt")) {
2216 for (i = 0; i<pservice->subcnt; i++) {
2217 struct device_node *sub_np;
2218 struct platform_device *sub_pdev;
2219 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2220 sub_pdev = of_find_device_by_node(sub_np);
2222 vcodec_subdev_probe(sub_pdev, pservice);
2225 vcodec_subdev_probe(pdev, pservice);
2227 platform_set_drvdata(pdev, pservice);
2229 vpu_service_power_off(pservice);
2231 pr_info("init success\n");
2236 pr_info("init failed\n");
2237 vpu_service_power_off(pservice);
2238 vpu_put_clk(pservice);
2239 wake_lock_destroy(&pservice->wake_lock);
2242 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2247 static int vcodec_remove(struct platform_device *pdev)
2249 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2250 struct resource *res;
2251 struct vpu_subdev_data *data, *n;
2253 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2254 vcodec_subdev_remove(data);
2257 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2258 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2259 vpu_put_clk(pservice);
2260 wake_lock_destroy(&pservice->wake_lock);
2265 #if defined(CONFIG_OF)
2266 static const struct of_device_id vcodec_service_dt_ids[] = {
2267 {.compatible = "vpu_service",},
2268 {.compatible = "rockchip,hevc_service",},
2269 {.compatible = "rockchip,vpu_combo",},
2274 static struct platform_driver vcodec_driver = {
2275 .probe = vcodec_probe,
2276 .remove = vcodec_remove,
2279 .owner = THIS_MODULE,
2280 #if defined(CONFIG_OF)
2281 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2286 static void get_hw_info(struct vpu_subdev_data *data)
2288 struct vpu_service_info *pservice = data->pservice;
2289 struct vpu_dec_config *dec = &pservice->dec_config;
2290 struct vpu_enc_config *enc = &pservice->enc_config;
2291 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2292 u32 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2293 u32 asicID = data->dec_dev.hwregs[0];
2295 dec->h264_support = (configReg >> DWL_H264_E) & 0x3U;
2296 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2297 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2298 dec->jpegSupport = JPEG_PROGRESSIVE;
2299 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2300 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2301 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2302 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2303 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2304 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2306 dec->maxDecPicWidth = 4096;
2308 /* 2nd Config register */
2309 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2310 if (dec->refBufSupport) {
2311 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2312 dec->refBufSupport |= 2;
2313 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2314 dec->refBufSupport |= 4;
2316 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2317 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2318 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2319 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2321 /* JPEG xtensions */
2322 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2323 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2325 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2327 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2328 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2330 dec->rvSupport = RV_NOT_SUPPORTED;
2331 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2333 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2334 dec->refBufSupport |= 8; /* enable HW support for offset */
2336 if (!cpu_is_rk3036()) {
2337 configReg = data->enc_dev.hwregs[63];
2338 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2339 enc->h264Enabled = (configReg >> 27) & 1;
2340 enc->mpeg4Enabled = (configReg >> 26) & 1;
2341 enc->jpegEnabled = (configReg >> 25) & 1;
2342 enc->vsEnabled = (configReg >> 24) & 1;
2343 enc->rgbEnabled = (configReg >> 28) & 1;
2344 enc->reg_size = data->reg_size;
2345 enc->reserv[0] = enc->reserv[1] = 0;
2347 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2348 if (pservice->auto_freq) {
2349 vpu_debug(3, "vpu_service set to auto frequency mode\n");
2350 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2353 pservice->bug_dec_addr = cpu_is_rk30xx();
2355 if (cpu_is_rk3036() || cpu_is_rk312x())
2356 dec->maxDecPicWidth = 1920;
2358 dec->maxDecPicWidth = 4096;
2359 /* disable frequency switch in hevc.*/
2360 pservice->auto_freq = false;
2364 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2366 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2367 struct vpu_service_info *pservice = data->pservice;
2368 vpu_device *dev = &data->dec_dev;
2372 vcodec_enter_mode(data);
2374 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2376 vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2378 if (irq_status & DEC_INTERRUPT_BIT) {
2379 pr_debug("dec_isr dec %x\n", irq_status);
2380 if ((irq_status & 0x40001) == 0x40001) {
2384 DEC_INTERRUPT_REGISTER);
2385 } while ((irq_status & 0x40001) == 0x40001);
2388 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2389 atomic_add(1, &dev->irq_count_codec);
2392 if (data->hw_info->hw_id != HEVC_ID) {
2393 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2394 if (irq_status & PP_INTERRUPT_BIT) {
2395 pr_debug("vdpu_isr pp %x\n", irq_status);
2397 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2398 atomic_add(1, &dev->irq_count_pp);
2402 pservice->irq_status = raw_status;
2404 vcodec_exit_mode(pservice);
2406 return IRQ_WAKE_THREAD;
2409 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2411 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2412 struct vpu_service_info *pservice = data->pservice;
2413 vpu_device *dev = &data->dec_dev;
2415 mutex_lock(&pservice->lock);
2416 if (atomic_read(&dev->irq_count_codec)) {
2417 #if VPU_SERVICE_SHOW_TIME
2418 do_gettimeofday(&dec_end);
2419 vpu_debug(3, "dec task: %ld ms\n",
2420 (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
2421 (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2423 atomic_sub(1, &dev->irq_count_codec);
2424 if (NULL == pservice->reg_codec) {
2425 vpu_err("error: dec isr with no task waiting\n");
2427 reg_from_run_to_done(data, pservice->reg_codec);
2431 if (atomic_read(&dev->irq_count_pp)) {
2432 #if VPU_SERVICE_SHOW_TIME
2433 do_gettimeofday(&pp_end);
2434 printk("pp task: %ld ms\n",
2435 (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
2436 (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2438 atomic_sub(1, &dev->irq_count_pp);
2439 if (NULL == pservice->reg_pproc) {
2440 vpu_err("error: pp isr with no task waiting\n");
2442 reg_from_run_to_done(data, pservice->reg_pproc);
2446 mutex_unlock(&pservice->lock);
2450 static irqreturn_t vepu_irq(int irq, void *dev_id)
2452 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2453 struct vpu_service_info *pservice = data->pservice;
2454 vpu_device *dev = &data->enc_dev;
2457 vcodec_enter_mode(data);
2458 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2460 pr_debug("vepu_irq irq status %x\n", irq_status);
2462 #if VPU_SERVICE_SHOW_TIME
2463 do_gettimeofday(&enc_end);
2464 vpu_debug(3, "enc task: %ld ms\n",
2465 (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
2466 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2468 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2470 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2471 atomic_add(1, &dev->irq_count_codec);
2474 pservice->irq_status = irq_status;
2476 vcodec_exit_mode(pservice);
2478 return IRQ_WAKE_THREAD;
2481 static irqreturn_t vepu_isr(int irq, void *dev_id)
2483 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2484 struct vpu_service_info *pservice = data->pservice;
2485 vpu_device *dev = &data->enc_dev;
2487 mutex_lock(&pservice->lock);
2488 if (atomic_read(&dev->irq_count_codec)) {
2489 atomic_sub(1, &dev->irq_count_codec);
2490 if (NULL == pservice->reg_codec) {
2491 vpu_err("error: enc isr with no task waiting\n");
2493 reg_from_run_to_done(data, pservice->reg_codec);
2497 mutex_unlock(&pservice->lock);
2501 static int __init vcodec_service_init(void)
2505 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2506 vpu_err("Platform device register failed (%d).\n", ret);
2510 #ifdef CONFIG_DEBUG_FS
2511 vcodec_debugfs_init();
2517 static void __exit vcodec_service_exit(void)
2519 #ifdef CONFIG_DEBUG_FS
2520 vcodec_debugfs_exit();
2523 platform_driver_unregister(&vcodec_driver);
2526 module_init(vcodec_service_init);
2527 module_exit(vcodec_service_exit);
2529 #ifdef CONFIG_DEBUG_FS
2530 #include <linux/seq_file.h>
2532 static int vcodec_debugfs_init()
2534 parent = debugfs_create_dir("vcodec", NULL);
2541 static void vcodec_debugfs_exit()
2543 debugfs_remove(parent);
2546 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2548 return debugfs_create_dir(dirname, parent);
2551 static int debug_vcodec_show(struct seq_file *s, void *unused)
2553 struct vpu_subdev_data *data = s->private;
2554 struct vpu_service_info *pservice = data->pservice;
2556 vpu_reg *reg, *reg_tmp;
2557 vpu_session *session, *session_tmp;
2559 mutex_lock(&pservice->lock);
2560 vpu_service_power_on(pservice);
2561 if (data->hw_info->hw_id != HEVC_ID) {
2562 seq_printf(s, "\nENC Registers:\n");
2563 n = data->enc_dev.iosize >> 2;
2564 for (i = 0; i < n; i++)
2565 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2567 seq_printf(s, "\nDEC Registers:\n");
2568 n = data->dec_dev.iosize >> 2;
2569 for (i = 0; i < n; i++)
2570 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2572 seq_printf(s, "\nvpu service status:\n");
2573 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2574 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2575 /*seq_printf(s, "waiting reg set %d\n");*/
2576 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2577 seq_printf(s, "waiting register set\n");
2579 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2580 seq_printf(s, "running register set\n");
2582 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2583 seq_printf(s, "done register set\n");
2586 mutex_unlock(&pservice->lock);
2591 static int debug_vcodec_open(struct inode *inode, struct file *file)
2593 return single_open(file, debug_vcodec_show, inode->i_private);
2598 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2599 #include "hevc_test_inc/pps_00.h"
2600 #include "hevc_test_inc/register_00.h"
2601 #include "hevc_test_inc/rps_00.h"
2602 #include "hevc_test_inc/scaling_list_00.h"
2603 #include "hevc_test_inc/stream_00.h"
2605 #include "hevc_test_inc/pps_01.h"
2606 #include "hevc_test_inc/register_01.h"
2607 #include "hevc_test_inc/rps_01.h"
2608 #include "hevc_test_inc/scaling_list_01.h"
2609 #include "hevc_test_inc/stream_01.h"
2611 #include "hevc_test_inc/cabac.h"
2613 extern struct ion_client *rockchip_ion_client_create(const char * name);
2615 static struct ion_client *ion_client = NULL;
2616 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2618 int size = (len+15) & (~15);
2619 struct ion_handle *handle;
2620 u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2622 if (ion_client == NULL)
2623 ion_client = rockchip_ion_client_create("vcodec");
2625 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2627 ptr = ion_map_kernel(ion_client, handle);
2629 ion_phys(ion_client, handle, phy, &size);
2631 memcpy(ptr, tbl, len);
2636 u8* get_align_ptr_no_copy(int len, u32 *phy)
2638 int size = (len+15) & (~15);
2639 struct ion_handle *handle;
2642 if (ion_client == NULL)
2643 ion_client = rockchip_ion_client_create("vcodec");
2645 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2647 ptr = ion_map_kernel(ion_client, handle);
2649 ion_phys(ion_client, handle, phy, &size);
2655 static int hevc_test_case0(vpu_service_info *pservice)
2657 vpu_session session;
2659 unsigned long size = 272;//sizeof(register_00); // registers array length
2662 u8 *pps_tbl[TEST_CNT];
2663 u8 *register_tbl[TEST_CNT];
2664 u8 *rps_tbl[TEST_CNT];
2665 u8 *scaling_list_tbl[TEST_CNT];
2666 u8 *stream_tbl[TEST_CNT];
2682 volatile u8 *stream_buf;
2683 volatile u8 *pps_buf;
2684 volatile u8 *rps_buf;
2685 volatile u8 *scl_buf;
2686 volatile u8 *yuv_buf;
2687 volatile u8 *cabac_buf;
2688 volatile u8 *ref_buf;
2694 pps_tbl[0] = pps_00;
2695 pps_tbl[1] = pps_01;
2697 register_tbl[0] = register_00;
2698 register_tbl[1] = register_01;
2700 rps_tbl[0] = rps_00;
2701 rps_tbl[1] = rps_01;
2703 scaling_list_tbl[0] = scaling_list_00;
2704 scaling_list_tbl[1] = scaling_list_01;
2706 stream_tbl[0] = stream_00;
2707 stream_tbl[1] = stream_01;
2709 stream_size[0] = sizeof(stream_00);
2710 stream_size[1] = sizeof(stream_01);
2712 pps_size[0] = sizeof(pps_00);
2713 pps_size[1] = sizeof(pps_01);
2715 rps_size[0] = sizeof(rps_00);
2716 rps_size[1] = sizeof(rps_01);
2718 scl_size[0] = sizeof(scaling_list_00);
2719 scl_size[1] = sizeof(scaling_list_01);
2721 cabac_size[0] = sizeof(Cabac_table);
2722 cabac_size[1] = sizeof(Cabac_table);
2724 /* create session */
2725 session.pid = current->pid;
2726 session.type = VPU_DEC;
2727 INIT_LIST_HEAD(&session.waiting);
2728 INIT_LIST_HEAD(&session.running);
2729 INIT_LIST_HEAD(&session.done);
2730 INIT_LIST_HEAD(&session.list_session);
2731 init_waitqueue_head(&session.wait);
2732 atomic_set(&session.task_running, 0);
2733 list_add_tail(&session.list_session, &pservice->session);
2735 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2736 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2738 while (testidx < TEST_CNT) {
2739 /* create registers */
2740 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2742 vpu_err("error: kmalloc fail in reg_init\n");
2746 if (size > pservice->reg_size) {
2747 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2748 size = pservice->reg_size;
2750 reg->session = &session;
2751 reg->type = session.type;
2753 reg->freq = VPU_FREQ_DEFAULT;
2754 reg->reg = (unsigned long *)®[1];
2755 INIT_LIST_HEAD(®->session_link);
2756 INIT_LIST_HEAD(®->status_link);
2758 /* TODO: stuff registers */
2759 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2761 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2762 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2763 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2764 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2765 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2769 /* TODO: replace reigster address */
2770 for (i=0; i<64; i++) {
2774 scaling_offset = (u32)pps[i*80+74];
2775 scaling_offset += (u32)pps[i*80+75] << 8;
2776 scaling_offset += (u32)pps[i*80+76] << 16;
2777 scaling_offset += (u32)pps[i*80+77] << 24;
2779 tmp = phy_scl + scaling_offset;
2781 pps[i*80+74] = tmp & 0xff;
2782 pps[i*80+75] = (tmp >> 8) & 0xff;
2783 pps[i*80+76] = (tmp >> 16) & 0xff;
2784 pps[i*80+77] = (tmp >> 24) & 0xff;
2787 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2788 __func__, __LINE__, phy_str, phy_pps, phy_rps);
2791 reg->reg[4] = phy_str;
2792 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2793 reg->reg[6] = phy_cabac;
2794 reg->reg[7] = testidx?phy_ref:phy_yuv;
2795 reg->reg[42] = phy_pps;
2796 reg->reg[43] = phy_rps;
2797 for (i = 10; i <= 24; i++)
2798 reg->reg[i] = phy_yuv;
2800 mutex_lock(pservice->lock);
2801 list_add_tail(®->status_link, &pservice->waiting);
2802 list_add_tail(®->session_link, &session.waiting);
2803 mutex_unlock(pservice->lock);
2805 /* stuff hardware */
2808 /* wait for result */
2809 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2810 if (!list_empty(&session.done)) {
2812 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2815 if (unlikely(ret < 0)) {
2816 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2817 } else if (0 == ret) {
2818 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2823 int task_running = atomic_read(&session.task_running);
2825 mutex_lock(pservice->lock);
2826 vpu_service_dump(pservice);
2828 atomic_set(&session.task_running, 0);
2829 atomic_sub(task_running, &pservice->total_running);
2830 printk("%d task is running but not return, reset hardware...", task_running);
2834 vpu_service_session_clear(pservice, &session);
2835 mutex_unlock(pservice->lock);
2837 printk("\nDEC Registers:\n");
2838 n = data->dec_dev.iosize >> 2;
2840 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2842 vpu_err("test index %d failed\n", testidx);
2845 vpu_debug(3, "test index %d success\n", testidx);
2847 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2849 for (i=0; i<68; i++) {
2851 printk("%02d: ", i);
2852 printk("%08x ", reg->reg[i]);
2860 reg_deinit(data, reg);