2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/clk.h>
20 #include <linux/compat.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/miscdevice.h>
31 #include <linux/poll.h>
32 #include <linux/platform_device.h>
33 #include <linux/reset.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
36 #include <linux/wakelock.h>
37 #include <linux/cdev.h>
39 #include <linux/of_platform.h>
40 #include <linux/of_irq.h>
41 #include <linux/rockchip/cpu.h>
42 #include <linux/rockchip/cru.h>
43 #include <linux/rockchip/pmu.h>
44 #ifdef CONFIG_MFD_SYSCON
45 #include <linux/regmap.h>
47 #include <linux/mfd/syscon.h>
49 #include <asm/cacheflush.h>
50 #include <linux/uaccess.h>
51 #include <linux/rockchip/grf.h>
53 #if defined(CONFIG_ION_ROCKCHIP)
54 #include <linux/rockchip_ion.h>
57 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
58 #define CONFIG_VCODEC_MMU
61 #ifdef CONFIG_VCODEC_MMU
62 #include <linux/rockchip-iovmm.h>
63 #include <linux/dma-buf.h>
66 #ifdef CONFIG_DEBUG_FS
67 #include <linux/debugfs.h>
70 #if defined(CONFIG_ARCH_RK319X)
74 #include "vcodec_service.h"
78 * +------+-------------------+
80 * +------+-------------------+
81 * 0~23 bit is for different information type
82 * 24~31 bit is for information print format
85 #define DEBUG_POWER 0x00000001
86 #define DEBUG_CLOCK 0x00000002
87 #define DEBUG_IRQ_STATUS 0x00000004
88 #define DEBUG_IOMMU 0x00000008
89 #define DEBUG_IOCTL 0x00000010
90 #define DEBUG_FUNCTION 0x00000020
91 #define DEBUG_REGISTER 0x00000040
92 #define DEBUG_EXTRA_INFO 0x00000080
93 #define DEBUG_TIMING 0x00000100
95 #define PRINT_FUNCTION 0x80000000
96 #define PRINT_LINE 0x40000000
99 module_param(debug, int, S_IRUGO | S_IWUSR);
100 MODULE_PARM_DESC(debug,
101 "Debug level - higher value produces more verbose messages");
103 #define HEVC_TEST_ENABLE 0
104 #define VCODEC_CLOCK_ENABLE 1
107 VPU_DEC_ID_9190 = 0x6731,
108 VPU_ID_8270 = 0x8270,
109 VPU_ID_4831 = 0x4831,
116 VPU_TYPE_COMBO_NOENC,
121 VPU_DEC_TYPE_9190 = 0,
122 VPU_ENC_TYPE_8270 = 0x100,
126 typedef enum VPU_FREQ {
139 unsigned long hw_addr;
140 unsigned long enc_offset;
141 unsigned long enc_reg_num;
142 unsigned long enc_io_size;
143 unsigned long dec_offset;
144 unsigned long dec_reg_num;
145 unsigned long dec_io_size;
148 struct extra_info_elem {
153 #define EXTRA_INFO_MAGIC 0x4C4A46
155 struct extra_info_for_iommu {
158 struct extra_info_elem elem[20];
161 #define MHZ (1000*1000)
163 #define REG_NUM_9190_DEC (60)
164 #define REG_NUM_9190_PP (41)
165 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
167 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
169 #define REG_NUM_ENC_8270 (96)
170 #define REG_SIZE_ENC_8270 (0x200)
171 #define REG_NUM_ENC_4831 (164)
172 #define REG_SIZE_ENC_4831 (0x400)
174 #define REG_NUM_HEVC_DEC (68)
176 #define SIZE_REG(reg) ((reg)*4)
178 static VPU_HW_INFO_E vpu_hw_set[] = {
180 .hw_id = VPU_ID_8270,
183 .enc_reg_num = REG_NUM_ENC_8270,
184 .enc_io_size = REG_NUM_ENC_8270 * 4,
185 .dec_offset = REG_SIZE_ENC_8270,
186 .dec_reg_num = REG_NUM_9190_DEC_PP,
187 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
190 .hw_id = VPU_ID_4831,
193 .enc_reg_num = REG_NUM_ENC_4831,
194 .enc_io_size = REG_NUM_ENC_4831 * 4,
195 .dec_offset = REG_SIZE_ENC_4831,
196 .dec_reg_num = REG_NUM_9190_DEC_PP,
197 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
203 .dec_reg_num = REG_NUM_HEVC_DEC,
204 .dec_io_size = REG_NUM_HEVC_DEC * 4,
207 .hw_id = VPU_DEC_ID_9190,
213 .dec_reg_num = REG_NUM_9190_DEC_PP,
214 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
219 #define BIT(x) (1<<(x))
222 // interrupt and error status register
223 #define DEC_INTERRUPT_REGISTER 1
224 #define DEC_INTERRUPT_BIT BIT(8)
225 #define DEC_READY_BIT BIT(12)
226 #define DEC_BUS_ERROR_BIT BIT(13)
227 #define DEC_BUFFER_EMPTY_BIT BIT(14)
228 #define DEC_ASO_ERROR_BIT BIT(15)
229 #define DEC_STREAM_ERROR_BIT BIT(16)
230 #define DEC_SLICE_DONE_BIT BIT(17)
231 #define DEC_TIMEOUT_BIT BIT(18)
232 #define DEC_ERR_MASK DEC_BUS_ERROR_BIT \
233 |DEC_BUFFER_EMPTY_BIT \
234 |DEC_STREAM_ERROR_BIT \
237 #define PP_INTERRUPT_REGISTER 60
238 #define PP_INTERRUPT_BIT BIT(8)
239 #define PP_READY_BIT BIT(12)
240 #define PP_BUS_ERROR_BIT BIT(13)
241 #define PP_ERR_MASK PP_BUS_ERROR_BIT
243 #define ENC_INTERRUPT_REGISTER 1
244 #define ENC_INTERRUPT_BIT BIT(0)
245 #define ENC_READY_BIT BIT(2)
246 #define ENC_BUS_ERROR_BIT BIT(3)
247 #define ENC_BUFFER_FULL_BIT BIT(5)
248 #define ENC_TIMEOUT_BIT BIT(6)
249 #define ENC_ERR_MASK ENC_BUS_ERROR_BIT \
250 |ENC_BUFFER_FULL_BIT \
253 #define HEVC_INTERRUPT_REGISTER 1
254 #define HEVC_DEC_INT_RAW_BIT BIT(9)
255 #define HEVC_DEC_BUS_ERROR_BIT BIT(13)
256 #define HEVC_DEC_STR_ERROR_BIT BIT(14)
257 #define HEVC_DEC_TIMEOUT_BIT BIT(15)
258 #define HEVC_DEC_BUFFER_EMPTY_BIT BIT(16)
259 #define HEVC_DEC_COLMV_ERROR_BIT BIT(17)
260 #define HEVC_DEC_ERR_MASK HEVC_DEC_BUS_ERROR_BIT \
261 |HEVC_DEC_STR_ERROR_BIT \
262 |HEVC_DEC_TIMEOUT_BIT \
263 |HEVC_DEC_BUFFER_EMPTY_BIT \
264 |HEVC_DEC_COLMV_ERROR_BIT
267 // gating configuration set
268 #define VPU_REG_EN_ENC 14
269 #define VPU_REG_ENC_GATE 2
270 #define VPU_REG_ENC_GATE_BIT (1<<4)
272 #define VPU_REG_EN_DEC 1
273 #define VPU_REG_DEC_GATE 2
274 #define VPU_REG_DEC_GATE_BIT (1<<10)
275 #define VPU_REG_EN_PP 0
276 #define VPU_REG_PP_GATE 1
277 #define VPU_REG_PP_GATE_BIT (1<<8)
278 #define VPU_REG_EN_DEC_PP 1
279 #define VPU_REG_DEC_PP_GATE 61
280 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
284 #define vpu_debug_func(type, fmt, args...) \
286 if (unlikely(debug & type)) { \
287 pr_info("%s:%d: " fmt, \
288 __func__, __LINE__, ##args); \
291 #define vpu_debug(type, fmt, args...) \
293 if (unlikely(debug & type)) { \
294 pr_info(fmt, ##args); \
298 #define vpu_debug_func(level, fmt, args...)
299 #define vpu_debug(level, fmt, args...)
302 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
303 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
305 #define vpu_err(fmt, args...) \
306 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
308 #if defined(CONFIG_VCODEC_MMU)
309 static u8 addr_tbl_vpu_h264dec[] = {
310 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
311 25, 26, 27, 28, 29, 40, 41
314 static u8 addr_tbl_vpu_vp8dec[] = {
315 10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
318 static u8 addr_tbl_vpu_vp6dec[] = {
319 12, 13, 14, 18, 27, 40
322 static u8 addr_tbl_vpu_vc1dec[] = {
323 12, 13, 14, 15, 16, 17, 27, 41
326 static u8 addr_tbl_vpu_jpegdec[] = {
330 static u8 addr_tbl_vpu_defaultdec[] = {
331 12, 13, 14, 15, 16, 17, 40, 41
334 static u8 addr_tbl_vpu_enc[] = {
335 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
338 static u8 addr_tbl_hevc_dec[] = {
339 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
340 21, 22, 23, 24, 42, 43
365 * struct for process session which connect to vpu
367 * @author ChenHengming (2011-5-3)
369 typedef struct vpu_session {
370 enum VPU_CLIENT_TYPE type;
371 /* a linked list of data so we can access them for debugging */
372 struct list_head list_session;
373 /* a linked list of register data waiting for process */
374 struct list_head waiting;
375 /* a linked list of register data in processing */
376 struct list_head running;
377 /* a linked list of register data processed */
378 struct list_head done;
379 wait_queue_head_t wait;
381 atomic_t task_running;
385 * struct for process register set
387 * @author ChenHengming (2011-5-4)
389 typedef struct vpu_reg {
390 enum VPU_CLIENT_TYPE type;
392 vpu_session *session;
393 struct vpu_subdev_data *data;
394 struct list_head session_link; /* link to vpu service session */
395 struct list_head status_link; /* link to register set list */
397 #if defined(CONFIG_VCODEC_MMU)
398 struct list_head mem_region_list;
404 typedef struct vpu_device {
405 atomic_t irq_count_codec;
406 atomic_t irq_count_pp;
407 unsigned long iobaseaddr;
409 volatile u32 *hwregs;
412 enum vcodec_device_id {
413 VCODEC_DEVICE_ID_VPU,
414 VCODEC_DEVICE_ID_HEVC,
415 VCODEC_DEVICE_ID_COMBO
418 enum VCODEC_RUNNING_MODE {
419 VCODEC_RUNNING_MODE_NONE = -1,
420 VCODEC_RUNNING_MODE_VPU,
421 VCODEC_RUNNING_MODE_HEVC,
424 struct vcodec_mem_region {
425 struct list_head srv_lnk;
426 struct list_head reg_lnk;
427 struct list_head session_lnk;
428 unsigned long iova; /* virtual address for iommu */
431 struct ion_handle *hdl;
435 MMU_ACTIVATED = BIT(0)
438 struct vpu_subdev_data {
442 struct device *child_dev;
446 struct vpu_service_info *pservice;
449 enum VCODEC_RUNNING_MODE mode;
450 struct list_head lnk_service;
456 VPU_HW_INFO_E *hw_info;
461 #ifdef CONFIG_DEBUG_FS
462 struct dentry *debugfs_dir;
463 struct dentry *debugfs_file_regs;
466 #if defined(CONFIG_VCODEC_MMU)
467 struct device *mmu_dev;
471 typedef struct vpu_service_info {
472 struct wake_lock wake_lock;
473 struct delayed_work power_off_work;
475 struct list_head waiting; /* link to link_reg in struct vpu_reg */
476 struct list_head running; /* link to link_reg in struct vpu_reg */
477 struct list_head done; /* link to link_reg in struct vpu_reg */
478 struct list_head session; /* link to list_session in struct vpu_session */
479 atomic_t total_running;
481 atomic_t power_on_cnt;
482 atomic_t power_off_cnt;
486 struct vpu_dec_config dec_config;
487 struct vpu_enc_config enc_config;
491 atomic_t freq_status;
493 struct clk *aclk_vcodec;
494 struct clk *hclk_vcodec;
495 struct clk *clk_core;
496 struct clk *clk_cabac;
497 struct clk *pd_video;
499 #ifdef CONFIG_RESET_CONTROLLER
500 struct reset_control *rst_a;
501 struct reset_control *rst_h;
502 struct reset_control *rst_v;
507 atomic_t reset_request;
508 #if defined(CONFIG_VCODEC_MMU)
509 struct ion_client *ion_client;
510 struct list_head mem_region_list;
513 enum vcodec_device_id dev_id;
515 enum VCODEC_RUNNING_MODE curr_mode;
518 struct delayed_work simulate_work;
524 #ifdef CONFIG_MFD_SYSCON
525 struct regmap *grf_base;
532 struct list_head subdev_list;
535 struct vcodec_combo {
536 struct vpu_service_info *vpu_srv;
537 struct vpu_service_info *hevc_srv;
538 struct list_head waiting;
539 struct list_head running;
540 struct mutex run_lock;
542 enum vcodec_device_id current_hw_mode;
551 struct compat_vpu_request {
557 /* debugfs root directory for all device (vpu, hevc).*/
558 static struct dentry *parent;
560 #ifdef CONFIG_DEBUG_FS
561 static int vcodec_debugfs_init(void);
562 static void vcodec_debugfs_exit(void);
563 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
564 static int debug_vcodec_open(struct inode *inode, struct file *file);
566 static const struct file_operations debug_vcodec_fops = {
567 .open = debug_vcodec_open,
570 .release = single_release,
574 #define VDPU_SOFT_RESET_REG 101
575 #define VDPU_CLEAN_CACHE_REG 516
576 #define VEPU_CLEAN_CACHE_REG 772
577 #define HEVC_CLEAN_CACHE_REG 260
579 #define VPU_REG_ENABLE(base, reg) do { \
583 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
584 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
585 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
586 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
588 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
589 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
593 struct timeval start;
606 task_info tasks[TASK_TYPE_BUTT] = {
609 .error_mask = ENC_ERR_MASK
613 .error_mask = DEC_ERR_MASK
617 .error_mask = PP_ERR_MASK
621 .error_mask = HEVC_DEC_ERR_MASK
625 static void time_record(task_info *task, int is_end)
627 if (unlikely(debug & DEBUG_TIMING)) {
628 do_gettimeofday((is_end)?(&task->end):(&task->start));
632 static void time_diff(task_info *task)
634 vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
635 (task->end.tv_sec - task->start.tv_sec) * 1000 +
636 (task->end.tv_usec - task->start.tv_usec) / 1000);
639 static void vcodec_enter_mode(struct vpu_subdev_data *data)
643 struct vpu_service_info *pservice = data->pservice;
644 struct vpu_subdev_data *subdata, *n;
645 if (pservice->subcnt < 2) {
646 #if defined(CONFIG_VCODEC_MMU)
647 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
648 set_bit(MMU_ACTIVATED, &data->state);
649 if (atomic_read(&pservice->enabled))
650 rockchip_iovmm_activate(data->dev);
652 BUG_ON(!atomic_read(&pservice->enabled));
658 if (pservice->curr_mode == data->mode)
661 vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
662 #if defined(CONFIG_VCODEC_MMU)
663 list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
664 if (data != subdata && subdata->mmu_dev &&
665 test_bit(MMU_ACTIVATED, &subdata->state)) {
666 clear_bit(MMU_ACTIVATED, &subdata->state);
667 rockchip_iovmm_deactivate(subdata->dev);
671 bits = 1 << pservice->mode_bit;
672 #ifdef CONFIG_MFD_SYSCON
673 regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
675 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
676 regmap_write(pservice->grf_base, pservice->mode_ctrl,
677 raw | bits | (bits << 16));
679 regmap_write(pservice->grf_base, pservice->mode_ctrl,
680 (raw & (~bits)) | (bits << 16));
682 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
683 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
684 writel_relaxed(raw | bits | (bits << 16),
685 pservice->grf_base + pservice->mode_ctrl / 4);
687 writel_relaxed((raw & (~bits)) | (bits << 16),
688 pservice->grf_base + pservice->mode_ctrl / 4);
690 #if defined(CONFIG_VCODEC_MMU)
691 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
692 set_bit(MMU_ACTIVATED, &data->state);
693 if (atomic_read(&pservice->enabled))
694 rockchip_iovmm_activate(data->dev);
696 BUG_ON(!atomic_read(&pservice->enabled));
699 pservice->prev_mode = pservice->curr_mode;
700 pservice->curr_mode = data->mode;
703 static void vcodec_exit_mode(struct vpu_subdev_data *data)
705 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
706 clear_bit(MMU_ACTIVATED, &data->state);
707 rockchip_iovmm_deactivate(data->dev);
708 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
712 static int vpu_get_clk(struct vpu_service_info *pservice)
714 #if VCODEC_CLOCK_ENABLE
715 switch (pservice->dev_id) {
716 case VCODEC_DEVICE_ID_HEVC:
717 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
718 if (IS_ERR(pservice->pd_video)) {
719 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
722 case VCODEC_DEVICE_ID_COMBO:
723 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
724 if (IS_ERR(pservice->clk_cabac)) {
725 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
726 pservice->clk_cabac = NULL;
728 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
729 if (IS_ERR(pservice->clk_core)) {
730 dev_err(pservice->dev, "failed on clk_get clk_core\n");
733 case VCODEC_DEVICE_ID_VPU:
734 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
735 if (IS_ERR(pservice->aclk_vcodec)) {
736 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
740 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
741 if (IS_ERR(pservice->hclk_vcodec)) {
742 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
745 if (pservice->pd_video == NULL) {
746 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
747 if (IS_ERR(pservice->pd_video)) {
748 pservice->pd_video = NULL;
749 dev_info(pservice->dev, "do not have pd_video\n");
763 static void vpu_put_clk(struct vpu_service_info *pservice)
765 #if VCODEC_CLOCK_ENABLE
766 if (pservice->pd_video)
767 devm_clk_put(pservice->dev, pservice->pd_video);
768 if (pservice->aclk_vcodec)
769 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
770 if (pservice->hclk_vcodec)
771 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
772 if (pservice->clk_core)
773 devm_clk_put(pservice->dev, pservice->clk_core);
774 if (pservice->clk_cabac)
775 devm_clk_put(pservice->dev, pservice->clk_cabac);
779 static void vpu_reset(struct vpu_subdev_data *data)
781 struct vpu_service_info *pservice = data->pservice;
782 pr_info("%s: resetting...", dev_name(pservice->dev));
784 #if defined(CONFIG_ARCH_RK29)
785 clk_disable(aclk_ddr_vepu);
786 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
787 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
788 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
789 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
791 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
792 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
793 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
794 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
795 clk_enable(aclk_ddr_vepu);
796 #elif defined(CONFIG_ARCH_RK30)
797 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
798 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
799 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
800 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
801 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
803 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
804 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
805 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
806 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
807 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
810 WARN_ON(pservice->reg_codec != NULL);
811 WARN_ON(pservice->reg_pproc != NULL);
812 WARN_ON(pservice->reg_resev != NULL);
813 pservice->reg_codec = NULL;
814 pservice->reg_pproc = NULL;
815 pservice->reg_resev = NULL;
817 pr_info("for 3288/3368...");
818 #ifdef CONFIG_RESET_CONTROLLER
819 if (pservice->rst_a && pservice->rst_h) {
821 reset_control_assert(pservice->rst_v);
822 reset_control_assert(pservice->rst_a);
823 reset_control_assert(pservice->rst_h);
824 usleep_range(10, 20);
825 reset_control_deassert(pservice->rst_h);
826 reset_control_deassert(pservice->rst_a);
828 reset_control_deassert(pservice->rst_v);
832 #if defined(CONFIG_VCODEC_MMU)
833 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
834 clear_bit(MMU_ACTIVATED, &data->state);
835 if (atomic_read(&pservice->enabled))
836 rockchip_iovmm_deactivate(data->dev);
838 BUG_ON(!atomic_read(&pservice->enabled));
841 atomic_set(&pservice->reset_request, 0);
845 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
846 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
849 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
850 reg_deinit(data, reg);
852 list_for_each_entry_safe(reg, n, &session->running, session_link) {
853 reg_deinit(data, reg);
855 list_for_each_entry_safe(reg, n, &session->done, session_link) {
856 reg_deinit(data, reg);
860 static void vpu_service_dump(struct vpu_service_info *pservice)
864 static void vpu_service_power_off(struct vpu_service_info *pservice)
867 struct vpu_subdev_data *data = NULL, *n;
868 int ret = atomic_add_unless(&pservice->enabled, -1, 0);
872 total_running = atomic_read(&pservice->total_running);
874 pr_alert("alert: power off when %d task running!!\n", total_running);
876 pr_alert("alert: delay 50 ms for running task\n");
877 vpu_service_dump(pservice);
880 pr_info("%s: power off...", dev_name(pservice->dev));
882 #if defined(CONFIG_VCODEC_MMU)
883 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
884 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
885 clear_bit(MMU_ACTIVATED, &data->state);
886 rockchip_iovmm_deactivate(data->dev);
889 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
892 #if VCODEC_CLOCK_ENABLE
893 if (pservice->pd_video)
894 clk_disable_unprepare(pservice->pd_video);
895 if (pservice->hclk_vcodec)
896 clk_disable_unprepare(pservice->hclk_vcodec);
897 if (pservice->aclk_vcodec)
898 clk_disable_unprepare(pservice->aclk_vcodec);
899 if (pservice->clk_core)
900 clk_disable_unprepare(pservice->clk_core);
901 if (pservice->clk_cabac)
902 clk_disable_unprepare(pservice->clk_cabac);
905 atomic_add(1, &pservice->power_off_cnt);
906 wake_unlock(&pservice->wake_lock);
910 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
912 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
915 static void vpu_power_off_work(struct work_struct *work_s)
917 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
918 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
920 if (mutex_trylock(&pservice->lock)) {
921 vpu_service_power_off(pservice);
922 mutex_unlock(&pservice->lock);
924 /* Come back later if the device is busy... */
925 vpu_queue_power_off_work(pservice);
929 static void vpu_service_power_on(struct vpu_service_info *pservice)
933 ktime_t now = ktime_get();
934 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
935 cancel_delayed_work_sync(&pservice->power_off_work);
936 vpu_queue_power_off_work(pservice);
939 ret = atomic_add_unless(&pservice->enabled, 1, 1);
943 pr_info("%s: power on\n", dev_name(pservice->dev));
945 #define BIT_VCODEC_CLK_SEL (1<<10)
947 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
948 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
949 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
951 #if VCODEC_CLOCK_ENABLE
952 if (pservice->aclk_vcodec)
953 clk_prepare_enable(pservice->aclk_vcodec);
954 if (pservice->hclk_vcodec)
955 clk_prepare_enable(pservice->hclk_vcodec);
956 if (pservice->clk_core)
957 clk_prepare_enable(pservice->clk_core);
958 if (pservice->clk_cabac)
959 clk_prepare_enable(pservice->clk_cabac);
960 if (pservice->pd_video)
961 clk_prepare_enable(pservice->pd_video);
965 atomic_add(1, &pservice->power_on_cnt);
966 wake_lock(&pservice->wake_lock);
969 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
971 u32 type = (reg->reg[3] & 0xF0000000) >> 28;
972 return ((type == 8) || (type == 4));
975 static inline bool reg_check_interlace(vpu_reg *reg)
977 u32 type = (reg->reg[3] & (1 << 23));
981 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
983 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
987 static inline int reg_probe_width(vpu_reg *reg)
989 int width_in_mb = reg->reg[4] >> 23;
990 return width_in_mb * 16;
993 #if defined(CONFIG_VCODEC_MMU)
994 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
996 struct vpu_service_info *pservice = data->pservice;
997 struct ion_handle *hdl;
999 struct vcodec_mem_region *mem_region;
1001 hdl = ion_import_dma_buf(pservice->ion_client, fd);
1003 vpu_err("import dma-buf from fd %d failed\n", fd);
1004 return PTR_ERR(hdl);
1006 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1008 if (mem_region == NULL) {
1009 vpu_err("allocate memory for iommu memory region failed\n");
1010 ion_free(pservice->ion_client, hdl);
1014 mem_region->hdl = hdl;
1015 ret = ion_map_iommu(data->dev, pservice->ion_client,
1016 mem_region->hdl, &mem_region->iova, &mem_region->len);
1019 vpu_err("ion map iommu failed\n");
1021 ion_free(pservice->ion_client, hdl);
1024 INIT_LIST_HEAD(&mem_region->reg_lnk);
1025 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1026 return mem_region->iova;
1029 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1030 int size, vpu_reg *reg,
1031 struct extra_info_for_iommu *ext_inf)
1033 struct vpu_service_info *pservice = data->pservice;
1038 if (tbl == NULL || size <= 0) {
1039 dev_err(pservice->dev, "input arguments invalidate\n");
1043 for (i = 0; i < size; i++) {
1044 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1046 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1047 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1048 /* special for vpu dec num 41 regitster */
1049 offset = reg->reg[tbl[i]] >> 10 << 4;
1051 offset = reg->reg[tbl[i]] >> 10;
1054 struct ion_handle *hdl;
1056 struct vcodec_mem_region *mem_region;
1058 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1060 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1061 return PTR_ERR(hdl);
1064 if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1067 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1068 for (i=0; i<64; i++) {
1072 scaling_offset = (u32)pps[i*80+74];
1073 scaling_offset += (u32)pps[i*80+75] << 8;
1074 scaling_offset += (u32)pps[i*80+76] << 16;
1075 scaling_offset += (u32)pps[i*80+77] << 24;
1076 scaling_fd = scaling_offset&0x3ff;
1077 scaling_offset = scaling_offset >> 10;
1078 if(scaling_fd > 0) {
1079 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1080 tmp += scaling_offset;
1081 pps[i*80+74] = tmp & 0xff;
1082 pps[i*80+75] = (tmp >> 8) & 0xff;
1083 pps[i*80+76] = (tmp >> 16) & 0xff;
1084 pps[i*80+77] = (tmp >> 24) & 0xff;
1089 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1091 if (mem_region == NULL) {
1092 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1093 ion_free(pservice->ion_client, hdl);
1097 mem_region->hdl = hdl;
1098 mem_region->reg_idx = tbl[i];
1099 ret = ion_map_iommu(data->dev,
1100 pservice->ion_client,
1106 dev_err(pservice->dev, "ion map iommu failed\n");
1108 ion_free(pservice->ion_client, hdl);
1112 /* special for vpu dec num 12: record decoded length
1113 hacking for decoded length
1114 NOTE: not a perfect fix, the fd is not recorded */
1115 if (tbl[i] == 12 && data->hw_info->hw_id != HEVC_ID &&
1116 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {
1117 reg->dec_base = mem_region->iova + offset;
1118 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n", reg->dec_base);
1121 reg->reg[tbl[i]] = mem_region->iova + offset;
1122 INIT_LIST_HEAD(&mem_region->reg_lnk);
1123 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
1127 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1128 for (i=0; i<ext_inf->cnt; i++) {
1129 vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1130 ext_inf->elem[i].index,
1131 ext_inf->elem[i].offset);
1132 reg->reg[ext_inf->elem[i].index] +=
1133 ext_inf->elem[i].offset;
1140 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1142 struct extra_info_for_iommu *ext_inf)
1148 hw_id = data->hw_info->hw_id;
1150 if (hw_id == HEVC_ID) {
1151 tbl = addr_tbl_hevc_dec;
1152 size = sizeof(addr_tbl_hevc_dec);
1154 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1155 switch (reg_check_fmt(reg)) {
1156 case VPU_DEC_FMT_H264:
1158 tbl = addr_tbl_vpu_h264dec;
1159 size = sizeof(addr_tbl_vpu_h264dec);
1162 case VPU_DEC_FMT_VP8:
1163 case VPU_DEC_FMT_VP7:
1165 tbl = addr_tbl_vpu_vp8dec;
1166 size = sizeof(addr_tbl_vpu_vp8dec);
1170 case VPU_DEC_FMT_VP6:
1172 tbl = addr_tbl_vpu_vp6dec;
1173 size = sizeof(addr_tbl_vpu_vp6dec);
1176 case VPU_DEC_FMT_VC1:
1178 tbl = addr_tbl_vpu_vc1dec;
1179 size = sizeof(addr_tbl_vpu_vc1dec);
1183 case VPU_DEC_FMT_JPEG:
1185 tbl = addr_tbl_vpu_jpegdec;
1186 size = sizeof(addr_tbl_vpu_jpegdec);
1190 tbl = addr_tbl_vpu_defaultdec;
1191 size = sizeof(addr_tbl_vpu_defaultdec);
1194 } else if (reg->type == VPU_ENC) {
1195 tbl = addr_tbl_vpu_enc;
1196 size = sizeof(addr_tbl_vpu_enc);
1201 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1208 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1209 vpu_session *session, void __user *src, u32 size)
1211 struct vpu_service_info *pservice = data->pservice;
1213 struct extra_info_for_iommu extra_info;
1214 vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1219 vpu_err("error: kmalloc fail in reg_init\n");
1223 if (size > data->reg_size) {
1224 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1225 size, data->reg_size);*/
1226 extra_size = size - data->reg_size;
1227 size = data->reg_size;
1229 reg->session = session;
1231 reg->type = session->type;
1233 reg->freq = VPU_FREQ_DEFAULT;
1234 reg->reg = (u32 *)®[1];
1235 INIT_LIST_HEAD(®->session_link);
1236 INIT_LIST_HEAD(®->status_link);
1238 #if defined(CONFIG_VCODEC_MMU)
1240 INIT_LIST_HEAD(®->mem_region_list);
1243 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1244 vpu_err("error: copy_from_user failed in reg_init\n");
1249 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1250 vpu_err("error: copy_from_user failed in reg_init\n");
1255 #if defined(CONFIG_VCODEC_MMU)
1256 if (data->mmu_dev &&
1257 0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1258 vpu_err("error: translate reg address failed\n");
1264 mutex_lock(&pservice->lock);
1265 list_add_tail(®->status_link, &pservice->waiting);
1266 list_add_tail(®->session_link, &session->waiting);
1267 mutex_unlock(&pservice->lock);
1269 if (pservice->auto_freq) {
1270 if (!soc_is_rk2928g()) {
1271 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1272 if (reg_check_rmvb_wmv(reg)) {
1273 reg->freq = VPU_FREQ_200M;
1274 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1275 if (reg_probe_width(reg) > 3200) {
1276 /*raise frequency for 4k avc.*/
1277 reg->freq = VPU_FREQ_600M;
1280 if (reg_check_interlace(reg)) {
1281 reg->freq = VPU_FREQ_400M;
1285 if (reg->type == VPU_PP) {
1286 reg->freq = VPU_FREQ_400M;
1294 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1296 struct vpu_service_info *pservice = data->pservice;
1297 #if defined(CONFIG_VCODEC_MMU)
1298 struct vcodec_mem_region *mem_region = NULL, *n;
1301 list_del_init(®->session_link);
1302 list_del_init(®->status_link);
1303 if (reg == pservice->reg_codec)
1304 pservice->reg_codec = NULL;
1305 if (reg == pservice->reg_pproc)
1306 pservice->reg_pproc = NULL;
1308 #if defined(CONFIG_VCODEC_MMU)
1309 /* release memory region attach to this registers table. */
1310 if (data->mmu_dev) {
1311 list_for_each_entry_safe(mem_region, n,
1312 ®->mem_region_list, reg_lnk) {
1313 /* do not unmap iommu manually,
1314 unmap will proccess when memory release */
1315 /*vcodec_enter_mode(data);
1316 ion_unmap_iommu(data->dev,
1317 pservice->ion_client,
1319 vcodec_exit_mode();*/
1320 ion_free(pservice->ion_client, mem_region->hdl);
1321 list_del_init(&mem_region->reg_lnk);
1330 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1333 list_del_init(®->status_link);
1334 list_add_tail(®->status_link, &pservice->running);
1336 list_del_init(®->session_link);
1337 list_add_tail(®->session_link, ®->session->running);
1341 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1344 u32 *dst = (u32 *)®->reg[0];
1346 for (i = 0; i < count; i++)
1351 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1354 struct vpu_service_info *pservice = data->pservice;
1359 list_del_init(®->status_link);
1360 list_add_tail(®->status_link, &pservice->done);
1362 list_del_init(®->session_link);
1363 list_add_tail(®->session_link, ®->session->done);
1365 /*vcodec_enter_mode(data);*/
1366 switch (reg->type) {
1368 pservice->reg_codec = NULL;
1369 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1370 irq_reg = ENC_INTERRUPT_REGISTER;
1374 int reg_len = REG_NUM_9190_DEC;
1375 pservice->reg_codec = NULL;
1376 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1377 #if defined(CONFIG_VCODEC_MMU)
1378 /* revert hack for decoded length */
1379 if (data->hw_info->hw_id != HEVC_ID) {
1380 u32 dec_get = reg->reg[12];
1381 s32 dec_length = dec_get - reg->dec_base;
1382 vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1383 reg->reg[12] = dec_length << 10;
1386 irq_reg = DEC_INTERRUPT_REGISTER;
1390 pservice->reg_pproc = NULL;
1391 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1392 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1396 pservice->reg_codec = NULL;
1397 pservice->reg_pproc = NULL;
1398 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1399 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1400 #if defined(CONFIG_VCODEC_MMU)
1401 /* revert hack for decoded length */
1402 if (data->hw_info->hw_id != HEVC_ID) {
1403 u32 dec_get = reg->reg[12];
1404 s32 dec_length = dec_get - reg->dec_base;
1405 vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1406 reg->reg[12] = dec_length << 10;
1412 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1416 vcodec_exit_mode(data);
1419 reg->reg[irq_reg] = pservice->irq_status;
1421 atomic_sub(1, ®->session->task_running);
1422 atomic_sub(1, &pservice->total_running);
1423 wake_up(®->session->wait);
1428 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1430 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1431 if (curr == reg->freq)
1433 atomic_set(&pservice->freq_status, reg->freq);
1434 switch (reg->freq) {
1435 case VPU_FREQ_200M : {
1436 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1438 case VPU_FREQ_266M : {
1439 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1441 case VPU_FREQ_300M : {
1442 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1444 case VPU_FREQ_400M : {
1445 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1447 case VPU_FREQ_500M : {
1448 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1450 case VPU_FREQ_600M : {
1451 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1454 if (soc_is_rk2928g())
1455 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1457 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1462 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1464 struct vpu_service_info *pservice = data->pservice;
1466 u32 *src = (u32 *)®->reg[0];
1469 atomic_add(1, &pservice->total_running);
1470 atomic_add(1, ®->session->task_running);
1471 if (pservice->auto_freq)
1472 vpu_service_set_freq(pservice, reg);
1474 vcodec_enter_mode(data);
1476 switch (reg->type) {
1478 int enc_count = data->hw_info->enc_reg_num;
1479 u32 *dst = (u32 *)data->enc_dev.hwregs;
1481 pservice->reg_codec = reg;
1483 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1485 for (i = 0; i < VPU_REG_EN_ENC; i++)
1488 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1491 VEPU_CLEAN_CACHE(dst);
1495 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1496 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1498 time_record(&tasks[TASK_VPU_ENC], 0);
1501 u32 *dst = (u32 *)data->dec_dev.hwregs;
1503 pservice->reg_codec = reg;
1505 if (data->hw_info->hw_id != HEVC_ID) {
1506 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1508 VDPU_CLEAN_CACHE(dst);
1510 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1512 HEVC_CLEAN_CACHE(dst);
1517 if (data->hw_info->hw_id != HEVC_ID) {
1518 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1519 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1521 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1526 time_record(&tasks[TASK_VPU_DEC], 0);
1529 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1530 pservice->reg_pproc = reg;
1532 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1534 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1539 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1541 time_record(&tasks[TASK_VPU_PP], 0);
1544 u32 *dst = (u32 *)data->dec_dev.hwregs;
1545 pservice->reg_codec = reg;
1546 pservice->reg_pproc = reg;
1548 VDPU_SOFT_RESET(dst);
1549 VDPU_CLEAN_CACHE(dst);
1551 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1554 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1557 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1558 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1559 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1561 time_record(&tasks[TASK_VPU_DEC], 0);
1564 vpu_err("error: unsupport session type %d", reg->type);
1565 atomic_sub(1, &pservice->total_running);
1566 atomic_sub(1, ®->session->task_running);
1570 /*vcodec_exit_mode(data);*/
1574 static void try_set_reg(struct vpu_subdev_data *data)
1576 struct vpu_service_info *pservice = data->pservice;
1578 if (!list_empty(&pservice->waiting)) {
1580 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1581 int reset_request = atomic_read(&pservice->reset_request);
1582 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1584 vpu_service_power_on(pservice);
1586 // first check can_set flag
1587 if (change_able || !reset_request) {
1588 switch (reg->type) {
1594 if (NULL == pservice->reg_codec)
1596 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1600 if (NULL == pservice->reg_codec) {
1601 if (NULL == pservice->reg_pproc)
1604 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1606 /* can not charge frequency when vpu is working */
1607 if (pservice->auto_freq)
1616 printk("undefined reg type %d\n", reg->type);
1621 // then check reset request
1622 if (reset_request && !change_able)
1625 // do reset before setting registers
1630 reg_from_wait_to_run(pservice, reg);
1631 reg_copy_to_hw(reg->data, reg);
1637 static int return_reg(struct vpu_subdev_data *data,
1638 vpu_reg *reg, u32 __user *dst)
1642 switch (reg->type) {
1644 if (copy_to_user(dst, ®->reg[0], data->hw_info->enc_io_size))
1649 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1650 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1655 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1660 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1666 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1670 reg_deinit(data, reg);
1675 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1678 struct vpu_subdev_data *data =
1679 container_of(filp->f_dentry->d_inode->i_cdev,
1680 struct vpu_subdev_data, cdev);
1681 struct vpu_service_info *pservice = data->pservice;
1682 vpu_session *session = (vpu_session *)filp->private_data;
1684 if (NULL == session)
1688 case VPU_IOC_SET_CLIENT_TYPE : {
1689 session->type = (enum VPU_CLIENT_TYPE)arg;
1690 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1693 case VPU_IOC_GET_HW_FUSE_STATUS : {
1694 struct vpu_request req;
1695 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1696 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1697 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1700 if (VPU_ENC != session->type) {
1701 if (copy_to_user((void __user *)req.req,
1702 &pservice->dec_config,
1703 sizeof(struct vpu_dec_config))) {
1704 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1709 if (copy_to_user((void __user *)req.req,
1710 &pservice->enc_config,
1711 sizeof(struct vpu_enc_config ))) {
1712 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1721 case VPU_IOC_SET_REG : {
1722 struct vpu_request req;
1724 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1725 if (copy_from_user(&req, (void __user *)arg,
1726 sizeof(struct vpu_request))) {
1727 vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1730 reg = reg_init(data, session,
1731 (void __user *)req.req, req.size);
1735 mutex_lock(&pservice->lock);
1737 mutex_unlock(&pservice->lock);
1742 case VPU_IOC_GET_REG : {
1743 struct vpu_request req;
1745 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1746 if (copy_from_user(&req, (void __user *)arg,
1747 sizeof(struct vpu_request))) {
1748 vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1751 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1752 if (!list_empty(&session->done)) {
1754 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1758 if (unlikely(ret < 0)) {
1759 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1760 } else if (0 == ret) {
1761 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1766 int task_running = atomic_read(&session->task_running);
1767 mutex_lock(&pservice->lock);
1768 vpu_service_dump(pservice);
1770 atomic_set(&session->task_running, 0);
1771 atomic_sub(task_running, &pservice->total_running);
1772 printk("%d task is running but not return, reset hardware...", task_running);
1776 vpu_service_session_clear(data, session);
1777 mutex_unlock(&pservice->lock);
1781 mutex_lock(&pservice->lock);
1782 reg = list_entry(session->done.next, vpu_reg, session_link);
1783 return_reg(data, reg, (u32 __user *)req.req);
1784 mutex_unlock(&pservice->lock);
1787 case VPU_IOC_PROBE_IOMMU_STATUS: {
1788 int iommu_enable = 0;
1790 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1792 #if defined(CONFIG_VCODEC_MMU)
1793 iommu_enable = data->mmu_dev ? 1 : 0;
1796 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1797 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1803 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1811 #ifdef CONFIG_COMPAT
1812 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1815 struct vpu_subdev_data *data =
1816 container_of(filp->f_dentry->d_inode->i_cdev,
1817 struct vpu_subdev_data, cdev);
1818 struct vpu_service_info *pservice = data->pservice;
1819 vpu_session *session = (vpu_session *)filp->private_data;
1821 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1822 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1823 if (NULL == session)
1827 case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1828 session->type = (enum VPU_CLIENT_TYPE)arg;
1829 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1832 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1833 struct compat_vpu_request req;
1834 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1835 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1836 sizeof(struct compat_vpu_request))) {
1837 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1838 " copy_from_user failed\n");
1841 if (VPU_ENC != session->type) {
1842 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1843 &pservice->dec_config,
1844 sizeof(struct vpu_dec_config))) {
1845 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1846 "copy_to_user failed type %d\n",
1851 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1852 &pservice->enc_config,
1853 sizeof(struct vpu_enc_config ))) {
1854 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1855 " copy_to_user failed type %d\n",
1864 case COMPAT_VPU_IOC_SET_REG : {
1865 struct compat_vpu_request req;
1867 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1868 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1869 sizeof(struct compat_vpu_request))) {
1870 vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1873 reg = reg_init(data, session,
1874 compat_ptr((compat_uptr_t)req.req), req.size);
1878 mutex_lock(&pservice->lock);
1880 mutex_unlock(&pservice->lock);
1885 case COMPAT_VPU_IOC_GET_REG : {
1886 struct compat_vpu_request req;
1888 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1889 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1890 sizeof(struct compat_vpu_request))) {
1891 vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1894 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1895 if (!list_empty(&session->done)) {
1897 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1901 if (unlikely(ret < 0)) {
1902 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1903 } else if (0 == ret) {
1904 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1909 int task_running = atomic_read(&session->task_running);
1910 mutex_lock(&pservice->lock);
1911 vpu_service_dump(pservice);
1913 atomic_set(&session->task_running, 0);
1914 atomic_sub(task_running, &pservice->total_running);
1915 printk("%d task is running but not return, reset hardware...", task_running);
1919 vpu_service_session_clear(data, session);
1920 mutex_unlock(&pservice->lock);
1924 mutex_lock(&pservice->lock);
1925 reg = list_entry(session->done.next, vpu_reg, session_link);
1926 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1927 mutex_unlock(&pservice->lock);
1930 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1931 int iommu_enable = 0;
1933 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1934 #if defined(CONFIG_VCODEC_MMU)
1935 iommu_enable = data->mmu_dev ? 1 : 0;
1938 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1939 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1945 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1954 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1956 int ret = -EINVAL, i = 0;
1957 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1960 enc_id = (enc_id >> 16) & 0xFFFF;
1961 pr_info("checking hw id %x\n", enc_id);
1962 data->hw_info = NULL;
1963 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1964 if (enc_id == vpu_hw_set[i].hw_id) {
1965 data->hw_info = &vpu_hw_set[i];
1970 iounmap((void *)tmp);
1974 static int vpu_service_open(struct inode *inode, struct file *filp)
1976 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1977 struct vpu_service_info *pservice = data->pservice;
1978 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1982 if (NULL == session) {
1983 vpu_err("error: unable to allocate memory for vpu_session.");
1987 session->type = VPU_TYPE_BUTT;
1988 session->pid = current->pid;
1989 INIT_LIST_HEAD(&session->waiting);
1990 INIT_LIST_HEAD(&session->running);
1991 INIT_LIST_HEAD(&session->done);
1992 INIT_LIST_HEAD(&session->list_session);
1993 init_waitqueue_head(&session->wait);
1994 atomic_set(&session->task_running, 0);
1995 mutex_lock(&pservice->lock);
1996 list_add_tail(&session->list_session, &pservice->session);
1997 filp->private_data = (void *)session;
1998 mutex_unlock(&pservice->lock);
2000 pr_debug("dev opened\n");
2002 return nonseekable_open(inode, filp);
2005 static int vpu_service_release(struct inode *inode, struct file *filp)
2007 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
2008 struct vpu_service_info *pservice = data->pservice;
2010 vpu_session *session = (vpu_session *)filp->private_data;
2012 if (NULL == session)
2015 task_running = atomic_read(&session->task_running);
2017 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
2020 wake_up(&session->wait);
2022 mutex_lock(&pservice->lock);
2023 /* remove this filp from the asynchronusly notified filp's */
2024 list_del_init(&session->list_session);
2025 vpu_service_session_clear(data, session);
2027 filp->private_data = NULL;
2028 mutex_unlock(&pservice->lock);
2030 pr_debug("dev closed\n");
2035 static const struct file_operations vpu_service_fops = {
2036 .unlocked_ioctl = vpu_service_ioctl,
2037 .open = vpu_service_open,
2038 .release = vpu_service_release,
2039 #ifdef CONFIG_COMPAT
2040 .compat_ioctl = compat_vpu_service_ioctl,
2044 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2045 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2046 static irqreturn_t vepu_irq(int irq, void *dev_id);
2047 static irqreturn_t vepu_isr(int irq, void *dev_id);
2048 static void get_hw_info(struct vpu_subdev_data *data);
2050 #ifdef CONFIG_VCODEC_MMU
2051 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2053 struct device_node *dn = NULL;
2054 struct platform_device *pd = NULL;
2055 struct device *ret = NULL ;
2057 dn = of_find_compatible_node(NULL,NULL,compt);
2059 printk("can't find device node %s \r\n",compt);
2063 pd = of_find_device_by_node(dn);
2065 printk("can't find platform device in device node %s\n",compt);
2073 #ifdef CONFIG_IOMMU_API
2074 static inline void platform_set_sysmmu(struct device *iommu,
2077 dev->archdata.iommu = iommu;
2080 static inline void platform_set_sysmmu(struct device *iommu,
2086 int vcodec_sysmmu_fault_hdl(struct device *dev,
2087 enum rk_iommu_inttype itype,
2088 unsigned long pgtable_base,
2089 unsigned long fault_addr, unsigned int status)
2091 struct platform_device *pdev;
2092 struct vpu_subdev_data *data;
2093 struct vpu_service_info *pservice;
2097 pdev = container_of(dev, struct platform_device, dev);
2099 data = platform_get_drvdata(pdev);
2100 pservice = data->pservice;
2102 if (pservice->reg_codec) {
2103 struct vcodec_mem_region *mem, *n;
2105 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2106 list_for_each_entry_safe(mem, n,
2107 &pservice->reg_codec->mem_region_list,
2109 vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2110 mem->reg_idx, i, (u32)mem->iova, mem->len);
2114 pr_alert("vcodec, page fault occur, reset hw\n");
2115 pservice->reg_codec->reg[101] = 1;
2123 #if HEVC_TEST_ENABLE
2124 static int hevc_test_case0(vpu_service_info *pservice);
2126 #if defined(CONFIG_ION_ROCKCHIP)
2127 extern struct ion_client *rockchip_ion_client_create(const char * name);
2130 static int vcodec_subdev_probe(struct platform_device *pdev,
2131 struct vpu_service_info *pservice)
2134 struct resource *res = NULL;
2136 struct device *dev = &pdev->dev;
2137 char *name = (char*)dev_name(dev);
2138 struct device_node *np = pdev->dev.of_node;
2139 struct vpu_subdev_data *data =
2140 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2141 #if defined(CONFIG_VCODEC_MMU)
2143 char mmu_dev_dts_name[40];
2144 of_property_read_u32(np, "iommu_enabled", &iommu_en);
2146 pr_info("probe device %s\n", dev_name(dev));
2148 data->pservice = pservice;
2151 of_property_read_string(np, "name", (const char**)&name);
2152 of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2153 /*dev_set_name(dev, name);*/
2155 if (pservice->reg_base == 0) {
2156 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2157 data->regs = devm_ioremap_resource(dev, res);
2158 if (IS_ERR(data->regs)) {
2159 ret = PTR_ERR(data->regs);
2162 ioaddr = res->start;
2164 data->regs = pservice->reg_base;
2165 ioaddr = pservice->ioaddr;
2168 clear_bit(MMU_ACTIVATED, &data->state);
2169 vcodec_enter_mode(data);
2170 ret = vpu_service_check_hw(data, ioaddr);
2172 vpu_err("error: hw info check faild\n");
2176 data->dec_dev.iosize = data->hw_info->dec_io_size;
2177 data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2178 data->reg_size = data->dec_dev.iosize;
2180 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2181 data->enc_dev.iosize = data->hw_info->enc_io_size;
2182 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2183 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2186 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2187 if (data->irq_enc > 0) {
2188 ret = devm_request_threaded_irq(dev,
2189 data->irq_enc, vepu_irq, vepu_isr,
2190 IRQF_SHARED, dev_name(dev),
2194 "error: can't request vepu irq %d\n",
2199 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2200 if (data->irq_dec > 0) {
2201 ret = devm_request_threaded_irq(dev,
2202 data->irq_dec, vdpu_irq, vdpu_isr,
2203 IRQF_SHARED, dev_name(dev),
2207 "error: can't request vdpu irq %d\n",
2212 atomic_set(&data->dec_dev.irq_count_codec, 0);
2213 atomic_set(&data->dec_dev.irq_count_pp, 0);
2214 atomic_set(&data->enc_dev.irq_count_codec, 0);
2215 atomic_set(&data->enc_dev.irq_count_pp, 0);
2216 #if defined(CONFIG_VCODEC_MMU)
2218 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2219 sprintf(mmu_dev_dts_name,
2220 HEVC_IOMMU_COMPATIBLE_NAME);
2222 sprintf(mmu_dev_dts_name,
2223 VPU_IOMMU_COMPATIBLE_NAME);
2226 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2229 platform_set_sysmmu(data->mmu_dev, dev);
2231 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2235 pservice->auto_freq = true;
2237 vcodec_exit_mode(data);
2238 /* create device node */
2239 ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2241 dev_err(dev, "alloc dev_t failed\n");
2245 cdev_init(&data->cdev, &vpu_service_fops);
2247 data->cdev.owner = THIS_MODULE;
2248 data->cdev.ops = &vpu_service_fops;
2250 ret = cdev_add(&data->cdev, data->dev_t, 1);
2253 dev_err(dev, "add dev_t failed\n");
2257 data->cls = class_create(THIS_MODULE, name);
2259 if (IS_ERR(data->cls)) {
2260 ret = PTR_ERR(data->cls);
2261 dev_err(dev, "class_create err:%d\n", ret);
2265 data->child_dev = device_create(data->cls, dev,
2266 data->dev_t, NULL, name);
2268 platform_set_drvdata(pdev, data);
2270 INIT_LIST_HEAD(&data->lnk_service);
2271 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2273 #ifdef CONFIG_DEBUG_FS
2275 vcodec_debugfs_create_device_dir((char*)name, parent);
2276 if (data->debugfs_dir == NULL)
2277 vpu_err("create debugfs dir %s failed\n", name);
2279 data->debugfs_file_regs =
2280 debugfs_create_file("regs", 0664,
2281 data->debugfs_dir, data,
2282 &debug_vcodec_fops);
2286 if (data->irq_enc > 0)
2287 free_irq(data->irq_enc, (void *)data);
2288 if (data->irq_dec > 0)
2289 free_irq(data->irq_dec, (void *)data);
2291 if (data->child_dev) {
2292 device_destroy(data->cls, data->dev_t);
2293 cdev_del(&data->cdev);
2294 unregister_chrdev_region(data->dev_t, 1);
2298 class_destroy(data->cls);
2302 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2304 device_destroy(data->cls, data->dev_t);
2305 class_destroy(data->cls);
2306 cdev_del(&data->cdev);
2307 unregister_chrdev_region(data->dev_t, 1);
2309 free_irq(data->irq_enc, (void *)&data);
2310 free_irq(data->irq_dec, (void *)&data);
2312 #ifdef CONFIG_DEBUG_FS
2313 debugfs_remove_recursive(data->debugfs_dir);
2317 static void vcodec_read_property(struct device_node *np,
2318 struct vpu_service_info *pservice)
2320 pservice->mode_bit = 0;
2321 pservice->mode_ctrl = 0;
2322 pservice->subcnt = 0;
2324 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2326 if (pservice->subcnt > 1) {
2327 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2328 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2330 #ifdef CONFIG_MFD_SYSCON
2331 pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2333 pservice->grf_base = (u32*)RK_GRF_VIRT;
2335 if (IS_ERR(pservice->grf_base)) {
2337 pservice->grf_base = RK_GRF_VIRT;
2339 vpu_err("can't find vpu grf property\n");
2344 #ifdef CONFIG_RESET_CONTROLLER
2345 pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2346 pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2347 pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2349 if (IS_ERR_OR_NULL(pservice->rst_a)) {
2350 pr_warn("No reset resource define\n");
2351 pservice->rst_a = NULL;
2354 if (IS_ERR_OR_NULL(pservice->rst_h)) {
2355 pr_warn("No reset resource define\n");
2356 pservice->rst_h = NULL;
2359 if (IS_ERR_OR_NULL(pservice->rst_v)) {
2360 pr_warn("No reset resource define\n");
2361 pservice->rst_v = NULL;
2365 of_property_read_string(np, "name", (const char**)&pservice->name);
2368 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2370 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2371 pservice->curr_mode = -1;
2373 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2374 INIT_LIST_HEAD(&pservice->waiting);
2375 INIT_LIST_HEAD(&pservice->running);
2376 mutex_init(&pservice->lock);
2378 INIT_LIST_HEAD(&pservice->done);
2379 INIT_LIST_HEAD(&pservice->session);
2380 INIT_LIST_HEAD(&pservice->subdev_list);
2382 pservice->reg_pproc = NULL;
2383 atomic_set(&pservice->total_running, 0);
2384 atomic_set(&pservice->enabled, 0);
2385 atomic_set(&pservice->power_on_cnt, 0);
2386 atomic_set(&pservice->power_off_cnt, 0);
2387 atomic_set(&pservice->reset_request, 0);
2389 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2391 pservice->ion_client = rockchip_ion_client_create("vpu");
2392 if (IS_ERR(pservice->ion_client)) {
2393 vpu_err("failed to create ion client for vcodec ret %ld\n",
2394 PTR_ERR(pservice->ion_client));
2396 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2400 static int vcodec_probe(struct platform_device *pdev)
2404 struct resource *res = NULL;
2405 struct device *dev = &pdev->dev;
2406 struct device_node *np = pdev->dev.of_node;
2407 struct vpu_service_info *pservice =
2408 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2410 pr_info("probe device %s\n", dev_name(dev));
2412 pservice->dev = dev;
2414 vcodec_read_property(np, pservice);
2415 vcodec_init_drvdata(pservice);
2417 if (strncmp(pservice->name, "hevc_service", 12) == 0)
2418 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2419 else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2420 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2422 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2424 if (0 > vpu_get_clk(pservice))
2427 vpu_service_power_on(pservice);
2429 if (of_property_read_bool(np, "reg")) {
2430 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2432 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2433 if (IS_ERR(pservice->reg_base)) {
2434 vpu_err("ioremap registers base failed\n");
2435 ret = PTR_ERR(pservice->reg_base);
2438 pservice->ioaddr = res->start;
2440 pservice->reg_base = 0;
2443 if (of_property_read_bool(np, "subcnt")) {
2444 for (i = 0; i<pservice->subcnt; i++) {
2445 struct device_node *sub_np;
2446 struct platform_device *sub_pdev;
2447 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2448 sub_pdev = of_find_device_by_node(sub_np);
2450 vcodec_subdev_probe(sub_pdev, pservice);
2453 vcodec_subdev_probe(pdev, pservice);
2455 platform_set_drvdata(pdev, pservice);
2457 vpu_service_power_off(pservice);
2459 pr_info("init success\n");
2464 pr_info("init failed\n");
2465 vpu_service_power_off(pservice);
2466 vpu_put_clk(pservice);
2467 wake_lock_destroy(&pservice->wake_lock);
2470 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2475 static int vcodec_remove(struct platform_device *pdev)
2477 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2478 struct resource *res;
2479 struct vpu_subdev_data *data, *n;
2481 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2482 vcodec_subdev_remove(data);
2485 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2486 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2487 vpu_put_clk(pservice);
2488 wake_lock_destroy(&pservice->wake_lock);
2493 #if defined(CONFIG_OF)
2494 static const struct of_device_id vcodec_service_dt_ids[] = {
2495 {.compatible = "vpu_service",},
2496 {.compatible = "rockchip,hevc_service",},
2497 {.compatible = "rockchip,vpu_combo",},
2502 static struct platform_driver vcodec_driver = {
2503 .probe = vcodec_probe,
2504 .remove = vcodec_remove,
2507 .owner = THIS_MODULE,
2508 #if defined(CONFIG_OF)
2509 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2514 static void get_hw_info(struct vpu_subdev_data *data)
2516 struct vpu_service_info *pservice = data->pservice;
2517 struct vpu_dec_config *dec = &pservice->dec_config;
2518 struct vpu_enc_config *enc = &pservice->enc_config;
2519 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2520 u32 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2521 u32 asicID = data->dec_dev.hwregs[0];
2523 dec->h264_support = (configReg >> DWL_H264_E) & 0x3U;
2524 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2525 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2526 dec->jpegSupport = JPEG_PROGRESSIVE;
2527 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2528 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2529 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2530 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2531 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2532 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2534 dec->maxDecPicWidth = 4096;
2536 /* 2nd Config register */
2537 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2538 if (dec->refBufSupport) {
2539 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2540 dec->refBufSupport |= 2;
2541 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2542 dec->refBufSupport |= 4;
2544 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2545 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2546 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2547 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2549 /* JPEG xtensions */
2550 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2551 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2553 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2555 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2556 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2558 dec->rvSupport = RV_NOT_SUPPORTED;
2559 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2561 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2562 dec->refBufSupport |= 8; /* enable HW support for offset */
2564 if (!cpu_is_rk3036()) {
2565 configReg = data->enc_dev.hwregs[63];
2566 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2567 enc->h264Enabled = (configReg >> 27) & 1;
2568 enc->mpeg4Enabled = (configReg >> 26) & 1;
2569 enc->jpegEnabled = (configReg >> 25) & 1;
2570 enc->vsEnabled = (configReg >> 24) & 1;
2571 enc->rgbEnabled = (configReg >> 28) & 1;
2572 enc->reg_size = data->reg_size;
2573 enc->reserv[0] = enc->reserv[1] = 0;
2575 pservice->auto_freq = true;
2576 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2577 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2579 pservice->bug_dec_addr = cpu_is_rk30xx();
2581 if (cpu_is_rk3036() || cpu_is_rk312x())
2582 dec->maxDecPicWidth = 1920;
2584 dec->maxDecPicWidth = 4096;
2585 /* disable frequency switch in hevc.*/
2586 pservice->auto_freq = false;
2590 static bool check_irq_err(task_info *task, u32 irq_status)
2592 return (task->error_mask & irq_status) ? true : false;
2595 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2597 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2598 struct vpu_service_info *pservice = data->pservice;
2599 vpu_device *dev = &data->dec_dev;
2603 /*vcodec_enter_mode(data);*/
2605 dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2607 if (dec_status & DEC_INTERRUPT_BIT) {
2608 time_record(&tasks[TASK_VPU_DEC], 1);
2609 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2610 if ((dec_status & 0x40001) == 0x40001) {
2614 DEC_INTERRUPT_REGISTER);
2615 } while ((dec_status & 0x40001) == 0x40001);
2618 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2619 (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2621 atomic_add(1, &pservice->reset_request);
2624 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2625 atomic_add(1, &dev->irq_count_codec);
2626 time_diff(&tasks[TASK_VPU_DEC]);
2629 if (data->hw_info->hw_id != HEVC_ID) {
2630 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2631 if (pp_status & PP_INTERRUPT_BIT) {
2632 time_record(&tasks[TASK_VPU_PP], 1);
2633 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2635 if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2636 atomic_add(1, &pservice->reset_request);
2639 writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2640 atomic_add(1, &dev->irq_count_pp);
2641 time_diff(&tasks[TASK_VPU_PP]);
2645 pservice->irq_status = raw_status;
2647 /*vcodec_exit_mode(pservice);*/
2649 if (atomic_read(&dev->irq_count_pp) ||
2650 atomic_read(&dev->irq_count_codec))
2651 return IRQ_WAKE_THREAD;
2656 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2658 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2659 struct vpu_service_info *pservice = data->pservice;
2660 vpu_device *dev = &data->dec_dev;
2662 mutex_lock(&pservice->lock);
2663 if (atomic_read(&dev->irq_count_codec)) {
2664 atomic_sub(1, &dev->irq_count_codec);
2665 if (NULL == pservice->reg_codec) {
2666 vpu_err("error: dec isr with no task waiting\n");
2668 reg_from_run_to_done(data, pservice->reg_codec);
2669 /* avoid vpu timeout and can't recover problem */
2670 VDPU_SOFT_RESET(data->regs);
2674 if (atomic_read(&dev->irq_count_pp)) {
2675 atomic_sub(1, &dev->irq_count_pp);
2676 if (NULL == pservice->reg_pproc) {
2677 vpu_err("error: pp isr with no task waiting\n");
2679 reg_from_run_to_done(data, pservice->reg_pproc);
2683 mutex_unlock(&pservice->lock);
2687 static irqreturn_t vepu_irq(int irq, void *dev_id)
2689 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2690 struct vpu_service_info *pservice = data->pservice;
2691 vpu_device *dev = &data->enc_dev;
2694 /*vcodec_enter_mode(data);*/
2695 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2697 vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2699 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2700 time_record(&tasks[TASK_VPU_ENC], 1);
2702 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2703 atomic_add(1, &pservice->reset_request);
2706 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2707 atomic_add(1, &dev->irq_count_codec);
2708 time_diff(&tasks[TASK_VPU_ENC]);
2711 pservice->irq_status = irq_status;
2713 /*vcodec_exit_mode(pservice);*/
2715 if (atomic_read(&dev->irq_count_codec))
2716 return IRQ_WAKE_THREAD;
2721 static irqreturn_t vepu_isr(int irq, void *dev_id)
2723 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2724 struct vpu_service_info *pservice = data->pservice;
2725 vpu_device *dev = &data->enc_dev;
2727 mutex_lock(&pservice->lock);
2728 if (atomic_read(&dev->irq_count_codec)) {
2729 atomic_sub(1, &dev->irq_count_codec);
2730 if (NULL == pservice->reg_codec) {
2731 vpu_err("error: enc isr with no task waiting\n");
2733 reg_from_run_to_done(data, pservice->reg_codec);
2737 mutex_unlock(&pservice->lock);
2741 static int __init vcodec_service_init(void)
2745 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2746 vpu_err("Platform device register failed (%d).\n", ret);
2750 #ifdef CONFIG_DEBUG_FS
2751 vcodec_debugfs_init();
2757 static void __exit vcodec_service_exit(void)
2759 #ifdef CONFIG_DEBUG_FS
2760 vcodec_debugfs_exit();
2763 platform_driver_unregister(&vcodec_driver);
2766 module_init(vcodec_service_init);
2767 module_exit(vcodec_service_exit);
2769 #ifdef CONFIG_DEBUG_FS
2770 #include <linux/seq_file.h>
2772 static int vcodec_debugfs_init()
2774 parent = debugfs_create_dir("vcodec", NULL);
2781 static void vcodec_debugfs_exit()
2783 debugfs_remove(parent);
2786 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2788 return debugfs_create_dir(dirname, parent);
2791 static int debug_vcodec_show(struct seq_file *s, void *unused)
2793 struct vpu_subdev_data *data = s->private;
2794 struct vpu_service_info *pservice = data->pservice;
2796 vpu_reg *reg, *reg_tmp;
2797 vpu_session *session, *session_tmp;
2799 mutex_lock(&pservice->lock);
2800 vpu_service_power_on(pservice);
2801 if (data->hw_info->hw_id != HEVC_ID) {
2802 seq_printf(s, "\nENC Registers:\n");
2803 n = data->enc_dev.iosize >> 2;
2804 for (i = 0; i < n; i++)
2805 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2807 seq_printf(s, "\nDEC Registers:\n");
2808 n = data->dec_dev.iosize >> 2;
2809 for (i = 0; i < n; i++)
2810 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2812 seq_printf(s, "\nvpu service status:\n");
2813 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2814 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2815 /*seq_printf(s, "waiting reg set %d\n");*/
2816 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2817 seq_printf(s, "waiting register set\n");
2819 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2820 seq_printf(s, "running register set\n");
2822 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2823 seq_printf(s, "done register set\n");
2827 seq_printf(s, "\npower counter: on %d off %d\n",
2828 atomic_read(&pservice->power_on_cnt),
2829 atomic_read(&pservice->power_off_cnt));
2830 mutex_unlock(&pservice->lock);
2831 vpu_service_power_off(pservice);
2836 static int debug_vcodec_open(struct inode *inode, struct file *file)
2838 return single_open(file, debug_vcodec_show, inode->i_private);
2843 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2844 #include "hevc_test_inc/pps_00.h"
2845 #include "hevc_test_inc/register_00.h"
2846 #include "hevc_test_inc/rps_00.h"
2847 #include "hevc_test_inc/scaling_list_00.h"
2848 #include "hevc_test_inc/stream_00.h"
2850 #include "hevc_test_inc/pps_01.h"
2851 #include "hevc_test_inc/register_01.h"
2852 #include "hevc_test_inc/rps_01.h"
2853 #include "hevc_test_inc/scaling_list_01.h"
2854 #include "hevc_test_inc/stream_01.h"
2856 #include "hevc_test_inc/cabac.h"
2858 extern struct ion_client *rockchip_ion_client_create(const char * name);
2860 static struct ion_client *ion_client = NULL;
2861 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2863 int size = (len+15) & (~15);
2864 struct ion_handle *handle;
2867 if (ion_client == NULL)
2868 ion_client = rockchip_ion_client_create("vcodec");
2870 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2872 ptr = ion_map_kernel(ion_client, handle);
2874 ion_phys(ion_client, handle, phy, &size);
2876 memcpy(ptr, tbl, len);
2881 u8* get_align_ptr_no_copy(int len, u32 *phy)
2883 int size = (len+15) & (~15);
2884 struct ion_handle *handle;
2887 if (ion_client == NULL)
2888 ion_client = rockchip_ion_client_create("vcodec");
2890 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2892 ptr = ion_map_kernel(ion_client, handle);
2894 ion_phys(ion_client, handle, phy, &size);
2900 static int hevc_test_case0(vpu_service_info *pservice)
2902 vpu_session session;
2904 unsigned long size = 272;
2907 u8 *pps_tbl[TEST_CNT];
2908 u8 *register_tbl[TEST_CNT];
2909 u8 *rps_tbl[TEST_CNT];
2910 u8 *scaling_list_tbl[TEST_CNT];
2911 u8 *stream_tbl[TEST_CNT];
2927 volatile u8 *stream_buf;
2928 volatile u8 *pps_buf;
2929 volatile u8 *rps_buf;
2930 volatile u8 *scl_buf;
2931 volatile u8 *yuv_buf;
2932 volatile u8 *cabac_buf;
2933 volatile u8 *ref_buf;
2939 pps_tbl[0] = pps_00;
2940 pps_tbl[1] = pps_01;
2942 register_tbl[0] = register_00;
2943 register_tbl[1] = register_01;
2945 rps_tbl[0] = rps_00;
2946 rps_tbl[1] = rps_01;
2948 scaling_list_tbl[0] = scaling_list_00;
2949 scaling_list_tbl[1] = scaling_list_01;
2951 stream_tbl[0] = stream_00;
2952 stream_tbl[1] = stream_01;
2954 stream_size[0] = sizeof(stream_00);
2955 stream_size[1] = sizeof(stream_01);
2957 pps_size[0] = sizeof(pps_00);
2958 pps_size[1] = sizeof(pps_01);
2960 rps_size[0] = sizeof(rps_00);
2961 rps_size[1] = sizeof(rps_01);
2963 scl_size[0] = sizeof(scaling_list_00);
2964 scl_size[1] = sizeof(scaling_list_01);
2966 cabac_size[0] = sizeof(Cabac_table);
2967 cabac_size[1] = sizeof(Cabac_table);
2969 /* create session */
2970 session.pid = current->pid;
2971 session.type = VPU_DEC;
2972 INIT_LIST_HEAD(&session.waiting);
2973 INIT_LIST_HEAD(&session.running);
2974 INIT_LIST_HEAD(&session.done);
2975 INIT_LIST_HEAD(&session.list_session);
2976 init_waitqueue_head(&session.wait);
2977 atomic_set(&session.task_running, 0);
2978 list_add_tail(&session.list_session, &pservice->session);
2980 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2981 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2983 while (testidx < TEST_CNT) {
2984 /* create registers */
2985 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2987 vpu_err("error: kmalloc fail in reg_init\n");
2991 if (size > pservice->reg_size) {
2992 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2993 size = pservice->reg_size;
2995 reg->session = &session;
2996 reg->type = session.type;
2998 reg->freq = VPU_FREQ_DEFAULT;
2999 reg->reg = (unsigned long *)®[1];
3000 INIT_LIST_HEAD(®->session_link);
3001 INIT_LIST_HEAD(®->status_link);
3003 /* TODO: stuff registers */
3004 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
3006 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
3007 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
3008 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
3009 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
3010 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
3014 /* TODO: replace reigster address */
3015 for (i=0; i<64; i++) {
3019 scaling_offset = (u32)pps[i*80+74];
3020 scaling_offset += (u32)pps[i*80+75] << 8;
3021 scaling_offset += (u32)pps[i*80+76] << 16;
3022 scaling_offset += (u32)pps[i*80+77] << 24;
3024 tmp = phy_scl + scaling_offset;
3026 pps[i*80+74] = tmp & 0xff;
3027 pps[i*80+75] = (tmp >> 8) & 0xff;
3028 pps[i*80+76] = (tmp >> 16) & 0xff;
3029 pps[i*80+77] = (tmp >> 24) & 0xff;
3032 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
3033 __func__, __LINE__, phy_str, phy_pps, phy_rps);
3036 reg->reg[4] = phy_str;
3037 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
3038 reg->reg[6] = phy_cabac;
3039 reg->reg[7] = testidx?phy_ref:phy_yuv;
3040 reg->reg[42] = phy_pps;
3041 reg->reg[43] = phy_rps;
3042 for (i = 10; i <= 24; i++)
3043 reg->reg[i] = phy_yuv;
3045 mutex_lock(pservice->lock);
3046 list_add_tail(®->status_link, &pservice->waiting);
3047 list_add_tail(®->session_link, &session.waiting);
3048 mutex_unlock(pservice->lock);
3050 /* stuff hardware */
3053 /* wait for result */
3054 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3055 if (!list_empty(&session.done)) {
3057 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3060 if (unlikely(ret < 0)) {
3061 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3062 } else if (0 == ret) {
3063 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3068 int task_running = atomic_read(&session.task_running);
3070 mutex_lock(pservice->lock);
3071 vpu_service_dump(pservice);
3073 atomic_set(&session.task_running, 0);
3074 atomic_sub(task_running, &pservice->total_running);
3075 printk("%d task is running but not return, reset hardware...", task_running);
3079 vpu_service_session_clear(pservice, &session);
3080 mutex_unlock(pservice->lock);
3082 printk("\nDEC Registers:\n");
3083 n = data->dec_dev.iosize >> 2;
3085 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3087 vpu_err("test index %d failed\n", testidx);
3090 vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3092 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3094 for (i=0; i<68; i++) {
3096 printk("%02d: ", i);
3097 printk("%08x ", reg->reg[i]);
3105 reg_deinit(data, reg);