2 * Copyright (C) 2014 ROCKCHIP, Inc.
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/miscdevice.h>
28 #include <linux/poll.h>
29 #include <linux/platform_device.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/wakelock.h>
33 #include <linux/cdev.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_irq.h>
37 #include <linux/rockchip/cpu.h>
38 #include <linux/rockchip/cru.h>
40 #include <linux/regmap.h>
42 #include <linux/mfd/syscon.h>
44 #include <asm/cacheflush.h>
45 #include <linux/uaccess.h>
46 #include <linux/rockchip/grf.h>
48 #if defined(CONFIG_ION_ROCKCHIP)
49 #include <linux/rockchip_ion.h>
52 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
53 #define CONFIG_VCODEC_MMU
56 #ifdef CONFIG_VCODEC_MMU
57 #include <linux/rockchip-iovmm.h>
58 #include <linux/dma-buf.h>
61 #ifdef CONFIG_DEBUG_FS
62 #include <linux/debugfs.h>
65 #if defined(CONFIG_ARCH_RK319X)
69 #include "vcodec_service.h"
72 module_param(debug, int, S_IRUGO | S_IWUSR);
73 MODULE_PARM_DESC(debug,
74 "Debug level - higher value produces more verbose messages");
76 #define HEVC_TEST_ENABLE 0
77 #define VCODEC_CLOCK_ENABLE 1
80 VPU_DEC_ID_9190 = 0x6731,
94 VPU_DEC_TYPE_9190 = 0,
95 VPU_ENC_TYPE_8270 = 0x100,
99 typedef enum VPU_FREQ {
112 unsigned long hw_addr;
113 unsigned long enc_offset;
114 unsigned long enc_reg_num;
115 unsigned long enc_io_size;
116 unsigned long dec_offset;
117 unsigned long dec_reg_num;
118 unsigned long dec_io_size;
121 struct extra_info_elem {
126 #define EXTRA_INFO_MAGIC 0x4C4A46
128 struct extra_info_for_iommu {
131 struct extra_info_elem elem[20];
134 #define VPU_SERVICE_SHOW_TIME 0
136 #if VPU_SERVICE_SHOW_TIME
137 static struct timeval enc_start, enc_end;
138 static struct timeval dec_start, dec_end;
139 static struct timeval pp_start, pp_end;
142 #define MHZ (1000*1000)
144 #define REG_NUM_9190_DEC (60)
145 #define REG_NUM_9190_PP (41)
146 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
148 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
150 #define REG_NUM_ENC_8270 (96)
151 #define REG_SIZE_ENC_8270 (0x200)
152 #define REG_NUM_ENC_4831 (164)
153 #define REG_SIZE_ENC_4831 (0x400)
155 #define REG_NUM_HEVC_DEC (68)
157 #define SIZE_REG(reg) ((reg)*4)
159 static VPU_HW_INFO_E vpu_hw_set[] = {
161 .hw_id = VPU_ID_8270,
164 .enc_reg_num = REG_NUM_ENC_8270,
165 .enc_io_size = REG_NUM_ENC_8270 * 4,
166 .dec_offset = REG_SIZE_ENC_8270,
167 .dec_reg_num = REG_NUM_9190_DEC_PP,
168 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
171 .hw_id = VPU_ID_4831,
174 .enc_reg_num = REG_NUM_ENC_4831,
175 .enc_io_size = REG_NUM_ENC_4831 * 4,
176 .dec_offset = REG_SIZE_ENC_4831,
177 .dec_reg_num = REG_NUM_9190_DEC_PP,
178 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
184 .dec_reg_num = REG_NUM_HEVC_DEC,
185 .dec_io_size = REG_NUM_HEVC_DEC * 4,
188 .hw_id = VPU_DEC_ID_9190,
194 .dec_reg_num = REG_NUM_9190_DEC_PP,
195 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
200 #define DEC_INTERRUPT_REGISTER 1
201 #define PP_INTERRUPT_REGISTER 60
202 #define ENC_INTERRUPT_REGISTER 1
204 #define DEC_INTERRUPT_BIT 0x100
205 #define DEC_BUFFER_EMPTY_BIT 0x4000
206 #define PP_INTERRUPT_BIT 0x100
207 #define ENC_INTERRUPT_BIT 0x1
209 #define HEVC_DEC_INT_RAW_BIT 0x200
210 #define HEVC_DEC_STR_ERROR_BIT 0x4000
211 #define HEVC_DEC_BUS_ERROR_BIT 0x2000
212 #define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000
214 #define VPU_REG_EN_ENC 14
215 #define VPU_REG_ENC_GATE 2
216 #define VPU_REG_ENC_GATE_BIT (1<<4)
218 #define VPU_REG_EN_DEC 1
219 #define VPU_REG_DEC_GATE 2
220 #define VPU_REG_DEC_GATE_BIT (1<<10)
221 #define VPU_REG_EN_PP 0
222 #define VPU_REG_PP_GATE 1
223 #define VPU_REG_PP_GATE_BIT (1<<8)
224 #define VPU_REG_EN_DEC_PP 1
225 #define VPU_REG_DEC_PP_GATE 61
226 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
230 #define vpu_debug(level, fmt, args...) \
232 if (debug >= level) \
233 pr_info("%s:%d: " fmt, \
234 __func__, __LINE__, ##args); \
237 #define vpu_debug(level, fmt, args...)
240 #define vpu_debug_enter() vpu_debug(4, "enter\n")
241 #define vpu_debug_leave() vpu_debug(4, "leave\n")
243 #define vpu_err(fmt, args...) \
244 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
246 #if defined(CONFIG_VCODEC_MMU)
247 static u8 addr_tbl_vpu_h264dec[] = {
248 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
249 25, 26, 27, 28, 29, 40, 41
252 static u8 addr_tbl_vpu_vp8dec[] = {
253 10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
256 static u8 addr_tbl_vpu_vp6dec[] = {
257 12, 13, 14, 18, 27, 40
260 static u8 addr_tbl_vpu_vc1dec[] = {
261 12, 13, 14, 15, 16, 17, 27, 41
264 static u8 addr_tbl_vpu_jpegdec[] = {
268 static u8 addr_tbl_vpu_defaultdec[] = {
269 12, 13, 14, 15, 16, 17, 40, 41
272 static u8 addr_tbl_vpu_enc[] = {
273 5, 6, 7, 8, 9, 10, 11, 12, 13, 51
276 static u8 addr_tbl_hevc_dec[] = {
277 4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
278 21, 22, 23, 24, 42, 43
303 * struct for process session which connect to vpu
305 * @author ChenHengming (2011-5-3)
307 typedef struct vpu_session {
308 enum VPU_CLIENT_TYPE type;
309 /* a linked list of data so we can access them for debugging */
310 struct list_head list_session;
311 /* a linked list of register data waiting for process */
312 struct list_head waiting;
313 /* a linked list of register data in processing */
314 struct list_head running;
315 /* a linked list of register data processed */
316 struct list_head done;
317 wait_queue_head_t wait;
319 atomic_t task_running;
323 * struct for process register set
325 * @author ChenHengming (2011-5-4)
327 typedef struct vpu_reg {
328 enum VPU_CLIENT_TYPE type;
330 vpu_session *session;
331 struct list_head session_link; /* link to vpu service session */
332 struct list_head status_link; /* link to register set list */
334 #if defined(CONFIG_VCODEC_MMU)
335 struct list_head mem_region_list;
340 typedef struct vpu_device {
341 atomic_t irq_count_codec;
342 atomic_t irq_count_pp;
343 unsigned long iobaseaddr;
345 volatile u32 *hwregs;
348 enum vcodec_device_id {
349 VCODEC_DEVICE_ID_VPU,
350 VCODEC_DEVICE_ID_HEVC,
351 VCODEC_DEVICE_ID_COMBO
354 enum VCODEC_RUNNING_MODE {
355 VCODEC_RUNNING_MODE_NONE = -1,
356 VCODEC_RUNNING_MODE_VPU,
357 VCODEC_RUNNING_MODE_HEVC,
360 struct vcodec_mem_region {
361 struct list_head srv_lnk;
362 struct list_head reg_lnk;
363 struct list_head session_lnk;
364 unsigned long iova; /* virtual address for iommu */
367 struct ion_handle *hdl;
371 MMU_ACTIVATED = BIT(0)
374 struct vpu_subdev_data {
378 struct device *child_dev;
382 struct vpu_service_info *pservice;
385 enum VCODEC_RUNNING_MODE mode;
386 struct list_head lnk_service;
392 VPU_HW_INFO_E *hw_info;
397 #ifdef CONFIG_DEBUG_FS
398 struct dentry *debugfs_dir;
399 struct dentry *debugfs_file_regs;
402 #if defined(CONFIG_VCODEC_MMU)
403 struct device *mmu_dev;
407 typedef struct vpu_service_info {
408 struct wake_lock wake_lock;
409 struct delayed_work power_off_work;
411 struct list_head waiting; /* link to link_reg in struct vpu_reg */
412 struct list_head running; /* link to link_reg in struct vpu_reg */
413 struct list_head done; /* link to link_reg in struct vpu_reg */
414 struct list_head session; /* link to list_session in struct vpu_session */
415 atomic_t total_running;
420 struct vpu_dec_config dec_config;
421 struct vpu_enc_config enc_config;
425 atomic_t freq_status;
427 struct clk *aclk_vcodec;
428 struct clk *hclk_vcodec;
429 struct clk *clk_core;
430 struct clk *clk_cabac;
431 struct clk *pd_video;
436 #if defined(CONFIG_VCODEC_MMU)
437 struct ion_client *ion_client;
438 struct list_head mem_region_list;
441 enum vcodec_device_id dev_id;
443 enum VCODEC_RUNNING_MODE curr_mode;
446 struct delayed_work simulate_work;
453 struct regmap *grf_base;
460 struct list_head subdev_list;
463 struct vcodec_combo {
464 struct vpu_service_info *vpu_srv;
465 struct vpu_service_info *hevc_srv;
466 struct list_head waiting;
467 struct list_head running;
468 struct mutex run_lock;
470 enum vcodec_device_id current_hw_mode;
473 typedef struct vpu_request {
478 /* debugfs root directory for all device (vpu, hevc).*/
479 static struct dentry *parent;
481 #ifdef CONFIG_DEBUG_FS
482 static int vcodec_debugfs_init(void);
483 static void vcodec_debugfs_exit(void);
484 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
485 static int debug_vcodec_open(struct inode *inode, struct file *file);
487 static const struct file_operations debug_vcodec_fops = {
488 .open = debug_vcodec_open,
491 .release = single_release,
495 #define VDPU_SOFT_RESET_REG 101
496 #define VDPU_CLEAN_CACHE_REG 516
497 #define VEPU_CLEAN_CACHE_REG 772
498 #define HEVC_CLEAN_CACHE_REG 260
500 #define VPU_REG_ENABLE(base, reg) do { \
504 #define VDPU_SOFT_RESET(base) VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
505 #define VDPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
506 #define VEPU_CLEAN_CACHE(base) VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
507 #define HEVC_CLEAN_CACHE(base) VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
509 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
510 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
512 static void vcodec_enter_mode(struct vpu_subdev_data *data)
516 struct vpu_service_info *pservice = data->pservice;
517 struct vpu_subdev_data *subdata, *n;
518 if (pservice->subcnt < 2 || pservice->curr_mode == data->mode) {
519 pservice->prev_mode = pservice->curr_mode;
522 vpu_debug(3, "vcodec enter mode %d\n", data->mode);
523 #if defined(CONFIG_VCODEC_MMU)
524 list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
525 if (data != subdata && subdata->mmu_dev &&
526 test_bit(MMU_ACTIVATED, &subdata->state)) {
527 clear_bit(MMU_ACTIVATED, &subdata->state);
528 rockchip_iovmm_deactivate(subdata->dev);
532 bits = 1 << pservice->mode_bit;
534 regmap_read(pservice->grf_base, pservice->mode_ctrl, &raw);
536 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
537 regmap_write(pservice->grf_base, pservice->mode_ctrl,
538 raw | bits | (bits << 16));
540 regmap_write(pservice->grf_base, pservice->mode_ctrl,
541 (raw & (~bits)) | (bits << 16));
543 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
544 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
545 writel_relaxed(raw | bits | (bits << 16),
546 pservice->grf_base + pservice->mode_ctrl / 4);
548 writel_relaxed((raw & (~bits)) | (bits << 16),
549 pservice->grf_base + pservice->mode_ctrl / 4);
551 #if defined(CONFIG_VCODEC_MMU)
552 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
553 set_bit(MMU_ACTIVATED, &data->state);
554 BUG_ON(!pservice->enabled);
555 if (pservice->enabled)
556 rockchip_iovmm_activate(data->dev);
559 pservice->prev_mode = pservice->curr_mode;
560 pservice->curr_mode = data->mode;
563 static void vcodec_exit_mode(struct vpu_service_info *pservice)
568 static int vpu_get_clk(struct vpu_service_info *pservice)
570 #if VCODEC_CLOCK_ENABLE
571 switch (pservice->dev_id) {
572 case VCODEC_DEVICE_ID_HEVC:
573 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
574 if (IS_ERR(pservice->clk_cabac)) {
575 dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
579 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
580 if (IS_ERR(pservice->pd_video)) {
581 dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
584 case VCODEC_DEVICE_ID_COMBO:
585 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
586 if (IS_ERR(pservice->clk_core)) {
587 dev_err(pservice->dev, "failed on clk_get clk_core\n");
590 case VCODEC_DEVICE_ID_VPU:
591 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
592 if (IS_ERR(pservice->aclk_vcodec)) {
593 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
597 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
598 if (IS_ERR(pservice->hclk_vcodec)) {
599 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
602 if (pservice->pd_video == NULL) {
603 pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
604 if (IS_ERR(pservice->pd_video))
605 pservice->pd_video = NULL;
618 static void vpu_put_clk(struct vpu_service_info *pservice)
620 #if VCODEC_CLOCK_ENABLE
621 if (pservice->pd_video)
622 devm_clk_put(pservice->dev, pservice->pd_video);
623 if (pservice->aclk_vcodec)
624 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
625 if (pservice->hclk_vcodec)
626 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
627 if (pservice->clk_core)
628 devm_clk_put(pservice->dev, pservice->clk_core);
629 if (pservice->clk_cabac)
630 devm_clk_put(pservice->dev, pservice->clk_cabac);
634 static void vpu_reset(struct vpu_subdev_data *data)
636 struct vpu_service_info *pservice = data->pservice;
637 #if defined(CONFIG_ARCH_RK29)
638 clk_disable(aclk_ddr_vepu);
639 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
640 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
641 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
642 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
644 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
645 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
646 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
647 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
648 clk_enable(aclk_ddr_vepu);
649 #elif defined(CONFIG_ARCH_RK30)
650 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
651 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
652 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
653 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
654 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
656 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
657 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
658 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
659 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
660 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
662 pservice->reg_codec = NULL;
663 pservice->reg_pproc = NULL;
664 pservice->reg_resev = NULL;
666 #if defined(CONFIG_VCODEC_MMU)
667 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
668 set_bit(MMU_ACTIVATED, &data->state);
669 BUG_ON(!pservice->enabled);
670 if (pservice->enabled)
671 rockchip_iovmm_activate(data->dev);
676 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
677 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
680 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
681 reg_deinit(data, reg);
683 list_for_each_entry_safe(reg, n, &session->running, session_link) {
684 reg_deinit(data, reg);
686 list_for_each_entry_safe(reg, n, &session->done, session_link) {
687 reg_deinit(data, reg);
691 static void vpu_service_dump(struct vpu_service_info *pservice)
695 static void vpu_service_power_off(struct vpu_service_info *pservice)
698 struct vpu_subdev_data *data = NULL, *n;
699 if (!pservice->enabled)
702 pservice->enabled = false;
703 total_running = atomic_read(&pservice->total_running);
705 pr_alert("alert: power off when %d task running!!\n", total_running);
707 pr_alert("alert: delay 50 ms for running task\n");
708 vpu_service_dump(pservice);
711 pr_info("%s: power off...", dev_name(pservice->dev));
713 #if defined(CONFIG_VCODEC_MMU)
714 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
715 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
716 clear_bit(MMU_ACTIVATED, &data->state);
717 rockchip_iovmm_deactivate(data->dev);
720 pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
723 #if VCODEC_CLOCK_ENABLE
724 if (pservice->pd_video)
725 clk_disable_unprepare(pservice->pd_video);
726 if (pservice->hclk_vcodec)
727 clk_disable_unprepare(pservice->hclk_vcodec);
728 if (pservice->aclk_vcodec)
729 clk_disable_unprepare(pservice->aclk_vcodec);
730 if (pservice->clk_core)
731 clk_disable_unprepare(pservice->clk_core);
732 if (pservice->clk_cabac)
733 clk_disable_unprepare(pservice->clk_cabac);
736 wake_unlock(&pservice->wake_lock);
740 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
742 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
745 static void vpu_power_off_work(struct work_struct *work_s)
747 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
748 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
750 if (mutex_trylock(&pservice->lock)) {
751 vpu_service_power_off(pservice);
752 mutex_unlock(&pservice->lock);
754 /* Come back later if the device is busy... */
755 vpu_queue_power_off_work(pservice);
759 static void vpu_service_power_on(struct vpu_service_info *pservice)
762 ktime_t now = ktime_get();
763 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
764 cancel_delayed_work_sync(&pservice->power_off_work);
765 vpu_queue_power_off_work(pservice);
768 if (pservice->enabled)
771 pservice->enabled = true;
772 pr_info("%s: power on\n", dev_name(pservice->dev));
774 #define BIT_VCODEC_CLK_SEL (1<<10)
776 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
777 BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
778 RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
780 #if VCODEC_CLOCK_ENABLE
781 if (pservice->aclk_vcodec)
782 clk_prepare_enable(pservice->aclk_vcodec);
783 if (pservice->hclk_vcodec)
784 clk_prepare_enable(pservice->hclk_vcodec);
785 if (pservice->clk_core)
786 clk_prepare_enable(pservice->clk_core);
787 if (pservice->clk_cabac)
788 clk_prepare_enable(pservice->clk_cabac);
789 if (pservice->pd_video)
790 clk_prepare_enable(pservice->pd_video);
794 wake_lock(&pservice->wake_lock);
797 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
799 unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
800 return ((type == 8) || (type == 4));
803 static inline bool reg_check_interlace(vpu_reg *reg)
805 unsigned long type = (reg->reg[3] & (1 << 23));
809 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
811 enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
815 static inline int reg_probe_width(vpu_reg *reg)
817 int width_in_mb = reg->reg[4] >> 23;
818 return width_in_mb * 16;
821 #if defined(CONFIG_VCODEC_MMU)
822 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
824 struct vpu_service_info *pservice = data->pservice;
825 struct ion_handle *hdl;
827 struct vcodec_mem_region *mem_region;
829 hdl = ion_import_dma_buf(pservice->ion_client, fd);
831 vpu_err("import dma-buf from fd %d failed\n", fd);
834 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
836 if (mem_region == NULL) {
837 vpu_err("allocate memory for iommu memory region failed\n");
838 ion_free(pservice->ion_client, hdl);
842 mem_region->hdl = hdl;
843 vcodec_enter_mode(data);
844 ret = ion_map_iommu(data->dev, pservice->ion_client,
845 mem_region->hdl, &mem_region->iova, &mem_region->len);
846 vcodec_exit_mode(pservice);
849 vpu_err("ion map iommu failed\n");
851 ion_free(pservice->ion_client, hdl);
854 INIT_LIST_HEAD(&mem_region->reg_lnk);
855 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
856 return mem_region->iova;
859 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
860 int size, vpu_reg *reg,
861 struct extra_info_for_iommu *ext_inf)
863 struct vpu_service_info *pservice = data->pservice;
868 if (tbl == NULL || size <= 0) {
869 dev_err(pservice->dev, "input arguments invalidate\n");
873 vpu_service_power_on(pservice);
875 for (i = 0; i < size; i++) {
876 usr_fd = reg->reg[tbl[i]] & 0x3FF;
878 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
879 (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
880 /* special for vpu dec num 41 regitster */
881 offset = reg->reg[tbl[i]] >> 10 << 4;
883 offset = reg->reg[tbl[i]] >> 10;
886 struct ion_handle *hdl;
888 struct vcodec_mem_region *mem_region;
890 hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
892 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
896 if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
899 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
900 for (i=0; i<64; i++) {
904 scaling_offset = (u32)pps[i*80+74];
905 scaling_offset += (u32)pps[i*80+75] << 8;
906 scaling_offset += (u32)pps[i*80+76] << 16;
907 scaling_offset += (u32)pps[i*80+77] << 24;
908 scaling_fd = scaling_offset&0x3ff;
909 scaling_offset = scaling_offset >> 10;
911 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
912 tmp += scaling_offset;
913 pps[i*80+74] = tmp & 0xff;
914 pps[i*80+75] = (tmp >> 8) & 0xff;
915 pps[i*80+76] = (tmp >> 16) & 0xff;
916 pps[i*80+77] = (tmp >> 24) & 0xff;
921 mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
923 if (mem_region == NULL) {
924 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
925 ion_free(pservice->ion_client, hdl);
929 mem_region->hdl = hdl;
930 mem_region->reg_idx = tbl[i];
931 vcodec_enter_mode(data);
932 ret = ion_map_iommu(data->dev,
933 pservice->ion_client,
937 vcodec_exit_mode(pservice);
940 dev_err(pservice->dev, "ion map iommu failed\n");
942 ion_free(pservice->ion_client, hdl);
945 reg->reg[tbl[i]] = mem_region->iova + offset;
946 INIT_LIST_HEAD(&mem_region->reg_lnk);
947 list_add_tail(&mem_region->reg_lnk, ®->mem_region_list);
951 if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
952 for (i=0; i<ext_inf->cnt; i++) {
953 vpu_debug(3, "reg[%d] + offset %d\n",
954 ext_inf->elem[i].index,
955 ext_inf->elem[i].offset);
956 reg->reg[ext_inf->elem[i].index] +=
957 ext_inf->elem[i].offset;
964 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
966 struct extra_info_for_iommu *ext_inf)
972 hw_id = data->hw_info->hw_id;
974 if (hw_id == HEVC_ID) {
975 tbl = addr_tbl_hevc_dec;
976 size = sizeof(addr_tbl_hevc_dec);
978 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
979 switch (reg_check_fmt(reg)) {
980 case VPU_DEC_FMT_H264:
982 tbl = addr_tbl_vpu_h264dec;
983 size = sizeof(addr_tbl_vpu_h264dec);
986 case VPU_DEC_FMT_VP8:
987 case VPU_DEC_FMT_VP7:
989 tbl = addr_tbl_vpu_vp8dec;
990 size = sizeof(addr_tbl_vpu_vp8dec);
994 case VPU_DEC_FMT_VP6:
996 tbl = addr_tbl_vpu_vp6dec;
997 size = sizeof(addr_tbl_vpu_vp6dec);
1000 case VPU_DEC_FMT_VC1:
1002 tbl = addr_tbl_vpu_vc1dec;
1003 size = sizeof(addr_tbl_vpu_vc1dec);
1007 case VPU_DEC_FMT_JPEG:
1009 tbl = addr_tbl_vpu_jpegdec;
1010 size = sizeof(addr_tbl_vpu_jpegdec);
1014 tbl = addr_tbl_vpu_defaultdec;
1015 size = sizeof(addr_tbl_vpu_defaultdec);
1018 } else if (reg->type == VPU_ENC) {
1019 tbl = addr_tbl_vpu_enc;
1020 size = sizeof(addr_tbl_vpu_enc);
1025 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1032 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1033 vpu_session *session, void __user *src, u32 size)
1035 struct vpu_service_info *pservice = data->pservice;
1037 struct extra_info_for_iommu extra_info;
1038 vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1043 vpu_err("error: kmalloc fail in reg_init\n");
1047 if (size > data->reg_size) {
1048 /*printk("warning: vpu reg size %lu is larger than hw reg size %lu\n",
1049 size, pservice->reg_size);
1050 size = pservice->reg_size;*/
1051 extra_size = size - data->reg_size;
1052 size = data->reg_size;
1054 reg->session = session;
1055 reg->type = session->type;
1057 reg->freq = VPU_FREQ_DEFAULT;
1058 reg->reg = (unsigned long *)®[1];
1059 INIT_LIST_HEAD(®->session_link);
1060 INIT_LIST_HEAD(®->status_link);
1062 #if defined(CONFIG_VCODEC_MMU)
1064 INIT_LIST_HEAD(®->mem_region_list);
1067 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
1068 vpu_err("error: copy_from_user failed in reg_init\n");
1073 if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1074 vpu_err("error: copy_from_user failed in reg_init\n");
1079 #if defined(CONFIG_VCODEC_MMU)
1080 if (data->mmu_dev &&
1081 0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1082 vpu_err("error: translate reg address failed\n");
1088 mutex_lock(&pservice->lock);
1089 list_add_tail(®->status_link, &pservice->waiting);
1090 list_add_tail(®->session_link, &session->waiting);
1091 mutex_unlock(&pservice->lock);
1093 if (pservice->auto_freq) {
1094 if (!soc_is_rk2928g()) {
1095 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1096 if (reg_check_rmvb_wmv(reg)) {
1097 reg->freq = VPU_FREQ_200M;
1098 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1099 if (reg_probe_width(reg) > 3200) {
1100 // raise frequency for 4k avc.
1101 reg->freq = VPU_FREQ_500M;
1104 if (reg_check_interlace(reg)) {
1105 reg->freq = VPU_FREQ_400M;
1109 if (reg->type == VPU_PP) {
1110 reg->freq = VPU_FREQ_400M;
1118 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1120 struct vpu_service_info *pservice = data->pservice;
1121 #if defined(CONFIG_VCODEC_MMU)
1122 struct vcodec_mem_region *mem_region = NULL, *n;
1125 list_del_init(®->session_link);
1126 list_del_init(®->status_link);
1127 if (reg == pservice->reg_codec)
1128 pservice->reg_codec = NULL;
1129 if (reg == pservice->reg_pproc)
1130 pservice->reg_pproc = NULL;
1132 #if defined(CONFIG_VCODEC_MMU)
1133 /* release memory region attach to this registers table. */
1134 if (data->mmu_dev) {
1135 list_for_each_entry_safe(mem_region, n,
1136 ®->mem_region_list, reg_lnk) {
1137 /* do not unmap iommu manually,
1138 unmap will proccess when memory release */
1139 /*vcodec_enter_mode(data);
1140 ion_unmap_iommu(data->dev,
1141 pservice->ion_client,
1143 vcodec_exit_mode();*/
1144 ion_free(pservice->ion_client, mem_region->hdl);
1145 list_del_init(&mem_region->reg_lnk);
1154 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1157 list_del_init(®->status_link);
1158 list_add_tail(®->status_link, &pservice->running);
1160 list_del_init(®->session_link);
1161 list_add_tail(®->session_link, ®->session->running);
1165 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1168 u32 *dst = (u32 *)®->reg[0];
1170 for (i = 0; i < count; i++)
1175 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1178 struct vpu_service_info *pservice = data->pservice;
1183 list_del_init(®->status_link);
1184 list_add_tail(®->status_link, &pservice->done);
1186 list_del_init(®->session_link);
1187 list_add_tail(®->session_link, ®->session->done);
1189 vcodec_enter_mode(data);
1190 switch (reg->type) {
1192 pservice->reg_codec = NULL;
1193 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1194 irq_reg = ENC_INTERRUPT_REGISTER;
1198 int reg_len = REG_NUM_9190_DEC;
1199 pservice->reg_codec = NULL;
1200 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1201 irq_reg = DEC_INTERRUPT_REGISTER;
1205 pservice->reg_pproc = NULL;
1206 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1207 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1211 pservice->reg_codec = NULL;
1212 pservice->reg_pproc = NULL;
1213 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1214 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1218 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1222 vcodec_exit_mode(pservice);
1225 reg->reg[irq_reg] = pservice->irq_status;
1227 atomic_sub(1, ®->session->task_running);
1228 atomic_sub(1, &pservice->total_running);
1229 wake_up(®->session->wait);
1234 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1236 VPU_FREQ curr = atomic_read(&pservice->freq_status);
1237 if (curr == reg->freq)
1239 atomic_set(&pservice->freq_status, reg->freq);
1240 switch (reg->freq) {
1241 case VPU_FREQ_200M : {
1242 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1244 case VPU_FREQ_266M : {
1245 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1247 case VPU_FREQ_300M : {
1248 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1250 case VPU_FREQ_400M : {
1251 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1253 case VPU_FREQ_500M : {
1254 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1256 case VPU_FREQ_600M : {
1257 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1260 if (soc_is_rk2928g())
1261 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1263 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1268 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1270 struct vpu_service_info *pservice = data->pservice;
1272 u32 *src = (u32 *)®->reg[0];
1275 atomic_add(1, &pservice->total_running);
1276 atomic_add(1, ®->session->task_running);
1277 if (pservice->auto_freq)
1278 vpu_service_set_freq(pservice, reg);
1280 vcodec_enter_mode(data);
1282 switch (reg->type) {
1284 int enc_count = data->hw_info->enc_reg_num;
1285 u32 *dst = (u32 *)data->enc_dev.hwregs;
1287 pservice->reg_codec = reg;
1289 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1291 for (i = 0; i < VPU_REG_EN_ENC; i++)
1294 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1297 VEPU_CLEAN_CACHE(dst);
1301 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1302 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
1304 #if VPU_SERVICE_SHOW_TIME
1305 do_gettimeofday(&enc_start);
1310 u32 *dst = (u32 *)data->dec_dev.hwregs;
1312 pservice->reg_codec = reg;
1314 if (data->hw_info->hw_id != HEVC_ID) {
1315 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1317 VDPU_CLEAN_CACHE(dst);
1319 for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1321 HEVC_CLEAN_CACHE(dst);
1326 if (data->hw_info->hw_id != HEVC_ID) {
1327 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1328 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1330 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1334 #if VPU_SERVICE_SHOW_TIME
1335 do_gettimeofday(&dec_start);
1339 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1340 pservice->reg_pproc = reg;
1342 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1344 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1349 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1350 #if VPU_SERVICE_SHOW_TIME
1351 do_gettimeofday(&pp_start);
1356 u32 *dst = (u32 *)data->dec_dev.hwregs;
1357 pservice->reg_codec = reg;
1358 pservice->reg_pproc = reg;
1360 VDPU_SOFT_RESET(dst);
1361 VDPU_CLEAN_CACHE(dst);
1363 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1366 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
1369 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1370 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1371 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1372 #if VPU_SERVICE_SHOW_TIME
1373 do_gettimeofday(&dec_start);
1377 vpu_err("error: unsupport session type %d", reg->type);
1378 atomic_sub(1, &pservice->total_running);
1379 atomic_sub(1, ®->session->task_running);
1384 vcodec_exit_mode(pservice);
1388 static void try_set_reg(struct vpu_subdev_data *data)
1390 struct vpu_service_info *pservice = data->pservice;
1392 if (!list_empty(&pservice->waiting)) {
1394 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1396 vpu_service_power_on(pservice);
1398 switch (reg->type) {
1400 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1404 if (NULL == pservice->reg_codec)
1406 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1410 if (NULL == pservice->reg_codec) {
1411 if (NULL == pservice->reg_pproc)
1414 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1416 /* can not charge frequency when vpu is working */
1417 if (pservice->auto_freq)
1422 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
1426 printk("undefined reg type %d\n", reg->type);
1430 reg_from_wait_to_run(pservice, reg);
1431 reg_copy_to_hw(data, reg);
1437 static int return_reg(struct vpu_subdev_data *data,
1438 vpu_reg *reg, u32 __user *dst)
1442 switch (reg->type) {
1444 if (copy_to_user(dst, ®->reg[0], data->hw_info->enc_io_size))
1449 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1450 if (copy_to_user(dst, ®->reg[0], SIZE_REG(reg_len)))
1455 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1460 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1466 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1470 reg_deinit(data, reg);
1475 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1478 struct vpu_subdev_data *data =
1479 container_of(filp->f_dentry->d_inode->i_cdev,
1480 struct vpu_subdev_data, cdev);
1481 struct vpu_service_info *pservice = data->pservice;
1482 vpu_session *session = (vpu_session *)filp->private_data;
1484 vpu_debug(3, "cmd %x, VPU_IOC_SET_CLIENT_TYPE %x\n", cmd, (u32)VPU_IOC_SET_CLIENT_TYPE);
1485 if (NULL == session)
1489 case VPU_IOC_SET_CLIENT_TYPE : {
1490 session->type = (enum VPU_CLIENT_TYPE)arg;
1493 case VPU_IOC_GET_HW_FUSE_STATUS : {
1495 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
1496 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1499 if (VPU_ENC != session->type) {
1500 if (copy_to_user((void __user *)req.req,
1501 &pservice->dec_config,
1502 sizeof(struct vpu_dec_config))) {
1503 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1508 if (copy_to_user((void __user *)req.req,
1509 &pservice->enc_config,
1510 sizeof(struct vpu_enc_config ))) {
1511 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1520 case VPU_IOC_SET_REG : {
1523 if (copy_from_user(&req, (void __user *)arg,
1524 sizeof(vpu_request))) {
1525 vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1528 reg = reg_init(data, session,
1529 (void __user *)req.req, req.size);
1533 mutex_lock(&pservice->lock);
1535 mutex_unlock(&pservice->lock);
1540 case VPU_IOC_GET_REG : {
1543 if (copy_from_user(&req, (void __user *)arg,
1544 sizeof(vpu_request))) {
1545 vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1548 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1549 if (!list_empty(&session->done)) {
1551 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1555 if (unlikely(ret < 0)) {
1556 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1557 } else if (0 == ret) {
1558 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1563 int task_running = atomic_read(&session->task_running);
1564 mutex_lock(&pservice->lock);
1565 vpu_service_dump(pservice);
1567 atomic_set(&session->task_running, 0);
1568 atomic_sub(task_running, &pservice->total_running);
1569 printk("%d task is running but not return, reset hardware...", task_running);
1573 vpu_service_session_clear(data, session);
1574 mutex_unlock(&pservice->lock);
1578 mutex_lock(&pservice->lock);
1579 reg = list_entry(session->done.next, vpu_reg, session_link);
1580 return_reg(data, reg, (u32 __user *)req.req);
1581 mutex_unlock(&pservice->lock);
1584 case VPU_IOC_PROBE_IOMMU_STATUS: {
1585 int iommu_enable = 0;
1587 #if defined(CONFIG_VCODEC_MMU)
1588 iommu_enable = data->mmu_dev ? 1 : 0;
1591 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1592 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1598 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1606 #ifdef CONFIG_COMPAT
1607 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1610 struct vpu_subdev_data *data =
1611 container_of(filp->f_dentry->d_inode->i_cdev,
1612 struct vpu_subdev_data, cdev);
1613 struct vpu_service_info *pservice = data->pservice;
1614 vpu_session *session = (vpu_session *)filp->private_data;
1616 vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1617 (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1618 if (NULL == session)
1622 case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1623 session->type = (enum VPU_CLIENT_TYPE)arg;
1626 case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1628 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1629 sizeof(vpu_request))) {
1630 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1631 " copy_from_user failed\n");
1634 if (VPU_ENC != session->type) {
1635 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1636 &pservice->dec_config,
1637 sizeof(struct vpu_dec_config))) {
1638 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1639 "copy_to_user failed type %d\n",
1644 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1645 &pservice->enc_config,
1646 sizeof(struct vpu_enc_config ))) {
1647 vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1648 " copy_to_user failed type %d\n",
1657 case COMPAT_VPU_IOC_SET_REG : {
1660 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1661 sizeof(vpu_request))) {
1662 vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1665 reg = reg_init(data, session,
1666 compat_ptr((compat_uptr_t)req.req), req.size);
1670 mutex_lock(&pservice->lock);
1672 mutex_unlock(&pservice->lock);
1677 case COMPAT_VPU_IOC_GET_REG : {
1680 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1681 sizeof(vpu_request))) {
1682 vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1685 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1686 if (!list_empty(&session->done)) {
1688 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1692 if (unlikely(ret < 0)) {
1693 vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1694 } else if (0 == ret) {
1695 vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1700 int task_running = atomic_read(&session->task_running);
1701 mutex_lock(&pservice->lock);
1702 vpu_service_dump(pservice);
1704 atomic_set(&session->task_running, 0);
1705 atomic_sub(task_running, &pservice->total_running);
1706 printk("%d task is running but not return, reset hardware...", task_running);
1710 vpu_service_session_clear(data, session);
1711 mutex_unlock(&pservice->lock);
1715 mutex_lock(&pservice->lock);
1716 reg = list_entry(session->done.next, vpu_reg, session_link);
1717 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1718 mutex_unlock(&pservice->lock);
1721 case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1722 int iommu_enable = 0;
1724 #if defined(CONFIG_VCODEC_MMU)
1725 iommu_enable = data->mmu_dev ? 1 : 0;
1728 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1729 vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1735 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1744 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1746 int ret = -EINVAL, i = 0;
1747 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1750 enc_id = (enc_id >> 16) & 0xFFFF;
1751 pr_info("checking hw id %x\n", enc_id);
1752 data->hw_info = NULL;
1753 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1754 if (enc_id == vpu_hw_set[i].hw_id) {
1755 data->hw_info = &vpu_hw_set[i];
1760 iounmap((void *)tmp);
1764 static int vpu_service_open(struct inode *inode, struct file *filp)
1766 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1767 struct vpu_service_info *pservice = data->pservice;
1768 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
1772 if (NULL == session) {
1773 vpu_err("error: unable to allocate memory for vpu_session.");
1777 session->type = VPU_TYPE_BUTT;
1778 session->pid = current->pid;
1779 INIT_LIST_HEAD(&session->waiting);
1780 INIT_LIST_HEAD(&session->running);
1781 INIT_LIST_HEAD(&session->done);
1782 INIT_LIST_HEAD(&session->list_session);
1783 init_waitqueue_head(&session->wait);
1784 atomic_set(&session->task_running, 0);
1785 mutex_lock(&pservice->lock);
1786 list_add_tail(&session->list_session, &pservice->session);
1787 filp->private_data = (void *)session;
1788 mutex_unlock(&pservice->lock);
1790 pr_debug("dev opened\n");
1792 return nonseekable_open(inode, filp);
1795 static int vpu_service_release(struct inode *inode, struct file *filp)
1797 struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
1798 struct vpu_service_info *pservice = data->pservice;
1800 vpu_session *session = (vpu_session *)filp->private_data;
1802 if (NULL == session)
1805 task_running = atomic_read(&session->task_running);
1807 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
1810 wake_up(&session->wait);
1812 mutex_lock(&pservice->lock);
1813 /* remove this filp from the asynchronusly notified filp's */
1814 list_del_init(&session->list_session);
1815 vpu_service_session_clear(data, session);
1817 filp->private_data = NULL;
1818 mutex_unlock(&pservice->lock);
1820 pr_debug("dev closed\n");
1825 static const struct file_operations vpu_service_fops = {
1826 .unlocked_ioctl = vpu_service_ioctl,
1827 .open = vpu_service_open,
1828 .release = vpu_service_release,
1829 #ifdef CONFIG_COMPAT
1830 .compat_ioctl = compat_vpu_service_ioctl,
1832 //.fasync = vpu_service_fasync,
1835 static irqreturn_t vdpu_irq(int irq, void *dev_id);
1836 static irqreturn_t vdpu_isr(int irq, void *dev_id);
1837 static irqreturn_t vepu_irq(int irq, void *dev_id);
1838 static irqreturn_t vepu_isr(int irq, void *dev_id);
1839 static void get_hw_info(struct vpu_subdev_data *data);
1841 #ifdef CONFIG_VCODEC_MMU
1842 static struct device *rockchip_get_sysmmu_dev(const char *compt)
1844 struct device_node *dn = NULL;
1845 struct platform_device *pd = NULL;
1846 struct device *ret = NULL ;
1848 dn = of_find_compatible_node(NULL,NULL,compt);
1850 printk("can't find device node %s \r\n",compt);
1854 pd = of_find_device_by_node(dn);
1856 printk("can't find platform device in device node %s\n",compt);
1864 #ifdef CONFIG_IOMMU_API
1865 static inline void platform_set_sysmmu(struct device *iommu,
1868 dev->archdata.iommu = iommu;
1871 static inline void platform_set_sysmmu(struct device *iommu,
1877 int vcodec_sysmmu_fault_hdl(struct device *dev,
1878 enum rk_iommu_inttype itype,
1879 unsigned long pgtable_base,
1880 unsigned long fault_addr, unsigned int status)
1882 struct platform_device *pdev;
1883 struct vpu_subdev_data *data;
1884 struct vpu_service_info *pservice;
1888 pdev = container_of(dev, struct platform_device, dev);
1890 data = platform_get_drvdata(pdev);
1891 pservice = data->pservice;
1893 if (pservice->reg_codec) {
1894 struct vcodec_mem_region *mem, *n;
1896 vpu_debug(3, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
1897 list_for_each_entry_safe(mem, n,
1898 &pservice->reg_codec->mem_region_list,
1900 vpu_debug(3, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
1901 mem->reg_idx, i, (u32)mem->iova, mem->len);
1905 pr_alert("vcodec, page fault occur, reset hw\n");
1906 pservice->reg_codec->reg[101] = 1;
1914 #if HEVC_TEST_ENABLE
1915 static int hevc_test_case0(vpu_service_info *pservice);
1917 #if defined(CONFIG_ION_ROCKCHIP)
1918 extern struct ion_client *rockchip_ion_client_create(const char * name);
1921 static int vcodec_subdev_probe(struct platform_device *pdev,
1922 struct vpu_service_info *pservice)
1925 struct resource *res = NULL;
1927 struct device *dev = &pdev->dev;
1928 char *name = (char*)dev_name(dev);
1929 struct device_node *np = pdev->dev.of_node;
1930 struct vpu_subdev_data *data =
1931 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
1932 #if defined(CONFIG_VCODEC_MMU)
1934 char mmu_dev_dts_name[40];
1935 of_property_read_u32(np, "iommu_enabled", &iommu_en);
1937 pr_info("probe device %s\n", dev_name(dev));
1939 data->pservice = pservice;
1942 of_property_read_string(np, "name", (const char**)&name);
1943 of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
1944 dev_set_name(dev, name);
1946 if (pservice->reg_base == 0) {
1947 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1948 data->regs = devm_ioremap_resource(dev, res);
1949 if (IS_ERR(data->regs)) {
1950 ret = PTR_ERR(data->regs);
1953 ioaddr = res->start;
1955 data->regs = pservice->reg_base;
1956 ioaddr = pservice->ioaddr;
1959 clear_bit(MMU_ACTIVATED, &data->state);
1960 vcodec_enter_mode(data);
1961 ret = vpu_service_check_hw(data, ioaddr);
1963 vpu_err("error: hw info check faild\n");
1967 data->dec_dev.iosize = data->hw_info->dec_io_size;
1968 data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
1969 data->reg_size = data->dec_dev.iosize;
1971 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
1972 data->enc_dev.iosize = data->hw_info->enc_io_size;
1973 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
1974 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
1977 data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
1978 if (data->irq_enc > 0) {
1979 ret = devm_request_threaded_irq(dev,
1980 data->irq_enc, vepu_irq, vepu_isr,
1981 IRQF_SHARED, dev_name(dev),
1985 "error: can't request vepu irq %d\n",
1990 data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
1991 if (data->irq_dec > 0) {
1992 ret = devm_request_threaded_irq(dev,
1993 data->irq_dec, vdpu_irq, vdpu_isr,
1994 IRQF_SHARED, dev_name(dev),
1998 "error: can't request vdpu irq %d\n",
2003 atomic_set(&data->dec_dev.irq_count_codec, 0);
2004 atomic_set(&data->dec_dev.irq_count_pp, 0);
2005 atomic_set(&data->enc_dev.irq_count_codec, 0);
2006 atomic_set(&data->enc_dev.irq_count_pp, 0);
2007 #if defined(CONFIG_VCODEC_MMU)
2009 vcodec_enter_mode(data);
2010 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2011 sprintf(mmu_dev_dts_name,
2012 HEVC_IOMMU_COMPATIBLE_NAME);
2014 sprintf(mmu_dev_dts_name,
2015 VPU_IOMMU_COMPATIBLE_NAME);
2018 rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2021 platform_set_sysmmu(data->mmu_dev, dev);
2023 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2026 /* create device node */
2027 ret = alloc_chrdev_region(&data->dev_t, 0, 1, dev_name(dev));
2029 dev_err(dev, "alloc dev_t failed\n");
2033 cdev_init(&data->cdev, &vpu_service_fops);
2035 data->cdev.owner = THIS_MODULE;
2036 data->cdev.ops = &vpu_service_fops;
2038 ret = cdev_add(&data->cdev, data->dev_t, 1);
2041 dev_err(dev, "add dev_t failed\n");
2045 data->cls = class_create(THIS_MODULE, dev_name(dev));
2047 if (IS_ERR(data->cls)) {
2048 ret = PTR_ERR(data->cls);
2049 dev_err(dev, "class_create err:%d\n", ret);
2053 data->child_dev = device_create(data->cls, dev,
2054 data->dev_t, NULL, dev_name(dev));
2058 platform_set_drvdata(pdev, data);
2060 INIT_LIST_HEAD(&data->lnk_service);
2061 list_add_tail(&data->lnk_service, &pservice->subdev_list);
2063 #ifdef CONFIG_DEBUG_FS
2065 vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
2066 if (data->debugfs_dir == NULL)
2067 vpu_err("create debugfs dir %s failed\n", dev_name(dev));
2069 data->debugfs_file_regs =
2070 debugfs_create_file("regs", 0664,
2071 data->debugfs_dir, data,
2072 &debug_vcodec_fops);
2076 if (data->irq_enc > 0)
2077 free_irq(data->irq_enc, (void *)data);
2078 if (data->irq_dec > 0)
2079 free_irq(data->irq_dec, (void *)data);
2081 if (data->child_dev) {
2082 device_destroy(data->cls, data->dev_t);
2083 cdev_del(&data->cdev);
2084 unregister_chrdev_region(data->dev_t, 1);
2088 class_destroy(data->cls);
2092 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2094 device_destroy(data->cls, data->dev_t);
2095 class_destroy(data->cls);
2096 cdev_del(&data->cdev);
2097 unregister_chrdev_region(data->dev_t, 1);
2099 free_irq(data->irq_enc, (void *)&data);
2100 free_irq(data->irq_dec, (void *)&data);
2102 #ifdef CONFIG_DEBUG_FS
2103 debugfs_remove(data->debugfs_file_regs);
2104 debugfs_remove(data->debugfs_dir);
2108 static void vcodec_read_property(struct device_node *np,
2109 struct vpu_service_info *pservice)
2111 pservice->mode_bit = 0;
2112 pservice->mode_ctrl = 0;
2113 pservice->subcnt = 0;
2115 of_property_read_u32(np, "subcnt", &pservice->subcnt);
2117 if (pservice->subcnt > 1) {
2118 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2119 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2121 #ifdef CONFIG_REGMAP
2122 pservice->grf_base = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2124 pservice->grf_base = (u32*)RK_GRF_VIRT;
2126 if (IS_ERR(pservice->grf_base)) {
2127 vpu_err("can't find vpu grf property\n");
2130 of_property_read_string(np, "name", (const char**)&pservice->name);
2133 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2135 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2136 pservice->curr_mode = -1;
2138 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2139 INIT_LIST_HEAD(&pservice->waiting);
2140 INIT_LIST_HEAD(&pservice->running);
2141 mutex_init(&pservice->lock);
2143 INIT_LIST_HEAD(&pservice->done);
2144 INIT_LIST_HEAD(&pservice->session);
2145 INIT_LIST_HEAD(&pservice->subdev_list);
2147 pservice->reg_pproc = NULL;
2148 atomic_set(&pservice->total_running, 0);
2149 pservice->enabled = false;
2151 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2153 pservice->ion_client = rockchip_ion_client_create("vpu");
2154 if (IS_ERR(pservice->ion_client)) {
2155 vpu_err("failed to create ion client for vcodec ret %ld\n",
2156 PTR_ERR(pservice->ion_client));
2158 vpu_debug(3, "vcodec ion client create success!\n");
2162 static int vcodec_probe(struct platform_device *pdev)
2166 struct resource *res = NULL;
2167 struct device *dev = &pdev->dev;
2168 struct device_node *np = pdev->dev.of_node;
2169 struct vpu_service_info *pservice =
2170 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2172 pr_info("probe device %s\n", dev_name(dev));
2174 vcodec_read_property(np, pservice);
2175 vcodec_init_drvdata(pservice);
2177 if (strncmp(pservice->name, "hevc_service", 12) == 0)
2178 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2179 else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2180 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2182 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2184 pservice->dev = dev;
2186 if (0 > vpu_get_clk(pservice))
2189 vpu_service_power_on(pservice);
2191 if (of_property_read_bool(np, "reg")) {
2192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2194 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2195 if (IS_ERR(pservice->reg_base)) {
2196 vpu_err("ioremap registers base failed\n");
2197 ret = PTR_ERR(pservice->reg_base);
2200 pservice->ioaddr = res->start;
2202 pservice->reg_base = 0;
2205 if (of_property_read_bool(np, "subcnt")) {
2206 for (i = 0; i<pservice->subcnt; i++) {
2207 struct device_node *sub_np;
2208 struct platform_device *sub_pdev;
2209 sub_np = of_parse_phandle(np, "rockchip,sub", i);
2210 sub_pdev = of_find_device_by_node(sub_np);
2212 vcodec_subdev_probe(sub_pdev, pservice);
2215 vcodec_subdev_probe(pdev, pservice);
2217 platform_set_drvdata(pdev, pservice);
2219 vpu_service_power_off(pservice);
2221 pr_info("init success\n");
2226 pr_info("init failed\n");
2227 vpu_service_power_off(pservice);
2228 vpu_put_clk(pservice);
2229 wake_lock_destroy(&pservice->wake_lock);
2232 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2237 static int vcodec_remove(struct platform_device *pdev)
2239 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2240 struct resource *res;
2241 struct vpu_subdev_data *data, *n;
2243 list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2244 vcodec_subdev_remove(data);
2247 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2248 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2249 vpu_put_clk(pservice);
2250 wake_lock_destroy(&pservice->wake_lock);
2255 #if defined(CONFIG_OF)
2256 static const struct of_device_id vcodec_service_dt_ids[] = {
2257 {.compatible = "vpu_service",},
2258 {.compatible = "rockchip,hevc_service",},
2259 {.compatible = "rockchip,vpu_combo",},
2264 static struct platform_driver vcodec_driver = {
2265 .probe = vcodec_probe,
2266 .remove = vcodec_remove,
2269 .owner = THIS_MODULE,
2270 #if defined(CONFIG_OF)
2271 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2276 static void get_hw_info(struct vpu_subdev_data *data)
2278 struct vpu_service_info *pservice = data->pservice;
2279 struct vpu_dec_config *dec = &pservice->dec_config;
2280 struct vpu_enc_config *enc = &pservice->enc_config;
2281 if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2282 u32 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2283 u32 asicID = data->dec_dev.hwregs[0];
2285 dec->h264_support = (configReg >> DWL_H264_E) & 0x3U;
2286 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
2287 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2288 dec->jpegSupport = JPEG_PROGRESSIVE;
2289 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
2290 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
2291 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
2292 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2293 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2294 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
2296 dec->maxDecPicWidth = 4096;
2298 /* 2nd Config register */
2299 configReg = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2300 if (dec->refBufSupport) {
2301 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2302 dec->refBufSupport |= 2;
2303 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2304 dec->refBufSupport |= 4;
2306 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2307 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
2308 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
2309 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
2311 /* JPEG xtensions */
2312 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2313 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2315 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2317 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2318 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2320 dec->rvSupport = RV_NOT_SUPPORTED;
2321 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2323 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2324 dec->refBufSupport |= 8; /* enable HW support for offset */
2326 if (!cpu_is_rk3036()) {
2327 configReg = data->enc_dev.hwregs[63];
2328 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2329 enc->h264Enabled = (configReg >> 27) & 1;
2330 enc->mpeg4Enabled = (configReg >> 26) & 1;
2331 enc->jpegEnabled = (configReg >> 25) & 1;
2332 enc->vsEnabled = (configReg >> 24) & 1;
2333 enc->rgbEnabled = (configReg >> 28) & 1;
2334 enc->reg_size = data->reg_size;
2335 enc->reserv[0] = enc->reserv[1] = 0;
2337 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926() || soc_is_rk3288();
2338 if (pservice->auto_freq) {
2339 vpu_debug(3, "vpu_service set to auto frequency mode\n");
2340 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2343 pservice->bug_dec_addr = cpu_is_rk30xx();
2345 if (cpu_is_rk3036() || cpu_is_rk312x())
2346 dec->maxDecPicWidth = 1920;
2348 dec->maxDecPicWidth = 4096;
2349 /* disable frequency switch in hevc.*/
2350 pservice->auto_freq = false;
2354 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2356 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2357 struct vpu_service_info *pservice = data->pservice;
2358 vpu_device *dev = &data->dec_dev;
2362 vcodec_enter_mode(data);
2364 irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2366 vpu_debug(3, "%s status %08x\n", __func__, raw_status);
2368 if (irq_status & DEC_INTERRUPT_BIT) {
2369 pr_debug("dec_isr dec %x\n", irq_status);
2370 if ((irq_status & 0x40001) == 0x40001) {
2374 DEC_INTERRUPT_REGISTER);
2375 } while ((irq_status & 0x40001) == 0x40001);
2378 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2379 atomic_add(1, &dev->irq_count_codec);
2382 if (data->hw_info->hw_id != HEVC_ID) {
2383 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2384 if (irq_status & PP_INTERRUPT_BIT) {
2385 pr_debug("vdpu_isr pp %x\n", irq_status);
2387 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2388 atomic_add(1, &dev->irq_count_pp);
2392 pservice->irq_status = raw_status;
2394 vcodec_exit_mode(pservice);
2396 return IRQ_WAKE_THREAD;
2399 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2401 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2402 struct vpu_service_info *pservice = data->pservice;
2403 vpu_device *dev = &data->dec_dev;
2405 mutex_lock(&pservice->lock);
2406 if (atomic_read(&dev->irq_count_codec)) {
2407 #if VPU_SERVICE_SHOW_TIME
2408 do_gettimeofday(&dec_end);
2409 vpu_debug(3, "dec task: %ld ms\n",
2410 (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
2411 (dec_end.tv_usec - dec_start.tv_usec) / 1000);
2413 atomic_sub(1, &dev->irq_count_codec);
2414 if (NULL == pservice->reg_codec) {
2415 vpu_err("error: dec isr with no task waiting\n");
2417 reg_from_run_to_done(data, pservice->reg_codec);
2421 if (atomic_read(&dev->irq_count_pp)) {
2422 #if VPU_SERVICE_SHOW_TIME
2423 do_gettimeofday(&pp_end);
2424 printk("pp task: %ld ms\n",
2425 (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
2426 (pp_end.tv_usec - pp_start.tv_usec) / 1000);
2428 atomic_sub(1, &dev->irq_count_pp);
2429 if (NULL == pservice->reg_pproc) {
2430 vpu_err("error: pp isr with no task waiting\n");
2432 reg_from_run_to_done(data, pservice->reg_pproc);
2436 mutex_unlock(&pservice->lock);
2440 static irqreturn_t vepu_irq(int irq, void *dev_id)
2442 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2443 struct vpu_service_info *pservice = data->pservice;
2444 vpu_device *dev = &data->enc_dev;
2447 vcodec_enter_mode(data);
2448 irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2450 pr_debug("vepu_irq irq status %x\n", irq_status);
2452 #if VPU_SERVICE_SHOW_TIME
2453 do_gettimeofday(&enc_end);
2454 vpu_debug(3, "enc task: %ld ms\n",
2455 (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
2456 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
2458 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2460 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2461 atomic_add(1, &dev->irq_count_codec);
2464 pservice->irq_status = irq_status;
2466 vcodec_exit_mode(pservice);
2468 return IRQ_WAKE_THREAD;
2471 static irqreturn_t vepu_isr(int irq, void *dev_id)
2473 struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2474 struct vpu_service_info *pservice = data->pservice;
2475 vpu_device *dev = &data->enc_dev;
2477 mutex_lock(&pservice->lock);
2478 if (atomic_read(&dev->irq_count_codec)) {
2479 atomic_sub(1, &dev->irq_count_codec);
2480 if (NULL == pservice->reg_codec) {
2481 vpu_err("error: enc isr with no task waiting\n");
2483 reg_from_run_to_done(data, pservice->reg_codec);
2487 mutex_unlock(&pservice->lock);
2491 static int __init vcodec_service_init(void)
2495 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2496 vpu_err("Platform device register failed (%d).\n", ret);
2500 #ifdef CONFIG_DEBUG_FS
2501 vcodec_debugfs_init();
2507 static void __exit vcodec_service_exit(void)
2509 #ifdef CONFIG_DEBUG_FS
2510 vcodec_debugfs_exit();
2513 platform_driver_unregister(&vcodec_driver);
2516 module_init(vcodec_service_init);
2517 module_exit(vcodec_service_exit);
2519 #ifdef CONFIG_DEBUG_FS
2520 #include <linux/seq_file.h>
2522 static int vcodec_debugfs_init()
2524 parent = debugfs_create_dir("vcodec", NULL);
2531 static void vcodec_debugfs_exit()
2533 debugfs_remove(parent);
2536 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2538 return debugfs_create_dir(dirname, parent);
2541 static int debug_vcodec_show(struct seq_file *s, void *unused)
2543 struct vpu_subdev_data *data = s->private;
2544 struct vpu_service_info *pservice = data->pservice;
2546 vpu_reg *reg, *reg_tmp;
2547 vpu_session *session, *session_tmp;
2549 mutex_lock(&pservice->lock);
2550 vpu_service_power_on(pservice);
2551 if (data->hw_info->hw_id != HEVC_ID) {
2552 seq_printf(s, "\nENC Registers:\n");
2553 n = data->enc_dev.iosize >> 2;
2554 for (i = 0; i < n; i++)
2555 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2557 seq_printf(s, "\nDEC Registers:\n");
2558 n = data->dec_dev.iosize >> 2;
2559 for (i = 0; i < n; i++)
2560 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2562 seq_printf(s, "\nvpu service status:\n");
2563 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2564 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2565 /*seq_printf(s, "waiting reg set %d\n");*/
2566 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2567 seq_printf(s, "waiting register set\n");
2569 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2570 seq_printf(s, "running register set\n");
2572 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2573 seq_printf(s, "done register set\n");
2576 mutex_unlock(&pservice->lock);
2581 static int debug_vcodec_open(struct inode *inode, struct file *file)
2583 return single_open(file, debug_vcodec_show, inode->i_private);
2588 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2589 #include "hevc_test_inc/pps_00.h"
2590 #include "hevc_test_inc/register_00.h"
2591 #include "hevc_test_inc/rps_00.h"
2592 #include "hevc_test_inc/scaling_list_00.h"
2593 #include "hevc_test_inc/stream_00.h"
2595 #include "hevc_test_inc/pps_01.h"
2596 #include "hevc_test_inc/register_01.h"
2597 #include "hevc_test_inc/rps_01.h"
2598 #include "hevc_test_inc/scaling_list_01.h"
2599 #include "hevc_test_inc/stream_01.h"
2601 #include "hevc_test_inc/cabac.h"
2603 extern struct ion_client *rockchip_ion_client_create(const char * name);
2605 static struct ion_client *ion_client = NULL;
2606 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2608 int size = (len+15) & (~15);
2609 struct ion_handle *handle;
2610 u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
2612 if (ion_client == NULL)
2613 ion_client = rockchip_ion_client_create("vcodec");
2615 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2617 ptr = ion_map_kernel(ion_client, handle);
2619 ion_phys(ion_client, handle, phy, &size);
2621 memcpy(ptr, tbl, len);
2626 u8* get_align_ptr_no_copy(int len, u32 *phy)
2628 int size = (len+15) & (~15);
2629 struct ion_handle *handle;
2632 if (ion_client == NULL)
2633 ion_client = rockchip_ion_client_create("vcodec");
2635 handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2637 ptr = ion_map_kernel(ion_client, handle);
2639 ion_phys(ion_client, handle, phy, &size);
2645 static int hevc_test_case0(vpu_service_info *pservice)
2647 vpu_session session;
2649 unsigned long size = 272;//sizeof(register_00); // registers array length
2652 u8 *pps_tbl[TEST_CNT];
2653 u8 *register_tbl[TEST_CNT];
2654 u8 *rps_tbl[TEST_CNT];
2655 u8 *scaling_list_tbl[TEST_CNT];
2656 u8 *stream_tbl[TEST_CNT];
2672 volatile u8 *stream_buf;
2673 volatile u8 *pps_buf;
2674 volatile u8 *rps_buf;
2675 volatile u8 *scl_buf;
2676 volatile u8 *yuv_buf;
2677 volatile u8 *cabac_buf;
2678 volatile u8 *ref_buf;
2684 pps_tbl[0] = pps_00;
2685 pps_tbl[1] = pps_01;
2687 register_tbl[0] = register_00;
2688 register_tbl[1] = register_01;
2690 rps_tbl[0] = rps_00;
2691 rps_tbl[1] = rps_01;
2693 scaling_list_tbl[0] = scaling_list_00;
2694 scaling_list_tbl[1] = scaling_list_01;
2696 stream_tbl[0] = stream_00;
2697 stream_tbl[1] = stream_01;
2699 stream_size[0] = sizeof(stream_00);
2700 stream_size[1] = sizeof(stream_01);
2702 pps_size[0] = sizeof(pps_00);
2703 pps_size[1] = sizeof(pps_01);
2705 rps_size[0] = sizeof(rps_00);
2706 rps_size[1] = sizeof(rps_01);
2708 scl_size[0] = sizeof(scaling_list_00);
2709 scl_size[1] = sizeof(scaling_list_01);
2711 cabac_size[0] = sizeof(Cabac_table);
2712 cabac_size[1] = sizeof(Cabac_table);
2714 /* create session */
2715 session.pid = current->pid;
2716 session.type = VPU_DEC;
2717 INIT_LIST_HEAD(&session.waiting);
2718 INIT_LIST_HEAD(&session.running);
2719 INIT_LIST_HEAD(&session.done);
2720 INIT_LIST_HEAD(&session.list_session);
2721 init_waitqueue_head(&session.wait);
2722 atomic_set(&session.task_running, 0);
2723 list_add_tail(&session.list_session, &pservice->session);
2725 yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
2726 yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
2728 while (testidx < TEST_CNT) {
2729 /* create registers */
2730 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
2732 vpu_err("error: kmalloc fail in reg_init\n");
2736 if (size > pservice->reg_size) {
2737 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
2738 size = pservice->reg_size;
2740 reg->session = &session;
2741 reg->type = session.type;
2743 reg->freq = VPU_FREQ_DEFAULT;
2744 reg->reg = (unsigned long *)®[1];
2745 INIT_LIST_HEAD(®->session_link);
2746 INIT_LIST_HEAD(®->status_link);
2748 /* TODO: stuff registers */
2749 memcpy(®->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
2751 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
2752 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
2753 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
2754 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
2755 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
2759 /* TODO: replace reigster address */
2760 for (i=0; i<64; i++) {
2764 scaling_offset = (u32)pps[i*80+74];
2765 scaling_offset += (u32)pps[i*80+75] << 8;
2766 scaling_offset += (u32)pps[i*80+76] << 16;
2767 scaling_offset += (u32)pps[i*80+77] << 24;
2769 tmp = phy_scl + scaling_offset;
2771 pps[i*80+74] = tmp & 0xff;
2772 pps[i*80+75] = (tmp >> 8) & 0xff;
2773 pps[i*80+76] = (tmp >> 16) & 0xff;
2774 pps[i*80+77] = (tmp >> 24) & 0xff;
2777 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
2778 __func__, __LINE__, phy_str, phy_pps, phy_rps);
2781 reg->reg[4] = phy_str;
2782 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
2783 reg->reg[6] = phy_cabac;
2784 reg->reg[7] = testidx?phy_ref:phy_yuv;
2785 reg->reg[42] = phy_pps;
2786 reg->reg[43] = phy_rps;
2787 for (i = 10; i <= 24; i++)
2788 reg->reg[i] = phy_yuv;
2790 mutex_lock(pservice->lock);
2791 list_add_tail(®->status_link, &pservice->waiting);
2792 list_add_tail(®->session_link, &session.waiting);
2793 mutex_unlock(pservice->lock);
2795 /* stuff hardware */
2798 /* wait for result */
2799 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
2800 if (!list_empty(&session.done)) {
2802 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
2805 if (unlikely(ret < 0)) {
2806 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
2807 } else if (0 == ret) {
2808 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
2813 int task_running = atomic_read(&session.task_running);
2815 mutex_lock(pservice->lock);
2816 vpu_service_dump(pservice);
2818 atomic_set(&session.task_running, 0);
2819 atomic_sub(task_running, &pservice->total_running);
2820 printk("%d task is running but not return, reset hardware...", task_running);
2824 vpu_service_session_clear(pservice, &session);
2825 mutex_unlock(pservice->lock);
2827 printk("\nDEC Registers:\n");
2828 n = data->dec_dev.iosize >> 2;
2830 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2832 vpu_err("test index %d failed\n", testidx);
2835 vpu_debug(3, "test index %d success\n", testidx);
2837 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
2839 for (i=0; i<68; i++) {
2841 printk("%02d: ", i);
2842 printk("%08x ", reg->reg[i]);
2850 reg_deinit(data, reg);