2 /* arch/arm/mach-rk29/vpu.c
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4 * Copyright (C) 2010 ROCKCHIP, Inc.
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5 * author: chenhengming chm@rock-chips.com
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7 * This software is licensed under the terms of the GNU General Public
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8 * License version 2, as published by the Free Software Foundation, and
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9 * may be copied, distributed, and modified under those terms.
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11 * This program is distributed in the hope that it will be useful,
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 * GNU General Public License for more details.
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18 #include <linux/clk.h>
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19 #include <linux/delay.h>
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20 #include <linux/init.h>
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21 #include <linux/interrupt.h>
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22 #include <linux/io.h>
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23 #include <linux/kernel.h>
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24 #include <linux/module.h>
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25 #include <linux/fs.h>
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26 #include <linux/ioport.h>
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27 #include <linux/miscdevice.h>
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28 #include <linux/mm.h>
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29 #include <linux/poll.h>
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30 #include <linux/platform_device.h>
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31 #include <linux/sched.h>
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32 #include <linux/slab.h>
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33 #include <linux/wakelock.h>
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34 #include <linux/cdev.h>
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35 #include <linux/of.h>
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36 #include <linux/rockchip/cpu.h>
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37 #include <linux/rockchip/cru.h>
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39 #include <asm/cacheflush.h>
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40 #include <asm/uaccess.h>
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42 #ifdef CONFIG_DEBUG_FS
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43 #include <linux/debugfs.h>
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46 #if defined(CONFIG_ARCH_RK319X)
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47 #include <mach/grf.h>
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50 #include "vcodec_service.h"
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52 #define HEVC_TEST_ENABLE 0
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53 #define HEVC_SIM_ENABLE 0
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56 VPU_DEC_ID_9190 = 0x6731,
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57 VPU_ID_8270 = 0x8270,
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58 VPU_ID_4831 = 0x4831,
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63 VPU_DEC_TYPE_9190 = 0,
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64 VPU_ENC_TYPE_8270 = 0x100,
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68 typedef enum VPU_FREQ {
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79 unsigned long hw_addr;
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80 unsigned long enc_offset;
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81 unsigned long enc_reg_num;
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82 unsigned long enc_io_size;
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83 unsigned long dec_offset;
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84 unsigned long dec_reg_num;
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85 unsigned long dec_io_size;
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88 #define VPU_SERVICE_SHOW_TIME 0
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90 #if VPU_SERVICE_SHOW_TIME
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91 static struct timeval enc_start, enc_end;
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92 static struct timeval dec_start, dec_end;
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93 static struct timeval pp_start, pp_end;
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96 #define MHZ (1000*1000)
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99 #if defined(CONFIG_ARCH_RK319X)
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100 #define VCODEC_PHYS RK319X_VCODEC_PHYS
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102 #define VCODEC_PHYS (0x10104000)
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106 #define REG_NUM_9190_DEC (60)
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107 #define REG_NUM_9190_PP (41)
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108 #define REG_NUM_9190_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
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110 #define REG_NUM_DEC_PP (REG_NUM_9190_DEC+REG_NUM_9190_PP)
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112 #define REG_NUM_ENC_8270 (96)
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113 #define REG_SIZE_ENC_8270 (0x200)
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114 #define REG_NUM_ENC_4831 (164)
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115 #define REG_SIZE_ENC_4831 (0x400)
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117 #define REG_NUM_HEVC_DEC (68)
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119 #define SIZE_REG(reg) ((reg)*4)
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121 static VPU_HW_INFO_E vpu_hw_set[] = {
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123 .hw_id = VPU_ID_8270,
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126 .enc_reg_num = REG_NUM_ENC_8270,
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127 .enc_io_size = REG_NUM_ENC_8270 * 4,
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128 .dec_offset = REG_SIZE_ENC_8270,
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129 .dec_reg_num = REG_NUM_9190_DEC_PP,
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130 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
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133 .hw_id = VPU_ID_4831,
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136 .enc_reg_num = REG_NUM_ENC_4831,
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137 .enc_io_size = REG_NUM_ENC_4831 * 4,
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138 .dec_offset = REG_SIZE_ENC_4831,
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139 .dec_reg_num = REG_NUM_9190_DEC_PP,
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140 .dec_io_size = REG_NUM_9190_DEC_PP * 4,
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146 .dec_reg_num = REG_NUM_HEVC_DEC,
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147 .dec_io_size = REG_NUM_HEVC_DEC * 4,
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152 #define DEC_INTERRUPT_REGISTER 1
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153 #define PP_INTERRUPT_REGISTER 60
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154 #define ENC_INTERRUPT_REGISTER 1
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156 #define DEC_INTERRUPT_BIT 0x100
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157 #define DEC_BUFFER_EMPTY_BIT 0x4000
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158 #define PP_INTERRUPT_BIT 0x100
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159 #define ENC_INTERRUPT_BIT 0x1
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161 #define HEVC_DEC_INT_RAW_BIT 0x200
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162 #define HEVC_DEC_STR_ERROR_BIT 0x4000
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163 #define HEVC_DEC_BUS_ERROR_BIT 0x2000
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164 #define HEVC_DEC_BUFFER_EMPTY_BIT 0x10000
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166 #define VPU_REG_EN_ENC 14
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167 #define VPU_REG_ENC_GATE 2
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168 #define VPU_REG_ENC_GATE_BIT (1<<4)
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170 #define VPU_REG_EN_DEC 1
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171 #define VPU_REG_DEC_GATE 2
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172 #define VPU_REG_DEC_GATE_BIT (1<<10)
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173 #define VPU_REG_EN_PP 0
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174 #define VPU_REG_PP_GATE 1
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175 #define VPU_REG_PP_GATE_BIT (1<<8)
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176 #define VPU_REG_EN_DEC_PP 1
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177 #define VPU_REG_DEC_PP_GATE 61
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178 #define VPU_REG_DEC_PP_GATE_BIT (1<<8)
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181 * struct for process session which connect to vpu
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183 * @author ChenHengming (2011-5-3)
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185 typedef struct vpu_session {
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186 VPU_CLIENT_TYPE type;
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187 /* a linked list of data so we can access them for debugging */
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188 struct list_head list_session;
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189 /* a linked list of register data waiting for process */
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190 struct list_head waiting;
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191 /* a linked list of register data in processing */
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192 struct list_head running;
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193 /* a linked list of register data processed */
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194 struct list_head done;
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195 wait_queue_head_t wait;
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197 atomic_t task_running;
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201 * struct for process register set
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203 * @author ChenHengming (2011-5-4)
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205 typedef struct vpu_reg {
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206 VPU_CLIENT_TYPE type;
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208 vpu_session *session;
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209 struct list_head session_link; /* link to vpu service session */
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210 struct list_head status_link; /* link to register set list */
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211 unsigned long size;
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212 unsigned long *reg;
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215 typedef struct vpu_device {
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216 atomic_t irq_count_codec;
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217 atomic_t irq_count_pp;
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218 unsigned long iobaseaddr;
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219 unsigned int iosize;
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220 volatile u32 *hwregs;
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223 typedef struct vpu_service_info {
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224 struct wake_lock wake_lock;
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225 struct delayed_work power_off_work;
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227 struct list_head waiting; /* link to link_reg in struct vpu_reg */
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228 struct list_head running; /* link to link_reg in struct vpu_reg */
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229 struct list_head done; /* link to link_reg in struct vpu_reg */
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230 struct list_head session; /* link to list_session in struct vpu_session */
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231 atomic_t total_running;
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233 vpu_reg *reg_codec;
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234 vpu_reg *reg_pproc;
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235 vpu_reg *reg_resev;
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236 VPUHwDecConfig_t dec_config;
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237 VPUHwEncConfig_t enc_config;
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238 VPU_HW_INFO_E *hw_info;
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239 unsigned long reg_size;
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242 atomic_t freq_status;
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244 struct clk *aclk_vcodec;
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245 struct clk *hclk_vcodec;
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250 vpu_device enc_dev;
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251 vpu_device dec_dev;
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253 struct device *dev;
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258 struct device *child_dev;
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260 struct dentry *debugfs_dir;
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261 struct dentry *debugfs_file_regs;
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265 struct delayed_work simulate_work;
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266 } vpu_service_info;
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268 typedef struct vpu_request
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270 unsigned long *req;
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271 unsigned long size;
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274 /// global variable
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275 //static struct clk *pd_video;
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276 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).
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278 #ifdef CONFIG_DEBUG_FS
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279 static int vcodec_debugfs_init(void);
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280 static void vcodec_debugfs_exit(void);
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281 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
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282 static int debug_vcodec_open(struct inode *inode, struct file *file);
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284 static const struct file_operations debug_vcodec_fops = {
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285 .open = debug_vcodec_open,
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287 .llseek = seq_lseek,
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288 .release = single_release,
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292 #define VPU_POWER_OFF_DELAY 4*HZ /* 4s */
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293 #define VPU_TIMEOUT_DELAY 2*HZ /* 2s */
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295 #define VPU_SIMULATE_DELAY msecs_to_jiffies(5)
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297 static void vpu_get_clk(struct vpu_service_info *pservice)
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299 /*pd_video = clk_get(NULL, "pd_video");
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300 if (IS_ERR(pd_video)) {
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301 pr_err("failed on clk_get pd_video\n");
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303 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
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304 if (IS_ERR(pservice->aclk_vcodec)) {
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305 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
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307 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
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308 if (IS_ERR(pservice->hclk_vcodec)) {
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309 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
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313 static void vpu_put_clk(struct vpu_service_info *pservice)
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315 //clk_put(pd_video);
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317 if (pservice->aclk_vcodec) {
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318 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
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321 if (pservice->hclk_vcodec) {
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322 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
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326 static void vpu_reset(struct vpu_service_info *pservice)
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328 #if defined(CONFIG_ARCH_RK29)
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329 clk_disable(aclk_ddr_vepu);
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330 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
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331 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
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332 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
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333 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
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335 cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
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336 cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
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337 cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
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338 cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
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339 clk_enable(aclk_ddr_vepu);
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340 #elif defined(CONFIG_ARCH_RK30)
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341 pmu_set_idle_request(IDLE_REQ_VIDEO, true);
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342 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
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343 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
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344 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
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345 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
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347 cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
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348 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
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349 cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
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350 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
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351 pmu_set_idle_request(IDLE_REQ_VIDEO, false);
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353 pservice->reg_codec = NULL;
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354 pservice->reg_pproc = NULL;
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355 pservice->reg_resev = NULL;
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358 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);
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359 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)
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362 list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
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363 reg_deinit(pservice, reg);
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365 list_for_each_entry_safe(reg, n, &session->running, session_link) {
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366 reg_deinit(pservice, reg);
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368 list_for_each_entry_safe(reg, n, &session->done, session_link) {
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369 reg_deinit(pservice, reg);
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373 static void vpu_service_dump(struct vpu_service_info *pservice)
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376 vpu_reg *reg, *reg_tmp;
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377 vpu_session *session, *session_tmp;
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379 running = atomic_read(&pservice->total_running);
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380 printk("total_running %d\n", running);
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382 printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);
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383 printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);
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384 printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);
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386 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
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387 printk("session pid %d type %d:\n", session->pid, session->type);
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388 running = atomic_read(&session->task_running);
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389 printk("task_running %d\n", running);
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390 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
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391 printk("waiting register set 0x%.8x\n", (unsigned int)reg);
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393 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
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394 printk("running register set 0x%.8x\n", (unsigned int)reg);
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396 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
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397 printk("done register set 0x%.8x\n", (unsigned int)reg);
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402 static void vpu_service_power_off(struct vpu_service_info *pservice)
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405 if (!pservice->enabled) {
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409 pservice->enabled = false;
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410 total_running = atomic_read(&pservice->total_running);
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411 if (total_running) {
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412 pr_alert("alert: power off when %d task running!!\n", total_running);
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414 pr_alert("alert: delay 50 ms for running task\n");
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415 vpu_service_dump(pservice);
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418 printk("vpu: power off...");
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419 #ifdef CONFIG_ARCH_RK29
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420 pmu_set_power_domain(PD_VCODEC, false);
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422 //clk_disable(pd_video);
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425 //clk_disable(hclk_cpu_vcodec);
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426 //clk_disable(aclk_ddr_vepu);
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428 clk_disable_unprepare(pservice->hclk_vcodec);
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429 clk_disable_unprepare(pservice->aclk_vcodec);
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431 wake_unlock(&pservice->wake_lock);
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435 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
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437 queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
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440 static void vpu_power_off_work(struct work_struct *work_s)
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442 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
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443 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
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445 if (mutex_trylock(&pservice->lock)) {
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446 vpu_service_power_off(pservice);
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447 mutex_unlock(&pservice->lock);
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449 /* Come back later if the device is busy... */
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450 vpu_queue_power_off_work(pservice);
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454 static void vpu_service_power_on(struct vpu_service_info *pservice)
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456 static ktime_t last;
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457 ktime_t now = ktime_get();
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458 if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
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459 cancel_delayed_work_sync(&pservice->power_off_work);
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460 vpu_queue_power_off_work(pservice);
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463 if (pservice->enabled)
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466 pservice->enabled = true;
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467 printk("vpu: power on\n");
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470 clk_prepare_enable(pservice->aclk_vcodec);
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471 clk_prepare_enable(pservice->hclk_vcodec);
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473 //clk_prepare_enable(hclk_cpu_vcodec);
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474 #if defined(CONFIG_ARCH_RK319X)
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475 /// select aclk_vepu as vcodec clock source.
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476 #define BIT_VCODEC_SEL (1<<7)
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477 writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);
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480 #ifdef CONFIG_ARCH_RK29
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481 pmu_set_power_domain(PD_VCODEC, true);
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483 //clk_enable(pd_video);
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486 //clk_enable(aclk_ddr_vepu);
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487 wake_lock(&pservice->wake_lock);
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490 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
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492 unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;
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493 return ((type == 8) || (type == 4));
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496 static inline bool reg_check_interlace(vpu_reg *reg)
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498 unsigned long type = (reg->reg[3] & (1 << 23));
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502 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)
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504 vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
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506 pr_err("error: kmalloc fail in reg_init\n");
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510 if (size > pservice->reg_size) {
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511 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
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512 size = pservice->reg_size;
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514 reg->session = session;
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515 reg->type = session->type;
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517 reg->freq = VPU_FREQ_DEFAULT;
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518 reg->reg = (unsigned long *)®[1];
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519 INIT_LIST_HEAD(®->session_link);
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520 INIT_LIST_HEAD(®->status_link);
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522 if (copy_from_user(®->reg[0], (void __user *)src, size)) {
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523 pr_err("error: copy_from_user failed in reg_init\n");
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528 mutex_lock(&pservice->lock);
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529 list_add_tail(®->status_link, &pservice->waiting);
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530 list_add_tail(®->session_link, &session->waiting);
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531 mutex_unlock(&pservice->lock);
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533 if (pservice->auto_freq) {
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534 if (!soc_is_rk2928g()) {
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535 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
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536 if (reg_check_rmvb_wmv(reg)) {
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537 reg->freq = VPU_FREQ_200M;
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539 if (reg_check_interlace(reg)) {
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540 reg->freq = VPU_FREQ_400M;
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544 if (reg->type == VPU_PP) {
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545 reg->freq = VPU_FREQ_400M;
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553 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)
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555 list_del_init(®->session_link);
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556 list_del_init(®->status_link);
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557 if (reg == pservice->reg_codec) pservice->reg_codec = NULL;
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558 if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;
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562 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
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564 list_del_init(®->status_link);
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565 list_add_tail(®->status_link, &pservice->running);
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567 list_del_init(®->session_link);
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568 list_add_tail(®->session_link, ®->session->running);
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571 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
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574 u32 *dst = (u32 *)®->reg[0];
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575 for (i = 0; i < count; i++)
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579 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)
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582 list_del_init(®->status_link);
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583 list_add_tail(®->status_link, &pservice->done);
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585 list_del_init(®->session_link);
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586 list_add_tail(®->session_link, ®->session->done);
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588 switch (reg->type) {
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590 pservice->reg_codec = NULL;
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591 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);
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592 irq_reg = ENC_INTERRUPT_REGISTER;
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596 pservice->reg_codec = NULL;
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597 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC);
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598 irq_reg = DEC_INTERRUPT_REGISTER;
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602 pservice->reg_pproc = NULL;
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603 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
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604 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
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607 case VPU_DEC_PP : {
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608 pservice->reg_codec = NULL;
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609 pservice->reg_pproc = NULL;
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610 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
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611 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
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615 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);
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620 if (irq_reg != -1) {
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621 reg->reg[irq_reg] = pservice->irq_status;
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624 atomic_sub(1, ®->session->task_running);
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625 atomic_sub(1, &pservice->total_running);
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626 wake_up(®->session->wait);
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629 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
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631 VPU_FREQ curr = atomic_read(&pservice->freq_status);
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632 if (curr == reg->freq) {
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635 atomic_set(&pservice->freq_status, reg->freq);
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636 switch (reg->freq) {
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637 case VPU_FREQ_200M : {
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638 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
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639 //printk("default: 200M\n");
\r
641 case VPU_FREQ_266M : {
\r
642 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
\r
643 //printk("default: 266M\n");
\r
645 case VPU_FREQ_300M : {
\r
646 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
\r
647 //printk("default: 300M\n");
\r
649 case VPU_FREQ_400M : {
\r
650 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
\r
651 //printk("default: 400M\n");
\r
654 if (soc_is_rk2928g()) {
\r
655 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
\r
657 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
\r
659 //printk("default: 300M\n");
\r
664 #if HEVC_SIM_ENABLE
\r
665 static void simulate_start(struct vpu_service_info *pservice);
\r
667 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)
\r
670 u32 *src = (u32 *)®->reg[0];
\r
671 atomic_add(1, &pservice->total_running);
\r
672 atomic_add(1, ®->session->task_running);
\r
673 if (pservice->auto_freq) {
\r
674 vpu_service_set_freq(pservice, reg);
\r
676 switch (reg->type) {
\r
678 int enc_count = pservice->hw_info->enc_reg_num;
\r
679 u32 *dst = (u32 *)pservice->enc_dev.hwregs;
\r
681 if (pservice->bug_dec_addr) {
\r
682 #if !defined(CONFIG_ARCH_RK319X)
\r
683 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
\r
685 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
\r
686 cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
\r
687 #if !defined(CONFIG_ARCH_RK319X)
\r
688 cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
\r
692 pservice->reg_codec = reg;
\r
694 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
\r
696 for (i = 0; i < VPU_REG_EN_ENC; i++)
\r
699 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
\r
704 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
\r
705 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC];
\r
707 #if VPU_SERVICE_SHOW_TIME
\r
708 do_gettimeofday(&enc_start);
\r
713 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
\r
714 pservice->reg_codec = reg;
\r
716 for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
\r
721 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
\r
722 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
\r
724 #if VPU_SERVICE_SHOW_TIME
\r
725 do_gettimeofday(&dec_start);
\r
730 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
\r
731 pservice->reg_pproc = reg;
\r
733 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
\r
735 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
\r
740 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
\r
742 #if VPU_SERVICE_SHOW_TIME
\r
743 do_gettimeofday(&pp_start);
\r
747 case VPU_DEC_PP : {
\r
748 u32 *dst = (u32 *)pservice->dec_dev.hwregs;
\r
749 pservice->reg_codec = reg;
\r
750 pservice->reg_pproc = reg;
\r
752 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
\r
755 dst[VPU_REG_EN_DEC_PP] = src[VPU_REG_EN_DEC_PP] | 0x2;
\r
758 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
\r
759 dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
\r
760 dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
\r
762 #if VPU_SERVICE_SHOW_TIME
\r
763 do_gettimeofday(&dec_start);
\r
768 pr_err("error: unsupport session type %d", reg->type);
\r
769 atomic_sub(1, &pservice->total_running);
\r
770 atomic_sub(1, ®->session->task_running);
\r
775 #if HEVC_SIM_ENABLE
\r
776 if (pservice->hw_info->hw_id == HEVC_ID) {
\r
777 simulate_start(pservice);
\r
782 static void try_set_reg(struct vpu_service_info *pservice)
\r
784 // first get reg from reg list
\r
785 if (!list_empty(&pservice->waiting)) {
\r
787 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
\r
789 vpu_service_power_on(pservice);
\r
791 switch (reg->type) {
\r
793 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
\r
797 if (NULL == pservice->reg_codec)
\r
799 if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {
\r
804 if (NULL == pservice->reg_codec) {
\r
805 if (NULL == pservice->reg_pproc)
\r
808 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
\r
810 // can not charge frequency when vpu is working
\r
811 if (pservice->auto_freq) {
\r
816 case VPU_DEC_PP : {
\r
817 if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))
\r
821 printk("undefined reg type %d\n", reg->type);
\r
825 reg_from_wait_to_run(pservice, reg);
\r
826 reg_copy_to_hw(pservice, reg);
\r
831 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)
\r
834 switch (reg->type) {
\r
836 if (copy_to_user(dst, ®->reg[0], pservice->hw_info->enc_io_size))
\r
841 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC)))
\r
846 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_PP)))
\r
850 case VPU_DEC_PP : {
\r
851 if (copy_to_user(dst, ®->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
\r
857 pr_err("error: copy reg to user with unknown type %d\n", reg->type);
\r
861 reg_deinit(pservice, reg);
\r
865 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
\r
867 struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);
\r
868 vpu_session *session = (vpu_session *)filp->private_data;
\r
869 if (NULL == session) {
\r
874 case VPU_IOC_SET_CLIENT_TYPE : {
\r
875 session->type = (VPU_CLIENT_TYPE)arg;
\r
878 case VPU_IOC_GET_HW_FUSE_STATUS : {
\r
880 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
881 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
\r
884 if (VPU_ENC != session->type) {
\r
885 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {
\r
886 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
\r
890 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {
\r
891 pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);
\r
899 case VPU_IOC_SET_REG : {
\r
902 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
903 pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
\r
906 reg = reg_init(pservice, session, (void __user *)req.req, req.size);
\r
910 mutex_lock(&pservice->lock);
\r
911 try_set_reg(pservice);
\r
912 mutex_unlock(&pservice->lock);
\r
917 case VPU_IOC_GET_REG : {
\r
920 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {
\r
921 pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
\r
924 int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
\r
925 if (!list_empty(&session->done)) {
\r
927 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
\r
931 if (unlikely(ret < 0)) {
\r
932 pr_err("error: pid %d wait task ret %d\n", session->pid, ret);
\r
933 } else if (0 == ret) {
\r
934 pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
\r
939 int task_running = atomic_read(&session->task_running);
\r
940 mutex_lock(&pservice->lock);
\r
941 vpu_service_dump(pservice);
\r
942 if (task_running) {
\r
943 atomic_set(&session->task_running, 0);
\r
944 atomic_sub(task_running, &pservice->total_running);
\r
945 printk("%d task is running but not return, reset hardware...", task_running);
\r
946 vpu_reset(pservice);
\r
949 vpu_service_session_clear(pservice, session);
\r
950 mutex_unlock(&pservice->lock);
\r
954 mutex_lock(&pservice->lock);
\r
955 reg = list_entry(session->done.next, vpu_reg, session_link);
\r
956 return_reg(pservice, reg, (u32 __user *)req.req);
\r
957 mutex_unlock(&pservice->lock);
\r
961 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);
\r
969 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)
\r
971 int ret = -EINVAL, i = 0;
\r
972 volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
\r
976 /// temporary, hevc driver test.
\r
977 if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {
\r
978 p->hw_info = &vpu_hw_set[2];
\r
983 enc_id = (enc_id >> 16) & 0xFFFF;
\r
984 pr_info("checking hw id %x\n", enc_id);
\r
986 for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
\r
987 if (enc_id == vpu_hw_set[i].hw_id) {
\r
988 p->hw_info = &vpu_hw_set[i];
\r
993 iounmap((void *)tmp);
\r
997 static int vpu_service_open(struct inode *inode, struct file *filp)
\r
999 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
\r
1000 vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
\r
1001 if (NULL == session) {
\r
1002 pr_err("error: unable to allocate memory for vpu_session.");
\r
1006 session->type = VPU_TYPE_BUTT;
\r
1007 session->pid = current->pid;
\r
1008 INIT_LIST_HEAD(&session->waiting);
\r
1009 INIT_LIST_HEAD(&session->running);
\r
1010 INIT_LIST_HEAD(&session->done);
\r
1011 INIT_LIST_HEAD(&session->list_session);
\r
1012 init_waitqueue_head(&session->wait);
\r
1013 atomic_set(&session->task_running, 0);
\r
1014 mutex_lock(&pservice->lock);
\r
1015 list_add_tail(&session->list_session, &pservice->session);
\r
1016 filp->private_data = (void *)session;
\r
1017 mutex_unlock(&pservice->lock);
\r
1019 pr_debug("dev opened\n");
\r
1020 return nonseekable_open(inode, filp);
\r
1023 static int vpu_service_release(struct inode *inode, struct file *filp)
\r
1025 struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);
\r
1027 vpu_session *session = (vpu_session *)filp->private_data;
\r
1028 if (NULL == session)
\r
1031 task_running = atomic_read(&session->task_running);
\r
1032 if (task_running) {
\r
1033 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
\r
1036 wake_up(&session->wait);
\r
1038 mutex_lock(&pservice->lock);
\r
1039 /* remove this filp from the asynchronusly notified filp's */
\r
1040 list_del_init(&session->list_session);
\r
1041 vpu_service_session_clear(pservice, session);
\r
1043 filp->private_data = NULL;
\r
1044 mutex_unlock(&pservice->lock);
\r
1046 pr_debug("dev closed\n");
\r
1050 static const struct file_operations vpu_service_fops = {
\r
1051 .unlocked_ioctl = vpu_service_ioctl,
\r
1052 .open = vpu_service_open,
\r
1053 .release = vpu_service_release,
\r
1054 //.fasync = vpu_service_fasync,
\r
1057 static irqreturn_t vdpu_irq(int irq, void *dev_id);
\r
1058 static irqreturn_t vdpu_isr(int irq, void *dev_id);
\r
1059 static irqreturn_t vepu_irq(int irq, void *dev_id);
\r
1060 static irqreturn_t vepu_isr(int irq, void *dev_id);
\r
1061 static void get_hw_info(struct vpu_service_info *pservice);
\r
1063 #if HEVC_SIM_ENABLE
\r
1064 static void simulate_work(struct work_struct *work_s)
\r
1066 struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
\r
1067 struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);
\r
1068 vpu_device *dev = &pservice->dec_dev;
\r
1070 if (!list_empty(&pservice->running)) {
\r
1071 atomic_add(1, &dev->irq_count_codec);
\r
1072 vdpu_isr(0, (void*)pservice);
\r
1074 //simulate_start(pservice);
\r
1075 pr_err("empty running queue\n");
\r
1079 static void simulate_init(struct vpu_service_info *pservice)
\r
1081 INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);
\r
1084 static void simulate_start(struct vpu_service_info *pservice)
\r
1086 cancel_delayed_work_sync(&pservice->power_off_work);
\r
1087 queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);
\r
1091 #if HEVC_TEST_ENABLE
\r
1092 static int hevc_test_case0(vpu_service_info *pservice);
\r
1094 static int vcodec_probe(struct platform_device *pdev)
\r
1097 struct resource *res = NULL;
\r
1098 struct device *dev = &pdev->dev;
\r
1099 void __iomem *regs = NULL;
\r
1100 struct device_node *np = pdev->dev.of_node;
\r
1101 struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
\r
1102 char *prop = (char*)dev_name(dev);
\r
1104 pr_info("probe device %s\n", dev_name(dev));
\r
1106 of_property_read_string(np, "name", (const char**)&prop);
\r
1107 dev_set_name(dev, prop);
\r
1109 wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
\r
1110 INIT_LIST_HEAD(&pservice->waiting);
\r
1111 INIT_LIST_HEAD(&pservice->running);
\r
1112 INIT_LIST_HEAD(&pservice->done);
\r
1113 INIT_LIST_HEAD(&pservice->session);
\r
1114 mutex_init(&pservice->lock);
\r
1115 pservice->reg_codec = NULL;
\r
1116 pservice->reg_pproc = NULL;
\r
1117 atomic_set(&pservice->total_running, 0);
\r
1118 pservice->enabled = false;
\r
1120 pservice->dev = dev;
\r
1122 vpu_get_clk(pservice);
\r
1124 INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
\r
1126 vpu_service_power_on(pservice);
\r
1128 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1130 regs = devm_ioremap_resource(pservice->dev, res);
\r
1131 if (IS_ERR(regs)) {
\r
1132 ret = PTR_ERR(regs);
\r
1136 ret = vpu_service_check_hw(pservice, res->start);
\r
1138 pr_err("error: hw info check faild\n");
\r
1142 /// define regs address.
\r
1143 pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;
\r
1144 pservice->dec_dev.iosize = pservice->hw_info->dec_io_size;
\r
1146 pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);
\r
1148 pservice->reg_size = pservice->dec_dev.iosize;
\r
1150 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1151 pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;
\r
1152 pservice->enc_dev.iosize = pservice->hw_info->enc_io_size;
\r
1154 pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;
\r
1156 pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);
\r
1158 pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
\r
1159 if (pservice->irq_enc < 0) {
\r
1160 dev_err(pservice->dev, "cannot find IRQ encoder\n");
\r
1165 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);
\r
1167 dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);
\r
1172 pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
\r
1173 if (pservice->irq_dec < 0) {
\r
1174 dev_err(pservice->dev, "cannot find IRQ decoder\n");
\r
1179 /* get the IRQ line */
\r
1180 ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);
\r
1182 dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);
\r
1186 atomic_set(&pservice->dec_dev.irq_count_codec, 0);
\r
1187 atomic_set(&pservice->dec_dev.irq_count_pp, 0);
\r
1188 atomic_set(&pservice->enc_dev.irq_count_codec, 0);
\r
1189 atomic_set(&pservice->enc_dev.irq_count_pp, 0);
\r
1192 ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));
\r
1194 dev_err(dev, "alloc dev_t failed\n");
\r
1198 cdev_init(&pservice->cdev, &vpu_service_fops);
\r
1200 pservice->cdev.owner = THIS_MODULE;
\r
1201 pservice->cdev.ops = &vpu_service_fops;
\r
1203 ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);
\r
1206 dev_err(dev, "add dev_t failed\n");
\r
1210 pservice->cls = class_create(THIS_MODULE, dev_name(dev));
\r
1212 if (IS_ERR(pservice->cls)) {
\r
1213 ret = PTR_ERR(pservice->cls);
\r
1214 dev_err(dev, "class_create err:%d\n", ret);
\r
1218 pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));
\r
1220 platform_set_drvdata(pdev, pservice);
\r
1222 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1223 get_hw_info(pservice);
\r
1226 #ifdef CONFIG_DEBUG_FS
\r
1227 pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);
\r
1229 if (pservice->debugfs_dir == NULL) {
\r
1230 pr_err("create debugfs dir %s failed\n", dev_name(dev));
\r
1233 pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,
\r
1234 pservice->debugfs_dir, pservice,
\r
1235 &debug_vcodec_fops);
\r
1238 vpu_service_power_off(pservice);
\r
1239 pr_info("init success\n");
\r
1241 #if HEVC_SIM_ENABLE
\r
1242 if (pservice->hw_info->hw_id == HEVC_ID) {
\r
1243 simulate_init(pservice);
\r
1247 #if HEVC_TEST_ENABLE
\r
1248 hevc_test_case0(pservice);
\r
1254 pr_info("init failed\n");
\r
1255 vpu_service_power_off(pservice);
\r
1256 vpu_put_clk(pservice);
\r
1257 wake_lock_destroy(&pservice->wake_lock);
\r
1261 devm_ioremap_release(&pdev->dev, res);
\r
1263 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
\r
1266 if (pservice->irq_enc > 0) {
\r
1267 free_irq(pservice->irq_enc, (void *)pservice);
\r
1270 if (pservice->irq_dec > 0) {
\r
1271 free_irq(pservice->irq_dec, (void *)pservice);
\r
1274 if (pservice->child_dev) {
\r
1275 device_destroy(pservice->cls, pservice->dev_t);
\r
1276 cdev_del(&pservice->cdev);
\r
1277 unregister_chrdev_region(pservice->dev_t, 1);
\r
1280 if (pservice->cls) {
\r
1281 class_destroy(pservice->cls);
\r
1287 static int vcodec_remove(struct platform_device *pdev)
\r
1289 struct vpu_service_info *pservice = platform_get_drvdata(pdev);
\r
1290 struct resource *res;
\r
1292 device_destroy(pservice->cls, pservice->dev_t);
\r
1293 class_destroy(pservice->cls);
\r
1294 cdev_del(&pservice->cdev);
\r
1295 unregister_chrdev_region(pservice->dev_t, 1);
\r
1297 free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);
\r
1298 free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);
\r
1299 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1300 devm_ioremap_release(&pdev->dev, res);
\r
1301 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
\r
1302 vpu_put_clk(pservice);
\r
1303 wake_lock_destroy(&pservice->wake_lock);
\r
1305 #ifdef CONFIG_DEBUG_FS
\r
1306 if (pservice->debugfs_file_regs) {
\r
1307 debugfs_remove(pservice->debugfs_file_regs);
\r
1310 if (pservice->debugfs_dir) {
\r
1311 debugfs_remove(pservice->debugfs_dir);
\r
1318 #if defined(CONFIG_OF)
\r
1319 static const struct of_device_id vcodec_service_dt_ids[] = {
\r
1320 //{.compatible = "vpu_service",},
\r
1321 {.compatible = "rockchip,hevc_service",},
\r
1326 static struct platform_driver vcodec_driver = {
\r
1327 .probe = vcodec_probe,
\r
1328 .remove = vcodec_remove,
\r
1331 .owner = THIS_MODULE,
\r
1332 #if defined(CONFIG_OF)
\r
1333 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
\r
1338 static void get_hw_info(struct vpu_service_info *pservice)
\r
1340 VPUHwDecConfig_t *dec = &pservice->dec_config;
\r
1341 VPUHwEncConfig_t *enc = &pservice->enc_config;
\r
1342 u32 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];
\r
1343 u32 asicID = pservice->dec_dev.hwregs[0];
\r
1345 dec->h264Support = (configReg >> DWL_H264_E) & 0x3U;
\r
1346 dec->jpegSupport = (configReg >> DWL_JPEG_E) & 0x01U;
\r
1347 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
\r
1348 dec->jpegSupport = JPEG_PROGRESSIVE;
\r
1349 dec->mpeg4Support = (configReg >> DWL_MPEG4_E) & 0x3U;
\r
1350 dec->vc1Support = (configReg >> DWL_VC1_E) & 0x3U;
\r
1351 dec->mpeg2Support = (configReg >> DWL_MPEG2_E) & 0x01U;
\r
1352 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
\r
1353 dec->refBufSupport = (configReg >> DWL_REF_BUFF_E) & 0x01U;
\r
1354 dec->vp6Support = (configReg >> DWL_VP6_E) & 0x01U;
\r
1355 #if !defined(CONFIG_ARCH_RK319X)
\r
1356 /// invalidate max decode picture width value in rk319x vpu
\r
1357 dec->maxDecPicWidth = configReg & 0x07FFU;
\r
1359 dec->maxDecPicWidth = 3840;
\r
1362 /* 2nd Config register */
\r
1363 configReg = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];
\r
1364 if (dec->refBufSupport) {
\r
1365 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
\r
1366 dec->refBufSupport |= 2;
\r
1367 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
\r
1368 dec->refBufSupport |= 4;
\r
1370 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
\r
1371 dec->vp7Support = (configReg >> DWL_VP7_E) & 0x01U;
\r
1372 dec->vp8Support = (configReg >> DWL_VP8_E) & 0x01U;
\r
1373 dec->avsSupport = (configReg >> DWL_AVS_E) & 0x01U;
\r
1375 /* JPEG xtensions */
\r
1376 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
\r
1377 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
\r
1379 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
\r
1382 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {
\r
1383 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
\r
1385 dec->rvSupport = RV_NOT_SUPPORTED;
\r
1388 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
\r
1390 if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {
\r
1391 dec->refBufSupport |= 8; /* enable HW support for offset */
\r
1394 #if !defined(CONFIG_ARCH_RK319X)
\r
1395 /// invalidate fuse register value in rk319x vpu
\r
1397 VPUHwFuseStatus_t hwFuseSts;
\r
1398 /* Decoder fuse configuration */
\r
1399 u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
\r
1401 hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;
\r
1402 hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;
\r
1403 hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;
\r
1404 hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;
\r
1405 hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;
\r
1406 hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;
\r
1407 hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;
\r
1408 hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;
\r
1409 hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;
\r
1410 hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;
\r
1411 hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;
\r
1412 hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;
\r
1413 hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;
\r
1414 hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;
\r
1416 /* check max. decoder output width */
\r
1418 if (fuseReg & 0x8000U)
\r
1419 hwFuseSts.maxDecPicWidthFuse = 1920;
\r
1420 else if (fuseReg & 0x4000U)
\r
1421 hwFuseSts.maxDecPicWidthFuse = 1280;
\r
1422 else if (fuseReg & 0x2000U)
\r
1423 hwFuseSts.maxDecPicWidthFuse = 720;
\r
1424 else if (fuseReg & 0x1000U)
\r
1425 hwFuseSts.maxDecPicWidthFuse = 352;
\r
1426 else /* remove warning */
\r
1427 hwFuseSts.maxDecPicWidthFuse = 352;
\r
1429 hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;
\r
1431 /* Pp configuration */
\r
1432 configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];
\r
1434 if ((configReg >> DWL_PP_E) & 0x01U) {
\r
1435 dec->ppSupport = 1;
\r
1436 dec->maxPpOutPicWidth = configReg & 0x07FFU;
\r
1437 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */
\r
1438 dec->ppConfig = configReg;
\r
1440 dec->ppSupport = 0;
\r
1441 dec->maxPpOutPicWidth = 0;
\r
1442 dec->ppConfig = 0;
\r
1445 /* check the HW versio */
\r
1446 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {
\r
1447 /* Pp configuration */
\r
1448 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];
\r
1450 if ((configReg >> DWL_PP_E) & 0x01U) {
\r
1451 /* Pp fuse configuration */
\r
1452 u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];
\r
1454 if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {
\r
1455 hwFuseSts.ppSupportFuse = 1;
\r
1456 /* check max. pp output width */
\r
1457 if (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;
\r
1458 else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;
\r
1459 else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;
\r
1460 else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;
\r
1461 else hwFuseSts.maxPpOutPicWidthFuse = 352;
\r
1462 hwFuseSts.ppConfigFuse = fuseRegPp;
\r
1464 hwFuseSts.ppSupportFuse = 0;
\r
1465 hwFuseSts.maxPpOutPicWidthFuse = 0;
\r
1466 hwFuseSts.ppConfigFuse = 0;
\r
1469 hwFuseSts.ppSupportFuse = 0;
\r
1470 hwFuseSts.maxPpOutPicWidthFuse = 0;
\r
1471 hwFuseSts.ppConfigFuse = 0;
\r
1474 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)
\r
1475 dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;
\r
1476 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)
\r
1477 dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;
\r
1478 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;
\r
1479 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;
\r
1480 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;
\r
1481 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;
\r
1482 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)
\r
1483 dec->jpegSupport = JPEG_BASELINE;
\r
1484 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;
\r
1485 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;
\r
1486 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;
\r
1487 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;
\r
1488 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;
\r
1489 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;
\r
1491 /* check the pp config vs fuse status */
\r
1492 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {
\r
1493 u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);
\r
1494 u32 alphaBlend = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);
\r
1495 u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);
\r
1496 u32 alphaBlendFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);
\r
1498 if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;
\r
1499 if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;
\r
1501 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;
\r
1502 if (!hwFuseSts.refBufSupportFuse) dec->refBufSupport = REF_BUF_NOT_SUPPORTED;
\r
1503 if (!hwFuseSts.rvSupportFuse) dec->rvSupport = RV_NOT_SUPPORTED;
\r
1504 if (!hwFuseSts.avsSupportFuse) dec->avsSupport = AVS_NOT_SUPPORTED;
\r
1505 if (!hwFuseSts.mvcSupportFuse) dec->mvcSupport = MVC_NOT_SUPPORTED;
\r
1509 configReg = pservice->enc_dev.hwregs[63];
\r
1510 enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
\r
1511 enc->h264Enabled = (configReg >> 27) & 1;
\r
1512 enc->mpeg4Enabled = (configReg >> 26) & 1;
\r
1513 enc->jpegEnabled = (configReg >> 25) & 1;
\r
1514 enc->vsEnabled = (configReg >> 24) & 1;
\r
1515 enc->rgbEnabled = (configReg >> 28) & 1;
\r
1516 //enc->busType = (configReg >> 20) & 15;
\r
1517 //enc->synthesisLanguage = (configReg >> 16) & 15;
\r
1518 //enc->busWidth = (configReg >> 12) & 15;
\r
1519 enc->reg_size = pservice->reg_size;
\r
1520 enc->reserv[0] = enc->reserv[1] = 0;
\r
1522 pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();
\r
1523 if (pservice->auto_freq) {
\r
1524 printk("vpu_service set to auto frequency mode\n");
\r
1525 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
\r
1527 pservice->bug_dec_addr = cpu_is_rk30xx();
\r
1528 //printk("cpu 3066b bug %d\n", service.bug_dec_addr);
\r
1531 static irqreturn_t vdpu_irq(int irq, void *dev_id)
\r
1533 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1534 vpu_device *dev = &pservice->dec_dev;
\r
1535 u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1537 pr_debug("dec_irq\n");
\r
1539 if (irq_status & DEC_INTERRUPT_BIT) {
\r
1540 pr_debug("dec_isr dec %x\n", irq_status);
\r
1541 if ((irq_status & 0x40001) == 0x40001)
\r
1544 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1545 } while ((irq_status & 0x40001) == 0x40001);
\r
1548 /* clear dec IRQ */
\r
1549 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1550 writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1552 /*writel(irq_status
\r
1553 & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)),
\r
1554 dev->hwregs + DEC_INTERRUPT_REGISTER);*/
\r
1556 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
\r
1558 atomic_add(1, &dev->irq_count_codec);
\r
1561 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1562 irq_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
\r
1563 if (irq_status & PP_INTERRUPT_BIT) {
\r
1564 pr_debug("vdpu_isr pp %x\n", irq_status);
\r
1565 /* clear pp IRQ */
\r
1566 writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
\r
1567 atomic_add(1, &dev->irq_count_pp);
\r
1571 pservice->irq_status = irq_status;
\r
1573 return IRQ_WAKE_THREAD;
\r
1576 static irqreturn_t vdpu_isr(int irq, void *dev_id)
\r
1578 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1579 vpu_device *dev = &pservice->dec_dev;
\r
1581 mutex_lock(&pservice->lock);
\r
1582 if (atomic_read(&dev->irq_count_codec)) {
\r
1583 #if VPU_SERVICE_SHOW_TIME
\r
1584 do_gettimeofday(&dec_end);
\r
1585 pr_info("dec task: %ld ms\n",
\r
1586 (dec_end.tv_sec - dec_start.tv_sec) * 1000 +
\r
1587 (dec_end.tv_usec - dec_start.tv_usec) / 1000);
\r
1589 atomic_sub(1, &dev->irq_count_codec);
\r
1590 if (NULL == pservice->reg_codec) {
\r
1591 pr_err("error: dec isr with no task waiting\n");
\r
1593 reg_from_run_to_done(pservice, pservice->reg_codec);
\r
1597 if (atomic_read(&dev->irq_count_pp)) {
\r
1599 #if VPU_SERVICE_SHOW_TIME
\r
1600 do_gettimeofday(&pp_end);
\r
1601 printk("pp task: %ld ms\n",
\r
1602 (pp_end.tv_sec - pp_start.tv_sec) * 1000 +
\r
1603 (pp_end.tv_usec - pp_start.tv_usec) / 1000);
\r
1606 atomic_sub(1, &dev->irq_count_pp);
\r
1607 if (NULL == pservice->reg_pproc) {
\r
1608 pr_err("error: pp isr with no task waiting\n");
\r
1610 reg_from_run_to_done(pservice, pservice->reg_pproc);
\r
1613 try_set_reg(pservice);
\r
1614 mutex_unlock(&pservice->lock);
\r
1615 return IRQ_HANDLED;
\r
1618 static irqreturn_t vepu_irq(int irq, void *dev_id)
\r
1620 //struct vpu_device *dev = (struct vpu_device *) dev_id;
\r
1621 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1622 vpu_device *dev = &pservice->enc_dev;
\r
1623 u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
\r
1625 pr_debug("vepu_irq irq status %x\n", irq_status);
\r
1627 #if VPU_SERVICE_SHOW_TIME
\r
1628 do_gettimeofday(&enc_end);
\r
1629 pr_info("enc task: %ld ms\n",
\r
1630 (enc_end.tv_sec - enc_start.tv_sec) * 1000 +
\r
1631 (enc_end.tv_usec - enc_start.tv_usec) / 1000);
\r
1634 if (likely(irq_status & ENC_INTERRUPT_BIT)) {
\r
1635 /* clear enc IRQ */
\r
1636 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
\r
1637 atomic_add(1, &dev->irq_count_codec);
\r
1640 return IRQ_WAKE_THREAD;
\r
1643 static irqreturn_t vepu_isr(int irq, void *dev_id)
\r
1645 //struct vpu_device *dev = (struct vpu_device *) dev_id;
\r
1646 struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;
\r
1647 vpu_device *dev = &pservice->enc_dev;
\r
1649 mutex_lock(&pservice->lock);
\r
1650 if (atomic_read(&dev->irq_count_codec)) {
\r
1651 atomic_sub(1, &dev->irq_count_codec);
\r
1652 if (NULL == pservice->reg_codec) {
\r
1653 pr_err("error: enc isr with no task waiting\n");
\r
1655 reg_from_run_to_done(pservice, pservice->reg_codec);
\r
1658 try_set_reg(pservice);
\r
1659 mutex_unlock(&pservice->lock);
\r
1660 return IRQ_HANDLED;
\r
1663 static int __init vcodec_service_init(void)
\r
1667 if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
\r
1668 pr_err("Platform device register failed (%d).\n", ret);
\r
1672 #ifdef CONFIG_DEBUG_FS
\r
1673 vcodec_debugfs_init();
\r
1679 static void __exit vcodec_service_exit(void)
\r
1681 #ifdef CONFIG_DEBUG_FS
\r
1682 vcodec_debugfs_exit();
\r
1685 platform_driver_unregister(&vcodec_driver);
\r
1688 module_init(vcodec_service_init);
\r
1689 module_exit(vcodec_service_exit);
\r
1691 #ifdef CONFIG_DEBUG_FS
\r
1692 #include <linux/seq_file.h>
\r
1694 static int vcodec_debugfs_init()
\r
1696 parent = debugfs_create_dir("vcodec", NULL);
\r
1703 static void vcodec_debugfs_exit()
\r
1705 debugfs_remove(parent);
\r
1708 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
\r
1710 return debugfs_create_dir(dirname, parent);
\r
1713 static int debug_vcodec_show(struct seq_file *s, void *unused)
\r
1715 struct vpu_service_info *pservice = s->private;
\r
1716 unsigned int i, n;
\r
1717 vpu_reg *reg, *reg_tmp;
\r
1718 vpu_session *session, *session_tmp;
\r
1720 mutex_lock(&pservice->lock);
\r
1721 vpu_service_power_on(pservice);
\r
1722 if (pservice->hw_info->hw_id != HEVC_ID) {
\r
1723 seq_printf(s, "\nENC Registers:\n");
\r
1724 n = pservice->enc_dev.iosize >> 2;
\r
1725 for (i = 0; i < n; i++) {
\r
1726 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));
\r
1729 seq_printf(s, "\nDEC Registers:\n");
\r
1730 n = pservice->dec_dev.iosize >> 2;
\r
1731 for (i = 0; i < n; i++) {
\r
1732 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
\r
1735 seq_printf(s, "\nvpu service status:\n");
\r
1736 list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
\r
1737 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
\r
1738 //seq_printf(s, "waiting reg set %d\n");
\r
1739 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
\r
1740 seq_printf(s, "waiting register set\n");
\r
1742 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
\r
1743 seq_printf(s, "running register set\n");
\r
1745 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
\r
1746 seq_printf(s, "done register set\n");
\r
1749 mutex_unlock(&pservice->lock);
\r
1754 static int debug_vcodec_open(struct inode *inode, struct file *file)
\r
1756 return single_open(file, debug_vcodec_show, inode->i_private);
\r
1761 #if HEVC_TEST_ENABLE
\r
1762 #include "hevc_test_inc/pps_00.h"
\r
1763 #include "hevc_test_inc/register_00.h"
\r
1764 #include "hevc_test_inc/rps_00.h"
\r
1765 #include "hevc_test_inc/scaling_list_00.h"
\r
1766 #include "hevc_test_inc/stream_00.h"
\r
1768 #include "hevc_test_inc/pps_01.h"
\r
1769 #include "hevc_test_inc/register_01.h"
\r
1770 #include "hevc_test_inc/rps_01.h"
\r
1771 #include "hevc_test_inc/scaling_list_01.h"
\r
1772 #include "hevc_test_inc/stream_01.h"
\r
1774 #include "hevc_test_inc/cabac.h"
\r
1776 #define TEST_CNT 2
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1777 static int hevc_test_case0(vpu_service_info *pservice)
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1779 vpu_session session;
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1781 unsigned long size = sizeof(register_00); // registers array length
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1785 u8 *pps_tbl[TEST_CNT];
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1786 u8 *register_tbl[TEST_CNT];
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1787 u8 *rps_tbl[TEST_CNT];
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1788 u8 *scaling_list_tbl[TEST_CNT];
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1789 u8 *stream_tbl[TEST_CNT];
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1791 int stream_size[2];
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1804 pps_tbl[0] = pps_00;
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1805 pps_tbl[1] = pps_01;
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1807 register_tbl[0] = register_00;
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1808 register_tbl[1] = register_01;
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1810 rps_tbl[0] = rps_00;
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1811 rps_tbl[1] = rps_01;
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1813 scaling_list_tbl[0] = scaling_list_00;
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1814 scaling_list_tbl[1] = scaling_list_01;
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1816 stream_tbl[0] = stream_00;
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1817 stream_tbl[1] = stream_01;
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1819 stream_size[0] = sizeof(stream_00);
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1820 stream_size[1] = sizeof(stream_01);
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1823 session.pid = current->pid;
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1824 session.type = VPU_DEC;
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1825 INIT_LIST_HEAD(&session.waiting);
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1826 INIT_LIST_HEAD(&session.running);
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1827 INIT_LIST_HEAD(&session.done);
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1828 INIT_LIST_HEAD(&session.list_session);
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1829 init_waitqueue_head(&session.wait);
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1830 atomic_set(&session.task_running, 0);
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1831 list_add_tail(&session.list_session, &pservice->session);
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1833 while (testidx < TEST_CNT) {
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1834 // create registers
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1835 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
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1836 if (NULL == reg) {
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1837 pr_err("error: kmalloc fail in reg_init\n");
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1841 if (size > pservice->reg_size) {
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1842 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
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1843 size = pservice->reg_size;
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1845 reg->session = &session;
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1846 reg->type = session.type;
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1848 reg->freq = VPU_FREQ_DEFAULT;
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1849 reg->reg = (unsigned long *)®[1];
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1850 INIT_LIST_HEAD(®->session_link);
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1851 INIT_LIST_HEAD(®->status_link);
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1853 pps = kmalloc(sizeof(pps_00), GFP_KERNEL);
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1854 yuv = kzalloc(256*256*3/2, GFP_KERNEL);
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1855 memcpy(pps, pps_tbl[testidx], sizeof(pps_00));
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1857 // TODO: stuff registers
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1858 memcpy(®->reg[0], register_tbl[testidx], sizeof(register_00));
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1860 // TODO: replace reigster address
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1861 phy_pps = virt_to_phys(pps);
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1862 phy_rps = virt_to_phys(rps_tbl[testidx]);
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1863 phy_scl = virt_to_phys(scaling_list_tbl[testidx]);
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1864 phy_str = virt_to_phys(stream_tbl[testidx]);
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1865 phy_yuv = virt_to_phys(yuv);
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1866 phy_cabac = virt_to_phys(Cabac_table);
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1868 for (i=0; i<64; i++) {
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1869 u32 scaling_offset;
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1872 scaling_offset = (u32)pps[i*80+74];
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1873 scaling_offset += (u32)pps[i*80+75] << 8;
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1874 scaling_offset += (u32)pps[i*80+76] << 16;
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1875 scaling_offset += (u32)pps[i*80+77] << 24;
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1877 tmp = phy_scl + scaling_offset;
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1879 pps[i*80+74] = tmp & 0xff;
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1880 pps[i*80+75] = (tmp >> 8) & 0xff;
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1881 pps[i*80+76] = (tmp >> 16) & 0xff;
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1882 pps[i*80+77] = (tmp >> 24) & 0xff;
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1885 dmac_flush_range(&pps[0], &pps[sizeof(pps_00) - 1]);
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1886 outer_flush_range(phy_pps, phy_pps + sizeof(pps_00) - 1);
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1888 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);
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1890 reg->reg[4] = phy_str;
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1891 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
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1892 reg->reg[6] = phy_cabac;
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1893 reg->reg[7] = phy_yuv;
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1894 reg->reg[42] = phy_pps;
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1895 reg->reg[43] = phy_rps;
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1897 mutex_lock(&pservice->lock);
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1898 list_add_tail(®->status_link, &pservice->waiting);
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1899 list_add_tail(®->session_link, &session.waiting);
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1900 mutex_unlock(&pservice->lock);
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1902 printk("%s %d %p\n", __func__, __LINE__, pservice);
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1905 try_set_reg(pservice);
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1907 // wait for result
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1908 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
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1909 if (!list_empty(&session.done)) {
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1911 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
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1915 if (unlikely(ret < 0)) {
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1916 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);
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1917 } else if (0 == ret) {
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1918 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
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1923 int task_running = atomic_read(&session.task_running);
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1925 mutex_lock(&pservice->lock);
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1926 vpu_service_dump(pservice);
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1927 if (task_running) {
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1928 atomic_set(&session.task_running, 0);
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1929 atomic_sub(task_running, &pservice->total_running);
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1930 printk("%d task is running but not return, reset hardware...", task_running);
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1931 vpu_reset(pservice);
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1934 vpu_service_session_clear(pservice, &session);
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1935 mutex_unlock(&pservice->lock);
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1937 printk("\nDEC Registers:\n");
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1938 n = pservice->dec_dev.iosize >> 2;
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1939 for (i=0; i<n; i++) {
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1940 printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));
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1943 pr_err("test index %d failed\n", testidx);
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1948 pr_info("test index %d success\n", testidx);
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1950 vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
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1952 for (i=0; i<68; i++) {
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1954 printk("%02d: ", i);
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1956 printk("%08x ", reg->reg[i]);
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1957 if ((i+1) % 4 == 0) {
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1965 reg_deinit(pservice, reg);
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