arch/arm/mach-rockchip/vcodec_service.c

   1 \r
   2 /* arch/arm/mach-rk29/vpu.c\r
   3  *\r
   4  * Copyright (C) 2010 ROCKCHIP, Inc.\r
   5  * author: chenhengming chm@rock-chips.com\r
   6  *\r
   7  * This software is licensed under the terms of the GNU General Public\r
   8  * License version 2, as published by the Free Software Foundation, and\r
   9  * may be copied, distributed, and modified under those terms.\r
  10  *\r
  11  * This program is distributed in the hope that it will be useful,\r
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14  * GNU General Public License for more details.\r
  15  *\r
  16  */\r
  17 \r
  18 #include <linux/clk.h>\r
  19 #include <linux/delay.h>\r
  20 #include <linux/init.h>\r
  21 #include <linux/interrupt.h>\r
  22 #include <linux/io.h>\r
  23 #include <linux/kernel.h>\r
  24 #include <linux/module.h>\r
  25 #include <linux/fs.h>\r
  26 #include <linux/ioport.h>\r
  27 #include <linux/miscdevice.h>\r
  28 #include <linux/mm.h>\r
  29 #include <linux/poll.h>\r
  30 #include <linux/platform_device.h>\r
  31 #include <linux/sched.h>\r
  32 #include <linux/slab.h>\r
  33 #include <linux/wakelock.h>\r
  34 #include <linux/cdev.h>\r
  35 #include <linux/of.h>\r
  36 #include <linux/rockchip/cpu.h>\r
  37 #include <linux/rockchip/cru.h>\r
  38 \r
  39 #include <asm/cacheflush.h>\r
  40 #include <asm/uaccess.h>\r
  41 \r
  42 #if defined(CONFIG_ION_ROCKCHIP)\r
  43 #include <linux/rockchip_ion.h>\r
  44 #endif\r
  45 \r
  46 #ifdef CONFIG_DEBUG_FS\r
  47 #include <linux/debugfs.h>\r
  48 #endif\r
  49 \r
  50 #if defined(CONFIG_ARCH_RK319X)\r
  51 #include <mach/grf.h>\r
  52 #endif\r
  53 \r
  54 #include "vcodec_service.h"\r
  55 \r
  56 #define HEVC_TEST_ENABLE    0\r
  57 #define HEVC_SIM_ENABLE         0\r
  58 \r
  59 typedef enum {\r
  60         VPU_DEC_ID_9190         = 0x6731,\r
  61         VPU_ID_8270             = 0x8270,\r
  62         VPU_ID_4831             = 0x4831,\r
  63     HEVC_ID         = 0x6867,\r
  64 } VPU_HW_ID;\r
  65 \r
  66 typedef enum {\r
  67         VPU_DEC_TYPE_9190       = 0,\r
  68         VPU_ENC_TYPE_8270       = 0x100,\r
  69         VPU_ENC_TYPE_4831       ,\r
  70 } VPU_HW_TYPE_E;\r
  71 \r
  72 typedef enum VPU_FREQ {\r
  73         VPU_FREQ_200M,\r
  74         VPU_FREQ_266M,\r
  75         VPU_FREQ_300M,\r
  76         VPU_FREQ_400M,\r
  77         VPU_FREQ_DEFAULT,\r
  78         VPU_FREQ_BUT,\r
  79 } VPU_FREQ;\r
  80 \r
  81 typedef struct {\r
  82         VPU_HW_ID               hw_id;\r
  83         unsigned long           hw_addr;\r
  84         unsigned long           enc_offset;\r
  85         unsigned long           enc_reg_num;\r
  86         unsigned long           enc_io_size;\r
  87         unsigned long           dec_offset;\r
  88         unsigned long           dec_reg_num;\r
  89         unsigned long           dec_io_size;\r
  90 } VPU_HW_INFO_E;\r
  91 \r
  92 #define VPU_SERVICE_SHOW_TIME                   0\r
  93 \r
  94 #if VPU_SERVICE_SHOW_TIME\r
  95 static struct timeval enc_start, enc_end;\r
  96 static struct timeval dec_start, dec_end;\r
  97 static struct timeval pp_start,  pp_end;\r
  98 #endif\r
  99 \r
 100 #define MHZ                                     (1000*1000)\r
 101 \r
 102 #define REG_NUM_9190_DEC                        (60)\r
 103 #define REG_NUM_9190_PP                         (41)\r
 104 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 105 \r
 106 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)\r
 107 \r
 108 #define REG_NUM_ENC_8270                        (96)\r
 109 #define REG_SIZE_ENC_8270                       (0x200)\r
 110 #define REG_NUM_ENC_4831                        (164)\r
 111 #define REG_SIZE_ENC_4831                       (0x400)\r
 112 \r
 113 #define REG_NUM_HEVC_DEC            (68)\r
 114 \r
 115 #define SIZE_REG(reg)                           ((reg)*4)\r
 116 \r
 117 static VPU_HW_INFO_E vpu_hw_set[] = {\r
 118         [0] = {\r
 119                 .hw_id          = VPU_ID_8270,\r
 120                 .hw_addr        = 0,\r
 121                 .enc_offset     = 0x0,\r
 122                 .enc_reg_num    = REG_NUM_ENC_8270,\r
 123                 .enc_io_size    = REG_NUM_ENC_8270 * 4,\r
 124                 .dec_offset     = REG_SIZE_ENC_8270,\r
 125                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 126                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 127         },\r
 128         [1] = {\r
 129                 .hw_id          = VPU_ID_4831,\r
 130                 .hw_addr        = 0,\r
 131                 .enc_offset     = 0x0,\r
 132                 .enc_reg_num    = REG_NUM_ENC_4831,\r
 133                 .enc_io_size    = REG_NUM_ENC_4831 * 4,\r
 134                 .dec_offset     = REG_SIZE_ENC_4831,\r
 135                 .dec_reg_num    = REG_NUM_9190_DEC_PP,\r
 136                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,\r
 137         },\r
 138     [2] = {\r
 139         .hw_id      = HEVC_ID,\r
 140         .hw_addr    = 0,\r
 141         .dec_offset = 0x0,\r
 142         .dec_reg_num    = REG_NUM_HEVC_DEC,\r
 143         .dec_io_size    = REG_NUM_HEVC_DEC * 4,\r
 144     },\r
 145 };\r
 146 \r
 147 \r
 148 #define DEC_INTERRUPT_REGISTER                  1\r
 149 #define PP_INTERRUPT_REGISTER                   60\r
 150 #define ENC_INTERRUPT_REGISTER                  1\r
 151 \r
 152 #define DEC_INTERRUPT_BIT                       0x100\r
 153 #define DEC_BUFFER_EMPTY_BIT                    0x4000\r
 154 #define PP_INTERRUPT_BIT                        0x100\r
 155 #define ENC_INTERRUPT_BIT                       0x1\r
 156 \r
 157 #define HEVC_DEC_INT_RAW_BIT        0x200\r
 158 #define HEVC_DEC_STR_ERROR_BIT      0x4000\r
 159 #define HEVC_DEC_BUS_ERROR_BIT      0x2000\r
 160 #define HEVC_DEC_BUFFER_EMPTY_BIT   0x10000\r
 161 \r
 162 #define VPU_REG_EN_ENC                          14\r
 163 #define VPU_REG_ENC_GATE                        2\r
 164 #define VPU_REG_ENC_GATE_BIT                    (1<<4)\r
 165 \r
 166 #define VPU_REG_EN_DEC                          1\r
 167 #define VPU_REG_DEC_GATE                        2\r
 168 #define VPU_REG_DEC_GATE_BIT                    (1<<10)\r
 169 #define VPU_REG_EN_PP                           0\r
 170 #define VPU_REG_PP_GATE                         1\r
 171 #define VPU_REG_PP_GATE_BIT                     (1<<8)\r
 172 #define VPU_REG_EN_DEC_PP                       1\r
 173 #define VPU_REG_DEC_PP_GATE                     61\r
 174 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)\r
 175 \r
 176 /**\r
 177  * struct for process session which connect to vpu\r
 178  *\r
 179  * @author ChenHengming (2011-5-3)\r
 180  */\r
 181 typedef struct vpu_session {\r
 182         VPU_CLIENT_TYPE         type;\r
 183         /* a linked list of data so we can access them for debugging */\r
 184         struct list_head        list_session;\r
 185         /* a linked list of register data waiting for process */\r
 186         struct list_head        waiting;\r
 187         /* a linked list of register data in processing */\r
 188         struct list_head        running;\r
 189         /* a linked list of register data processed */\r
 190         struct list_head        done;\r
 191         wait_queue_head_t       wait;\r
 192         pid_t                   pid;\r
 193         atomic_t                task_running;\r
 194 } vpu_session;\r
 195 \r
 196 /**\r
 197  * struct for process register set\r
 198  *\r
 199  * @author ChenHengming (2011-5-4)\r
 200  */\r
 201 typedef struct vpu_reg {\r
 202         VPU_CLIENT_TYPE         type;\r
 203         VPU_FREQ                freq;\r
 204         vpu_session             *session;\r
 205         struct list_head        session_link;           /* link to vpu service session */\r
 206         struct list_head        status_link;            /* link to register set list */\r
 207         unsigned long           size;\r
 208         unsigned long           *reg;\r
 209 } vpu_reg;\r
 210 \r
 211 typedef struct vpu_device {\r
 212         atomic_t                irq_count_codec;\r
 213         atomic_t                irq_count_pp;\r
 214         unsigned long           iobaseaddr;\r
 215         unsigned int            iosize;\r
 216         volatile u32            *hwregs;\r
 217 } vpu_device;\r
 218 \r
 219 enum vcodec_device_id {\r
 220         VCODEC_DEVICE_ID_VPU,\r
 221         VCODEC_DEVICE_ID_HEVC\r
 222 };\r
 223 \r
 224 typedef struct vpu_service_info {\r
 225         struct wake_lock        wake_lock;\r
 226         struct delayed_work     power_off_work;\r
 227         struct mutex            lock;\r
 228         struct list_head        waiting;                /* link to link_reg in struct vpu_reg */\r
 229         struct list_head        running;                /* link to link_reg in struct vpu_reg */\r
 230         struct list_head        done;                   /* link to link_reg in struct vpu_reg */\r
 231         struct list_head        session;                /* link to list_session in struct vpu_session */\r
 232         atomic_t                total_running;\r
 233         bool                    enabled;\r
 234         vpu_reg                 *reg_codec;\r
 235         vpu_reg                 *reg_pproc;\r
 236         vpu_reg                 *reg_resev;\r
 237         VPUHwDecConfig_t        dec_config;\r
 238         VPUHwEncConfig_t        enc_config;\r
 239         VPU_HW_INFO_E           *hw_info;\r
 240         unsigned long           reg_size;\r
 241         bool                    auto_freq;\r
 242         bool                    bug_dec_addr;\r
 243         atomic_t                freq_status;\r
 244 \r
 245     struct clk *aclk_vcodec;\r
 246     struct clk *hclk_vcodec;\r
 247     struct clk *clk_core;\r
 248     struct clk *clk_cabac;\r
 249 \r
 250     int irq_dec;\r
 251     int irq_enc;\r
 252 \r
 253     vpu_device enc_dev;\r
 254     vpu_device dec_dev;\r
 255 \r
 256     struct device   *dev;\r
 257 \r
 258     struct cdev     cdev;\r
 259     dev_t           dev_t;\r
 260     struct class    *cls;\r
 261     struct device   *child_dev;\r
 262 \r
 263     struct dentry   *debugfs_dir;\r
 264     struct dentry   *debugfs_file_regs;\r
 265 \r
 266     u32 irq_status;\r
 267 #if defined(CONFIG_ION_ROCKCHIP)        \r
 268         struct ion_client * ion_client;\r
 269 #endif  \r
 270 \r
 271         enum vcodec_device_id dev_id;\r
 272 \r
 273     struct delayed_work simulate_work;\r
 274 } vpu_service_info;\r
 275 \r
 276 typedef struct vpu_request\r
 277 {\r
 278         unsigned long   *req;\r
 279         unsigned long   size;\r
 280 } vpu_request;\r
 281 \r
 282 /// global variable\r
 283 //static struct clk *pd_video;\r
 284 static struct dentry *parent; // debugfs root directory for all device (vpu, hevc).\r
 285 \r
 286 #ifdef CONFIG_DEBUG_FS\r
 287 static int vcodec_debugfs_init(void);\r
 288 static void vcodec_debugfs_exit(void);\r
 289 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);\r
 290 static int debug_vcodec_open(struct inode *inode, struct file *file);\r
 291 \r
 292 static const struct file_operations debug_vcodec_fops = {\r
 293         .open = debug_vcodec_open,\r
 294         .read = seq_read,\r
 295         .llseek = seq_lseek,\r
 296         .release = single_release,\r
 297 };\r
 298 #endif\r
 299 \r
 300 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */\r
 301 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */\r
 302 \r
 303 #define VPU_SIMULATE_DELAY      msecs_to_jiffies(15)\r
 304 \r
 305 static void vpu_get_clk(struct vpu_service_info *pservice)\r
 306 {\r
 307         /*pd_video      = clk_get(NULL, "pd_video");\r
 308         if (IS_ERR(pd_video)) {\r
 309                 pr_err("failed on clk_get pd_video\n");\r
 310         }*/\r
 311 \r
 312         pservice->aclk_vcodec   = devm_clk_get(pservice->dev, "aclk_vcodec");\r
 313         if (IS_ERR(pservice->aclk_vcodec)) {\r
 314                 dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");\r
 315         }\r
 316 \r
 317         pservice->hclk_vcodec   = devm_clk_get(pservice->dev, "hclk_vcodec");\r
 318         if (IS_ERR(pservice->hclk_vcodec)) {\r
 319                 dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");\r
 320         }\r
 321 \r
 322         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC) {\r
 323                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");\r
 324                 if (IS_ERR(pservice->clk_core)) {\r
 325                         dev_err(pservice->dev, "failed on clk_get clk_core\n");\r
 326                 }\r
 327 \r
 328                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");\r
 329                 if (IS_ERR(pservice->clk_cabac)) {\r
 330                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");\r
 331                 }\r
 332         }\r
 333 }\r
 334 \r
 335 static void vpu_put_clk(struct vpu_service_info *pservice)\r
 336 {\r
 337     //clk_put(pd_video);\r
 338 \r
 339     if (pservice->aclk_vcodec) {\r
 340         devm_clk_put(pservice->dev, pservice->aclk_vcodec);\r
 341     }\r
 342 \r
 343     if (pservice->hclk_vcodec) {\r
 344         devm_clk_put(pservice->dev, pservice->hclk_vcodec);\r
 345     }\r
 346 \r
 347     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 348         if (pservice->clk_core) {\r
 349             devm_clk_put(pservice->dev, pservice->clk_core);\r
 350         }\r
 351         \r
 352         if (pservice->clk_cabac) {\r
 353             devm_clk_put(pservice->dev, pservice->clk_cabac);\r
 354         }\r
 355     }\r
 356 }\r
 357 \r
 358 static void vpu_reset(struct vpu_service_info *pservice)\r
 359 {\r
 360 #if defined(CONFIG_ARCH_RK29)\r
 361         clk_disable(aclk_ddr_vepu);\r
 362         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);\r
 363         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);\r
 364         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);\r
 365         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);\r
 366         mdelay(10);\r
 367         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);\r
 368         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);\r
 369         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);\r
 370         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);\r
 371         clk_enable(aclk_ddr_vepu);\r
 372 #elif defined(CONFIG_ARCH_RK30)\r
 373         pmu_set_idle_request(IDLE_REQ_VIDEO, true);\r
 374         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 375         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);\r
 376         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 377         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);\r
 378         mdelay(1);\r
 379         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);\r
 380         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 381         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);\r
 382         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 383         pmu_set_idle_request(IDLE_REQ_VIDEO, false);\r
 384 #endif\r
 385         pservice->reg_codec = NULL;\r
 386         pservice->reg_pproc = NULL;\r
 387         pservice->reg_resev = NULL;\r
 388 }\r
 389 \r
 390 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg);\r
 391 static void vpu_service_session_clear(struct vpu_service_info *pservice, vpu_session *session)\r
 392 {\r
 393         vpu_reg *reg, *n;\r
 394         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {\r
 395                 reg_deinit(pservice, reg);\r
 396         }\r
 397         list_for_each_entry_safe(reg, n, &session->running, session_link) {\r
 398                 reg_deinit(pservice, reg);\r
 399         }\r
 400         list_for_each_entry_safe(reg, n, &session->done, session_link) {\r
 401                 reg_deinit(pservice, reg);\r
 402         }\r
 403 }\r
 404 \r
 405 static void vpu_service_dump(struct vpu_service_info *pservice)\r
 406 {\r
 407         int running;\r
 408         vpu_reg *reg, *reg_tmp;\r
 409         vpu_session *session, *session_tmp;\r
 410 \r
 411         running = atomic_read(&pservice->total_running);\r
 412         printk("total_running %d\n", running);\r
 413 \r
 414         printk("reg_codec 0x%.8x\n", (unsigned int)pservice->reg_codec);\r
 415         printk("reg_pproc 0x%.8x\n", (unsigned int)pservice->reg_pproc);\r
 416         printk("reg_resev 0x%.8x\n", (unsigned int)pservice->reg_resev);\r
 417 \r
 418         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
 419                 printk("session pid %d type %d:\n", session->pid, session->type);\r
 420                 running = atomic_read(&session->task_running);\r
 421                 printk("task_running %d\n", running);\r
 422                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
 423                         printk("waiting register set 0x%.8x\n", (unsigned int)reg);\r
 424                 }\r
 425                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
 426                         printk("running register set 0x%.8x\n", (unsigned int)reg);\r
 427                 }\r
 428                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
 429                         printk("done    register set 0x%.8x\n", (unsigned int)reg);\r
 430                 }\r
 431         }\r
 432 }\r
 433 \r
 434 static void vpu_service_power_off(struct vpu_service_info *pservice)\r
 435 {\r
 436         int total_running;\r
 437         if (!pservice->enabled) {\r
 438                 return;\r
 439         }\r
 440 \r
 441         pservice->enabled = false;\r
 442         total_running = atomic_read(&pservice->total_running);\r
 443         if (total_running) {\r
 444                 pr_alert("alert: power off when %d task running!!\n", total_running);\r
 445                 mdelay(50);\r
 446                 pr_alert("alert: delay 50 ms for running task\n");\r
 447                 vpu_service_dump(pservice);\r
 448         }\r
 449 \r
 450         printk("vpu: power off...");\r
 451 #ifdef CONFIG_ARCH_RK29\r
 452         pmu_set_power_domain(PD_VCODEC, false);\r
 453 #else\r
 454         //clk_disable(pd_video);\r
 455 #endif\r
 456         udelay(10);\r
 457 #if 0\r
 458         clk_disable_unprepare(pservice->hclk_vcodec);\r
 459         clk_disable_unprepare(pservice->aclk_vcodec);\r
 460     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 461         clk_disable_unprepare(pservice->clk_core);\r
 462         clk_disable_unprepare(pservice->clk_cabac);\r
 463     }\r
 464 #endif\r
 465         wake_unlock(&pservice->wake_lock);\r
 466         printk("done\n");\r
 467 }\r
 468 \r
 469 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)\r
 470 {\r
 471         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);\r
 472 }\r
 473 \r
 474 static void vpu_power_off_work(struct work_struct *work_s)\r
 475 {\r
 476     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
 477     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);\r
 478 \r
 479         if (mutex_trylock(&pservice->lock)) {\r
 480                 vpu_service_power_off(pservice);\r
 481                 mutex_unlock(&pservice->lock);\r
 482         } else {\r
 483                 /* Come back later if the device is busy... */\r
 484                 vpu_queue_power_off_work(pservice);\r
 485         }\r
 486 }\r
 487 \r
 488 static void vpu_service_power_on(struct vpu_service_info *pservice)\r
 489 {\r
 490         static ktime_t last;\r
 491         ktime_t now = ktime_get();\r
 492         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {\r
 493                 cancel_delayed_work_sync(&pservice->power_off_work);\r
 494                 vpu_queue_power_off_work(pservice);\r
 495                 last = now;\r
 496         }\r
 497         if (pservice->enabled)\r
 498                 return ;\r
 499 \r
 500         pservice->enabled = true;\r
 501         printk("vpu: power on\n");\r
 502 \r
 503 #if 0\r
 504     clk_prepare_enable(pservice->aclk_vcodec);\r
 505         clk_prepare_enable(pservice->hclk_vcodec);\r
 506     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 507         clk_prepare_enable(pservice->clk_core);\r
 508         clk_prepare_enable(pservice->clk_cabac);\r
 509     }\r
 510 #endif\r
 511 \r
 512 #if defined(CONFIG_ARCH_RK319X)\r
 513     /// select aclk_vepu as vcodec clock source. \r
 514     #define BIT_VCODEC_SEL  (1<<7)\r
 515     writel_relaxed(readl_relaxed(RK319X_GRF_BASE + GRF_SOC_CON1) | (BIT_VCODEC_SEL) | (BIT_VCODEC_SEL << 16), RK319X_GRF_BASE + GRF_SOC_CON1);\r
 516 #endif\r
 517         udelay(10);\r
 518 #ifdef CONFIG_ARCH_RK29\r
 519         pmu_set_power_domain(PD_VCODEC, true);\r
 520 #else\r
 521         //clk_enable(pd_video);\r
 522 #endif\r
 523         udelay(10);\r
 524         wake_lock(&pservice->wake_lock);\r
 525 }\r
 526 \r
 527 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)\r
 528 {\r
 529         unsigned long type = (reg->reg[3] & 0xF0000000) >> 28;\r
 530         return ((type == 8) || (type == 4));\r
 531 }\r
 532 \r
 533 static inline bool reg_check_interlace(vpu_reg *reg)\r
 534 {\r
 535         unsigned long type = (reg->reg[3] & (1 << 23));\r
 536         return (type > 0);\r
 537 }\r
 538 \r
 539 #if defined(CONFIG_VCODEC_MMU)\r
 540 static u8 table_vpu_dec[] = {\r
 541         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 40, 41\r
 542 };\r
 543 \r
 544 static u8 table_vpu_enc[] = {\r
 545         5, 6, 7, 8, 9, 10, 11, 12, 13, 51\r
 546 };\r
 547 \r
 548 static u8 table_hevc_dec[1] = {\r
 549 \r
 550 };\r
 551 \r
 552 static int reg_address_translate(struct vpu_service_info *pservice, vpu_reg *reg)\r
 553 {\r
 554         VPU_HW_ID hw_id;\r
 555         int i;\r
 556 \r
 557         hw_id = pservice->hw_info->hw_id;\r
 558 \r
 559     if (hw_id == HEVC_ID) {\r
 560 \r
 561     } else {\r
 562         if (reg->type == VPU_DEC) {\r
 563             for (i=0; i<sizeof(table_vpu_dec); i++) {\r
 564                                 int usr_fd;\r
 565                                 struct ion_handle *hdl;\r
 566                                 ion_phys_addr_t phy_addr;\r
 567                                 size_t len;\r
 568                                 int offset;\r
 569 \r
 570 #if 0\r
 571                                 if (copy_from_user(&usr_fd, &reg->reg[table_vpu_dec[i]], sizeof(usr_fd)))\r
 572                                         return -EFAULT;\r
 573 #else\r
 574                                 usr_fd = reg->reg[table_vpu_dec[i]] & 0xFF;\r
 575                                 offset = reg->reg[table_vpu_dec[i]] >> 8;\r
 576 #endif\r
 577                 if (usr_fd != 0) {\r
 578 \r
 579                                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);\r
 580                     if (IS_ERR(hdl)) {\r
 581                                                 pr_err("import dma-buf from fd %d failed\n", usr_fd);\r
 582                                                 return ERR_PTR(hdl);\r
 583                     }\r
 584 \r
 585                                         ion_phys(pservice->ion_client, hdl, &phy_addr, &len);\r
 586 \r
 587                                         reg->reg[table_vpu_dec[i]] = phy_addr + offset;\r
 588 \r
 589                                         ion_free(pservice->ion_client, hdl);\r
 590                 }\r
 591             }\r
 592         } else if (reg->type == VPU_ENC) {\r
 593 \r
 594         }\r
 595         }\r
 596 \r
 597         return 0;\r
 598 }\r
 599 #endif\r
 600 \r
 601 static vpu_reg *reg_init(struct vpu_service_info *pservice, vpu_session *session, void __user *src, unsigned long size)\r
 602 {\r
 603         vpu_reg *reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
 604         if (NULL == reg) {\r
 605                 pr_err("error: kmalloc fail in reg_init\n");\r
 606                 return NULL;\r
 607         }\r
 608 \r
 609         if (size > pservice->reg_size) {\r
 610                 printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
 611                 size = pservice->reg_size;\r
 612         }\r
 613         reg->session = session;\r
 614         reg->type = session->type;\r
 615         reg->size = size;\r
 616         reg->freq = VPU_FREQ_DEFAULT;\r
 617         reg->reg = (unsigned long *)&reg[1];\r
 618         INIT_LIST_HEAD(&reg->session_link);\r
 619         INIT_LIST_HEAD(&reg->status_link);\r
 620 \r
 621         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {\r
 622                 pr_err("error: copy_from_user failed in reg_init\n");\r
 623                 kfree(reg);\r
 624                 return NULL;\r
 625         }\r
 626 \r
 627 #if defined(CONFIG_VCODEC_MMU)\r
 628     if (0 > reg_address_translate(pservice, reg)) {\r
 629                 pr_err("error: translate reg address failed\n");\r
 630                 kfree(reg);\r
 631                 return NULL;\r
 632     }\r
 633 #endif\r
 634 \r
 635         mutex_lock(&pservice->lock);\r
 636         list_add_tail(&reg->status_link, &pservice->waiting);\r
 637         list_add_tail(&reg->session_link, &session->waiting);\r
 638         mutex_unlock(&pservice->lock);\r
 639 \r
 640         if (pservice->auto_freq) {\r
 641                 if (!soc_is_rk2928g()) {\r
 642                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {\r
 643                                 if (reg_check_rmvb_wmv(reg)) {\r
 644                                         reg->freq = VPU_FREQ_200M;\r
 645                                 } else {\r
 646                                         if (reg_check_interlace(reg)) {\r
 647                                                 reg->freq = VPU_FREQ_400M;\r
 648                                         }\r
 649                                 }\r
 650                         }\r
 651                         if (reg->type == VPU_PP) {\r
 652                                 reg->freq = VPU_FREQ_400M;\r
 653                         }\r
 654                 }\r
 655         }\r
 656 \r
 657         return reg;\r
 658 }\r
 659 \r
 660 static void reg_deinit(struct vpu_service_info *pservice, vpu_reg *reg)\r
 661 {\r
 662         list_del_init(&reg->session_link);\r
 663         list_del_init(&reg->status_link);\r
 664         if (reg == pservice->reg_codec) pservice->reg_codec = NULL;\r
 665         if (reg == pservice->reg_pproc) pservice->reg_pproc = NULL;\r
 666         kfree(reg);\r
 667 }\r
 668 \r
 669 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)\r
 670 {\r
 671         list_del_init(&reg->status_link);\r
 672         list_add_tail(&reg->status_link, &pservice->running);\r
 673 \r
 674         list_del_init(&reg->session_link);\r
 675         list_add_tail(&reg->session_link, &reg->session->running);\r
 676 }\r
 677 \r
 678 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)\r
 679 {\r
 680         int i;\r
 681         u32 *dst = (u32 *)&reg->reg[0];\r
 682         for (i = 0; i < count; i++)\r
 683                 *dst++ = *src++;\r
 684 }\r
 685 \r
 686 static void reg_from_run_to_done(struct vpu_service_info *pservice, vpu_reg *reg)\r
 687 {\r
 688     int irq_reg = -1;\r
 689         list_del_init(&reg->status_link);\r
 690         list_add_tail(&reg->status_link, &pservice->done);\r
 691 \r
 692         list_del_init(&reg->session_link);\r
 693         list_add_tail(&reg->session_link, &reg->session->done);\r
 694 \r
 695         switch (reg->type) {\r
 696         case VPU_ENC : {\r
 697                 pservice->reg_codec = NULL;\r
 698                 reg_copy_from_hw(reg, pservice->enc_dev.hwregs, pservice->hw_info->enc_reg_num);\r
 699         irq_reg = ENC_INTERRUPT_REGISTER;\r
 700                 break;\r
 701         }\r
 702         case VPU_DEC : {\r
 703                 pservice->reg_codec = NULL;\r
 704                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC);\r
 705         irq_reg = DEC_INTERRUPT_REGISTER;\r
 706                 break;\r
 707         }\r
 708         case VPU_PP : {\r
 709                 pservice->reg_pproc = NULL;\r
 710                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);\r
 711                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 712                 break;\r
 713         }\r
 714         case VPU_DEC_PP : {\r
 715                 pservice->reg_codec = NULL;\r
 716                 pservice->reg_pproc = NULL;\r
 717                 reg_copy_from_hw(reg, pservice->dec_dev.hwregs, REG_NUM_9190_DEC_PP);\r
 718                 pservice->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;\r
 719                 break;\r
 720         }\r
 721         default : {\r
 722                 pr_err("error: copy reg from hw with unknown type %d\n", reg->type);\r
 723                 break;\r
 724         }\r
 725         }\r
 726 \r
 727     if (irq_reg != -1) {\r
 728         reg->reg[irq_reg] = pservice->irq_status;\r
 729     }\r
 730 \r
 731         atomic_sub(1, &reg->session->task_running);\r
 732         atomic_sub(1, &pservice->total_running);\r
 733         wake_up(&reg->session->wait);\r
 734 }\r
 735 \r
 736 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)\r
 737 {\r
 738         VPU_FREQ curr = atomic_read(&pservice->freq_status);\r
 739         if (curr == reg->freq) {\r
 740                 return ;\r
 741         }\r
 742         atomic_set(&pservice->freq_status, reg->freq);\r
 743         switch (reg->freq) {\r
 744         case VPU_FREQ_200M : {\r
 745                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);\r
 746                 //printk("default: 200M\n");\r
 747         } break;\r
 748         case VPU_FREQ_266M : {\r
 749                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);\r
 750                 //printk("default: 266M\n");\r
 751         } break;\r
 752         case VPU_FREQ_300M : {\r
 753                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 754                 //printk("default: 300M\n");\r
 755         } break;\r
 756         case VPU_FREQ_400M : {\r
 757                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 758                 //printk("default: 400M\n");\r
 759         } break;\r
 760         default : {\r
 761                 if (soc_is_rk2928g()) {\r
 762                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);\r
 763                 } else {\r
 764                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);\r
 765                 }\r
 766                 //printk("default: 300M\n");\r
 767         } break;\r
 768         }\r
 769 }\r
 770 \r
 771 #if HEVC_SIM_ENABLE\r
 772 static void simulate_start(struct vpu_service_info *pservice);\r
 773 #endif\r
 774 static void reg_copy_to_hw(struct vpu_service_info *pservice, vpu_reg *reg)\r
 775 {\r
 776         int i;\r
 777         u32 *src = (u32 *)&reg->reg[0];\r
 778         atomic_add(1, &pservice->total_running);\r
 779         atomic_add(1, &reg->session->task_running);\r
 780         if (pservice->auto_freq) {\r
 781                 vpu_service_set_freq(pservice, reg);\r
 782         }\r
 783         switch (reg->type) {\r
 784         case VPU_ENC : {\r
 785                 int enc_count = pservice->hw_info->enc_reg_num;\r
 786                 u32 *dst = (u32 *)pservice->enc_dev.hwregs;\r
 787 #if 0\r
 788                 if (pservice->bug_dec_addr) {\r
 789 #if !defined(CONFIG_ARCH_RK319X)\r
 790                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);\r
 791 #endif\r
 792                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);\r
 793                         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);\r
 794 #if !defined(CONFIG_ARCH_RK319X)\r
 795                         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);\r
 796 #endif\r
 797                 }\r
 798 #endif\r
 799                 pservice->reg_codec = reg;\r
 800 \r
 801                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;\r
 802 \r
 803                 for (i = 0; i < VPU_REG_EN_ENC; i++)\r
 804                         dst[i] = src[i];\r
 805 \r
 806                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)\r
 807                         dst[i] = src[i];\r
 808 \r
 809                 dsb();\r
 810 \r
 811                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;\r
 812                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];\r
 813 \r
 814 #if VPU_SERVICE_SHOW_TIME\r
 815                 do_gettimeofday(&enc_start);\r
 816 #endif\r
 817 \r
 818         } break;\r
 819         case VPU_DEC : {\r
 820                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 821 \r
 822                 pservice->reg_codec = reg;\r
 823 \r
 824         if (pservice->hw_info->hw_id != HEVC_ID) {\r
 825                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)\r
 826                                 dst[i] = src[i];\r
 827         } else {\r
 828             for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--) {\r
 829                                 dst[i] = src[i];\r
 830             }\r
 831                 }\r
 832 \r
 833                 dsb();\r
 834 \r
 835                 if (pservice->hw_info->hw_id != HEVC_ID) {\r
 836                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;\r
 837                         dst[VPU_REG_EN_DEC]   = src[VPU_REG_EN_DEC];\r
 838                 } else {\r
 839                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];\r
 840                 }\r
 841         dsb();\r
 842         dmb();\r
 843 \r
 844 #if VPU_SERVICE_SHOW_TIME\r
 845                 do_gettimeofday(&dec_start);\r
 846 #endif\r
 847 \r
 848         } break;\r
 849         case VPU_PP : {\r
 850                 u32 *dst = (u32 *)pservice->dec_dev.hwregs + PP_INTERRUPT_REGISTER;\r
 851                 pservice->reg_pproc = reg;\r
 852 \r
 853                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 854 \r
 855                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)\r
 856                         dst[i] = src[i];\r
 857 \r
 858                 dsb();\r
 859 \r
 860                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];\r
 861 \r
 862 #if VPU_SERVICE_SHOW_TIME\r
 863                 do_gettimeofday(&pp_start);\r
 864 #endif\r
 865 \r
 866         } break;\r
 867         case VPU_DEC_PP : {\r
 868                 u32 *dst = (u32 *)pservice->dec_dev.hwregs;\r
 869                 pservice->reg_codec = reg;\r
 870                 pservice->reg_pproc = reg;\r
 871 \r
 872                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)\r
 873                         dst[i] = src[i];\r
 874 \r
 875                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;\r
 876                 dsb();\r
 877 \r
 878                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;\r
 879                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;\r
 880                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];\r
 881 \r
 882 #if VPU_SERVICE_SHOW_TIME\r
 883                 do_gettimeofday(&dec_start);\r
 884 #endif\r
 885 \r
 886         } break;\r
 887         default : {\r
 888                 pr_err("error: unsupport session type %d", reg->type);\r
 889                 atomic_sub(1, &pservice->total_running);\r
 890                 atomic_sub(1, &reg->session->task_running);\r
 891                 break;\r
 892         }\r
 893         }\r
 894 \r
 895 #if HEVC_SIM_ENABLE\r
 896     if (pservice->hw_info->hw_id == HEVC_ID) {\r
 897         simulate_start(pservice);\r
 898     }\r
 899 #endif\r
 900 }\r
 901 \r
 902 static void try_set_reg(struct vpu_service_info *pservice)\r
 903 {\r
 904         // first get reg from reg list\r
 905         if (!list_empty(&pservice->waiting)) {\r
 906                 int can_set = 0;\r
 907                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);\r
 908 \r
 909                 vpu_service_power_on(pservice);\r
 910 \r
 911                 switch (reg->type) {\r
 912                 case VPU_ENC : {\r
 913                         if ((NULL == pservice->reg_codec) &&  (NULL == pservice->reg_pproc))\r
 914                                 can_set = 1;\r
 915                 } break;\r
 916                 case VPU_DEC : {\r
 917                         if (NULL == pservice->reg_codec)\r
 918                                 can_set = 1;\r
 919                         if (pservice->auto_freq && (NULL != pservice->reg_pproc)) {\r
 920                                 can_set = 0;\r
 921                         }\r
 922                 } break;\r
 923                 case VPU_PP : {\r
 924                         if (NULL == pservice->reg_codec) {\r
 925                                 if (NULL == pservice->reg_pproc)\r
 926                                         can_set = 1;\r
 927                         } else {\r
 928                                 if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))\r
 929                                         can_set = 1;\r
 930                                 // can not charge frequency when vpu is working\r
 931                                 if (pservice->auto_freq) {\r
 932                                         can_set = 0;\r
 933                                 }\r
 934                         }\r
 935                 } break;\r
 936                 case VPU_DEC_PP : {\r
 937                         if ((NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc))\r
 938                                 can_set = 1;\r
 939                         } break;\r
 940                 default : {\r
 941                         printk("undefined reg type %d\n", reg->type);\r
 942                 } break;\r
 943                 }\r
 944                 if (can_set) {\r
 945                         reg_from_wait_to_run(pservice, reg);\r
 946                         reg_copy_to_hw(pservice, reg);\r
 947                 }\r
 948         }\r
 949 }\r
 950 \r
 951 static int return_reg(struct vpu_service_info *pservice, vpu_reg *reg, u32 __user *dst)\r
 952 {\r
 953         int ret = 0;\r
 954         switch (reg->type) {\r
 955         case VPU_ENC : {\r
 956                 if (copy_to_user(dst, &reg->reg[0], pservice->hw_info->enc_io_size))\r
 957                         ret = -EFAULT;\r
 958                 break;\r
 959         }\r
 960         case VPU_DEC : {\r
 961                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC)))\r
 962                         ret = -EFAULT;\r
 963                 break;\r
 964         }\r
 965         case VPU_PP : {\r
 966                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))\r
 967                         ret = -EFAULT;\r
 968                 break;\r
 969         }\r
 970         case VPU_DEC_PP : {\r
 971                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))\r
 972                         ret = -EFAULT;\r
 973                 break;\r
 974         }\r
 975         default : {\r
 976                 ret = -EFAULT;\r
 977                 pr_err("error: copy reg to user with unknown type %d\n", reg->type);\r
 978                 break;\r
 979         }\r
 980         }\r
 981         reg_deinit(pservice, reg);\r
 982         return ret;\r
 983 }\r
 984 \r
 985 static long vpu_service_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)\r
 986 {\r
 987     struct vpu_service_info *pservice = container_of(filp->f_dentry->d_inode->i_cdev, struct vpu_service_info, cdev);\r
 988         vpu_session *session = (vpu_session *)filp->private_data;\r
 989         if (NULL == session) {\r
 990                 return -EINVAL;\r
 991         }\r
 992 \r
 993         switch (cmd) {\r
 994         case VPU_IOC_SET_CLIENT_TYPE : {\r
 995                 session->type = (VPU_CLIENT_TYPE)arg;\r
 996                 break;\r
 997         }\r
 998         case VPU_IOC_GET_HW_FUSE_STATUS : {\r
 999                 vpu_request req;\r
1000                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1001                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");\r
1002                         return -EFAULT;\r
1003                 } else {\r
1004                         if (VPU_ENC != session->type) {\r
1005                                 if (copy_to_user((void __user *)req.req, &pservice->dec_config, sizeof(VPUHwDecConfig_t))) {\r
1006                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1007                                         return -EFAULT;\r
1008                                 }\r
1009                         } else {\r
1010                                 if (copy_to_user((void __user *)req.req, &pservice->enc_config, sizeof(VPUHwEncConfig_t))) {\r
1011                                         pr_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n", session->type);\r
1012                                         return -EFAULT;\r
1013                                 }\r
1014                         }\r
1015                 }\r
1016 \r
1017                 break;\r
1018         }\r
1019         case VPU_IOC_SET_REG : {\r
1020                 vpu_request req;\r
1021                 vpu_reg *reg;\r
1022                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1023                         pr_err("error: VPU_IOC_SET_REG copy_from_user failed\n");\r
1024                         return -EFAULT;\r
1025                 }\r
1026                 reg = reg_init(pservice, session, (void __user *)req.req, req.size);\r
1027                 if (NULL == reg) {\r
1028                         return -EFAULT;\r
1029                 } else {\r
1030                         mutex_lock(&pservice->lock);\r
1031                         try_set_reg(pservice);\r
1032                         mutex_unlock(&pservice->lock);\r
1033                 }\r
1034 \r
1035                 break;\r
1036         }\r
1037         case VPU_IOC_GET_REG : {\r
1038                 vpu_request req;\r
1039                 vpu_reg *reg;\r
1040                 if (copy_from_user(&req, (void __user *)arg, sizeof(vpu_request))) {\r
1041                         pr_err("error: VPU_IOC_GET_REG copy_from_user failed\n");\r
1042                         return -EFAULT;\r
1043                 } else {\r
1044                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);\r
1045                         if (!list_empty(&session->done)) {\r
1046                                 if (ret < 0) {\r
1047                                         pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);\r
1048                                 }\r
1049                                 ret = 0;\r
1050                         } else {\r
1051                                 if (unlikely(ret < 0)) {\r
1052                                         pr_err("error: pid %d wait task ret %d\n", session->pid, ret);\r
1053                                 } else if (0 == ret) {\r
1054                                         pr_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
1055                                         ret = -ETIMEDOUT;\r
1056                                 }\r
1057                         }\r
1058                         if (ret < 0) {\r
1059                                 int task_running = atomic_read(&session->task_running);\r
1060                                 mutex_lock(&pservice->lock);\r
1061                                 vpu_service_dump(pservice);\r
1062                                 if (task_running) {\r
1063                                         atomic_set(&session->task_running, 0);\r
1064                                         atomic_sub(task_running, &pservice->total_running);\r
1065                                         printk("%d task is running but not return, reset hardware...", task_running);\r
1066                                         vpu_reset(pservice);\r
1067                                         printk("done\n");\r
1068                                 }\r
1069                                 vpu_service_session_clear(pservice, session);\r
1070                                 mutex_unlock(&pservice->lock);\r
1071                                 return ret;\r
1072                         }\r
1073                 }\r
1074                 mutex_lock(&pservice->lock);\r
1075                 reg = list_entry(session->done.next, vpu_reg, session_link);\r
1076                 return_reg(pservice, reg, (u32 __user *)req.req);\r
1077                 mutex_unlock(&pservice->lock);\r
1078                 break;\r
1079         }\r
1080         default : {\r
1081                 pr_err("error: unknow vpu service ioctl cmd %x\n", cmd);\r
1082                 break;\r
1083         }\r
1084         }\r
1085 \r
1086         return 0;\r
1087 }\r
1088 \r
1089 static int vpu_service_check_hw(vpu_service_info *p, unsigned long hw_addr)\r
1090 {\r
1091         int ret = -EINVAL, i = 0;\r
1092         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);\r
1093         u32 enc_id = *tmp;\r
1094 \r
1095 #if HEVC_SIM_ENABLE\r
1096     /// temporary, hevc driver test.\r
1097     if (strncmp(dev_name(p->dev), "hevc_service", strlen("hevc_service")) == 0) {\r
1098         p->hw_info = &vpu_hw_set[2];\r
1099         return 0;\r
1100     }\r
1101 #endif\r
1102 \r
1103         enc_id = (enc_id >> 16) & 0xFFFF;\r
1104         pr_info("checking hw id %x\n", enc_id);\r
1105     p->hw_info = NULL;\r
1106         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {\r
1107                 if (enc_id == vpu_hw_set[i].hw_id) {\r
1108                         p->hw_info = &vpu_hw_set[i];\r
1109                         ret = 0;\r
1110                         break;\r
1111                 }\r
1112         }\r
1113         iounmap((void *)tmp);\r
1114         return ret;\r
1115 }\r
1116 \r
1117 static int vpu_service_open(struct inode *inode, struct file *filp)\r
1118 {\r
1119     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1120         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);\r
1121         if (NULL == session) {\r
1122                 pr_err("error: unable to allocate memory for vpu_session.");\r
1123                 return -ENOMEM;\r
1124         }\r
1125 \r
1126         session->type   = VPU_TYPE_BUTT;\r
1127         session->pid    = current->pid;\r
1128         INIT_LIST_HEAD(&session->waiting);\r
1129         INIT_LIST_HEAD(&session->running);\r
1130         INIT_LIST_HEAD(&session->done);\r
1131         INIT_LIST_HEAD(&session->list_session);\r
1132         init_waitqueue_head(&session->wait);\r
1133         atomic_set(&session->task_running, 0);\r
1134         mutex_lock(&pservice->lock);\r
1135         list_add_tail(&session->list_session, &pservice->session);\r
1136         filp->private_data = (void *)session;\r
1137         mutex_unlock(&pservice->lock);\r
1138 \r
1139         pr_debug("dev opened\n");\r
1140         return nonseekable_open(inode, filp);\r
1141 }\r
1142 \r
1143 static int vpu_service_release(struct inode *inode, struct file *filp)\r
1144 {\r
1145     struct vpu_service_info *pservice = container_of(inode->i_cdev, struct vpu_service_info, cdev);\r
1146         int task_running;\r
1147         vpu_session *session = (vpu_session *)filp->private_data;\r
1148         if (NULL == session)\r
1149                 return -EINVAL;\r
1150 \r
1151         task_running = atomic_read(&session->task_running);\r
1152         if (task_running) {\r
1153                 pr_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);\r
1154                 msleep(50);\r
1155         }\r
1156         wake_up(&session->wait);\r
1157 \r
1158         mutex_lock(&pservice->lock);\r
1159         /* remove this filp from the asynchronusly notified filp's */\r
1160         list_del_init(&session->list_session);\r
1161         vpu_service_session_clear(pservice, session);\r
1162         kfree(session);\r
1163         filp->private_data = NULL;\r
1164         mutex_unlock(&pservice->lock);\r
1165 \r
1166     pr_debug("dev closed\n");\r
1167         return 0;\r
1168 }\r
1169 \r
1170 static const struct file_operations vpu_service_fops = {\r
1171         .unlocked_ioctl = vpu_service_ioctl,\r
1172         .open           = vpu_service_open,\r
1173         .release        = vpu_service_release,\r
1174         //.fasync       = vpu_service_fasync,\r
1175 };\r
1176 \r
1177 static irqreturn_t vdpu_irq(int irq, void *dev_id);\r
1178 static irqreturn_t vdpu_isr(int irq, void *dev_id);\r
1179 static irqreturn_t vepu_irq(int irq, void *dev_id);\r
1180 static irqreturn_t vepu_isr(int irq, void *dev_id);\r
1181 static void get_hw_info(struct vpu_service_info *pservice);\r
1182 \r
1183 #if HEVC_SIM_ENABLE\r
1184 static void simulate_work(struct work_struct *work_s)\r
1185 {\r
1186     struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);\r
1187     struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, simulate_work);\r
1188     vpu_device *dev = &pservice->dec_dev;\r
1189 \r
1190     if (!list_empty(&pservice->running)) {\r
1191         atomic_add(1, &dev->irq_count_codec);\r
1192         vdpu_isr(0, (void*)pservice);\r
1193     } else {\r
1194         //simulate_start(pservice);\r
1195         pr_err("empty running queue\n");\r
1196     }\r
1197 }\r
1198 \r
1199 static void simulate_init(struct vpu_service_info *pservice)\r
1200 {\r
1201     INIT_DELAYED_WORK(&pservice->simulate_work, simulate_work);\r
1202 }\r
1203 \r
1204 static void simulate_start(struct vpu_service_info *pservice)\r
1205 {\r
1206     cancel_delayed_work_sync(&pservice->power_off_work);\r
1207     queue_delayed_work(system_nrt_wq, &pservice->simulate_work, VPU_SIMULATE_DELAY);\r
1208 }\r
1209 #endif\r
1210 \r
1211 #if HEVC_TEST_ENABLE\r
1212 static int hevc_test_case0(vpu_service_info *pservice);\r
1213 #endif\r
1214 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1215 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1216 #endif\r
1217 static int vcodec_probe(struct platform_device *pdev)\r
1218 {\r
1219     int ret = 0;\r
1220     struct resource *res = NULL;\r
1221     struct device *dev = &pdev->dev;\r
1222     void __iomem *regs = NULL;\r
1223     struct device_node *np = pdev->dev.of_node;\r
1224     struct vpu_service_info *pservice = devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);\r
1225     char *prop = (char*)dev_name(dev);\r
1226 \r
1227     pr_info("probe device %s\n", dev_name(dev));\r
1228 \r
1229     of_property_read_string(np, "name", (const char**)&prop);\r
1230     dev_set_name(dev, prop);\r
1231 \r
1232         if (strcmp(dev_name(dev), "hevc_service") == 0) {\r
1233                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;\r
1234     } else if (strcmp(dev_name(dev), "vpu_service") == 0) {\r
1235                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;\r
1236     } else {\r
1237                 dev_err(dev, "Unknown device %s to probe\n", dev_name(dev));\r
1238                 return -1;\r
1239         }\r
1240 \r
1241     wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");\r
1242     INIT_LIST_HEAD(&pservice->waiting);\r
1243     INIT_LIST_HEAD(&pservice->running);\r
1244     INIT_LIST_HEAD(&pservice->done);\r
1245     INIT_LIST_HEAD(&pservice->session);\r
1246     mutex_init(&pservice->lock);\r
1247     pservice->reg_codec = NULL;\r
1248     pservice->reg_pproc = NULL;\r
1249     atomic_set(&pservice->total_running, 0);\r
1250     pservice->enabled = false;\r
1251 \r
1252     pservice->dev = dev;\r
1253 \r
1254     vpu_get_clk(pservice);\r
1255 \r
1256     INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);\r
1257 \r
1258     vpu_service_power_on(pservice);\r
1259 \r
1260     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1261 \r
1262     regs = devm_ioremap_resource(pservice->dev, res);\r
1263     if (IS_ERR(regs)) {\r
1264         ret = PTR_ERR(regs);\r
1265         goto err;\r
1266     }\r
1267 \r
1268     ret = vpu_service_check_hw(pservice, res->start);\r
1269     if (ret < 0) {\r
1270         pr_err("error: hw info check faild\n");\r
1271         goto err;\r
1272     }\r
1273 \r
1274     /// define regs address.\r
1275     pservice->dec_dev.iobaseaddr = res->start + pservice->hw_info->dec_offset;\r
1276     pservice->dec_dev.iosize     = pservice->hw_info->dec_io_size;\r
1277 \r
1278     pservice->dec_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->dec_offset);\r
1279 \r
1280     pservice->reg_size   = pservice->dec_dev.iosize;\r
1281 \r
1282     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1283         pservice->enc_dev.iobaseaddr = res->start + pservice->hw_info->enc_offset;\r
1284         pservice->enc_dev.iosize     = pservice->hw_info->enc_io_size;\r
1285 \r
1286         pservice->reg_size = pservice->reg_size > pservice->enc_dev.iosize ? pservice->reg_size : pservice->enc_dev.iosize;\r
1287 \r
1288         pservice->enc_dev.hwregs = (volatile u32 *)((u8 *)regs + pservice->hw_info->enc_offset);\r
1289 \r
1290         pservice->irq_enc = platform_get_irq_byname(pdev, "irq_enc");\r
1291         if (pservice->irq_enc < 0) {\r
1292             dev_err(pservice->dev, "cannot find IRQ encoder\n");\r
1293             ret = -ENXIO;\r
1294             goto err;\r
1295         }\r
1296 \r
1297         ret = devm_request_threaded_irq(pservice->dev, pservice->irq_enc, vepu_irq, vepu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1298         if (ret) {\r
1299             dev_err(pservice->dev, "error: can't request vepu irq %d\n", pservice->irq_enc);\r
1300             goto err;\r
1301         }\r
1302     }\r
1303 \r
1304     pservice->irq_dec = platform_get_irq_byname(pdev, "irq_dec");\r
1305     if (pservice->irq_dec < 0) {\r
1306         dev_err(pservice->dev, "cannot find IRQ decoder\n");\r
1307         ret = -ENXIO;\r
1308         goto err;\r
1309     }\r
1310 \r
1311     /* get the IRQ line */\r
1312     ret = devm_request_threaded_irq(pservice->dev, pservice->irq_dec, vdpu_irq, vdpu_isr, 0, dev_name(pservice->dev), (void *)pservice);\r
1313     if (ret) {\r
1314         dev_err(pservice->dev, "error: can't request vdpu irq %d\n", pservice->irq_dec);\r
1315         goto err;\r
1316     }\r
1317 \r
1318     atomic_set(&pservice->dec_dev.irq_count_codec, 0);\r
1319     atomic_set(&pservice->dec_dev.irq_count_pp, 0);\r
1320     atomic_set(&pservice->enc_dev.irq_count_codec, 0);\r
1321     atomic_set(&pservice->enc_dev.irq_count_pp, 0);\r
1322 \r
1323     /// create device\r
1324     ret = alloc_chrdev_region(&pservice->dev_t, 0, 1, dev_name(dev));\r
1325     if (ret) {\r
1326         dev_err(dev, "alloc dev_t failed\n");\r
1327         goto err;\r
1328     }\r
1329 \r
1330     cdev_init(&pservice->cdev, &vpu_service_fops);\r
1331 \r
1332     pservice->cdev.owner = THIS_MODULE;\r
1333     pservice->cdev.ops = &vpu_service_fops;\r
1334 \r
1335     ret = cdev_add(&pservice->cdev, pservice->dev_t, 1);\r
1336 \r
1337     if (ret) {\r
1338         dev_err(dev, "add dev_t failed\n");\r
1339         goto err;\r
1340     }\r
1341 \r
1342     pservice->cls = class_create(THIS_MODULE, dev_name(dev));\r
1343 \r
1344     if (IS_ERR(pservice->cls)) {\r
1345         ret = PTR_ERR(pservice->cls);\r
1346         dev_err(dev, "class_create err:%d\n", ret);\r
1347         goto err;\r
1348     }\r
1349 \r
1350     pservice->child_dev = device_create(pservice->cls, dev, pservice->dev_t, NULL, dev_name(dev));\r
1351 \r
1352     platform_set_drvdata(pdev, pservice);\r
1353 \r
1354     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1355         get_hw_info(pservice);\r
1356     }\r
1357 \r
1358 #ifdef CONFIG_DEBUG_FS\r
1359     pservice->debugfs_dir = vcodec_debugfs_create_device_dir((char*)dev_name(dev), parent);\r
1360     \r
1361     if (pservice->debugfs_dir == NULL) {\r
1362         pr_err("create debugfs dir %s failed\n", dev_name(dev));\r
1363     }\r
1364 \r
1365     pservice->debugfs_file_regs = debugfs_create_file("regs", 0664,\r
1366                     pservice->debugfs_dir, pservice,\r
1367                     &debug_vcodec_fops);\r
1368 #endif\r
1369 \r
1370     vpu_service_power_off(pservice);\r
1371     pr_info("init success\n");\r
1372 \r
1373 #if defined(CONFIG_VCODEC_MMU) & defined(CONFIG_ION_ROCKCHIP)\r
1374         pservice->ion_client = rockchip_ion_client_create("vpu");\r
1375         if (IS_ERR(pservice->ion_client)) {\r
1376                 dev_err(&pdev->dev, "failed to create ion client for vcodec");\r
1377                 return PTR_ERR(pservice->ion_client);\r
1378         } else {\r
1379                 dev_info(&pdev->dev, "vcodec ion client create success!\n");\r
1380         }\r
1381 #endif\r
1382 \r
1383 #if HEVC_SIM_ENABLE\r
1384     if (pservice->hw_info->hw_id == HEVC_ID) {\r
1385         simulate_init(pservice);\r
1386     }\r
1387 #endif\r
1388 \r
1389 #if HEVC_TEST_ENABLE\r
1390     hevc_test_case0(pservice);\r
1391 #endif\r
1392 \r
1393     return 0;\r
1394 \r
1395 err:\r
1396     pr_info("init failed\n");\r
1397     vpu_service_power_off(pservice);\r
1398     vpu_put_clk(pservice);\r
1399     wake_lock_destroy(&pservice->wake_lock);\r
1400 \r
1401     if (res) {\r
1402         if (regs) {\r
1403             devm_ioremap_release(&pdev->dev, res);\r
1404         }\r
1405         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1406     }\r
1407 \r
1408     if (pservice->irq_enc > 0) {\r
1409         free_irq(pservice->irq_enc, (void *)pservice);\r
1410     }\r
1411 \r
1412     if (pservice->irq_dec > 0) {\r
1413         free_irq(pservice->irq_dec, (void *)pservice);\r
1414     }\r
1415 \r
1416     if (pservice->child_dev) {\r
1417         device_destroy(pservice->cls, pservice->dev_t);\r
1418         cdev_del(&pservice->cdev);\r
1419         unregister_chrdev_region(pservice->dev_t, 1);\r
1420     }\r
1421 \r
1422     if (pservice->cls) {\r
1423         class_destroy(pservice->cls);\r
1424     }\r
1425 \r
1426     return ret;\r
1427 }\r
1428 \r
1429 static int vcodec_remove(struct platform_device *pdev)\r
1430 {\r
1431     struct vpu_service_info *pservice = platform_get_drvdata(pdev);\r
1432     struct resource *res;\r
1433 \r
1434     device_destroy(pservice->cls, pservice->dev_t);\r
1435     class_destroy(pservice->cls);\r
1436     cdev_del(&pservice->cdev);\r
1437     unregister_chrdev_region(pservice->dev_t, 1);\r
1438 \r
1439     free_irq(pservice->irq_enc, (void *)&pservice->enc_dev);\r
1440     free_irq(pservice->irq_dec, (void *)&pservice->dec_dev);\r
1441     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1442     devm_ioremap_release(&pdev->dev, res);\r
1443     devm_release_mem_region(&pdev->dev, res->start, resource_size(res));\r
1444     vpu_put_clk(pservice);\r
1445     wake_lock_destroy(&pservice->wake_lock);\r
1446     \r
1447 #ifdef CONFIG_DEBUG_FS\r
1448     if (pservice->debugfs_file_regs) {\r
1449         debugfs_remove(pservice->debugfs_file_regs);\r
1450     }\r
1451 \r
1452     if (pservice->debugfs_dir) {\r
1453         debugfs_remove(pservice->debugfs_dir);\r
1454     }\r
1455 #endif\r
1456 \r
1457     return 0;\r
1458 }\r
1459 \r
1460 #if defined(CONFIG_OF)\r
1461 static const struct of_device_id vcodec_service_dt_ids[] = {\r
1462         {.compatible = "vpu_service",},\r
1463         {.compatible = "rockchip,hevc_service",},\r
1464     {},\r
1465 };\r
1466 #endif\r
1467 \r
1468 static struct platform_driver vcodec_driver = {\r
1469         .probe     = vcodec_probe,\r
1470     .remove        = vcodec_remove,\r
1471     .driver = {\r
1472         .name = "vcodec",\r
1473         .owner = THIS_MODULE,\r
1474 #if defined(CONFIG_OF)\r
1475         .of_match_table = of_match_ptr(vcodec_service_dt_ids),\r
1476 #endif\r
1477         },\r
1478 };\r
1479 \r
1480 static void get_hw_info(struct vpu_service_info *pservice)\r
1481 {\r
1482         VPUHwDecConfig_t *dec = &pservice->dec_config;\r
1483         VPUHwEncConfig_t *enc = &pservice->enc_config;\r
1484         u32 configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG0];\r
1485         u32 asicID      = pservice->dec_dev.hwregs[0];\r
1486 \r
1487         dec->h264Support    = (configReg >> DWL_H264_E) & 0x3U;\r
1488         dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;\r
1489         if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))\r
1490                 dec->jpegSupport = JPEG_PROGRESSIVE;\r
1491         dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;\r
1492         dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;\r
1493         dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;\r
1494         dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;\r
1495         dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;\r
1496         dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;\r
1497 #if !defined(CONFIG_ARCH_RK319X)\r
1498     /// invalidate max decode picture width value in rk319x vpu\r
1499         dec->maxDecPicWidth = configReg & 0x07FFU;\r
1500 #else\r
1501     dec->maxDecPicWidth = 3840;\r
1502 #endif\r
1503 \r
1504         /* 2nd Config register */\r
1505         configReg   = pservice->dec_dev.hwregs[VPU_DEC_HWCFG1];\r
1506         if (dec->refBufSupport) {\r
1507                 if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)\r
1508                         dec->refBufSupport |= 2;\r
1509                 if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)\r
1510                         dec->refBufSupport |= 4;\r
1511         }\r
1512         dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;\r
1513         dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;\r
1514         dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;\r
1515         dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;\r
1516 \r
1517         /* JPEG xtensions */\r
1518         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1519                 dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;\r
1520         } else {\r
1521                 dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;\r
1522         }\r
1523 \r
1524         if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) ) {\r
1525                 dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;\r
1526         } else {\r
1527                 dec->rvSupport = RV_NOT_SUPPORTED;\r
1528         }\r
1529 \r
1530         dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;\r
1531 \r
1532         if (dec->refBufSupport && (asicID >> 16) == 0x6731U ) {\r
1533                 dec->refBufSupport |= 8; /* enable HW support for offset */\r
1534         }\r
1535 \r
1536 #if !defined(CONFIG_ARCH_RK319X)\r
1537     /// invalidate fuse register value in rk319x vpu\r
1538         {\r
1539         VPUHwFuseStatus_t hwFuseSts;\r
1540         /* Decoder fuse configuration */\r
1541         u32 fuseReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1542 \r
1543         hwFuseSts.h264SupportFuse = (fuseReg >> DWL_H264_FUSE_E) & 0x01U;\r
1544         hwFuseSts.mpeg4SupportFuse = (fuseReg >> DWL_MPEG4_FUSE_E) & 0x01U;\r
1545         hwFuseSts.mpeg2SupportFuse = (fuseReg >> DWL_MPEG2_FUSE_E) & 0x01U;\r
1546         hwFuseSts.sorensonSparkSupportFuse = (fuseReg >> DWL_SORENSONSPARK_FUSE_E) & 0x01U;\r
1547         hwFuseSts.jpegSupportFuse = (fuseReg >> DWL_JPEG_FUSE_E) & 0x01U;\r
1548         hwFuseSts.vp6SupportFuse = (fuseReg >> DWL_VP6_FUSE_E) & 0x01U;\r
1549         hwFuseSts.vc1SupportFuse = (fuseReg >> DWL_VC1_FUSE_E) & 0x01U;\r
1550         hwFuseSts.jpegProgSupportFuse = (fuseReg >> DWL_PJPEG_FUSE_E) & 0x01U;\r
1551         hwFuseSts.rvSupportFuse = (fuseReg >> DWL_RV_FUSE_E) & 0x01U;\r
1552         hwFuseSts.avsSupportFuse = (fuseReg >> DWL_AVS_FUSE_E) & 0x01U;\r
1553         hwFuseSts.vp7SupportFuse = (fuseReg >> DWL_VP7_FUSE_E) & 0x01U;\r
1554         hwFuseSts.vp8SupportFuse = (fuseReg >> DWL_VP8_FUSE_E) & 0x01U;\r
1555         hwFuseSts.customMpeg4SupportFuse = (fuseReg >> DWL_CUSTOM_MPEG4_FUSE_E) & 0x01U;\r
1556         hwFuseSts.mvcSupportFuse = (fuseReg >> DWL_MVC_FUSE_E) & 0x01U;\r
1557 \r
1558         /* check max. decoder output width */\r
1559 \r
1560         if (fuseReg & 0x8000U)\r
1561                 hwFuseSts.maxDecPicWidthFuse = 1920;\r
1562         else if (fuseReg & 0x4000U)\r
1563                 hwFuseSts.maxDecPicWidthFuse = 1280;\r
1564         else if (fuseReg & 0x2000U)\r
1565                 hwFuseSts.maxDecPicWidthFuse = 720;\r
1566         else if (fuseReg & 0x1000U)\r
1567                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1568         else    /* remove warning */\r
1569                 hwFuseSts.maxDecPicWidthFuse = 352;\r
1570 \r
1571         hwFuseSts.refBufSupportFuse = (fuseReg >> DWL_REF_BUFF_FUSE_E) & 0x01U;\r
1572 \r
1573         /* Pp configuration */\r
1574         configReg = pservice->dec_dev.hwregs[VPU_PP_HW_SYNTH_CFG];\r
1575 \r
1576         if ((configReg >> DWL_PP_E) & 0x01U) {\r
1577                 dec->ppSupport = 1;\r
1578                 dec->maxPpOutPicWidth = configReg & 0x07FFU;\r
1579                 /*pHwCfg->ppConfig = (configReg >> DWL_CFG_E) & 0x0FU; */\r
1580                 dec->ppConfig = configReg;\r
1581         } else {\r
1582                 dec->ppSupport = 0;\r
1583                 dec->maxPpOutPicWidth = 0;\r
1584                 dec->ppConfig = 0;\r
1585         }\r
1586 \r
1587         /* check the HW versio */\r
1588         if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U)) {\r
1589                 /* Pp configuration */\r
1590                 configReg = pservice->dec_dev.hwregs[VPU_DEC_HW_FUSE_CFG];\r
1591 \r
1592                 if ((configReg >> DWL_PP_E) & 0x01U) {\r
1593                         /* Pp fuse configuration */\r
1594                         u32 fuseRegPp = pservice->dec_dev.hwregs[VPU_PP_HW_FUSE_CFG];\r
1595 \r
1596                         if ((fuseRegPp >> DWL_PP_FUSE_E) & 0x01U) {\r
1597                                 hwFuseSts.ppSupportFuse = 1;\r
1598                                 /* check max. pp output width */\r
1599                                 if      (fuseRegPp & 0x8000U) hwFuseSts.maxPpOutPicWidthFuse = 1920;\r
1600                                 else if (fuseRegPp & 0x4000U) hwFuseSts.maxPpOutPicWidthFuse = 1280;\r
1601                                 else if (fuseRegPp & 0x2000U) hwFuseSts.maxPpOutPicWidthFuse = 720;\r
1602                                 else if (fuseRegPp & 0x1000U) hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1603                                 else                          hwFuseSts.maxPpOutPicWidthFuse = 352;\r
1604                                 hwFuseSts.ppConfigFuse = fuseRegPp;\r
1605                         } else {\r
1606                                 hwFuseSts.ppSupportFuse = 0;\r
1607                                 hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1608                                 hwFuseSts.ppConfigFuse = 0;\r
1609                         }\r
1610                 } else {\r
1611                         hwFuseSts.ppSupportFuse = 0;\r
1612                         hwFuseSts.maxPpOutPicWidthFuse = 0;\r
1613                         hwFuseSts.ppConfigFuse = 0;\r
1614                 }\r
1615 \r
1616                 if (dec->maxDecPicWidth > hwFuseSts.maxDecPicWidthFuse)\r
1617                         dec->maxDecPicWidth = hwFuseSts.maxDecPicWidthFuse;\r
1618                 if (dec->maxPpOutPicWidth > hwFuseSts.maxPpOutPicWidthFuse)\r
1619                         dec->maxPpOutPicWidth = hwFuseSts.maxPpOutPicWidthFuse;\r
1620                 if (!hwFuseSts.h264SupportFuse) dec->h264Support = H264_NOT_SUPPORTED;\r
1621                 if (!hwFuseSts.mpeg4SupportFuse) dec->mpeg4Support = MPEG4_NOT_SUPPORTED;\r
1622                 if (!hwFuseSts.customMpeg4SupportFuse) dec->customMpeg4Support = MPEG4_CUSTOM_NOT_SUPPORTED;\r
1623                 if (!hwFuseSts.jpegSupportFuse) dec->jpegSupport = JPEG_NOT_SUPPORTED;\r
1624                 if ((dec->jpegSupport == JPEG_PROGRESSIVE) && !hwFuseSts.jpegProgSupportFuse)\r
1625                         dec->jpegSupport = JPEG_BASELINE;\r
1626                 if (!hwFuseSts.mpeg2SupportFuse) dec->mpeg2Support = MPEG2_NOT_SUPPORTED;\r
1627                 if (!hwFuseSts.vc1SupportFuse) dec->vc1Support = VC1_NOT_SUPPORTED;\r
1628                 if (!hwFuseSts.vp6SupportFuse) dec->vp6Support = VP6_NOT_SUPPORTED;\r
1629                 if (!hwFuseSts.vp7SupportFuse) dec->vp7Support = VP7_NOT_SUPPORTED;\r
1630                 if (!hwFuseSts.vp8SupportFuse) dec->vp8Support = VP8_NOT_SUPPORTED;\r
1631                 if (!hwFuseSts.ppSupportFuse) dec->ppSupport = PP_NOT_SUPPORTED;\r
1632 \r
1633                 /* check the pp config vs fuse status */\r
1634                 if ((dec->ppConfig & 0xFC000000) && ((hwFuseSts.ppConfigFuse & 0xF0000000) >> 5)) {\r
1635                         u32 deInterlace = ((dec->ppConfig & PP_DEINTERLACING) >> 25);\r
1636                         u32 alphaBlend  = ((dec->ppConfig & PP_ALPHA_BLENDING) >> 24);\r
1637                         u32 deInterlaceFuse = (((hwFuseSts.ppConfigFuse >> 5) & PP_DEINTERLACING) >> 25);\r
1638                         u32 alphaBlendFuse  = (((hwFuseSts.ppConfigFuse >> 5) & PP_ALPHA_BLENDING) >> 24);\r
1639 \r
1640                         if (deInterlace && !deInterlaceFuse) dec->ppConfig &= 0xFD000000;\r
1641                         if (alphaBlend && !alphaBlendFuse) dec->ppConfig &= 0xFE000000;\r
1642                 }\r
1643                 if (!hwFuseSts.sorensonSparkSupportFuse) dec->sorensonSparkSupport = SORENSON_SPARK_NOT_SUPPORTED;\r
1644                 if (!hwFuseSts.refBufSupportFuse)   dec->refBufSupport = REF_BUF_NOT_SUPPORTED;\r
1645                 if (!hwFuseSts.rvSupportFuse)       dec->rvSupport = RV_NOT_SUPPORTED;\r
1646                 if (!hwFuseSts.avsSupportFuse)      dec->avsSupport = AVS_NOT_SUPPORTED;\r
1647                 if (!hwFuseSts.mvcSupportFuse)      dec->mvcSupport = MVC_NOT_SUPPORTED;\r
1648         }\r
1649         }\r
1650 #endif\r
1651         configReg = pservice->enc_dev.hwregs[63];\r
1652         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);\r
1653         enc->h264Enabled = (configReg >> 27) & 1;\r
1654         enc->mpeg4Enabled = (configReg >> 26) & 1;\r
1655         enc->jpegEnabled = (configReg >> 25) & 1;\r
1656         enc->vsEnabled = (configReg >> 24) & 1;\r
1657         enc->rgbEnabled = (configReg >> 28) & 1;\r
1658         //enc->busType = (configReg >> 20) & 15;\r
1659         //enc->synthesisLanguage = (configReg >> 16) & 15;\r
1660         //enc->busWidth = (configReg >> 12) & 15;\r
1661         enc->reg_size = pservice->reg_size;\r
1662         enc->reserv[0] = enc->reserv[1] = 0;\r
1663 \r
1664         pservice->auto_freq = soc_is_rk2928g() || soc_is_rk2928l() || soc_is_rk2926();\r
1665         if (pservice->auto_freq) {\r
1666                 printk("vpu_service set to auto frequency mode\n");\r
1667                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);\r
1668         }\r
1669         pservice->bug_dec_addr = cpu_is_rk30xx();\r
1670         //printk("cpu 3066b bug %d\n", service.bug_dec_addr);\r
1671 }\r
1672 \r
1673 static irqreturn_t vdpu_irq(int irq, void *dev_id)\r
1674 {\r
1675     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1676     vpu_device *dev = &pservice->dec_dev;\r
1677         u32 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1678     int i;\r
1679 \r
1680         pr_debug("dec_irq\n");\r
1681 \r
1682         if (irq_status & DEC_INTERRUPT_BIT) {\r
1683                 pr_debug("dec_isr dec %x\n", irq_status);\r
1684                 if ((irq_status & 0x40001) == 0x40001)\r
1685                 {\r
1686                         do {\r
1687                                 irq_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1688                         } while ((irq_status & 0x40001) == 0x40001);\r
1689                 }\r
1690 \r
1691                 /* clear dec IRQ */\r
1692         if (pservice->hw_info->hw_id != HEVC_ID) {\r
1693             writel(irq_status & (~DEC_INTERRUPT_BIT|DEC_BUFFER_EMPTY_BIT), dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1694         } else {\r
1695             /*writel(irq_status \r
1696               & (~(DEC_INTERRUPT_BIT|HEVC_DEC_INT_RAW_BIT|HEVC_DEC_STR_ERROR_BIT|HEVC_DEC_BUS_ERROR_BIT|HEVC_DEC_BUFFER_EMPTY_BIT)), \r
1697                    dev->hwregs + DEC_INTERRUPT_REGISTER);*/\r
1698 \r
1699             writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);\r
1700         }\r
1701                 atomic_add(1, &dev->irq_count_codec);\r
1702         }\r
1703 \r
1704     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1705         irq_status  = readl(dev->hwregs + PP_INTERRUPT_REGISTER);\r
1706         if (irq_status & PP_INTERRUPT_BIT) {\r
1707             pr_debug("vdpu_isr pp  %x\n", irq_status);\r
1708             /* clear pp IRQ */\r
1709             writel(irq_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);\r
1710             atomic_add(1, &dev->irq_count_pp);\r
1711         }\r
1712     }\r
1713 \r
1714     pservice->irq_status = irq_status;\r
1715 \r
1716         return IRQ_WAKE_THREAD;\r
1717 }\r
1718 \r
1719 static irqreturn_t vdpu_isr(int irq, void *dev_id)\r
1720 {\r
1721     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1722     vpu_device *dev = &pservice->dec_dev;\r
1723 \r
1724         mutex_lock(&pservice->lock);\r
1725         if (atomic_read(&dev->irq_count_codec)) {\r
1726 #if VPU_SERVICE_SHOW_TIME\r
1727                 do_gettimeofday(&dec_end);\r
1728                 pr_info("dec task: %ld ms\n",\r
1729                         (dec_end.tv_sec  - dec_start.tv_sec)  * 1000 +\r
1730                         (dec_end.tv_usec - dec_start.tv_usec) / 1000);\r
1731 #endif\r
1732                 atomic_sub(1, &dev->irq_count_codec);\r
1733                 if (NULL == pservice->reg_codec) {\r
1734                         pr_err("error: dec isr with no task waiting\n");\r
1735                 } else {\r
1736                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1737                 }\r
1738         }\r
1739 \r
1740         if (atomic_read(&dev->irq_count_pp)) {\r
1741 \r
1742 #if VPU_SERVICE_SHOW_TIME\r
1743                 do_gettimeofday(&pp_end);\r
1744                 printk("pp  task: %ld ms\n",\r
1745                         (pp_end.tv_sec  - pp_start.tv_sec)  * 1000 +\r
1746                         (pp_end.tv_usec - pp_start.tv_usec) / 1000);\r
1747 #endif\r
1748 \r
1749                 atomic_sub(1, &dev->irq_count_pp);\r
1750                 if (NULL == pservice->reg_pproc) {\r
1751                         pr_err("error: pp isr with no task waiting\n");\r
1752                 } else {\r
1753                         reg_from_run_to_done(pservice, pservice->reg_pproc);\r
1754                 }\r
1755         }\r
1756         try_set_reg(pservice);\r
1757         mutex_unlock(&pservice->lock);\r
1758         return IRQ_HANDLED;\r
1759 }\r
1760 \r
1761 static irqreturn_t vepu_irq(int irq, void *dev_id)\r
1762 {\r
1763         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1764     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1765     vpu_device *dev = &pservice->enc_dev;\r
1766         u32 irq_status = readl(dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1767 \r
1768         pr_debug("vepu_irq irq status %x\n", irq_status);\r
1769 \r
1770 #if VPU_SERVICE_SHOW_TIME\r
1771         do_gettimeofday(&enc_end);\r
1772         pr_info("enc task: %ld ms\n",\r
1773                 (enc_end.tv_sec  - enc_start.tv_sec)  * 1000 +\r
1774                 (enc_end.tv_usec - enc_start.tv_usec) / 1000);\r
1775 #endif\r
1776 \r
1777         if (likely(irq_status & ENC_INTERRUPT_BIT)) {\r
1778                 /* clear enc IRQ */\r
1779                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);\r
1780                 atomic_add(1, &dev->irq_count_codec);\r
1781         }\r
1782 \r
1783         return IRQ_WAKE_THREAD;\r
1784 }\r
1785 \r
1786 static irqreturn_t vepu_isr(int irq, void *dev_id)\r
1787 {\r
1788         //struct vpu_device *dev = (struct vpu_device *) dev_id;\r
1789     struct vpu_service_info *pservice = (struct vpu_service_info*)dev_id;\r
1790     vpu_device *dev = &pservice->enc_dev;\r
1791 \r
1792         mutex_lock(&pservice->lock);\r
1793         if (atomic_read(&dev->irq_count_codec)) {\r
1794                 atomic_sub(1, &dev->irq_count_codec);\r
1795                 if (NULL == pservice->reg_codec) {\r
1796                         pr_err("error: enc isr with no task waiting\n");\r
1797                 } else {\r
1798                         reg_from_run_to_done(pservice, pservice->reg_codec);\r
1799                 }\r
1800         }\r
1801         try_set_reg(pservice);\r
1802         mutex_unlock(&pservice->lock);\r
1803         return IRQ_HANDLED;\r
1804 }\r
1805 \r
1806 static int __init vcodec_service_init(void)\r
1807 {\r
1808     int ret;\r
1809 \r
1810     if ((ret = platform_driver_register(&vcodec_driver)) != 0) {\r
1811         pr_err("Platform device register failed (%d).\n", ret);\r
1812         return ret;\r
1813     }\r
1814 \r
1815 #ifdef CONFIG_DEBUG_FS\r
1816     vcodec_debugfs_init();\r
1817 #endif\r
1818 \r
1819     return ret;\r
1820 }\r
1821 \r
1822 static void __exit vcodec_service_exit(void)\r
1823 {\r
1824 #ifdef CONFIG_DEBUG_FS\r
1825     vcodec_debugfs_exit();\r
1826 #endif\r
1827 \r
1828         platform_driver_unregister(&vcodec_driver);\r
1829 }\r
1830 \r
1831 module_init(vcodec_service_init);\r
1832 module_exit(vcodec_service_exit);\r
1833 \r
1834 #ifdef CONFIG_DEBUG_FS\r
1835 #include <linux/seq_file.h>\r
1836 \r
1837 static int vcodec_debugfs_init()\r
1838 {\r
1839     parent = debugfs_create_dir("vcodec", NULL);\r
1840     if (!parent)\r
1841         return -1;\r
1842 \r
1843     return 0;\r
1844 }\r
1845 \r
1846 static void vcodec_debugfs_exit()\r
1847 {\r
1848     debugfs_remove(parent);\r
1849 }\r
1850 \r
1851 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)\r
1852 {\r
1853     return debugfs_create_dir(dirname, parent);\r
1854 }\r
1855 \r
1856 static int debug_vcodec_show(struct seq_file *s, void *unused)\r
1857 {\r
1858         struct vpu_service_info *pservice = s->private;\r
1859     unsigned int i, n;\r
1860         vpu_reg *reg, *reg_tmp;\r
1861         vpu_session *session, *session_tmp;\r
1862 \r
1863         mutex_lock(&pservice->lock);\r
1864         vpu_service_power_on(pservice);\r
1865     if (pservice->hw_info->hw_id != HEVC_ID) {\r
1866         seq_printf(s, "\nENC Registers:\n");\r
1867         n = pservice->enc_dev.iosize >> 2;\r
1868         for (i = 0; i < n; i++) {\r
1869             seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->enc_dev.hwregs + i));\r
1870         }\r
1871     }\r
1872         seq_printf(s, "\nDEC Registers:\n");\r
1873         n = pservice->dec_dev.iosize >> 2;\r
1874         for (i = 0; i < n; i++) {\r
1875                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
1876         }\r
1877 \r
1878         seq_printf(s, "\nvpu service status:\n");\r
1879         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {\r
1880                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);\r
1881                 //seq_printf(s, "waiting reg set %d\n");\r
1882                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {\r
1883                         seq_printf(s, "waiting register set\n");\r
1884                 }\r
1885                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {\r
1886                         seq_printf(s, "running register set\n");\r
1887                 }\r
1888                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {\r
1889                         seq_printf(s, "done    register set\n");\r
1890                 }\r
1891         }\r
1892         mutex_unlock(&pservice->lock);\r
1893 \r
1894     return 0;\r
1895 }\r
1896 \r
1897 static int debug_vcodec_open(struct inode *inode, struct file *file)\r
1898 {\r
1899         return single_open(file, debug_vcodec_show, inode->i_private);\r
1900 }\r
1901 \r
1902 #endif\r
1903 \r
1904 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)\r
1905 #include "hevc_test_inc/pps_00.h"\r
1906 #include "hevc_test_inc/register_00.h"\r
1907 #include "hevc_test_inc/rps_00.h"\r
1908 #include "hevc_test_inc/scaling_list_00.h"\r
1909 #include "hevc_test_inc/stream_00.h"\r
1910 \r
1911 #include "hevc_test_inc/pps_01.h"\r
1912 #include "hevc_test_inc/register_01.h"\r
1913 #include "hevc_test_inc/rps_01.h"\r
1914 #include "hevc_test_inc/scaling_list_01.h"\r
1915 #include "hevc_test_inc/stream_01.h"\r
1916 \r
1917 #include "hevc_test_inc/cabac.h"\r
1918 \r
1919 extern struct ion_client *rockchip_ion_client_create(const char * name);\r
1920 \r
1921 static struct ion_client *ion_client = NULL;\r
1922 u8* get_align_ptr(u8* tbl, int len, u32 *phy)\r
1923 {\r
1924         int size = (len+15) & (~15);\r
1925     struct ion_handle *handle;\r
1926         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
1927 \r
1928     if (ion_client == NULL) {\r
1929         ion_client = rockchip_ion_client_create("vcodec");\r
1930     }\r
1931 \r
1932     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
1933 \r
1934     ptr = ion_map_kernel(ion_client, handle);\r
1935 \r
1936     ion_phys(ion_client, handle, phy, &size);\r
1937 \r
1938         memcpy(ptr, tbl, len);\r
1939 \r
1940         return ptr;\r
1941 }\r
1942 \r
1943 u8* get_align_ptr_no_copy(int len, u32 *phy)\r
1944 {\r
1945         int size = (len+15) & (~15);\r
1946     struct ion_handle *handle;\r
1947         u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);\r
1948 \r
1949     if (ion_client == NULL) {\r
1950         ion_client = rockchip_ion_client_create("vcodec");\r
1951     }\r
1952 \r
1953     handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);\r
1954 \r
1955     ptr = ion_map_kernel(ion_client, handle);\r
1956 \r
1957     ion_phys(ion_client, handle, phy, &size);\r
1958 \r
1959         return ptr;\r
1960 }\r
1961 \r
1962 #define TEST_CNT    2\r
1963 static int hevc_test_case0(vpu_service_info *pservice)\r
1964 {\r
1965     vpu_session session;\r
1966     vpu_reg *reg; \r
1967     unsigned long size = 272;//sizeof(register_00); // registers array length\r
1968     int testidx = 0;\r
1969     int ret = 0;\r
1970 \r
1971     u8 *pps_tbl[TEST_CNT];\r
1972     u8 *register_tbl[TEST_CNT];\r
1973     u8 *rps_tbl[TEST_CNT];\r
1974     u8 *scaling_list_tbl[TEST_CNT];\r
1975     u8 *stream_tbl[TEST_CNT];\r
1976 \r
1977         int stream_size[2];\r
1978         int pps_size[2];\r
1979         int rps_size[2];\r
1980         int scl_size[2];\r
1981         int cabac_size[2];\r
1982         \r
1983     u32 phy_pps;\r
1984     u32 phy_rps;\r
1985     u32 phy_scl;\r
1986     u32 phy_str;\r
1987     u32 phy_yuv;\r
1988     u32 phy_ref;\r
1989     u32 phy_cabac;\r
1990 \r
1991         volatile u8 *stream_buf;\r
1992         volatile u8 *pps_buf;\r
1993         volatile u8 *rps_buf;\r
1994         volatile u8 *scl_buf;\r
1995         volatile u8 *yuv_buf;\r
1996         volatile u8 *cabac_buf;\r
1997         volatile u8 *ref_buf;\r
1998 \r
1999     u8 *pps;\r
2000     u8 *yuv[2];\r
2001     int i;\r
2002     \r
2003     pps_tbl[0] = pps_00;\r
2004     pps_tbl[1] = pps_01;\r
2005 \r
2006     register_tbl[0] = register_00;\r
2007     register_tbl[1] = register_01;\r
2008     \r
2009     rps_tbl[0] = rps_00;\r
2010     rps_tbl[1] = rps_01;\r
2011     \r
2012     scaling_list_tbl[0] = scaling_list_00;\r
2013     scaling_list_tbl[1] = scaling_list_01;\r
2014 \r
2015     stream_tbl[0] = stream_00;\r
2016     stream_tbl[1] = stream_01;\r
2017 \r
2018     stream_size[0] = sizeof(stream_00);\r
2019     stream_size[1] = sizeof(stream_01);\r
2020 \r
2021         pps_size[0] = sizeof(pps_00);\r
2022         pps_size[1] = sizeof(pps_01);\r
2023 \r
2024         rps_size[0] = sizeof(rps_00);\r
2025         rps_size[1] = sizeof(rps_01);\r
2026 \r
2027         scl_size[0] = sizeof(scaling_list_00);\r
2028         scl_size[1] = sizeof(scaling_list_01);\r
2029         \r
2030         cabac_size[0] = sizeof(Cabac_table);\r
2031         cabac_size[1] = sizeof(Cabac_table);\r
2032 \r
2033     // create session\r
2034     session.pid = current->pid;\r
2035     session.type = VPU_DEC;\r
2036     INIT_LIST_HEAD(&session.waiting);\r
2037         INIT_LIST_HEAD(&session.running);\r
2038         INIT_LIST_HEAD(&session.done);\r
2039         INIT_LIST_HEAD(&session.list_session);\r
2040         init_waitqueue_head(&session.wait);\r
2041         atomic_set(&session.task_running, 0);\r
2042         list_add_tail(&session.list_session, &pservice->session);\r
2043 \r
2044     yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);\r
2045     yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);\r
2046 \r
2047         while (testidx < TEST_CNT) {\r
2048         \r
2049         // create registers\r
2050         reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);\r
2051         if (NULL == reg) {\r
2052             pr_err("error: kmalloc fail in reg_init\n");\r
2053             return -1;\r
2054         }\r
2055 \r
2056 \r
2057         if (size > pservice->reg_size) {\r
2058             printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);\r
2059             size = pservice->reg_size;\r
2060         }\r
2061         reg->session = &session;\r
2062         reg->type = session.type;\r
2063         reg->size = size;\r
2064         reg->freq = VPU_FREQ_DEFAULT;\r
2065         reg->reg = (unsigned long *)&reg[1];\r
2066         INIT_LIST_HEAD(&reg->session_link);\r
2067         INIT_LIST_HEAD(&reg->status_link);\r
2068 \r
2069         // TODO: stuff registers\r
2070         memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);\r
2071 \r
2072                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);\r
2073                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);\r
2074                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);\r
2075                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);\r
2076                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);\r
2077 \r
2078                 pps = pps_buf;\r
2079 \r
2080         // TODO: replace reigster address\r
2081 \r
2082         for (i=0; i<64; i++) {\r
2083             u32 scaling_offset;\r
2084             u32 tmp;\r
2085 \r
2086             scaling_offset = (u32)pps[i*80+74];\r
2087             scaling_offset += (u32)pps[i*80+75] << 8;\r
2088             scaling_offset += (u32)pps[i*80+76] << 16;\r
2089             scaling_offset += (u32)pps[i*80+77] << 24;\r
2090 \r
2091             tmp = phy_scl + scaling_offset;\r
2092 \r
2093             pps[i*80+74] = tmp & 0xff;\r
2094             pps[i*80+75] = (tmp >> 8) & 0xff;\r
2095             pps[i*80+76] = (tmp >> 16) & 0xff;\r
2096             pps[i*80+77] = (tmp >> 24) & 0xff;\r
2097         }\r
2098 \r
2099         printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n", __func__, __LINE__, phy_str, phy_pps, phy_rps);\r
2100 \r
2101         reg->reg[1] = 0x21;\r
2102         reg->reg[4] = phy_str;\r
2103         reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;\r
2104         reg->reg[6] = phy_cabac;\r
2105         reg->reg[7] = testidx?phy_ref:phy_yuv;\r
2106         reg->reg[42] = phy_pps;\r
2107         reg->reg[43] = phy_rps;\r
2108         for (i = 10; i <= 24; i++) {\r
2109             reg->reg[i] = phy_yuv;\r
2110         }\r
2111 \r
2112         mutex_lock(&pservice->lock);\r
2113         list_add_tail(&reg->status_link, &pservice->waiting);\r
2114         list_add_tail(&reg->session_link, &session.waiting);\r
2115         mutex_unlock(&pservice->lock);\r
2116 \r
2117         printk("%s %d %p\n", __func__, __LINE__, pservice);\r
2118 \r
2119         // stuff hardware\r
2120         try_set_reg(pservice);\r
2121 \r
2122         // wait for result\r
2123         ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);\r
2124         if (!list_empty(&session.done)) {\r
2125             if (ret < 0) {\r
2126                 pr_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);\r
2127             }\r
2128             ret = 0;\r
2129         } else {\r
2130             if (unlikely(ret < 0)) {\r
2131                 pr_err("error: pid %d wait task ret %d\n", session.pid, ret);\r
2132             } else if (0 == ret) {\r
2133                 pr_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));\r
2134                 ret = -ETIMEDOUT;\r
2135             }\r
2136         }\r
2137         if (ret < 0) {\r
2138             int task_running = atomic_read(&session.task_running);\r
2139             int n;\r
2140             mutex_lock(&pservice->lock);\r
2141             vpu_service_dump(pservice);\r
2142             if (task_running) {\r
2143                 atomic_set(&session.task_running, 0);\r
2144                 atomic_sub(task_running, &pservice->total_running);\r
2145                 printk("%d task is running but not return, reset hardware...", task_running);\r
2146                 vpu_reset(pservice);\r
2147                 printk("done\n");\r
2148             }\r
2149             vpu_service_session_clear(pservice, &session);\r
2150             mutex_unlock(&pservice->lock);\r
2151 \r
2152             printk("\nDEC Registers:\n");\r
2153                 n = pservice->dec_dev.iosize >> 2;\r
2154                 for (i=0; i<n; i++) {\r
2155                         printk("\tswreg%d = %08X\n", i, readl(pservice->dec_dev.hwregs + i));\r
2156                 }\r
2157 \r
2158             pr_err("test index %d failed\n", testidx);\r
2159             break;\r
2160         } else {\r
2161             pr_info("test index %d success\n", testidx);\r
2162 \r
2163             vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);\r
2164 \r
2165             for (i=0; i<68; i++) {\r
2166                 if (i % 4 == 0) {\r
2167                     printk("%02d: ", i);\r
2168                 }\r
2169                 printk("%08x ", reg->reg[i]);\r
2170                 if ((i+1) % 4 == 0) {\r
2171                     printk("\n");\r
2172                 }\r
2173             }\r
2174 \r
2175             testidx++;\r
2176         }\r
2177 \r
2178         reg_deinit(pservice, reg);\r
2179     }\r
2180 \r
2181     return 0;\r
2182 }\r
2183 \r
2184 #endif\r
2185 \r