arch/arm/mach-s3c2410/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright 2003-2008 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dm9000.h>
  24 #include <linux/ata_platform.h>
  25 #include <linux/i2c.h>
  26 #include <linux/io.h>
  27
  28 #include <net/ax88796.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/bast-map.h>
  35 #include <mach/bast-irq.h>
  36 #include <mach/bast-cpld.h>
  37
  38 #include <mach/hardware.h>
  39 #include <asm/irq.h>
  40 #include <asm/mach-types.h>
  41
  42 //#include <asm/debug-ll.h>
  43 #include <plat/regs-serial.h>
  44 #include <mach/regs-gpio.h>
  45 #include <mach/regs-mem.h>
  46 #include <mach/regs-lcd.h>
  47
  48 #include <plat/hwmon.h>
  49 #include <plat/nand.h>
  50 #include <plat/iic.h>
  51 #include <mach/fb.h>
  52
  53 #include <linux/mtd/mtd.h>
  54 #include <linux/mtd/nand.h>
  55 #include <linux/mtd/nand_ecc.h>
  56 #include <linux/mtd/partitions.h>
  57
  58 #include <linux/serial_8250.h>
  59
  60 #include <plat/clock.h>
  61 #include <plat/devs.h>
  62 #include <plat/cpu.h>
  63 #include <plat/cpu-freq.h>
  64 #include <plat/gpio-cfg.h>
  65 #include <plat/audio-simtec.h>
  66
  67 #include "usb-simtec.h"
  68 #include "nor-simtec.h"
  69 #include "common.h"
  70
  71 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
  72
  73 /* macros for virtual address mods for the io space entries */
  74 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  75 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  76 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  77 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  78
  79 /* macros to modify the physical addresses for io space */
  80
  81 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  82 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  83 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  84 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  85
  86 static struct map_desc bast_iodesc[] __initdata = {
  87   /* ISA IO areas */
  88   {
  89           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  90           .pfn          = PA_CS2(BAST_PA_ISAIO),
  91           .length       = SZ_16M,
  92           .type         = MT_DEVICE,
  93   }, {
  94           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  95           .pfn          = PA_CS3(BAST_PA_ISAIO),
  96           .length       = SZ_16M,
  97           .type         = MT_DEVICE,
  98   },
  99   /* bast CPLD control registers, and external interrupt controls */
 100   {
 101           .virtual      = (u32)BAST_VA_CTRL1,
 102           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
 103           .length       = SZ_1M,
 104           .type         = MT_DEVICE,
 105   }, {
 106           .virtual      = (u32)BAST_VA_CTRL2,
 107           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 108           .length       = SZ_1M,
 109           .type         = MT_DEVICE,
 110   }, {
 111           .virtual      = (u32)BAST_VA_CTRL3,
 112           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 113           .length       = SZ_1M,
 114           .type         = MT_DEVICE,
 115   }, {
 116           .virtual      = (u32)BAST_VA_CTRL4,
 117           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 118           .length       = SZ_1M,
 119           .type         = MT_DEVICE,
 120   },
 121   /* PC104 IRQ mux */
 122   {
 123           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 124           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 125           .length       = SZ_1M,
 126           .type         = MT_DEVICE,
 127   }, {
 128           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 129           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 130           .length       = SZ_1M,
 131           .type         = MT_DEVICE,
 132   }, {
 133           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 134           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 135           .length       = SZ_1M,
 136           .type         = MT_DEVICE,
 137   },
 138
 139   /* peripheral space... one for each of fast/slow/byte/16bit */
 140   /* note, ide is only decoded in word space, even though some registers
 141    * are only 8bit */
 142
 143   /* slow, byte */
 144   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 145   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 146   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 147
 148   /* slow, word */
 149   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 150   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 151   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 152
 153   /* fast, byte */
 154   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 155   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 156   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 157
 158   /* fast, word */
 159   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 160   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 161   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 162 };
 163
 164 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 165 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 166 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 167
 168 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 169         [0] = {
 170                 .name           = "uclk",
 171                 .divisor        = 1,
 172                 .min_baud       = 0,
 173                 .max_baud       = 0,
 174         },
 175         [1] = {
 176                 .name           = "pclk",
 177                 .divisor        = 1,
 178                 .min_baud       = 0,
 179                 .max_baud       = 0,
 180         }
 181 };
 182
 183
 184 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 185         [0] = {
 186                 .hwport      = 0,
 187                 .flags       = 0,
 188                 .ucon        = UCON,
 189                 .ulcon       = ULCON,
 190                 .ufcon       = UFCON,
 191                 .clocks      = bast_serial_clocks,
 192                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 193         },
 194         [1] = {
 195                 .hwport      = 1,
 196                 .flags       = 0,
 197                 .ucon        = UCON,
 198                 .ulcon       = ULCON,
 199                 .ufcon       = UFCON,
 200                 .clocks      = bast_serial_clocks,
 201                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 202         },
 203         /* port 2 is not actually used */
 204         [2] = {
 205                 .hwport      = 2,
 206                 .flags       = 0,
 207                 .ucon        = UCON,
 208                 .ulcon       = ULCON,
 209                 .ufcon       = UFCON,
 210                 .clocks      = bast_serial_clocks,
 211                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 212         }
 213 };
 214
 215 /* NAND Flash on BAST board */
 216
 217 #ifdef CONFIG_PM
 218 static int bast_pm_suspend(void)
 219 {
 220         /* ensure that an nRESET is not generated on resume. */
 221         gpio_direction_output(S3C2410_GPA(21), 1);
 222         return 0;
 223 }
 224
 225 static void bast_pm_resume(void)
 226 {
 227         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 228 }
 229
 230 #else
 231 #define bast_pm_suspend NULL
 232 #define bast_pm_resume NULL
 233 #endif
 234
 235 static struct syscore_ops bast_pm_syscore_ops = {
 236         .suspend        = bast_pm_suspend,
 237         .resume         = bast_pm_resume,
 238 };
 239
 240 static int smartmedia_map[] = { 0 };
 241 static int chip0_map[] = { 1 };
 242 static int chip1_map[] = { 2 };
 243 static int chip2_map[] = { 3 };
 244
 245 static struct mtd_partition __initdata bast_default_nand_part[] = {
 246         [0] = {
 247                 .name   = "Boot Agent",
 248                 .size   = SZ_16K,
 249                 .offset = 0,
 250         },
 251         [1] = {
 252                 .name   = "/boot",
 253                 .size   = SZ_4M - SZ_16K,
 254                 .offset = SZ_16K,
 255         },
 256         [2] = {
 257                 .name   = "user",
 258                 .offset = SZ_4M,
 259                 .size   = MTDPART_SIZ_FULL,
 260         }
 261 };
 262
 263 /* the bast has 4 selectable slots for nand-flash, the three
 264  * on-board chip areas, as well as the external SmartMedia
 265  * slot.
 266  *
 267  * Note, there is no current hot-plug support for the SmartMedia
 268  * socket.
 269 */
 270
 271 static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
 272         [0] = {
 273                 .name           = "SmartMedia",
 274                 .nr_chips       = 1,
 275                 .nr_map         = smartmedia_map,
 276                 .options        = NAND_SCAN_SILENT_NODEV,
 277                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 278                 .partitions     = bast_default_nand_part,
 279         },
 280         [1] = {
 281                 .name           = "chip0",
 282                 .nr_chips       = 1,
 283                 .nr_map         = chip0_map,
 284                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 285                 .partitions     = bast_default_nand_part,
 286         },
 287         [2] = {
 288                 .name           = "chip1",
 289                 .nr_chips       = 1,
 290                 .nr_map         = chip1_map,
 291                 .options        = NAND_SCAN_SILENT_NODEV,
 292                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 293                 .partitions     = bast_default_nand_part,
 294         },
 295         [3] = {
 296                 .name           = "chip2",
 297                 .nr_chips       = 1,
 298                 .nr_map         = chip2_map,
 299                 .options        = NAND_SCAN_SILENT_NODEV,
 300                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 301                 .partitions     = bast_default_nand_part,
 302         }
 303 };
 304
 305 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 306 {
 307         unsigned int tmp;
 308
 309         slot = set->nr_map[slot] & 3;
 310
 311         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 312                  slot, set, set->nr_map);
 313
 314         tmp = __raw_readb(BAST_VA_CTRL2);
 315         tmp &= BAST_CPLD_CTLR2_IDERST;
 316         tmp |= slot;
 317         tmp |= BAST_CPLD_CTRL2_WNAND;
 318
 319         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 320
 321         __raw_writeb(tmp, BAST_VA_CTRL2);
 322 }
 323
 324 static struct s3c2410_platform_nand __initdata bast_nand_info = {
 325         .tacls          = 30,
 326         .twrph0         = 60,
 327         .twrph1         = 60,
 328         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 329         .sets           = bast_nand_sets,
 330         .select_chip    = bast_nand_select,
 331 };
 332
 333 /* DM9000 */
 334
 335 static struct resource bast_dm9k_resource[] = {
 336         [0] = {
 337                 .start = S3C2410_CS5 + BAST_PA_DM9000,
 338                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
 339                 .flags = IORESOURCE_MEM,
 340         },
 341         [1] = {
 342                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
 343                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
 344                 .flags = IORESOURCE_MEM,
 345         },
 346         [2] = {
 347                 .start = IRQ_DM9000,
 348                 .end   = IRQ_DM9000,
 349                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 350         }
 351
 352 };
 353
 354 /* for the moment we limit ourselves to 16bit IO until some
 355  * better IO routines can be written and tested
 356 */
 357
 358 static struct dm9000_plat_data bast_dm9k_platdata = {
 359         .flags          = DM9000_PLATF_16BITONLY,
 360 };
 361
 362 static struct platform_device bast_device_dm9k = {
 363         .name           = "dm9000",
 364         .id             = 0,
 365         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 366         .resource       = bast_dm9k_resource,
 367         .dev            = {
 368                 .platform_data = &bast_dm9k_platdata,
 369         }
 370 };
 371
 372 /* serial devices */
 373
 374 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 375 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 376 #define SERIAL_CLK   (1843200)
 377
 378 static struct plat_serial8250_port bast_sio_data[] = {
 379         [0] = {
 380                 .mapbase        = SERIAL_BASE + 0x2f8,
 381                 .irq            = IRQ_PCSERIAL1,
 382                 .flags          = SERIAL_FLAGS,
 383                 .iotype         = UPIO_MEM,
 384                 .regshift       = 0,
 385                 .uartclk        = SERIAL_CLK,
 386         },
 387         [1] = {
 388                 .mapbase        = SERIAL_BASE + 0x3f8,
 389                 .irq            = IRQ_PCSERIAL2,
 390                 .flags          = SERIAL_FLAGS,
 391                 .iotype         = UPIO_MEM,
 392                 .regshift       = 0,
 393                 .uartclk        = SERIAL_CLK,
 394         },
 395         { }
 396 };
 397
 398 static struct platform_device bast_sio = {
 399         .name                   = "serial8250",
 400         .id                     = PLAT8250_DEV_PLATFORM,
 401         .dev                    = {
 402                 .platform_data  = &bast_sio_data,
 403         },
 404 };
 405
 406 /* we have devices on the bus which cannot work much over the
 407  * standard 100KHz i2c bus frequency
 408 */
 409
 410 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 411         .flags          = 0,
 412         .slave_addr     = 0x10,
 413         .frequency      = 100*1000,
 414 };
 415
 416 /* Asix AX88796 10/100 ethernet controller */
 417
 418 static struct ax_plat_data bast_asix_platdata = {
 419         .flags          = AXFLG_MAC_FROMDEV,
 420         .wordlength     = 2,
 421         .dcr_val        = 0x48,
 422         .rcr_val        = 0x40,
 423 };
 424
 425 static struct resource bast_asix_resource[] = {
 426         [0] = {
 427                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
 428                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
 429                 .flags = IORESOURCE_MEM,
 430         },
 431         [1] = {
 432                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 433                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 434                 .flags = IORESOURCE_MEM,
 435         },
 436         [2] = {
 437                 .start = IRQ_ASIX,
 438                 .end   = IRQ_ASIX,
 439                 .flags = IORESOURCE_IRQ
 440         }
 441 };
 442
 443 static struct platform_device bast_device_asix = {
 444         .name           = "ax88796",
 445         .id             = 0,
 446         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 447         .resource       = bast_asix_resource,
 448         .dev            = {
 449                 .platform_data = &bast_asix_platdata
 450         }
 451 };
 452
 453 /* Asix AX88796 10/100 ethernet controller parallel port */
 454
 455 static struct resource bast_asixpp_resource[] = {
 456         [0] = {
 457                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
 458                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
 459                 .flags = IORESOURCE_MEM,
 460         }
 461 };
 462
 463 static struct platform_device bast_device_axpp = {
 464         .name           = "ax88796-pp",
 465         .id             = 0,
 466         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 467         .resource       = bast_asixpp_resource,
 468 };
 469
 470 /* LCD/VGA controller */
 471
 472 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 473         {
 474                 .type           = S3C2410_LCDCON1_TFT,
 475                 .width          = 640,
 476                 .height         = 480,
 477
 478                 .pixclock       = 33333,
 479                 .xres           = 640,
 480                 .yres           = 480,
 481                 .bpp            = 4,
 482                 .left_margin    = 40,
 483                 .right_margin   = 20,
 484                 .hsync_len      = 88,
 485                 .upper_margin   = 30,
 486                 .lower_margin   = 32,
 487                 .vsync_len      = 3,
 488
 489                 .lcdcon5        = 0x00014b02,
 490         },
 491         {
 492                 .type           = S3C2410_LCDCON1_TFT,
 493                 .width          = 640,
 494                 .height         = 480,
 495
 496                 .pixclock       = 33333,
 497                 .xres           = 640,
 498                 .yres           = 480,
 499                 .bpp            = 8,
 500                 .left_margin    = 40,
 501                 .right_margin   = 20,
 502                 .hsync_len      = 88,
 503                 .upper_margin   = 30,
 504                 .lower_margin   = 32,
 505                 .vsync_len      = 3,
 506
 507                 .lcdcon5        = 0x00014b02,
 508         },
 509         {
 510                 .type           = S3C2410_LCDCON1_TFT,
 511                 .width          = 640,
 512                 .height         = 480,
 513
 514                 .pixclock       = 33333,
 515                 .xres           = 640,
 516                 .yres           = 480,
 517                 .bpp            = 16,
 518                 .left_margin    = 40,
 519                 .right_margin   = 20,
 520                 .hsync_len      = 88,
 521                 .upper_margin   = 30,
 522                 .lower_margin   = 32,
 523                 .vsync_len      = 3,
 524
 525                 .lcdcon5        = 0x00014b02,
 526         },
 527 };
 528
 529 /* LCD/VGA controller */
 530
 531 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 532
 533         .displays = bast_lcd_info,
 534         .num_displays = ARRAY_SIZE(bast_lcd_info),
 535         .default_display = 1,
 536 };
 537
 538 /* I2C devices fitted. */
 539
 540 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 541         {
 542                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 543         }, {
 544                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 545         }, {
 546                 I2C_BOARD_INFO("ch7013", 0x75),
 547         },
 548 };
 549
 550 static struct s3c_hwmon_pdata bast_hwmon_info = {
 551         /* LCD contrast (0-6.6V) */
 552         .in[0] = &(struct s3c_hwmon_chcfg) {
 553                 .name           = "lcd-contrast",
 554                 .mult           = 3300,
 555                 .div            = 512,
 556         },
 557         /* LED current feedback */
 558         .in[1] = &(struct s3c_hwmon_chcfg) {
 559                 .name           = "led-feedback",
 560                 .mult           = 3300,
 561                 .div            = 1024,
 562         },
 563         /* LCD feedback (0-6.6V) */
 564         .in[2] = &(struct s3c_hwmon_chcfg) {
 565                 .name           = "lcd-feedback",
 566                 .mult           = 3300,
 567                 .div            = 512,
 568         },
 569         /* Vcore (1.8-2.0V), Vref 3.3V  */
 570         .in[3] = &(struct s3c_hwmon_chcfg) {
 571                 .name           = "vcore",
 572                 .mult           = 3300,
 573                 .div            = 1024,
 574         },
 575 };
 576
 577 /* Standard BAST devices */
 578 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 579
 580 static struct platform_device *bast_devices[] __initdata = {
 581         &s3c_device_ohci,
 582         &s3c_device_lcd,
 583         &s3c_device_wdt,
 584         &s3c_device_i2c0,
 585         &s3c_device_rtc,
 586         &s3c_device_nand,
 587         &s3c_device_adc,
 588         &s3c_device_hwmon,
 589         &bast_device_dm9k,
 590         &bast_device_asix,
 591         &bast_device_axpp,
 592         &bast_sio,
 593 };
 594
 595 static struct clk *bast_clocks[] __initdata = {
 596         &s3c24xx_dclk0,
 597         &s3c24xx_dclk1,
 598         &s3c24xx_clkout0,
 599         &s3c24xx_clkout1,
 600         &s3c24xx_uclk,
 601 };
 602
 603 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 604         .refresh        = 7800, /* 7.8usec */
 605         .auto_io        = 1,
 606         .need_io        = 1,
 607 };
 608
 609 static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 610         .have_mic       = 1,
 611         .have_lout      = 1,
 612 };
 613
 614 static void __init bast_map_io(void)
 615 {
 616         /* initialise the clocks */
 617
 618         s3c24xx_dclk0.parent = &clk_upll;
 619         s3c24xx_dclk0.rate   = 12*1000*1000;
 620
 621         s3c24xx_dclk1.parent = &clk_upll;
 622         s3c24xx_dclk1.rate   = 24*1000*1000;
 623
 624         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 625         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 626
 627         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 628
 629         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 630
 631         s3c_hwmon_set_platdata(&bast_hwmon_info);
 632
 633         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 634         s3c24xx_init_clocks(0);
 635         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 636 }
 637
 638 static void __init bast_init(void)
 639 {
 640         register_syscore_ops(&bast_pm_syscore_ops);
 641
 642         s3c_i2c0_set_platdata(&bast_i2c_info);
 643         s3c_nand_set_platdata(&bast_nand_info);
 644         s3c24xx_fb_set_platdata(&bast_fb_info);
 645         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 646
 647         i2c_register_board_info(0, bast_i2c_devs,
 648                                 ARRAY_SIZE(bast_i2c_devs));
 649
 650         usb_simtec_init();
 651         nor_simtec_init();
 652         simtec_audio_add(NULL, true, &bast_audio);
 653
 654         WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
 655
 656         s3c_cpufreq_setboard(&bast_cpufreq);
 657 }
 658
 659 MACHINE_START(BAST, "Simtec-BAST")
 660         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 661         .atag_offset    = 0x100,
 662         .map_io         = bast_map_io,
 663         .init_irq       = s3c24xx_init_irq,
 664         .init_machine   = bast_init,
 665         .timer          = &s3c24xx_timer,
 666         .restart        = s3c2410_restart,
 667 MACHINE_END