1 /* linux/arch/arm/mach-s3c2412/clock.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412,S3C2413 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/device.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
44 #include <plat/s3c2412.h>
45 #include <plat/clock.h>
48 /* We currently have to assume that the system is running
49 * from the XTPll input, and that all ***REFCLKs are being
50 * fed from it, as we cannot read the state of OM[4] from
53 * It would be possible for each board initialisation to
54 * set the correct muxing at initialisation
57 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
59 unsigned int clocks = clk->ctrlbit;
62 clkcon = __raw_readl(S3C2410_CLKCON);
69 __raw_writel(clkcon, S3C2410_CLKCON);
74 static int s3c2412_upll_enable(struct clk *clk, int enable)
76 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
77 unsigned long orig = upllcon;
80 upllcon |= S3C2412_PLLCON_OFF;
82 upllcon &= ~S3C2412_PLLCON_OFF;
84 __raw_writel(upllcon, S3C2410_UPLLCON);
86 /* allow ~150uS for the PLL to settle and lock */
88 if (enable && (orig & S3C2412_PLLCON_OFF))
94 /* clock selections */
96 static struct clk clk_erefclk = {
100 static struct clk clk_urefclk = {
104 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
106 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
108 if (parent == &clk_urefclk)
109 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
110 else if (parent == &clk_upll)
111 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
115 clk->parent = parent;
117 __raw_writel(clksrc, S3C2412_CLKSRC);
121 static struct clk clk_usysclk = {
124 .ops = &(struct clk_ops) {
125 .set_parent = s3c2412_setparent_usysclk,
129 static struct clk clk_mrefclk = {
134 static struct clk clk_mdivclk = {
139 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
141 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
143 if (parent == &clk_usysclk)
144 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
145 else if (parent == &clk_h)
146 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
150 clk->parent = parent;
152 __raw_writel(clksrc, S3C2412_CLKSRC);
156 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
159 unsigned long parent_rate = clk_get_rate(clk->parent);
162 if (rate > parent_rate)
165 div = parent_rate / rate;
169 return parent_rate / div;
172 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
174 unsigned long parent_rate = clk_get_rate(clk->parent);
175 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
177 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
180 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
182 unsigned long parent_rate = clk_get_rate(clk->parent);
183 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
185 rate = s3c2412_roundrate_usbsrc(clk, rate);
187 if ((parent_rate / rate) == 2)
188 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
190 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
192 __raw_writel(clkdivn, S3C2410_CLKDIVN);
196 static struct clk clk_usbsrc = {
198 .ops = &(struct clk_ops) {
199 .get_rate = s3c2412_getrate_usbsrc,
200 .set_rate = s3c2412_setrate_usbsrc,
201 .round_rate = s3c2412_roundrate_usbsrc,
202 .set_parent = s3c2412_setparent_usbsrc,
206 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
208 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
210 if (parent == &clk_mdivclk)
211 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
212 else if (parent == &clk_mpll)
213 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
217 clk->parent = parent;
219 __raw_writel(clksrc, S3C2412_CLKSRC);
223 static struct clk clk_msysclk = {
225 .ops = &(struct clk_ops) {
226 .set_parent = s3c2412_setparent_msysclk,
230 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
233 unsigned long clkdiv;
236 /* Note, we current equate fclk andf msysclk for S3C2412 */
238 if (parent == &clk_msysclk || parent == &clk_f)
240 else if (parent == &clk_h)
241 dvs = S3C2412_CLKDIVN_DVSEN;
245 clk->parent = parent;
247 /* update this under irq lockdown, clkdivn is not protected
248 * by the clock system. */
250 local_irq_save(flags);
252 clkdiv = __raw_readl(S3C2410_CLKDIVN);
253 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
255 __raw_writel(clkdiv, S3C2410_CLKDIVN);
257 local_irq_restore(flags);
262 static struct clk clk_armclk = {
264 .parent = &clk_msysclk,
265 .ops = &(struct clk_ops) {
266 .set_parent = s3c2412_setparent_armclk,
270 /* these next clocks have an divider immediately after them,
271 * so we can register them with their divider and leave out the
272 * intermediate clock stage
274 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
277 unsigned long parent_rate = clk_get_rate(clk->parent);
280 if (rate > parent_rate)
283 /* note, we remove the +/- 1 calculations as they cancel out */
285 div = (rate / parent_rate);
292 return parent_rate / div;
295 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
297 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
299 if (parent == &clk_erefclk)
300 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
301 else if (parent == &clk_mpll)
302 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
306 clk->parent = parent;
308 __raw_writel(clksrc, S3C2412_CLKSRC);
312 static unsigned long s3c2412_getrate_uart(struct clk *clk)
314 unsigned long parent_rate = clk_get_rate(clk->parent);
315 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
317 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
318 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
320 return parent_rate / (div + 1);
323 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
325 unsigned long parent_rate = clk_get_rate(clk->parent);
326 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
328 rate = s3c2412_roundrate_clksrc(clk, rate);
330 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
331 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
333 __raw_writel(clkdivn, S3C2410_CLKDIVN);
337 static struct clk clk_uart = {
339 .ops = &(struct clk_ops) {
340 .get_rate = s3c2412_getrate_uart,
341 .set_rate = s3c2412_setrate_uart,
342 .set_parent = s3c2412_setparent_uart,
343 .round_rate = s3c2412_roundrate_clksrc,
347 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
349 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
351 if (parent == &clk_erefclk)
352 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
353 else if (parent == &clk_mpll)
354 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
358 clk->parent = parent;
360 __raw_writel(clksrc, S3C2412_CLKSRC);
364 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
366 unsigned long parent_rate = clk_get_rate(clk->parent);
367 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
369 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
370 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
372 return parent_rate / (div + 1);
375 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
377 unsigned long parent_rate = clk_get_rate(clk->parent);
378 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
380 rate = s3c2412_roundrate_clksrc(clk, rate);
382 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
383 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
385 __raw_writel(clkdivn, S3C2410_CLKDIVN);
389 static struct clk clk_i2s = {
391 .ops = &(struct clk_ops) {
392 .get_rate = s3c2412_getrate_i2s,
393 .set_rate = s3c2412_setrate_i2s,
394 .set_parent = s3c2412_setparent_i2s,
395 .round_rate = s3c2412_roundrate_clksrc,
399 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
401 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
403 if (parent == &clk_usysclk)
404 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
405 else if (parent == &clk_h)
406 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
410 clk->parent = parent;
412 __raw_writel(clksrc, S3C2412_CLKSRC);
415 static unsigned long s3c2412_getrate_cam(struct clk *clk)
417 unsigned long parent_rate = clk_get_rate(clk->parent);
418 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
420 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
421 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
423 return parent_rate / (div + 1);
426 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
428 unsigned long parent_rate = clk_get_rate(clk->parent);
429 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
431 rate = s3c2412_roundrate_clksrc(clk, rate);
433 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
434 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
436 __raw_writel(clkdivn, S3C2410_CLKDIVN);
440 static struct clk clk_cam = {
441 .name = "camif-upll", /* same as 2440 name */
442 .ops = &(struct clk_ops) {
443 .get_rate = s3c2412_getrate_cam,
444 .set_rate = s3c2412_setrate_cam,
445 .set_parent = s3c2412_setparent_cam,
446 .round_rate = s3c2412_roundrate_clksrc,
450 /* standard clock definitions */
452 static struct clk init_clocks_disable[] = {
456 .enable = s3c2412_clkcon_enable,
457 .ctrlbit = S3C2412_CLKCON_NAND,
461 .enable = s3c2412_clkcon_enable,
462 .ctrlbit = S3C2412_CLKCON_SDI,
466 .enable = s3c2412_clkcon_enable,
467 .ctrlbit = S3C2412_CLKCON_ADC,
471 .enable = s3c2412_clkcon_enable,
472 .ctrlbit = S3C2412_CLKCON_IIC,
476 .enable = s3c2412_clkcon_enable,
477 .ctrlbit = S3C2412_CLKCON_IIS,
481 .enable = s3c2412_clkcon_enable,
482 .ctrlbit = S3C2412_CLKCON_SPI,
486 static struct clk init_clocks[] = {
490 .enable = s3c2412_clkcon_enable,
491 .ctrlbit = S3C2412_CLKCON_DMA0,
495 .enable = s3c2412_clkcon_enable,
496 .ctrlbit = S3C2412_CLKCON_DMA1,
500 .enable = s3c2412_clkcon_enable,
501 .ctrlbit = S3C2412_CLKCON_DMA2,
505 .enable = s3c2412_clkcon_enable,
506 .ctrlbit = S3C2412_CLKCON_DMA3,
510 .enable = s3c2412_clkcon_enable,
511 .ctrlbit = S3C2412_CLKCON_LCDC,
515 .enable = s3c2412_clkcon_enable,
516 .ctrlbit = S3C2412_CLKCON_GPIO,
520 .enable = s3c2412_clkcon_enable,
521 .ctrlbit = S3C2412_CLKCON_USBH,
523 .name = "usb-device",
525 .enable = s3c2412_clkcon_enable,
526 .ctrlbit = S3C2412_CLKCON_USBD,
530 .enable = s3c2412_clkcon_enable,
531 .ctrlbit = S3C2412_CLKCON_PWMT,
534 .devname = "s3c2412-uart.0",
536 .enable = s3c2412_clkcon_enable,
537 .ctrlbit = S3C2412_CLKCON_UART0,
540 .devname = "s3c2412-uart.1",
542 .enable = s3c2412_clkcon_enable,
543 .ctrlbit = S3C2412_CLKCON_UART1,
546 .devname = "s3c2412-uart.2",
548 .enable = s3c2412_clkcon_enable,
549 .ctrlbit = S3C2412_CLKCON_UART2,
553 .enable = s3c2412_clkcon_enable,
554 .ctrlbit = S3C2412_CLKCON_RTC,
560 .name = "usb-bus-gadget",
561 .parent = &clk_usb_bus,
562 .enable = s3c2412_clkcon_enable,
563 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
565 .name = "usb-bus-host",
566 .parent = &clk_usb_bus,
567 .enable = s3c2412_clkcon_enable,
568 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
572 /* clocks to add where we need to check their parentage */
581 static struct clk_init clks_src[] __initdata = {
584 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
585 .src_0 = &clk_urefclk,
589 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
590 .src_0 = &clk_erefclk,
594 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
595 .src_0 = &clk_usysclk,
599 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
600 .src_0 = &clk_mdivclk,
604 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
605 .src_0 = &clk_erefclk,
609 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
610 .src_0 = &clk_usysclk,
612 /* here we assume OM[4] select xtal */
615 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
620 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
626 /* s3c2412_clk_initparents
628 * Initialise the parents for the clocks that we get at start-time
631 static void __init s3c2412_clk_initparents(void)
633 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
634 struct clk_init *cip = clks_src;
639 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
640 ret = s3c24xx_register_clock(cip->clk);
642 printk(KERN_ERR "Failed to register clock %s (%d)\n",
643 cip->clk->name, ret);
646 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
648 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
649 clk_set_parent(cip->clk, src);
653 /* clocks to add straight away */
655 static struct clk *clks[] __initdata = {
662 static struct clk_lookup s3c2412_clk_lookup[] = {
663 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
664 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
665 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
668 int __init s3c2412_baseclk_add(void)
670 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
676 clk_upll.enable = s3c2412_upll_enable;
677 clk_usb_bus.parent = &clk_usbsrc;
678 clk_usb_bus.rate = 0x0;
680 clk_f.parent = &clk_msysclk;
682 s3c2412_clk_initparents();
684 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
687 ret = s3c24xx_register_clock(clkp);
689 printk(KERN_ERR "Failed to register clock %s (%d)\n",
694 /* set the dvs state according to what we got at boot time */
696 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
699 clk_armclk.parent = &clk_h;
701 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
703 /* ensure usb bus clock is within correct rate of 48MHz */
705 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
706 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
708 /* for the moment, let's use the UPLL, and see if we can
711 clk_set_parent(&clk_usysclk, &clk_upll);
712 clk_set_parent(&clk_usbsrc, &clk_usysclk);
713 clk_set_rate(&clk_usbsrc, 48*1000*1000);
716 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
717 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
718 print_mhz(clk_get_rate(&clk_upll)),
719 print_mhz(clk_get_rate(&clk_usb_bus)));
721 /* register clocks from clock array */
724 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
725 /* ensure that we note the clock state */
727 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
729 ret = s3c24xx_register_clock(clkp);
731 printk(KERN_ERR "Failed to register clock %s (%d)\n",
736 /* We must be careful disabling the clocks we are not intending to
737 * be using at boot time, as subsystems such as the LCD which do
738 * their own DMA requests to the bus can cause the system to lockup
739 * if they where in the middle of requesting bus access.
741 * Disabling the LCD clock if the LCD is active is very dangerous,
742 * and therefore the bootloader should be careful to not enable
743 * the LCD clock if it is not needed.
746 /* install (and disable) the clocks we do not need immediately */
748 clkp = init_clocks_disable;
749 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
751 ret = s3c24xx_register_clock(clkp);
753 printk(KERN_ERR "Failed to register clock %s (%d)\n",
757 s3c2412_clkcon_enable(clkp, 0);
760 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));