1 /* linux/arch/arm/mach-s3c2412/clock.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412,S3C2413 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/device.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
36 #include <asm/mach/map.h>
38 #include <mach/hardware.h>
40 #include <plat/regs-serial.h>
41 #include <mach/regs-clock.h>
42 #include <mach/regs-gpio.h>
44 #include <plat/clock.h>
47 /* We currently have to assume that the system is running
48 * from the XTPll input, and that all ***REFCLKs are being
49 * fed from it, as we cannot read the state of OM[4] from
52 * It would be possible for each board initialisation to
53 * set the correct muxing at initialisation
56 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
58 unsigned int clocks = clk->ctrlbit;
61 clkcon = __raw_readl(S3C2410_CLKCON);
68 __raw_writel(clkcon, S3C2410_CLKCON);
73 static int s3c2412_upll_enable(struct clk *clk, int enable)
75 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
76 unsigned long orig = upllcon;
79 upllcon |= S3C2412_PLLCON_OFF;
81 upllcon &= ~S3C2412_PLLCON_OFF;
83 __raw_writel(upllcon, S3C2410_UPLLCON);
85 /* allow ~150uS for the PLL to settle and lock */
87 if (enable && (orig & S3C2412_PLLCON_OFF))
93 /* clock selections */
95 static struct clk clk_erefclk = {
99 static struct clk clk_urefclk = {
103 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
105 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
107 if (parent == &clk_urefclk)
108 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
109 else if (parent == &clk_upll)
110 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
114 clk->parent = parent;
116 __raw_writel(clksrc, S3C2412_CLKSRC);
120 static struct clk clk_usysclk = {
123 .ops = &(struct clk_ops) {
124 .set_parent = s3c2412_setparent_usysclk,
128 static struct clk clk_mrefclk = {
133 static struct clk clk_mdivclk = {
138 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
140 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
142 if (parent == &clk_usysclk)
143 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
144 else if (parent == &clk_h)
145 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
149 clk->parent = parent;
151 __raw_writel(clksrc, S3C2412_CLKSRC);
155 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
158 unsigned long parent_rate = clk_get_rate(clk->parent);
161 if (rate > parent_rate)
164 div = parent_rate / rate;
168 return parent_rate / div;
171 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
173 unsigned long parent_rate = clk_get_rate(clk->parent);
174 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
176 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
179 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
181 unsigned long parent_rate = clk_get_rate(clk->parent);
182 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
184 rate = s3c2412_roundrate_usbsrc(clk, rate);
186 if ((parent_rate / rate) == 2)
187 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
189 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
191 __raw_writel(clkdivn, S3C2410_CLKDIVN);
195 static struct clk clk_usbsrc = {
197 .ops = &(struct clk_ops) {
198 .get_rate = s3c2412_getrate_usbsrc,
199 .set_rate = s3c2412_setrate_usbsrc,
200 .round_rate = s3c2412_roundrate_usbsrc,
201 .set_parent = s3c2412_setparent_usbsrc,
205 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
207 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
209 if (parent == &clk_mdivclk)
210 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
211 else if (parent == &clk_mpll)
212 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
216 clk->parent = parent;
218 __raw_writel(clksrc, S3C2412_CLKSRC);
222 static struct clk clk_msysclk = {
224 .ops = &(struct clk_ops) {
225 .set_parent = s3c2412_setparent_msysclk,
229 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
232 unsigned long clkdiv;
235 /* Note, we current equate fclk andf msysclk for S3C2412 */
237 if (parent == &clk_msysclk || parent == &clk_f)
239 else if (parent == &clk_h)
240 dvs = S3C2412_CLKDIVN_DVSEN;
244 clk->parent = parent;
246 /* update this under irq lockdown, clkdivn is not protected
247 * by the clock system. */
249 local_irq_save(flags);
251 clkdiv = __raw_readl(S3C2410_CLKDIVN);
252 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
254 __raw_writel(clkdiv, S3C2410_CLKDIVN);
256 local_irq_restore(flags);
261 static struct clk clk_armclk = {
263 .parent = &clk_msysclk,
264 .ops = &(struct clk_ops) {
265 .set_parent = s3c2412_setparent_armclk,
269 /* these next clocks have an divider immediately after them,
270 * so we can register them with their divider and leave out the
271 * intermediate clock stage
273 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
276 unsigned long parent_rate = clk_get_rate(clk->parent);
279 if (rate > parent_rate)
282 /* note, we remove the +/- 1 calculations as they cancel out */
284 div = (rate / parent_rate);
291 return parent_rate / div;
294 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
296 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
298 if (parent == &clk_erefclk)
299 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
300 else if (parent == &clk_mpll)
301 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
305 clk->parent = parent;
307 __raw_writel(clksrc, S3C2412_CLKSRC);
311 static unsigned long s3c2412_getrate_uart(struct clk *clk)
313 unsigned long parent_rate = clk_get_rate(clk->parent);
314 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
316 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
317 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
319 return parent_rate / (div + 1);
322 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
324 unsigned long parent_rate = clk_get_rate(clk->parent);
325 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
327 rate = s3c2412_roundrate_clksrc(clk, rate);
329 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
330 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
332 __raw_writel(clkdivn, S3C2410_CLKDIVN);
336 static struct clk clk_uart = {
338 .ops = &(struct clk_ops) {
339 .get_rate = s3c2412_getrate_uart,
340 .set_rate = s3c2412_setrate_uart,
341 .set_parent = s3c2412_setparent_uart,
342 .round_rate = s3c2412_roundrate_clksrc,
346 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
348 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
350 if (parent == &clk_erefclk)
351 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
352 else if (parent == &clk_mpll)
353 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
357 clk->parent = parent;
359 __raw_writel(clksrc, S3C2412_CLKSRC);
363 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
365 unsigned long parent_rate = clk_get_rate(clk->parent);
366 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
368 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
369 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
371 return parent_rate / (div + 1);
374 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
376 unsigned long parent_rate = clk_get_rate(clk->parent);
377 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
379 rate = s3c2412_roundrate_clksrc(clk, rate);
381 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
382 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
384 __raw_writel(clkdivn, S3C2410_CLKDIVN);
388 static struct clk clk_i2s = {
390 .ops = &(struct clk_ops) {
391 .get_rate = s3c2412_getrate_i2s,
392 .set_rate = s3c2412_setrate_i2s,
393 .set_parent = s3c2412_setparent_i2s,
394 .round_rate = s3c2412_roundrate_clksrc,
398 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
400 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
402 if (parent == &clk_usysclk)
403 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
404 else if (parent == &clk_h)
405 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
409 clk->parent = parent;
411 __raw_writel(clksrc, S3C2412_CLKSRC);
414 static unsigned long s3c2412_getrate_cam(struct clk *clk)
416 unsigned long parent_rate = clk_get_rate(clk->parent);
417 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
419 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
420 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
422 return parent_rate / (div + 1);
425 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
427 unsigned long parent_rate = clk_get_rate(clk->parent);
428 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
430 rate = s3c2412_roundrate_clksrc(clk, rate);
432 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
433 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
435 __raw_writel(clkdivn, S3C2410_CLKDIVN);
439 static struct clk clk_cam = {
440 .name = "camif-upll", /* same as 2440 name */
441 .ops = &(struct clk_ops) {
442 .get_rate = s3c2412_getrate_cam,
443 .set_rate = s3c2412_setrate_cam,
444 .set_parent = s3c2412_setparent_cam,
445 .round_rate = s3c2412_roundrate_clksrc,
449 /* standard clock definitions */
451 static struct clk init_clocks_disable[] = {
455 .enable = s3c2412_clkcon_enable,
456 .ctrlbit = S3C2412_CLKCON_NAND,
460 .enable = s3c2412_clkcon_enable,
461 .ctrlbit = S3C2412_CLKCON_SDI,
465 .enable = s3c2412_clkcon_enable,
466 .ctrlbit = S3C2412_CLKCON_ADC,
470 .enable = s3c2412_clkcon_enable,
471 .ctrlbit = S3C2412_CLKCON_IIC,
475 .enable = s3c2412_clkcon_enable,
476 .ctrlbit = S3C2412_CLKCON_IIS,
480 .enable = s3c2412_clkcon_enable,
481 .ctrlbit = S3C2412_CLKCON_SPI,
485 static struct clk init_clocks[] = {
489 .enable = s3c2412_clkcon_enable,
490 .ctrlbit = S3C2412_CLKCON_DMA0,
494 .enable = s3c2412_clkcon_enable,
495 .ctrlbit = S3C2412_CLKCON_DMA1,
499 .enable = s3c2412_clkcon_enable,
500 .ctrlbit = S3C2412_CLKCON_DMA2,
504 .enable = s3c2412_clkcon_enable,
505 .ctrlbit = S3C2412_CLKCON_DMA3,
509 .enable = s3c2412_clkcon_enable,
510 .ctrlbit = S3C2412_CLKCON_LCDC,
514 .enable = s3c2412_clkcon_enable,
515 .ctrlbit = S3C2412_CLKCON_GPIO,
519 .enable = s3c2412_clkcon_enable,
520 .ctrlbit = S3C2412_CLKCON_USBH,
522 .name = "usb-device",
524 .enable = s3c2412_clkcon_enable,
525 .ctrlbit = S3C2412_CLKCON_USBD,
529 .enable = s3c2412_clkcon_enable,
530 .ctrlbit = S3C2412_CLKCON_PWMT,
533 .devname = "s3c2412-uart.0",
535 .enable = s3c2412_clkcon_enable,
536 .ctrlbit = S3C2412_CLKCON_UART0,
539 .devname = "s3c2412-uart.1",
541 .enable = s3c2412_clkcon_enable,
542 .ctrlbit = S3C2412_CLKCON_UART1,
545 .devname = "s3c2412-uart.2",
547 .enable = s3c2412_clkcon_enable,
548 .ctrlbit = S3C2412_CLKCON_UART2,
552 .enable = s3c2412_clkcon_enable,
553 .ctrlbit = S3C2412_CLKCON_RTC,
559 .name = "usb-bus-gadget",
560 .parent = &clk_usb_bus,
561 .enable = s3c2412_clkcon_enable,
562 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
564 .name = "usb-bus-host",
565 .parent = &clk_usb_bus,
566 .enable = s3c2412_clkcon_enable,
567 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
571 /* clocks to add where we need to check their parentage */
580 static struct clk_init clks_src[] __initdata = {
583 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
584 .src_0 = &clk_urefclk,
588 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
589 .src_0 = &clk_erefclk,
593 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
594 .src_0 = &clk_usysclk,
598 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
599 .src_0 = &clk_mdivclk,
603 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
604 .src_0 = &clk_erefclk,
608 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
609 .src_0 = &clk_usysclk,
611 /* here we assume OM[4] select xtal */
614 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
619 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
625 /* s3c2412_clk_initparents
627 * Initialise the parents for the clocks that we get at start-time
630 static void __init s3c2412_clk_initparents(void)
632 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
633 struct clk_init *cip = clks_src;
638 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
639 ret = s3c24xx_register_clock(cip->clk);
641 printk(KERN_ERR "Failed to register clock %s (%d)\n",
642 cip->clk->name, ret);
645 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
647 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
648 clk_set_parent(cip->clk, src);
652 /* clocks to add straight away */
654 static struct clk *clks[] __initdata = {
661 static struct clk_lookup s3c2412_clk_lookup[] = {
662 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
663 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
664 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
667 int __init s3c2412_baseclk_add(void)
669 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
675 clk_upll.enable = s3c2412_upll_enable;
676 clk_usb_bus.parent = &clk_usbsrc;
677 clk_usb_bus.rate = 0x0;
679 clk_f.parent = &clk_msysclk;
681 s3c2412_clk_initparents();
683 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
686 ret = s3c24xx_register_clock(clkp);
688 printk(KERN_ERR "Failed to register clock %s (%d)\n",
693 /* set the dvs state according to what we got at boot time */
695 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
698 clk_armclk.parent = &clk_h;
700 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
702 /* ensure usb bus clock is within correct rate of 48MHz */
704 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
705 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
707 /* for the moment, let's use the UPLL, and see if we can
710 clk_set_parent(&clk_usysclk, &clk_upll);
711 clk_set_parent(&clk_usbsrc, &clk_usysclk);
712 clk_set_rate(&clk_usbsrc, 48*1000*1000);
715 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
716 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
717 print_mhz(clk_get_rate(&clk_upll)),
718 print_mhz(clk_get_rate(&clk_usb_bus)));
720 /* register clocks from clock array */
723 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
724 /* ensure that we note the clock state */
726 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
728 ret = s3c24xx_register_clock(clkp);
730 printk(KERN_ERR "Failed to register clock %s (%d)\n",
735 /* We must be careful disabling the clocks we are not intending to
736 * be using at boot time, as subsystems such as the LCD which do
737 * their own DMA requests to the bus can cause the system to lockup
738 * if they where in the middle of requesting bus access.
740 * Disabling the LCD clock if the LCD is active is very dangerous,
741 * and therefore the bootloader should be careful to not enable
742 * the LCD clock if it is not needed.
745 /* install (and disable) the clocks we do not need immediately */
747 clkp = init_clocks_disable;
748 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
750 ret = s3c24xx_register_clock(clkp);
752 printk(KERN_ERR "Failed to register clock %s (%d)\n",
756 s3c2412_clkcon_enable(clkp, 0);
759 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));