1 /* linux/arch/arm/mach-s3c2412/clock.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2412,S3C2413 Clock control support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/device.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33 #include <linux/serial_core.h>
34 #include <linux/serial_s3c.h>
37 #include <asm/mach/map.h>
39 #include <mach/hardware.h>
40 #include <mach/regs-clock.h>
41 #include <mach/regs-gpio.h>
43 #include <plat/clock.h>
46 /* We currently have to assume that the system is running
47 * from the XTPll input, and that all ***REFCLKs are being
48 * fed from it, as we cannot read the state of OM[4] from
51 * It would be possible for each board initialisation to
52 * set the correct muxing at initialisation
55 static int s3c2412_clkcon_enable(struct clk *clk, int enable)
57 unsigned int clocks = clk->ctrlbit;
60 clkcon = __raw_readl(S3C2410_CLKCON);
67 __raw_writel(clkcon, S3C2410_CLKCON);
72 static int s3c2412_upll_enable(struct clk *clk, int enable)
74 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
75 unsigned long orig = upllcon;
78 upllcon |= S3C2412_PLLCON_OFF;
80 upllcon &= ~S3C2412_PLLCON_OFF;
82 __raw_writel(upllcon, S3C2410_UPLLCON);
84 /* allow ~150uS for the PLL to settle and lock */
86 if (enable && (orig & S3C2412_PLLCON_OFF))
92 /* clock selections */
94 static struct clk clk_erefclk = {
98 static struct clk clk_urefclk = {
102 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
104 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
106 if (parent == &clk_urefclk)
107 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
108 else if (parent == &clk_upll)
109 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
113 clk->parent = parent;
115 __raw_writel(clksrc, S3C2412_CLKSRC);
119 static struct clk clk_usysclk = {
122 .ops = &(struct clk_ops) {
123 .set_parent = s3c2412_setparent_usysclk,
127 static struct clk clk_mrefclk = {
132 static struct clk clk_mdivclk = {
137 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
139 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
141 if (parent == &clk_usysclk)
142 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
143 else if (parent == &clk_h)
144 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
148 clk->parent = parent;
150 __raw_writel(clksrc, S3C2412_CLKSRC);
154 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
157 unsigned long parent_rate = clk_get_rate(clk->parent);
160 if (rate > parent_rate)
163 div = parent_rate / rate;
167 return parent_rate / div;
170 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
172 unsigned long parent_rate = clk_get_rate(clk->parent);
173 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
175 return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
178 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
180 unsigned long parent_rate = clk_get_rate(clk->parent);
181 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
183 rate = s3c2412_roundrate_usbsrc(clk, rate);
185 if ((parent_rate / rate) == 2)
186 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
188 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
190 __raw_writel(clkdivn, S3C2410_CLKDIVN);
194 static struct clk clk_usbsrc = {
196 .ops = &(struct clk_ops) {
197 .get_rate = s3c2412_getrate_usbsrc,
198 .set_rate = s3c2412_setrate_usbsrc,
199 .round_rate = s3c2412_roundrate_usbsrc,
200 .set_parent = s3c2412_setparent_usbsrc,
204 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
206 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
208 if (parent == &clk_mdivclk)
209 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
210 else if (parent == &clk_mpll)
211 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
215 clk->parent = parent;
217 __raw_writel(clksrc, S3C2412_CLKSRC);
221 static struct clk clk_msysclk = {
223 .ops = &(struct clk_ops) {
224 .set_parent = s3c2412_setparent_msysclk,
228 static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
231 unsigned long clkdiv;
234 /* Note, we current equate fclk andf msysclk for S3C2412 */
236 if (parent == &clk_msysclk || parent == &clk_f)
238 else if (parent == &clk_h)
239 dvs = S3C2412_CLKDIVN_DVSEN;
243 clk->parent = parent;
245 /* update this under irq lockdown, clkdivn is not protected
246 * by the clock system. */
248 local_irq_save(flags);
250 clkdiv = __raw_readl(S3C2410_CLKDIVN);
251 clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
253 __raw_writel(clkdiv, S3C2410_CLKDIVN);
255 local_irq_restore(flags);
260 static struct clk clk_armclk = {
262 .parent = &clk_msysclk,
263 .ops = &(struct clk_ops) {
264 .set_parent = s3c2412_setparent_armclk,
268 /* these next clocks have an divider immediately after them,
269 * so we can register them with their divider and leave out the
270 * intermediate clock stage
272 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
275 unsigned long parent_rate = clk_get_rate(clk->parent);
278 if (rate > parent_rate)
281 /* note, we remove the +/- 1 calculations as they cancel out */
283 div = (rate / parent_rate);
290 return parent_rate / div;
293 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
295 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
297 if (parent == &clk_erefclk)
298 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
299 else if (parent == &clk_mpll)
300 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
304 clk->parent = parent;
306 __raw_writel(clksrc, S3C2412_CLKSRC);
310 static unsigned long s3c2412_getrate_uart(struct clk *clk)
312 unsigned long parent_rate = clk_get_rate(clk->parent);
313 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
315 div &= S3C2412_CLKDIVN_UARTDIV_MASK;
316 div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
318 return parent_rate / (div + 1);
321 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
323 unsigned long parent_rate = clk_get_rate(clk->parent);
324 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
326 rate = s3c2412_roundrate_clksrc(clk, rate);
328 clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
329 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
331 __raw_writel(clkdivn, S3C2410_CLKDIVN);
335 static struct clk clk_uart = {
337 .ops = &(struct clk_ops) {
338 .get_rate = s3c2412_getrate_uart,
339 .set_rate = s3c2412_setrate_uart,
340 .set_parent = s3c2412_setparent_uart,
341 .round_rate = s3c2412_roundrate_clksrc,
345 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
347 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
349 if (parent == &clk_erefclk)
350 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
351 else if (parent == &clk_mpll)
352 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
356 clk->parent = parent;
358 __raw_writel(clksrc, S3C2412_CLKSRC);
362 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
364 unsigned long parent_rate = clk_get_rate(clk->parent);
365 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
367 div &= S3C2412_CLKDIVN_I2SDIV_MASK;
368 div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
370 return parent_rate / (div + 1);
373 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
375 unsigned long parent_rate = clk_get_rate(clk->parent);
376 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
378 rate = s3c2412_roundrate_clksrc(clk, rate);
380 clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
381 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
383 __raw_writel(clkdivn, S3C2410_CLKDIVN);
387 static struct clk clk_i2s = {
389 .ops = &(struct clk_ops) {
390 .get_rate = s3c2412_getrate_i2s,
391 .set_rate = s3c2412_setrate_i2s,
392 .set_parent = s3c2412_setparent_i2s,
393 .round_rate = s3c2412_roundrate_clksrc,
397 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
399 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
401 if (parent == &clk_usysclk)
402 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
403 else if (parent == &clk_h)
404 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
408 clk->parent = parent;
410 __raw_writel(clksrc, S3C2412_CLKSRC);
413 static unsigned long s3c2412_getrate_cam(struct clk *clk)
415 unsigned long parent_rate = clk_get_rate(clk->parent);
416 unsigned long div = __raw_readl(S3C2410_CLKDIVN);
418 div &= S3C2412_CLKDIVN_CAMDIV_MASK;
419 div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
421 return parent_rate / (div + 1);
424 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
426 unsigned long parent_rate = clk_get_rate(clk->parent);
427 unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
429 rate = s3c2412_roundrate_clksrc(clk, rate);
431 clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
432 clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
434 __raw_writel(clkdivn, S3C2410_CLKDIVN);
438 static struct clk clk_cam = {
439 .name = "camif-upll", /* same as 2440 name */
440 .ops = &(struct clk_ops) {
441 .get_rate = s3c2412_getrate_cam,
442 .set_rate = s3c2412_setrate_cam,
443 .set_parent = s3c2412_setparent_cam,
444 .round_rate = s3c2412_roundrate_clksrc,
448 /* standard clock definitions */
450 static struct clk init_clocks_disable[] = {
454 .enable = s3c2412_clkcon_enable,
455 .ctrlbit = S3C2412_CLKCON_NAND,
459 .enable = s3c2412_clkcon_enable,
460 .ctrlbit = S3C2412_CLKCON_SDI,
464 .enable = s3c2412_clkcon_enable,
465 .ctrlbit = S3C2412_CLKCON_ADC,
469 .enable = s3c2412_clkcon_enable,
470 .ctrlbit = S3C2412_CLKCON_IIC,
474 .enable = s3c2412_clkcon_enable,
475 .ctrlbit = S3C2412_CLKCON_IIS,
479 .enable = s3c2412_clkcon_enable,
480 .ctrlbit = S3C2412_CLKCON_SPI,
484 static struct clk init_clocks[] = {
488 .enable = s3c2412_clkcon_enable,
489 .ctrlbit = S3C2412_CLKCON_DMA0,
493 .enable = s3c2412_clkcon_enable,
494 .ctrlbit = S3C2412_CLKCON_DMA1,
498 .enable = s3c2412_clkcon_enable,
499 .ctrlbit = S3C2412_CLKCON_DMA2,
503 .enable = s3c2412_clkcon_enable,
504 .ctrlbit = S3C2412_CLKCON_DMA3,
508 .enable = s3c2412_clkcon_enable,
509 .ctrlbit = S3C2412_CLKCON_LCDC,
513 .enable = s3c2412_clkcon_enable,
514 .ctrlbit = S3C2412_CLKCON_GPIO,
518 .enable = s3c2412_clkcon_enable,
519 .ctrlbit = S3C2412_CLKCON_USBH,
521 .name = "usb-device",
523 .enable = s3c2412_clkcon_enable,
524 .ctrlbit = S3C2412_CLKCON_USBD,
528 .enable = s3c2412_clkcon_enable,
529 .ctrlbit = S3C2412_CLKCON_PWMT,
532 .devname = "s3c2412-uart.0",
534 .enable = s3c2412_clkcon_enable,
535 .ctrlbit = S3C2412_CLKCON_UART0,
538 .devname = "s3c2412-uart.1",
540 .enable = s3c2412_clkcon_enable,
541 .ctrlbit = S3C2412_CLKCON_UART1,
544 .devname = "s3c2412-uart.2",
546 .enable = s3c2412_clkcon_enable,
547 .ctrlbit = S3C2412_CLKCON_UART2,
551 .enable = s3c2412_clkcon_enable,
552 .ctrlbit = S3C2412_CLKCON_RTC,
558 .name = "usb-bus-gadget",
559 .parent = &clk_usb_bus,
560 .enable = s3c2412_clkcon_enable,
561 .ctrlbit = S3C2412_CLKCON_USB_DEV48,
563 .name = "usb-bus-host",
564 .parent = &clk_usb_bus,
565 .enable = s3c2412_clkcon_enable,
566 .ctrlbit = S3C2412_CLKCON_USB_HOST48,
570 /* clocks to add where we need to check their parentage */
579 static struct clk_init clks_src[] __initdata = {
582 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
583 .src_0 = &clk_urefclk,
587 .bit = S3C2412_CLKSRC_I2SCLK_MPLL,
588 .src_0 = &clk_erefclk,
592 .bit = S3C2412_CLKSRC_CAMCLK_HCLK,
593 .src_0 = &clk_usysclk,
597 .bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
598 .src_0 = &clk_mdivclk,
602 .bit = S3C2412_CLKSRC_UARTCLK_MPLL,
603 .src_0 = &clk_erefclk,
607 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
608 .src_0 = &clk_usysclk,
610 /* here we assume OM[4] select xtal */
613 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
618 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
624 /* s3c2412_clk_initparents
626 * Initialise the parents for the clocks that we get at start-time
629 static void __init s3c2412_clk_initparents(void)
631 unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
632 struct clk_init *cip = clks_src;
637 for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
638 ret = s3c24xx_register_clock(cip->clk);
640 printk(KERN_ERR "Failed to register clock %s (%d)\n",
641 cip->clk->name, ret);
644 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
646 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
647 clk_set_parent(cip->clk, src);
651 /* clocks to add straight away */
653 static struct clk *clks[] __initdata = {
660 static struct clk_lookup s3c2412_clk_lookup[] = {
661 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
662 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
663 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
666 int __init s3c2412_baseclk_add(void)
668 unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
674 clk_upll.enable = s3c2412_upll_enable;
675 clk_usb_bus.parent = &clk_usbsrc;
676 clk_usb_bus.rate = 0x0;
678 clk_f.parent = &clk_msysclk;
680 s3c2412_clk_initparents();
682 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
685 ret = s3c24xx_register_clock(clkp);
687 printk(KERN_ERR "Failed to register clock %s (%d)\n",
692 /* set the dvs state according to what we got at boot time */
694 dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
697 clk_armclk.parent = &clk_h;
699 printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
701 /* ensure usb bus clock is within correct rate of 48MHz */
703 if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
704 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
706 /* for the moment, let's use the UPLL, and see if we can
709 clk_set_parent(&clk_usysclk, &clk_upll);
710 clk_set_parent(&clk_usbsrc, &clk_usysclk);
711 clk_set_rate(&clk_usbsrc, 48*1000*1000);
714 printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
715 (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
716 print_mhz(clk_get_rate(&clk_upll)),
717 print_mhz(clk_get_rate(&clk_usb_bus)));
719 /* register clocks from clock array */
722 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
723 /* ensure that we note the clock state */
725 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
727 ret = s3c24xx_register_clock(clkp);
729 printk(KERN_ERR "Failed to register clock %s (%d)\n",
734 /* We must be careful disabling the clocks we are not intending to
735 * be using at boot time, as subsystems such as the LCD which do
736 * their own DMA requests to the bus can cause the system to lockup
737 * if they where in the middle of requesting bus access.
739 * Disabling the LCD clock if the LCD is active is very dangerous,
740 * and therefore the bootloader should be careful to not enable
741 * the LCD clock if it is not needed.
744 /* install (and disable) the clocks we do not need immediately */
746 clkp = init_clocks_disable;
747 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
749 ret = s3c24xx_register_clock(clkp);
751 printk(KERN_ERR "Failed to register clock %s (%d)\n",
755 s3c2412_clkcon_enable(clkp, 0);
758 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));