2 * Common code for SoCs starting with the S3C2443
4 * Copyright (c) 2007, 2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/init.h>
19 #include <linux/clk.h>
22 #include <mach/regs-s3c2443-clock.h>
24 #include <plat/clock.h>
25 #include <plat/clock-clksrc.h>
28 #include <plat/cpu-freq.h>
31 static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
33 u32 ctrlbit = clk->ctrlbit;
34 u32 con = __raw_readl(reg);
41 __raw_writel(con, reg);
45 int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
47 return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
50 int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
52 return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
55 int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
57 return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
60 /* mpllref is a direct descendant of clk_xtal by default, but it is not
61 * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
62 * such directly equating the two source clocks is impossible.
64 static struct clk clk_mpllref = {
69 static struct clk *clk_epllref_sources[] = {
76 struct clksrc_clk clk_epllref = {
80 .sources = &(struct clksrc_sources) {
81 .sources = clk_epllref_sources,
82 .nr_sources = ARRAY_SIZE(clk_epllref_sources),
84 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
89 * this is sourced from either the EPLL or the EPLLref clock
92 static struct clk *clk_sysclk_sources[] = {
93 [0] = &clk_epllref.clk,
97 struct clksrc_clk clk_esysclk = {
102 .sources = &(struct clksrc_sources) {
103 .sources = clk_sysclk_sources,
104 .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
106 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
109 static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
111 unsigned long parent_rate = clk_get_rate(clk->parent);
112 unsigned long div = __raw_readl(S3C2443_CLKDIV0);
114 div &= S3C2443_CLKDIV0_EXTDIV_MASK;
115 div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
117 return parent_rate / (div + 1);
120 static struct clk clk_mdivclk = {
122 .parent = &clk_mpllref,
123 .ops = &(struct clk_ops) {
124 .get_rate = s3c2443_getrate_mdivclk,
128 static struct clk *clk_msysclk_sources[] = {
135 static struct clksrc_clk clk_msysclk = {
140 .sources = &(struct clksrc_sources) {
141 .sources = clk_msysclk_sources,
142 .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
144 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
149 * this divides the msysclk down to pass to h/p/etc.
152 static unsigned long s3c2443_prediv_getrate(struct clk *clk)
154 unsigned long rate = clk_get_rate(clk->parent);
155 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
157 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
158 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
160 return rate / (clkdiv0 + 1);
163 static struct clk clk_prediv = {
165 .parent = &clk_msysclk.clk,
166 .ops = &(struct clk_ops) {
167 .get_rate = s3c2443_prediv_getrate,
173 * divides the prediv and provides the hclk.
176 static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
178 unsigned long rate = clk_get_rate(clk->parent);
179 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
181 clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
183 return rate / (clkdiv0 + 1);
186 static struct clk_ops clk_h_ops = {
187 .get_rate = s3c2443_hclkdiv_getrate,
192 * divides the hclk and provides the pclk.
195 static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
197 unsigned long rate = clk_get_rate(clk->parent);
198 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
200 clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
202 return rate / (clkdiv0 + 1);
205 static struct clk_ops clk_p_ops = {
206 .get_rate = s3c2443_pclkdiv_getrate,
211 * this clock is sourced from msysclk and can have a number of
212 * divider values applied to it to then be fed into armclk.
215 static unsigned int *armdiv;
216 static int nr_armdiv;
217 static int armdivmask;
219 static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
222 unsigned long parent = clk_get_rate(clk->parent);
224 unsigned best = 256; /* bigger than any value */
231 for (ptr = 0; ptr < nr_armdiv; ptr++) {
234 /* cpufreq provides 266mhz as 266666000 not 266666666 */
235 calc = (parent / div / 1000) * 1000;
236 if (calc <= rate && div < best)
241 return parent / best;
244 static unsigned long s3c2443_armclk_getrate(struct clk *clk)
246 unsigned long rate = clk_get_rate(clk->parent);
247 unsigned long clkcon0;
250 if (!nr_armdiv || !armdivmask)
253 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
254 clkcon0 &= armdivmask;
255 val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
257 return rate / armdiv[val];
260 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
262 unsigned long parent = clk_get_rate(clk->parent);
265 unsigned best = 256; /* bigger than any value */
269 if (!nr_armdiv || !armdivmask)
272 for (ptr = 0; ptr < nr_armdiv; ptr++) {
275 /* cpufreq provides 266mhz as 266666000 not 266666666 */
276 calc = (parent / div / 1000) * 1000;
277 if (calc <= rate && div < best) {
285 unsigned long clkcon0;
287 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
288 clkcon0 &= ~armdivmask;
289 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
290 __raw_writel(clkcon0, S3C2443_CLKDIV0);
293 return (val == -1) ? -EINVAL : 0;
296 static struct clk clk_armdiv = {
298 .parent = &clk_msysclk.clk,
299 .ops = &(struct clk_ops) {
300 .round_rate = s3c2443_armclk_roundrate,
301 .get_rate = s3c2443_armclk_getrate,
302 .set_rate = s3c2443_armclk_setrate,
308 * this is the clock fed into the ARM core itself, from armdiv or from hclk.
311 static struct clk *clk_arm_sources[] = {
316 static struct clksrc_clk clk_arm = {
320 .sources = &(struct clksrc_sources) {
321 .sources = clk_arm_sources,
322 .nr_sources = ARRAY_SIZE(clk_arm_sources),
324 .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
329 * usb host bus-clock, usually 48MHz to provide USB bus clock timing
332 static struct clksrc_clk clk_usb_bus_host = {
334 .name = "usb-bus-host-parent",
335 .parent = &clk_esysclk.clk,
336 .ctrlbit = S3C2443_SCLKCON_USBHOST,
337 .enable = s3c2443_clkcon_enable_s,
339 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
342 /* common clksrc clocks */
344 static struct clksrc_clk clksrc_clks[] = {
346 /* camera interface bus-clock, divided down from esysclk */
348 .name = "camif-upll", /* same as 2440 name */
349 .parent = &clk_esysclk.clk,
350 .ctrlbit = S3C2443_SCLKCON_CAMCLK,
351 .enable = s3c2443_clkcon_enable_s,
353 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
356 .name = "display-if",
357 .parent = &clk_esysclk.clk,
358 .ctrlbit = S3C2443_SCLKCON_DISPCLK,
359 .enable = s3c2443_clkcon_enable_s,
361 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
365 static struct clksrc_clk clk_esys_uart = {
366 /* ART baud-rate clock sourced from esysclk via a divisor */
369 .parent = &clk_esysclk.clk,
371 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
374 static struct clk clk_i2s_ext = {
380 * This clock is the output from the I2S divisor of ESYSCLK, and is separate
381 * from the mux that comes after it (cannot merge into one single clock)
384 static struct clksrc_clk clk_i2s_eplldiv = {
386 .name = "i2s-eplldiv",
387 .parent = &clk_esysclk.clk,
389 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
394 * i2s bus reference clock, selectable from external, esysclk or epllref
396 * Note, this used to be two clocks, but was compressed into one.
399 static struct clk *clk_i2s_srclist[] = {
400 [0] = &clk_i2s_eplldiv.clk,
402 [2] = &clk_epllref.clk,
403 [3] = &clk_epllref.clk,
406 static struct clksrc_clk clk_i2s = {
409 .ctrlbit = S3C2443_SCLKCON_I2SCLK,
410 .enable = s3c2443_clkcon_enable_s,
413 .sources = &(struct clksrc_sources) {
414 .sources = clk_i2s_srclist,
415 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
417 .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
420 static struct clk init_clocks_off[] = {
424 .enable = s3c2443_clkcon_enable_p,
425 .ctrlbit = S3C2443_PCLKCON_IIS,
429 .enable = s3c2443_clkcon_enable_p,
430 .ctrlbit = S3C2443_PCLKCON_ADC,
434 .enable = s3c2443_clkcon_enable_p,
435 .ctrlbit = S3C2443_PCLKCON_IIC,
439 static struct clk init_clocks[] = {
443 .enable = s3c2443_clkcon_enable_h,
444 .ctrlbit = S3C2443_HCLKCON_DMA0,
448 .enable = s3c2443_clkcon_enable_h,
449 .ctrlbit = S3C2443_HCLKCON_DMA1,
453 .enable = s3c2443_clkcon_enable_h,
454 .ctrlbit = S3C2443_HCLKCON_DMA2,
458 .enable = s3c2443_clkcon_enable_h,
459 .ctrlbit = S3C2443_HCLKCON_DMA3,
463 .enable = s3c2443_clkcon_enable_h,
464 .ctrlbit = S3C2443_HCLKCON_DMA4,
468 .enable = s3c2443_clkcon_enable_h,
469 .ctrlbit = S3C2443_HCLKCON_DMA5,
473 .enable = s3c2443_clkcon_enable_p,
474 .ctrlbit = S3C2443_PCLKCON_GPIO,
478 .enable = s3c2443_clkcon_enable_h,
479 .ctrlbit = S3C2443_HCLKCON_USBH,
481 .name = "usb-device",
483 .enable = s3c2443_clkcon_enable_h,
484 .ctrlbit = S3C2443_HCLKCON_USBD,
488 .enable = s3c2443_clkcon_enable_h,
489 .ctrlbit = S3C2443_HCLKCON_LCDC,
494 .enable = s3c2443_clkcon_enable_p,
495 .ctrlbit = S3C2443_PCLKCON_PWMT,
499 .enable = s3c2443_clkcon_enable_h,
500 .ctrlbit = S3C2443_HCLKCON_CFC,
504 .enable = s3c2443_clkcon_enable_h,
505 .ctrlbit = S3C2443_HCLKCON_SSMC,
508 .devname = "s3c2440-uart.0",
510 .enable = s3c2443_clkcon_enable_p,
511 .ctrlbit = S3C2443_PCLKCON_UART0,
514 .devname = "s3c2440-uart.1",
516 .enable = s3c2443_clkcon_enable_p,
517 .ctrlbit = S3C2443_PCLKCON_UART1,
520 .devname = "s3c2440-uart.2",
522 .enable = s3c2443_clkcon_enable_p,
523 .ctrlbit = S3C2443_PCLKCON_UART2,
526 .devname = "s3c2440-uart.3",
528 .enable = s3c2443_clkcon_enable_p,
529 .ctrlbit = S3C2443_PCLKCON_UART3,
533 .enable = s3c2443_clkcon_enable_p,
534 .ctrlbit = S3C2443_PCLKCON_RTC,
538 .ctrlbit = S3C2443_PCLKCON_WDT,
542 .ctrlbit = S3C2443_PCLKCON_AC97,
547 .name = "usb-bus-host",
548 .parent = &clk_usb_bus_host.clk,
552 static struct clk hsmmc1_clk = {
554 .devname = "s3c-sdhci.1",
556 .enable = s3c2443_clkcon_enable_h,
557 .ctrlbit = S3C2443_HCLKCON_HSMMC,
560 static struct clk hsspi_clk = {
562 .devname = "s3c2443-spi.0",
564 .enable = s3c2443_clkcon_enable_p,
565 .ctrlbit = S3C2443_PCLKCON_HSSPI,
568 /* EPLLCON compatible enough to get on/off information */
570 void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
572 unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
573 unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
574 struct clk *xtal_clk;
579 xtal_clk = clk_get(NULL, "xtal");
580 xtal = clk_get_rate(xtal_clk);
583 pll = get_mpll(mpllcon, xtal);
584 clk_msysclk.clk.rate = pll;
587 printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
588 (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
589 print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
590 print_mhz(clk_get_rate(&clk_h)),
591 print_mhz(clk_get_rate(&clk_p)));
593 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
594 s3c_set_clksrc(&clksrc_clks[ptr], true);
596 /* ensure usb bus clock is within correct rate of 48MHz */
598 if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
599 printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
600 clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
603 printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
604 (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
605 print_mhz(clk_get_rate(&clk_epll)),
606 print_mhz(clk_get_rate(&clk_usb_bus)));
609 static struct clk *clks[] __initdata = {
621 static struct clksrc_clk *clksrcs[] __initdata = {
631 static struct clk_lookup s3c2443_clk_lookup[] = {
632 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
633 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
634 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
635 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
636 CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
639 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
640 unsigned int *divs, int nr_divs,
647 armdivmask = divmask;
649 /* s3c2443 parents h clock from prediv */
650 clk_h.parent = &clk_prediv;
651 clk_h.ops = &clk_h_ops;
653 /* and p clock from h clock */
654 clk_p.parent = &clk_h;
655 clk_p.ops = &clk_p_ops;
657 clk_usb_bus.parent = &clk_usb_bus_host.clk;
658 clk_epll.parent = &clk_epllref.clk;
660 s3c24xx_register_baseclocks(xtal);
661 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
663 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
664 s3c_register_clksrc(clksrcs[ptr], 1);
666 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
667 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
669 /* See s3c2443/etc notes on disabling clocks at init time */
670 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
671 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
672 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
674 s3c2443_common_setup_clocks(get_mpll);