1 /* linux/arch/arm/mach-s3c2440/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2440 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
19 #include <linux/serial_s3c.h>
24 #include <plat/dma-s3c24xx.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-dma.h>
29 #include <mach/regs-lcd.h>
30 #include <plat/regs-spi.h>
32 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
35 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
39 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
43 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
44 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
45 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
46 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
50 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
54 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
58 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
62 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
66 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
70 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
71 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
72 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
76 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
77 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
81 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
82 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
86 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
87 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
91 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
92 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
96 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
97 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
101 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
105 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
109 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
113 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
117 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
118 struct s3c24xx_dma_map *map)
120 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
123 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
124 .select = s3c2440_dma_select,
125 .dcon_mask = 7 << 24,
126 .map = s3c2440_dma_mappings,
127 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
130 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
134 [0] = 3 | DMA_CH_VALID,
135 [1] = 2 | DMA_CH_VALID,
136 [2] = 1 | DMA_CH_VALID,
137 [3] = 0 | DMA_CH_VALID,
142 [0] = 1 | DMA_CH_VALID,
143 [1] = 2 | DMA_CH_VALID,
148 [0] = 2 | DMA_CH_VALID,
149 [1] = 1 | DMA_CH_VALID,
154 [0] = 2 | DMA_CH_VALID,
155 [1] = 1 | DMA_CH_VALID,
160 [0] = 1 | DMA_CH_VALID,
161 [1] = 3 | DMA_CH_VALID,
166 [0] = 3 | DMA_CH_VALID,
167 [1] = 2 | DMA_CH_VALID,
173 static int __init s3c2440_dma_add(struct device *dev,
174 struct subsys_interface *sif)
177 s3c24xx_dma_order_set(&s3c2440_dma_order);
178 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
181 static struct subsys_interface s3c2440_dma_interface = {
182 .name = "s3c2440_dma",
183 .subsys = &s3c2440_subsys,
184 .add_dev = s3c2440_dma_add,
187 static int __init s3c2440_dma_init(void)
189 return subsys_interface_register(&s3c2440_dma_interface);
192 arch_initcall(s3c2440_dma_init);