arch/arm/mach-s3c24xx/mach-osiris.c

   1 /*
   2  * Copyright (c) 2005-2008 Simtec Electronics
   3  *      http://armlinux.simtec.co.uk/
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9 */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/list.h>
  15 #include <linux/timer.h>
  16 #include <linux/init.h>
  17 #include <linux/gpio.h>
  18 #include <linux/device.h>
  19 #include <linux/syscore_ops.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/clk.h>
  22 #include <linux/i2c.h>
  23 #include <linux/io.h>
  24
  25 #include <linux/i2c/tps65010.h>
  26
  27 #include <asm/mach-types.h>
  28 #include <asm/mach/arch.h>
  29 #include <asm/mach/map.h>
  30 #include <asm/mach/irq.h>
  31 #include <asm/irq.h>
  32
  33 #include <linux/platform_data/mtd-nand-s3c2410.h>
  34 #include <linux/platform_data/i2c-s3c2410.h>
  35
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <plat/clock.h>
  42 #include <plat/cpu.h>
  43 #include <plat/cpu-freq.h>
  44 #include <plat/devs.h>
  45 #include <plat/gpio-cfg.h>
  46 #include <plat/regs-serial.h>
  47
  48 #include <mach/hardware.h>
  49 #include <mach/regs-gpio.h>
  50 #include <mach/regs-lcd.h>
  51
  52 #include "common.h"
  53 #include "osiris.h"
  54 #include "regs-mem.h"
  55
  56 /* onboard perihperal map */
  57
  58 static struct map_desc osiris_iodesc[] __initdata = {
  59   /* ISA IO areas (may be over-written later) */
  60
  61   {
  62           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  63           .pfn          = __phys_to_pfn(S3C2410_CS5),
  64           .length       = SZ_16M,
  65           .type         = MT_DEVICE,
  66   }, {
  67           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  68           .pfn          = __phys_to_pfn(S3C2410_CS5),
  69           .length       = SZ_16M,
  70           .type         = MT_DEVICE,
  71   },
  72
  73   /* CPLD control registers */
  74
  75   {
  76           .virtual      = (u32)OSIRIS_VA_CTRL0,
  77           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  78           .length       = SZ_16K,
  79           .type         = MT_DEVICE,
  80   }, {
  81           .virtual      = (u32)OSIRIS_VA_CTRL1,
  82           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  83           .length       = SZ_16K,
  84           .type         = MT_DEVICE,
  85   }, {
  86           .virtual      = (u32)OSIRIS_VA_CTRL2,
  87           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  88           .length       = SZ_16K,
  89           .type         = MT_DEVICE,
  90   }, {
  91           .virtual      = (u32)OSIRIS_VA_IDREG,
  92           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  93           .length       = SZ_16K,
  94           .type         = MT_DEVICE,
  95   },
  96 };
  97
  98 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  99 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 100 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 101
 102 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 103         [0] = {
 104                 .hwport      = 0,
 105                 .flags       = 0,
 106                 .ucon        = UCON,
 107                 .ulcon       = ULCON,
 108                 .ufcon       = UFCON,
 109                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 110         },
 111         [1] = {
 112                 .hwport      = 1,
 113                 .flags       = 0,
 114                 .ucon        = UCON,
 115                 .ulcon       = ULCON,
 116                 .ufcon       = UFCON,
 117                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 118         },
 119         [2] = {
 120                 .hwport      = 2,
 121                 .flags       = 0,
 122                 .ucon        = UCON,
 123                 .ulcon       = ULCON,
 124                 .ufcon       = UFCON,
 125                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 126         }
 127 };
 128
 129 /* NAND Flash on Osiris board */
 130
 131 static int external_map[]   = { 2 };
 132 static int chip0_map[]      = { 0 };
 133 static int chip1_map[]      = { 1 };
 134
 135 static struct mtd_partition __initdata osiris_default_nand_part[] = {
 136         [0] = {
 137                 .name   = "Boot Agent",
 138                 .size   = SZ_16K,
 139                 .offset = 0,
 140         },
 141         [1] = {
 142                 .name   = "/boot",
 143                 .size   = SZ_4M - SZ_16K,
 144                 .offset = SZ_16K,
 145         },
 146         [2] = {
 147                 .name   = "user1",
 148                 .offset = SZ_4M,
 149                 .size   = SZ_32M - SZ_4M,
 150         },
 151         [3] = {
 152                 .name   = "user2",
 153                 .offset = SZ_32M,
 154                 .size   = MTDPART_SIZ_FULL,
 155         }
 156 };
 157
 158 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
 159         [0] = {
 160                 .name   = "Boot Agent",
 161                 .size   = SZ_128K,
 162                 .offset = 0,
 163         },
 164         [1] = {
 165                 .name   = "/boot",
 166                 .size   = SZ_4M - SZ_128K,
 167                 .offset = SZ_128K,
 168         },
 169         [2] = {
 170                 .name   = "user1",
 171                 .offset = SZ_4M,
 172                 .size   = SZ_32M - SZ_4M,
 173         },
 174         [3] = {
 175                 .name   = "user2",
 176                 .offset = SZ_32M,
 177                 .size   = MTDPART_SIZ_FULL,
 178         }
 179 };
 180
 181 /* the Osiris has 3 selectable slots for nand-flash, the two
 182  * on-board chip areas, as well as the external slot.
 183  *
 184  * Note, there is no current hot-plug support for the External
 185  * socket.
 186 */
 187
 188 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
 189         [1] = {
 190                 .name           = "External",
 191                 .nr_chips       = 1,
 192                 .nr_map         = external_map,
 193                 .options        = NAND_SCAN_SILENT_NODEV,
 194                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 195                 .partitions     = osiris_default_nand_part,
 196         },
 197         [0] = {
 198                 .name           = "chip0",
 199                 .nr_chips       = 1,
 200                 .nr_map         = chip0_map,
 201                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 202                 .partitions     = osiris_default_nand_part,
 203         },
 204         [2] = {
 205                 .name           = "chip1",
 206                 .nr_chips       = 1,
 207                 .nr_map         = chip1_map,
 208                 .options        = NAND_SCAN_SILENT_NODEV,
 209                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 210                 .partitions     = osiris_default_nand_part,
 211         },
 212 };
 213
 214 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 215 {
 216         unsigned int tmp;
 217
 218         slot = set->nr_map[slot] & 3;
 219
 220         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 221                  slot, set, set->nr_map);
 222
 223         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 224         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 225         tmp |= slot;
 226
 227         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 228
 229         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 230 }
 231
 232 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 233         .tacls          = 25,
 234         .twrph0         = 60,
 235         .twrph1         = 60,
 236         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 237         .sets           = osiris_nand_sets,
 238         .select_chip    = osiris_nand_select,
 239 };
 240
 241 /* PCMCIA control and configuration */
 242
 243 static struct resource osiris_pcmcia_resource[] = {
 244         [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
 245         [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
 246 };
 247
 248 static struct platform_device osiris_pcmcia = {
 249         .name           = "osiris-pcmcia",
 250         .id             = -1,
 251         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 252         .resource       = osiris_pcmcia_resource,
 253 };
 254
 255 /* Osiris power management device */
 256
 257 #ifdef CONFIG_PM
 258 static unsigned char pm_osiris_ctrl0;
 259
 260 static int osiris_pm_suspend(void)
 261 {
 262         unsigned int tmp;
 263
 264         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 265         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 266
 267         /* ensure correct NAND slot is selected on resume */
 268         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 269                 tmp |= 2;
 270
 271         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 272
 273         /* ensure that an nRESET is not generated on resume. */
 274         gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
 275         gpio_free(S3C2410_GPA(21));
 276
 277         return 0;
 278 }
 279
 280 static void osiris_pm_resume(void)
 281 {
 282         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 283                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 284
 285         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 286
 287         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 288 }
 289
 290 #else
 291 #define osiris_pm_suspend NULL
 292 #define osiris_pm_resume NULL
 293 #endif
 294
 295 static struct syscore_ops osiris_pm_syscore_ops = {
 296         .suspend        = osiris_pm_suspend,
 297         .resume         = osiris_pm_resume,
 298 };
 299
 300 /* Link for DVS driver to TPS65011 */
 301
 302 static void osiris_tps_release(struct device *dev)
 303 {
 304         /* static device, do not need to release anything */
 305 }
 306
 307 static struct platform_device osiris_tps_device = {
 308         .name   = "osiris-dvs",
 309         .id     = -1,
 310         .dev.release = osiris_tps_release,
 311 };
 312
 313 static int osiris_tps_setup(struct i2c_client *client, void *context)
 314 {
 315         osiris_tps_device.dev.parent = &client->dev;
 316         return platform_device_register(&osiris_tps_device);
 317 }
 318
 319 static int osiris_tps_remove(struct i2c_client *client, void *context)
 320 {
 321         platform_device_unregister(&osiris_tps_device);
 322         return 0;
 323 }
 324
 325 static struct tps65010_board osiris_tps_board = {
 326         .base           = -1,   /* GPIO can go anywhere at the moment */
 327         .setup          = osiris_tps_setup,
 328         .teardown       = osiris_tps_remove,
 329 };
 330
 331 /* I2C devices fitted. */
 332
 333 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 334         {
 335                 I2C_BOARD_INFO("tps65011", 0x48),
 336                 .irq    = IRQ_EINT20,
 337                 .platform_data = &osiris_tps_board,
 338         },
 339 };
 340
 341 /* Standard Osiris devices */
 342
 343 static struct platform_device *osiris_devices[] __initdata = {
 344         &s3c_device_i2c0,
 345         &s3c_device_wdt,
 346         &s3c_device_nand,
 347         &osiris_pcmcia,
 348 };
 349
 350 static struct clk *osiris_clocks[] __initdata = {
 351         &s3c24xx_dclk0,
 352         &s3c24xx_dclk1,
 353         &s3c24xx_clkout0,
 354         &s3c24xx_clkout1,
 355         &s3c24xx_uclk,
 356 };
 357
 358 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
 359         .refresh        = 7800, /* refresh period is 7.8usec */
 360         .auto_io        = 1,
 361         .need_io        = 1,
 362 };
 363
 364 static void __init osiris_map_io(void)
 365 {
 366         unsigned long flags;
 367
 368         /* initialise the clocks */
 369
 370         s3c24xx_dclk0.parent = &clk_upll;
 371         s3c24xx_dclk0.rate   = 12*1000*1000;
 372
 373         s3c24xx_dclk1.parent = &clk_upll;
 374         s3c24xx_dclk1.rate   = 24*1000*1000;
 375
 376         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 377         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 378
 379         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 380
 381         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 382
 383         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 384         s3c24xx_init_clocks(0);
 385         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 386
 387         /* check for the newer revision boards with large page nand */
 388
 389         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 390                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 391                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 392                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 393                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 394         } else {
 395                 /* write-protect line to the NAND */
 396                 gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
 397                 gpio_free(S3C2410_GPA(0));
 398         }
 399
 400         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 401
 402         local_irq_save(flags);
 403         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 404         local_irq_restore(flags);
 405 }
 406
 407 static void __init osiris_init(void)
 408 {
 409         register_syscore_ops(&osiris_pm_syscore_ops);
 410
 411         s3c_i2c0_set_platdata(NULL);
 412         s3c_nand_set_platdata(&osiris_nand_info);
 413
 414         s3c_cpufreq_setboard(&osiris_cpufreq);
 415
 416         i2c_register_board_info(0, osiris_i2c_devs,
 417                                 ARRAY_SIZE(osiris_i2c_devs));
 418
 419         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 420 };
 421
 422 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 423         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 424         .atag_offset    = 0x100,
 425         .map_io         = osiris_map_io,
 426         .init_irq       = s3c24xx_init_irq,
 427         .init_machine   = osiris_init,
 428         .init_time      = s3c24xx_timer_init,
 429         .restart        = s3c244x_restart,
 430 MACHINE_END