arch/arm/mach-s3c24xx/mach-osiris.c

   1 /* linux/arch/arm/mach-s3c2440/mach-osiris.c
   2  *
   3  * Copyright (c) 2005-2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/gpio.h>
  19 #include <linux/device.h>
  20 #include <linux/syscore_ops.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/clk.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/platform_device.h>
  26
  27 #include <linux/i2c/tps65010.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32
  33 #include <mach/osiris-map.h>
  34 #include <mach/osiris-cpld.h>
  35
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/mach-types.h>
  39
  40 #include <plat/cpu-freq.h>
  41 #include <plat/regs-serial.h>
  42 #include <mach/regs-gpio.h>
  43 #include <mach/regs-mem.h>
  44 #include <mach/regs-lcd.h>
  45 #include <linux/platform_data/mtd-nand-s3c2410.h>
  46 #include <linux/platform_data/i2c-s3c2410.h>
  47
  48 #include <linux/mtd/mtd.h>
  49 #include <linux/mtd/nand.h>
  50 #include <linux/mtd/nand_ecc.h>
  51 #include <linux/mtd/partitions.h>
  52
  53 #include <plat/gpio-cfg.h>
  54 #include <plat/clock.h>
  55 #include <plat/devs.h>
  56 #include <plat/cpu.h>
  57
  58 #include "common.h"
  59
  60 /* onboard perihperal map */
  61
  62 static struct map_desc osiris_iodesc[] __initdata = {
  63   /* ISA IO areas (may be over-written later) */
  64
  65   {
  66           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  67           .pfn          = __phys_to_pfn(S3C2410_CS5),
  68           .length       = SZ_16M,
  69           .type         = MT_DEVICE,
  70   }, {
  71           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  72           .pfn          = __phys_to_pfn(S3C2410_CS5),
  73           .length       = SZ_16M,
  74           .type         = MT_DEVICE,
  75   },
  76
  77   /* CPLD control registers */
  78
  79   {
  80           .virtual      = (u32)OSIRIS_VA_CTRL0,
  81           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL0),
  82           .length       = SZ_16K,
  83           .type         = MT_DEVICE,
  84   }, {
  85           .virtual      = (u32)OSIRIS_VA_CTRL1,
  86           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL1),
  87           .length       = SZ_16K,
  88           .type         = MT_DEVICE,
  89   }, {
  90           .virtual      = (u32)OSIRIS_VA_CTRL2,
  91           .pfn          = __phys_to_pfn(OSIRIS_PA_CTRL2),
  92           .length       = SZ_16K,
  93           .type         = MT_DEVICE,
  94   }, {
  95           .virtual      = (u32)OSIRIS_VA_IDREG,
  96           .pfn          = __phys_to_pfn(OSIRIS_PA_IDREG),
  97           .length       = SZ_16K,
  98           .type         = MT_DEVICE,
  99   },
 100 };
 101
 102 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 103 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 104 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 105
 106 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 107         [0] = {
 108                 .hwport      = 0,
 109                 .flags       = 0,
 110                 .ucon        = UCON,
 111                 .ulcon       = ULCON,
 112                 .ufcon       = UFCON,
 113                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 114         },
 115         [1] = {
 116                 .hwport      = 1,
 117                 .flags       = 0,
 118                 .ucon        = UCON,
 119                 .ulcon       = ULCON,
 120                 .ufcon       = UFCON,
 121                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 122         },
 123         [2] = {
 124                 .hwport      = 2,
 125                 .flags       = 0,
 126                 .ucon        = UCON,
 127                 .ulcon       = ULCON,
 128                 .ufcon       = UFCON,
 129                 .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
 130         }
 131 };
 132
 133 /* NAND Flash on Osiris board */
 134
 135 static int external_map[]   = { 2 };
 136 static int chip0_map[]      = { 0 };
 137 static int chip1_map[]      = { 1 };
 138
 139 static struct mtd_partition __initdata osiris_default_nand_part[] = {
 140         [0] = {
 141                 .name   = "Boot Agent",
 142                 .size   = SZ_16K,
 143                 .offset = 0,
 144         },
 145         [1] = {
 146                 .name   = "/boot",
 147                 .size   = SZ_4M - SZ_16K,
 148                 .offset = SZ_16K,
 149         },
 150         [2] = {
 151                 .name   = "user1",
 152                 .offset = SZ_4M,
 153                 .size   = SZ_32M - SZ_4M,
 154         },
 155         [3] = {
 156                 .name   = "user2",
 157                 .offset = SZ_32M,
 158                 .size   = MTDPART_SIZ_FULL,
 159         }
 160 };
 161
 162 static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
 163         [0] = {
 164                 .name   = "Boot Agent",
 165                 .size   = SZ_128K,
 166                 .offset = 0,
 167         },
 168         [1] = {
 169                 .name   = "/boot",
 170                 .size   = SZ_4M - SZ_128K,
 171                 .offset = SZ_128K,
 172         },
 173         [2] = {
 174                 .name   = "user1",
 175                 .offset = SZ_4M,
 176                 .size   = SZ_32M - SZ_4M,
 177         },
 178         [3] = {
 179                 .name   = "user2",
 180                 .offset = SZ_32M,
 181                 .size   = MTDPART_SIZ_FULL,
 182         }
 183 };
 184
 185 /* the Osiris has 3 selectable slots for nand-flash, the two
 186  * on-board chip areas, as well as the external slot.
 187  *
 188  * Note, there is no current hot-plug support for the External
 189  * socket.
 190 */
 191
 192 static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
 193         [1] = {
 194                 .name           = "External",
 195                 .nr_chips       = 1,
 196                 .nr_map         = external_map,
 197                 .options        = NAND_SCAN_SILENT_NODEV,
 198                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 199                 .partitions     = osiris_default_nand_part,
 200         },
 201         [0] = {
 202                 .name           = "chip0",
 203                 .nr_chips       = 1,
 204                 .nr_map         = chip0_map,
 205                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 206                 .partitions     = osiris_default_nand_part,
 207         },
 208         [2] = {
 209                 .name           = "chip1",
 210                 .nr_chips       = 1,
 211                 .nr_map         = chip1_map,
 212                 .options        = NAND_SCAN_SILENT_NODEV,
 213                 .nr_partitions  = ARRAY_SIZE(osiris_default_nand_part),
 214                 .partitions     = osiris_default_nand_part,
 215         },
 216 };
 217
 218 static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
 219 {
 220         unsigned int tmp;
 221
 222         slot = set->nr_map[slot] & 3;
 223
 224         pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
 225                  slot, set, set->nr_map);
 226
 227         tmp = __raw_readb(OSIRIS_VA_CTRL0);
 228         tmp &= ~OSIRIS_CTRL0_NANDSEL;
 229         tmp |= slot;
 230
 231         pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
 232
 233         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 234 }
 235
 236 static struct s3c2410_platform_nand __initdata osiris_nand_info = {
 237         .tacls          = 25,
 238         .twrph0         = 60,
 239         .twrph1         = 60,
 240         .nr_sets        = ARRAY_SIZE(osiris_nand_sets),
 241         .sets           = osiris_nand_sets,
 242         .select_chip    = osiris_nand_select,
 243 };
 244
 245 /* PCMCIA control and configuration */
 246
 247 static struct resource osiris_pcmcia_resource[] = {
 248         [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
 249         [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
 250 };
 251
 252 static struct platform_device osiris_pcmcia = {
 253         .name           = "osiris-pcmcia",
 254         .id             = -1,
 255         .num_resources  = ARRAY_SIZE(osiris_pcmcia_resource),
 256         .resource       = osiris_pcmcia_resource,
 257 };
 258
 259 /* Osiris power management device */
 260
 261 #ifdef CONFIG_PM
 262 static unsigned char pm_osiris_ctrl0;
 263
 264 static int osiris_pm_suspend(void)
 265 {
 266         unsigned int tmp;
 267
 268         pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
 269         tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
 270
 271         /* ensure correct NAND slot is selected on resume */
 272         if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
 273                 tmp |= 2;
 274
 275         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 276
 277         /* ensure that an nRESET is not generated on resume. */
 278         gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
 279         gpio_free(S3C2410_GPA(21));
 280
 281         return 0;
 282 }
 283
 284 static void osiris_pm_resume(void)
 285 {
 286         if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
 287                 __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
 288
 289         __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
 290
 291         s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 292 }
 293
 294 #else
 295 #define osiris_pm_suspend NULL
 296 #define osiris_pm_resume NULL
 297 #endif
 298
 299 static struct syscore_ops osiris_pm_syscore_ops = {
 300         .suspend        = osiris_pm_suspend,
 301         .resume         = osiris_pm_resume,
 302 };
 303
 304 /* Link for DVS driver to TPS65011 */
 305
 306 static void osiris_tps_release(struct device *dev)
 307 {
 308         /* static device, do not need to release anything */
 309 }
 310
 311 static struct platform_device osiris_tps_device = {
 312         .name   = "osiris-dvs",
 313         .id     = -1,
 314         .dev.release = osiris_tps_release,
 315 };
 316
 317 static int osiris_tps_setup(struct i2c_client *client, void *context)
 318 {
 319         osiris_tps_device.dev.parent = &client->dev;
 320         return platform_device_register(&osiris_tps_device);
 321 }
 322
 323 static int osiris_tps_remove(struct i2c_client *client, void *context)
 324 {
 325         platform_device_unregister(&osiris_tps_device);
 326         return 0;
 327 }
 328
 329 static struct tps65010_board osiris_tps_board = {
 330         .base           = -1,   /* GPIO can go anywhere at the moment */
 331         .setup          = osiris_tps_setup,
 332         .teardown       = osiris_tps_remove,
 333 };
 334
 335 /* I2C devices fitted. */
 336
 337 static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 338         {
 339                 I2C_BOARD_INFO("tps65011", 0x48),
 340                 .irq    = IRQ_EINT20,
 341                 .platform_data = &osiris_tps_board,
 342         },
 343 };
 344
 345 /* Standard Osiris devices */
 346
 347 static struct platform_device *osiris_devices[] __initdata = {
 348         &s3c_device_i2c0,
 349         &s3c_device_wdt,
 350         &s3c_device_nand,
 351         &osiris_pcmcia,
 352 };
 353
 354 static struct clk *osiris_clocks[] __initdata = {
 355         &s3c24xx_dclk0,
 356         &s3c24xx_dclk1,
 357         &s3c24xx_clkout0,
 358         &s3c24xx_clkout1,
 359         &s3c24xx_uclk,
 360 };
 361
 362 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
 363         .refresh        = 7800, /* refresh period is 7.8usec */
 364         .auto_io        = 1,
 365         .need_io        = 1,
 366 };
 367
 368 static void __init osiris_map_io(void)
 369 {
 370         unsigned long flags;
 371
 372         /* initialise the clocks */
 373
 374         s3c24xx_dclk0.parent = &clk_upll;
 375         s3c24xx_dclk0.rate   = 12*1000*1000;
 376
 377         s3c24xx_dclk1.parent = &clk_upll;
 378         s3c24xx_dclk1.rate   = 24*1000*1000;
 379
 380         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 381         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 382
 383         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 384
 385         s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
 386
 387         s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
 388         s3c24xx_init_clocks(0);
 389         s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
 390
 391         /* check for the newer revision boards with large page nand */
 392
 393         if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
 394                 printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
 395                        __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
 396                 osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
 397                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
 398         } else {
 399                 /* write-protect line to the NAND */
 400                 gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
 401                 gpio_free(S3C2410_GPA(0));
 402         }
 403
 404         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
 405
 406         local_irq_save(flags);
 407         __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
 408         local_irq_restore(flags);
 409 }
 410
 411 static void __init osiris_init(void)
 412 {
 413         register_syscore_ops(&osiris_pm_syscore_ops);
 414
 415         s3c_i2c0_set_platdata(NULL);
 416         s3c_nand_set_platdata(&osiris_nand_info);
 417
 418         s3c_cpufreq_setboard(&osiris_cpufreq);
 419
 420         i2c_register_board_info(0, osiris_i2c_devs,
 421                                 ARRAY_SIZE(osiris_i2c_devs));
 422
 423         platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
 424 };
 425
 426 MACHINE_START(OSIRIS, "Simtec-OSIRIS")
 427         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 428         .atag_offset    = 0x100,
 429         .map_io         = osiris_map_io,
 430         .init_irq       = s3c24xx_init_irq,
 431         .init_machine   = osiris_init,
 432         .timer          = &s3c24xx_timer,
 433         .restart        = s3c244x_restart,
 434 MACHINE_END