1 /* linux/arch/arm/plat-s3c64xx/clock.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C64XX Base clock support
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
23 #include <mach/hardware.h>
26 #include <mach/regs-sys.h>
27 #include <mach/regs-clock.h>
30 #include <plat/devs.h>
31 #include <plat/cpu-freq.h>
32 #include <plat/clock.h>
33 #include <plat/clock-clksrc.h>
36 /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
37 * ext_xtal_mux for want of an actual name from the manual.
40 static struct clk clk_ext_xtal_mux = {
44 #define clk_fin_apll clk_ext_xtal_mux
45 #define clk_fin_mpll clk_ext_xtal_mux
46 #define clk_fin_epll clk_ext_xtal_mux
48 #define clk_fout_mpll clk_mpll
49 #define clk_fout_epll clk_epll
56 struct clk clk_27m = {
61 static int clk_48m_ctrl(struct clk *clk, int enable)
66 /* can't rely on clock lock, this register has other usages */
67 local_irq_save(flags);
69 val = __raw_readl(S3C64XX_OTHERS);
71 val |= S3C64XX_OTHERS_USBMASK;
73 val &= ~S3C64XX_OTHERS_USBMASK;
75 __raw_writel(val, S3C64XX_OTHERS);
76 local_irq_restore(flags);
81 struct clk clk_48m = {
84 .enable = clk_48m_ctrl,
87 struct clk clk_xusbxti = {
92 static int inline s3c64xx_gate(void __iomem *reg,
96 unsigned int ctrlbit = clk->ctrlbit;
99 con = __raw_readl(reg);
106 __raw_writel(con, reg);
110 static int s3c64xx_pclk_ctrl(struct clk *clk, int enable)
112 return s3c64xx_gate(S3C_PCLK_GATE, clk, enable);
115 static int s3c64xx_hclk_ctrl(struct clk *clk, int enable)
117 return s3c64xx_gate(S3C_HCLK_GATE, clk, enable);
120 int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
122 return s3c64xx_gate(S3C_SCLK_GATE, clk, enable);
125 static struct clk init_clocks_off[] = {
132 .enable = s3c64xx_pclk_ctrl,
133 .ctrlbit = S3C_CLKCON_PCLK_RTC,
137 .enable = s3c64xx_pclk_ctrl,
138 .ctrlbit = S3C_CLKCON_PCLK_TSADC,
141 #ifdef CONFIG_S3C_DEV_I2C1
142 .devname = "s3c2440-i2c.0",
144 .devname = "s3c2440-i2c",
147 .enable = s3c64xx_pclk_ctrl,
148 .ctrlbit = S3C_CLKCON_PCLK_IIC,
151 .devname = "s3c2440-i2c.1",
153 .enable = s3c64xx_pclk_ctrl,
154 .ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
157 .devname = "samsung-i2s.0",
159 .enable = s3c64xx_pclk_ctrl,
160 .ctrlbit = S3C_CLKCON_PCLK_IIS0,
163 .devname = "samsung-i2s.1",
165 .enable = s3c64xx_pclk_ctrl,
166 .ctrlbit = S3C_CLKCON_PCLK_IIS1,
168 #ifdef CONFIG_CPU_S3C6410
171 .enable = s3c64xx_pclk_ctrl,
172 .ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
177 .enable = s3c64xx_pclk_ctrl,
178 .ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
181 .devname = "s3c64xx-spi.0",
183 .enable = s3c64xx_pclk_ctrl,
184 .ctrlbit = S3C_CLKCON_PCLK_SPI0,
187 .devname = "s3c64xx-spi.1",
189 .enable = s3c64xx_pclk_ctrl,
190 .ctrlbit = S3C_CLKCON_PCLK_SPI1,
193 .devname = "s3c-sdhci.0",
195 .enable = s3c64xx_sclk_ctrl,
196 .ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
199 .devname = "s3c-sdhci.1",
201 .enable = s3c64xx_sclk_ctrl,
202 .ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
205 .devname = "s3c-sdhci.2",
207 .enable = s3c64xx_sclk_ctrl,
208 .ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
212 .enable = s3c64xx_hclk_ctrl,
213 .ctrlbit = S3C_CLKCON_HCLK_DMA0,
217 .enable = s3c64xx_hclk_ctrl,
218 .ctrlbit = S3C_CLKCON_HCLK_DMA1,
222 static struct clk clk_48m_spi0 = {
224 .devname = "s3c64xx-spi.0",
226 .enable = s3c64xx_sclk_ctrl,
227 .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
230 static struct clk clk_48m_spi1 = {
232 .devname = "s3c64xx-spi.1",
234 .enable = s3c64xx_sclk_ctrl,
235 .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
238 static struct clk init_clocks[] = {
242 .enable = s3c64xx_hclk_ctrl,
243 .ctrlbit = S3C_CLKCON_HCLK_LCD,
247 .enable = s3c64xx_pclk_ctrl,
248 .ctrlbit = S3C_CLKCON_PCLK_GPIO,
252 .enable = s3c64xx_hclk_ctrl,
253 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
257 .enable = s3c64xx_hclk_ctrl,
258 .ctrlbit = S3C_CLKCON_HCLK_USB,
262 .enable = s3c64xx_pclk_ctrl,
263 .ctrlbit = S3C_CLKCON_PCLK_PWM,
266 .devname = "s3c6400-uart.0",
268 .enable = s3c64xx_pclk_ctrl,
269 .ctrlbit = S3C_CLKCON_PCLK_UART0,
272 .devname = "s3c6400-uart.1",
274 .enable = s3c64xx_pclk_ctrl,
275 .ctrlbit = S3C_CLKCON_PCLK_UART1,
278 .devname = "s3c6400-uart.2",
280 .enable = s3c64xx_pclk_ctrl,
281 .ctrlbit = S3C_CLKCON_PCLK_UART2,
284 .devname = "s3c6400-uart.3",
286 .enable = s3c64xx_pclk_ctrl,
287 .ctrlbit = S3C_CLKCON_PCLK_UART3,
291 .ctrlbit = S3C_CLKCON_PCLK_WDT,
295 .ctrlbit = S3C_CLKCON_PCLK_AC97,
299 .enable = s3c64xx_hclk_ctrl,
300 .ctrlbit = S3C_CLKCON_HCLK_IHOST,
304 static struct clk clk_hsmmc0 = {
306 .devname = "s3c-sdhci.0",
308 .enable = s3c64xx_hclk_ctrl,
309 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
312 static struct clk clk_hsmmc1 = {
314 .devname = "s3c-sdhci.1",
316 .enable = s3c64xx_hclk_ctrl,
317 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
320 static struct clk clk_hsmmc2 = {
322 .devname = "s3c-sdhci.2",
324 .enable = s3c64xx_hclk_ctrl,
325 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
328 static struct clk clk_fout_apll = {
332 static struct clk *clk_src_apll_list[] = {
334 [1] = &clk_fout_apll,
337 static struct clksrc_sources clk_src_apll = {
338 .sources = clk_src_apll_list,
339 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
342 static struct clksrc_clk clk_mout_apll = {
346 .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
347 .sources = &clk_src_apll,
350 static struct clk *clk_src_epll_list[] = {
352 [1] = &clk_fout_epll,
355 static struct clksrc_sources clk_src_epll = {
356 .sources = clk_src_epll_list,
357 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
360 static struct clksrc_clk clk_mout_epll = {
364 .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
365 .sources = &clk_src_epll,
368 static struct clk *clk_src_mpll_list[] = {
370 [1] = &clk_fout_mpll,
373 static struct clksrc_sources clk_src_mpll = {
374 .sources = clk_src_mpll_list,
375 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
378 static struct clksrc_clk clk_mout_mpll = {
382 .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
383 .sources = &clk_src_mpll,
386 static unsigned int armclk_mask;
388 static unsigned long s3c64xx_clk_arm_get_rate(struct clk *clk)
390 unsigned long rate = clk_get_rate(clk->parent);
393 /* divisor mask starts at bit0, so no need to shift */
394 clkdiv = __raw_readl(S3C_CLK_DIV0) & armclk_mask;
396 return rate / (clkdiv + 1);
399 static unsigned long s3c64xx_clk_arm_round_rate(struct clk *clk,
402 unsigned long parent = clk_get_rate(clk->parent);
408 div = (parent / rate) - 1;
409 if (div > armclk_mask)
412 return parent / (div + 1);
415 static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
417 unsigned long parent = clk_get_rate(clk->parent);
421 if (rate < parent / (armclk_mask + 1))
424 rate = clk_round_rate(clk, rate);
425 div = clk_get_rate(clk->parent) / rate;
427 val = __raw_readl(S3C_CLK_DIV0);
430 __raw_writel(val, S3C_CLK_DIV0);
436 static struct clk clk_arm = {
438 .parent = &clk_mout_apll.clk,
439 .ops = &(struct clk_ops) {
440 .get_rate = s3c64xx_clk_arm_get_rate,
441 .set_rate = s3c64xx_clk_arm_set_rate,
442 .round_rate = s3c64xx_clk_arm_round_rate,
446 static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk)
448 unsigned long rate = clk_get_rate(clk->parent);
450 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
452 if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK)
458 static struct clk_ops clk_dout_ops = {
459 .get_rate = s3c64xx_clk_doutmpll_get_rate,
462 static struct clk clk_dout_mpll = {
464 .parent = &clk_mout_mpll.clk,
465 .ops = &clk_dout_ops,
468 static struct clk *clkset_spi_mmc_list[] = {
475 static struct clksrc_sources clkset_spi_mmc = {
476 .sources = clkset_spi_mmc_list,
477 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
480 static struct clk *clkset_irda_list[] = {
487 static struct clksrc_sources clkset_irda = {
488 .sources = clkset_irda_list,
489 .nr_sources = ARRAY_SIZE(clkset_irda_list),
492 static struct clk *clkset_uart_list[] = {
499 static struct clksrc_sources clkset_uart = {
500 .sources = clkset_uart_list,
501 .nr_sources = ARRAY_SIZE(clkset_uart_list),
504 static struct clk *clkset_uhost_list[] = {
511 static struct clksrc_sources clkset_uhost = {
512 .sources = clkset_uhost_list,
513 .nr_sources = ARRAY_SIZE(clkset_uhost_list),
516 /* The peripheral clocks are all controlled via clocksource followed
517 * by an optional divider and gate stage. We currently roll this into
518 * one clock which hides the intermediate clock from the mux.
520 * Note, the JPEG clock can only be an even divider...
522 * The scaler and LCD clocks depend on the S3C64XX version, and also
523 * have a common parent divisor so are not included here.
526 /* clocks that feed other parts of the clock source tree */
528 static struct clk clk_iis_cd0 = {
529 .name = "iis_cdclk0",
532 static struct clk clk_iis_cd1 = {
533 .name = "iis_cdclk1",
536 static struct clk clk_iisv4_cd = {
537 .name = "iis_cdclk_v4",
540 static struct clk clk_pcm_cd = {
544 static struct clk *clkset_audio0_list[] = {
545 [0] = &clk_mout_epll.clk,
546 [1] = &clk_dout_mpll,
552 static struct clksrc_sources clkset_audio0 = {
553 .sources = clkset_audio0_list,
554 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
557 static struct clk *clkset_audio1_list[] = {
558 [0] = &clk_mout_epll.clk,
559 [1] = &clk_dout_mpll,
565 static struct clksrc_sources clkset_audio1 = {
566 .sources = clkset_audio1_list,
567 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
570 static struct clk *clkset_audio2_list[] = {
571 [0] = &clk_mout_epll.clk,
572 [1] = &clk_dout_mpll,
578 static struct clksrc_sources clkset_audio2 = {
579 .sources = clkset_audio2_list,
580 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
583 static struct clk *clkset_camif_list[] = {
587 static struct clksrc_sources clkset_camif = {
588 .sources = clkset_camif_list,
589 .nr_sources = ARRAY_SIZE(clkset_camif_list),
592 static struct clksrc_clk clksrcs[] = {
595 .name = "usb-bus-host",
596 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
597 .enable = s3c64xx_sclk_ctrl,
599 .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 },
600 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
601 .sources = &clkset_uhost,
605 .devname = "samsung-i2s.0",
606 .ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
607 .enable = s3c64xx_sclk_ctrl,
609 .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 },
610 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
611 .sources = &clkset_audio0,
615 .devname = "samsung-i2s.1",
616 .ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
617 .enable = s3c64xx_sclk_ctrl,
619 .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
620 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
621 .sources = &clkset_audio1,
625 .devname = "samsung-i2s.2",
626 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
627 .enable = s3c64xx_sclk_ctrl,
629 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
630 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
631 .sources = &clkset_audio2,
635 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
636 .enable = s3c64xx_sclk_ctrl,
638 .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 },
639 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 },
640 .sources = &clkset_irda,
644 .ctrlbit = S3C_CLKCON_SCLK_CAM,
645 .enable = s3c64xx_sclk_ctrl,
647 .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 },
648 .reg_src = { .reg = NULL, .shift = 0, .size = 0 },
649 .sources = &clkset_camif,
653 /* Where does UCLK0 come from? */
654 static struct clksrc_clk clk_sclk_uclk = {
657 .ctrlbit = S3C_CLKCON_SCLK_UART,
658 .enable = s3c64xx_sclk_ctrl,
660 .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 },
661 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
662 .sources = &clkset_uart,
665 static struct clksrc_clk clk_sclk_mmc0 = {
668 .devname = "s3c-sdhci.0",
669 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
670 .enable = s3c64xx_sclk_ctrl,
672 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
673 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
674 .sources = &clkset_spi_mmc,
677 static struct clksrc_clk clk_sclk_mmc1 = {
680 .devname = "s3c-sdhci.1",
681 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
682 .enable = s3c64xx_sclk_ctrl,
684 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
685 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
686 .sources = &clkset_spi_mmc,
689 static struct clksrc_clk clk_sclk_mmc2 = {
692 .devname = "s3c-sdhci.2",
693 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
694 .enable = s3c64xx_sclk_ctrl,
696 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
697 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
698 .sources = &clkset_spi_mmc,
701 static struct clksrc_clk clk_sclk_spi0 = {
704 .devname = "s3c64xx-spi.0",
705 .ctrlbit = S3C_CLKCON_SCLK_SPI0,
706 .enable = s3c64xx_sclk_ctrl,
708 .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
709 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
710 .sources = &clkset_spi_mmc,
713 static struct clksrc_clk clk_sclk_spi1 = {
716 .devname = "s3c64xx-spi.1",
717 .ctrlbit = S3C_CLKCON_SCLK_SPI1,
718 .enable = s3c64xx_sclk_ctrl,
720 .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
721 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
722 .sources = &clkset_spi_mmc,
725 /* Clock initialisation code */
727 static struct clksrc_clk *init_parents[] = {
733 static struct clksrc_clk *clksrc_cdev[] = {
742 static struct clk *clk_cdev[] = {
750 static struct clk_lookup s3c64xx_clk_lookup[] = {
751 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
752 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
753 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
754 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
755 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
756 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
757 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
758 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
759 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
760 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
761 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
762 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
763 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
766 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
768 void __init_or_cpufreq s3c64xx_setup_clocks(void)
770 struct clk *xtal_clk;
782 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
784 clkdiv0 = __raw_readl(S3C_CLK_DIV0);
785 printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);
787 xtal_clk = clk_get(NULL, "xtal");
788 BUG_ON(IS_ERR(xtal_clk));
790 xtal = clk_get_rate(xtal_clk);
793 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
795 /* For now assume the mux always selects the crystal */
796 clk_ext_xtal_mux.parent = xtal_clk;
798 epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),
799 __raw_readl(S3C_EPLL_CON1));
800 mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
801 apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
805 printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
808 if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL)
809 /* Synchronous mode */
810 hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
812 /* Asynchronous mode */
813 hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
815 hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
816 pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);
818 printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
821 clk_fout_mpll.rate = mpll;
822 clk_fout_epll.rate = epll;
823 clk_fout_apll.rate = apll;
830 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
831 s3c_set_clksrc(init_parents[ptr], true);
833 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
834 s3c_set_clksrc(&clksrcs[ptr], true);
837 static struct clk *clks1[] __initdata = {
849 static struct clk *clks[] __initdata = {
859 * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
860 * @xtal: The rate for the clock crystal feeding the PLLs.
861 * @armclk_divlimit: Divisor mask for ARMCLK.
863 * Register the clocks for the S3C6400 and S3C6410 SoC range, such
864 * as ARMCLK as well as the necessary parent clocks.
866 * This call does not setup the clocks, which is left to the
867 * s3c64xx_setup_clocks() call which may be needed by the cpufreq
868 * or resume code to re-set the clocks if the bootloader has changed
871 void __init s3c64xx_register_clocks(unsigned long xtal,
872 unsigned armclk_divlimit)
876 armclk_mask = armclk_divlimit;
878 s3c24xx_register_baseclocks(xtal);
879 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
881 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
883 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
884 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
886 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
887 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
888 s3c_disable_clocks(clk_cdev[cnt], 1);
890 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
891 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
892 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
893 s3c_register_clksrc(clksrc_cdev[cnt], 1);
894 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));