1 /* linux/arch/arm/mach-s5pv310/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV310 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
27 static struct clk clk_sclk_hdmi27m = {
28 .name = "sclk_hdmi27m",
33 /* Core list of CMU_CPU side */
35 static struct clksrc_clk clk_mout_apll = {
40 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
44 static struct clksrc_clk clk_sclk_apll = {
48 .parent = &clk_mout_apll.clk,
50 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
53 static struct clksrc_clk clk_mout_epll = {
58 .sources = &clk_src_epll,
59 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
62 static struct clksrc_clk clk_mout_mpll = {
67 .sources = &clk_src_mpll,
68 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
71 static struct clk *clkset_moutcore_list[] = {
72 [0] = &clk_sclk_apll.clk,
73 [1] = &clk_mout_mpll.clk,
76 static struct clksrc_sources clkset_moutcore = {
77 .sources = clkset_moutcore_list,
78 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
81 static struct clksrc_clk clk_moutcore = {
86 .sources = &clkset_moutcore,
87 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
90 static struct clksrc_clk clk_coreclk = {
94 .parent = &clk_moutcore.clk,
96 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
99 static struct clksrc_clk clk_armclk = {
103 .parent = &clk_coreclk.clk,
107 static struct clksrc_clk clk_aclk_corem0 = {
109 .name = "aclk_corem0",
111 .parent = &clk_coreclk.clk,
113 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
116 static struct clksrc_clk clk_aclk_cores = {
118 .name = "aclk_cores",
120 .parent = &clk_coreclk.clk,
122 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
125 static struct clksrc_clk clk_aclk_corem1 = {
127 .name = "aclk_corem1",
129 .parent = &clk_coreclk.clk,
131 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
134 static struct clksrc_clk clk_periphclk = {
138 .parent = &clk_coreclk.clk,
140 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
143 static struct clksrc_clk clk_atclk = {
147 .parent = &clk_moutcore.clk,
149 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
152 static struct clksrc_clk clk_pclk_dbg = {
156 .parent = &clk_atclk.clk,
158 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
161 /* Core list of CMU_CORE side */
163 static struct clk *clkset_corebus_list[] = {
164 [0] = &clk_mout_mpll.clk,
165 [1] = &clk_sclk_apll.clk,
168 static struct clksrc_sources clkset_mout_corebus = {
169 .sources = clkset_corebus_list,
170 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
173 static struct clksrc_clk clk_mout_corebus = {
175 .name = "mout_corebus",
178 .sources = &clkset_mout_corebus,
179 .reg_src = { .reg = S5P_CLKSRC_CORE, .shift = 4, .size = 1 },
182 static struct clksrc_clk clk_sclk_dmc = {
186 .parent = &clk_mout_corebus.clk,
188 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
191 static struct clksrc_clk clk_aclk_cored = {
193 .name = "aclk_cored",
195 .parent = &clk_sclk_dmc.clk,
197 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
200 static struct clksrc_clk clk_aclk_corep = {
202 .name = "aclk_corep",
204 .parent = &clk_aclk_cored.clk,
206 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
209 static struct clksrc_clk clk_aclk_acp = {
213 .parent = &clk_mout_corebus.clk,
215 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
218 static struct clksrc_clk clk_pclk_acp = {
222 .parent = &clk_aclk_acp.clk,
224 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
227 /* Core list of CMU_TOP side */
229 static struct clk *clkset_aclk_top_list[] = {
230 [0] = &clk_mout_mpll.clk,
231 [1] = &clk_sclk_apll.clk,
234 static struct clksrc_sources clkset_aclk_200 = {
235 .sources = clkset_aclk_top_list,
236 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
239 static struct clksrc_clk clk_aclk_200 = {
244 .sources = &clkset_aclk_200,
245 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
246 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
249 static struct clksrc_sources clkset_aclk_100 = {
250 .sources = clkset_aclk_top_list,
251 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
254 static struct clksrc_clk clk_aclk_100 = {
259 .sources = &clkset_aclk_100,
260 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
261 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
264 static struct clksrc_sources clkset_aclk_160 = {
265 .sources = clkset_aclk_top_list,
266 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
269 static struct clksrc_clk clk_aclk_160 = {
274 .sources = &clkset_aclk_160,
275 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
276 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
279 static struct clksrc_sources clkset_aclk_133 = {
280 .sources = clkset_aclk_top_list,
281 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
284 static struct clksrc_clk clk_aclk_133 = {
289 .sources = &clkset_aclk_133,
290 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
291 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
294 static struct clk *clkset_vpllsrc_list[] = {
296 [1] = &clk_sclk_hdmi27m,
299 static struct clksrc_sources clkset_vpllsrc = {
300 .sources = clkset_vpllsrc_list,
301 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
304 static struct clksrc_clk clk_vpllsrc = {
309 .sources = &clkset_vpllsrc,
310 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
313 static struct clk *clkset_sclk_vpll_list[] = {
314 [0] = &clk_vpllsrc.clk,
315 [1] = &clk_fout_vpll,
318 static struct clksrc_sources clkset_sclk_vpll = {
319 .sources = clkset_sclk_vpll_list,
320 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
323 static struct clksrc_clk clk_sclk_vpll = {
328 .sources = &clkset_sclk_vpll,
329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
332 static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
334 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
337 static struct clk init_clocks_disable[] = {
341 .parent = &clk_aclk_100.clk,
342 .enable = s5pv310_clk_ip_peril_ctrl,
347 static struct clk init_clocks[] = {
348 /* Nothing here yet */
351 static struct clk *clkset_group_list[] = {
352 [0] = &clk_ext_xtal_mux,
354 [2] = &clk_sclk_hdmi27m,
355 [6] = &clk_mout_mpll.clk,
356 [7] = &clk_mout_epll.clk,
357 [8] = &clk_sclk_vpll.clk,
360 static struct clksrc_sources clkset_group = {
361 .sources = clkset_group_list,
362 .nr_sources = ARRAY_SIZE(clkset_group_list),
365 static struct clksrc_clk clksrcs[] = {
371 .enable = s5pv310_clk_ip_peril_ctrl,
373 .sources = &clkset_group,
374 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
375 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
380 .enable = s5pv310_clk_ip_peril_ctrl,
383 .sources = &clkset_group,
384 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
385 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
390 .enable = s5pv310_clk_ip_peril_ctrl,
393 .sources = &clkset_group,
394 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
395 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
400 .enable = s5pv310_clk_ip_peril_ctrl,
403 .sources = &clkset_group,
404 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
405 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
410 .enable = s5pv310_clk_ip_peril_ctrl,
411 .ctrlbit = (1 << 24),
413 .sources = &clkset_group,
414 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
415 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
419 /* Clock initialization code */
420 static struct clksrc_clk *sysclks[] = {
448 void __init_or_cpufreq s5pv310_setup_clocks(void)
450 struct clk *xtal_clk;
455 unsigned long vpllsrc;
457 unsigned long armclk;
458 unsigned long aclk_corem0;
459 unsigned long aclk_cores;
460 unsigned long aclk_corem1;
461 unsigned long periphclk;
462 unsigned long sclk_dmc;
463 unsigned long aclk_cored;
464 unsigned long aclk_corep;
465 unsigned long aclk_acp;
466 unsigned long pclk_acp;
469 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
471 xtal_clk = clk_get(NULL, "xtal");
472 BUG_ON(IS_ERR(xtal_clk));
474 xtal = clk_get_rate(xtal_clk);
477 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
479 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
480 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
481 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
482 __raw_readl(S5P_EPLL_CON1), pll_4600);
484 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
485 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
486 __raw_readl(S5P_VPLL_CON1), pll_4650);
488 clk_fout_apll.rate = apll;
489 clk_fout_mpll.rate = mpll;
490 clk_fout_epll.rate = epll;
491 clk_fout_vpll.rate = vpll;
493 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
494 apll, mpll, epll, vpll);
496 armclk = clk_get_rate(&clk_armclk.clk);
497 aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
498 aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
499 aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
500 periphclk = clk_get_rate(&clk_periphclk.clk);
501 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
502 aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
503 aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
504 aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
505 pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
507 printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
508 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
509 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
510 armclk, aclk_corem0, aclk_cores, aclk_corem1,
511 periphclk, sclk_dmc, aclk_cored, aclk_corep,
515 clk_h.rate = sclk_dmc;
516 clk_p.rate = periphclk;
518 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
519 s3c_set_clksrc(&clksrcs[ptr], true);
522 static struct clk *clks[] __initdata = {
523 /* Nothing here yet */
526 void __init s5pv310_register_clocks(void)
532 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
534 printk(KERN_ERR "Failed to register %u clocks\n", ret);
536 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
537 s3c_register_clksrc(sysclks[ptr], 1);
539 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
540 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
542 clkp = init_clocks_disable;
543 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
544 ret = s3c24xx_register_clock(clkp);
546 printk(KERN_ERR "Failed to register clock %s (%d)\n",
549 (clkp->enable)(clkp, 0);