arch/arm/mach-shmobile/pm-sh7372.c

   1 /*
   2  * sh7372 Power management support
   3  *
   4  *  Copyright (C) 2011 Magnus Damm
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/pm.h>
  12 #include <linux/suspend.h>
  13 #include <linux/cpuidle.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/pm_clock.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/delay.h>
  21 #include <linux/irq.h>
  22 #include <linux/bitrev.h>
  23 #include <linux/console.h>
  24 #include <asm/cpuidle.h>
  25 #include <asm/io.h>
  26 #include <asm/tlbflush.h>
  27 #include <asm/suspend.h>
  28 #include <mach/common.h>
  29 #include <mach/sh7372.h>
  30 #include <mach/pm-rmobile.h>
  31
  32 /* DBG */
  33 #define DBGREG1 0xe6100020
  34 #define DBGREG9 0xe6100040
  35
  36 /* CPGA */
  37 #define SYSTBCR 0xe6150024
  38 #define MSTPSR0 0xe6150030
  39 #define MSTPSR1 0xe6150038
  40 #define MSTPSR2 0xe6150040
  41 #define MSTPSR3 0xe6150048
  42 #define MSTPSR4 0xe615004c
  43 #define PLLC01STPCR 0xe61500c8
  44
  45 /* SYSC */
  46 #define SBAR 0xe6180020
  47 #define WUPRMSK 0xe6180028
  48 #define WUPSMSK 0xe618002c
  49 #define WUPSMSK2 0xe6180048
  50 #define WUPSFAC 0xe6180098
  51 #define IRQCR 0xe618022c
  52 #define IRQCR2 0xe6180238
  53 #define IRQCR3 0xe6180244
  54 #define IRQCR4 0xe6180248
  55 #define PDNSEL 0xe6180254
  56
  57 /* INTC */
  58 #define ICR1A 0xe6900000
  59 #define ICR2A 0xe6900004
  60 #define ICR3A 0xe6900008
  61 #define ICR4A 0xe690000c
  62 #define INTMSK00A 0xe6900040
  63 #define INTMSK10A 0xe6900044
  64 #define INTMSK20A 0xe6900048
  65 #define INTMSK30A 0xe690004c
  66
  67 /* MFIS */
  68 #define SMFRAM 0xe6a70000
  69
  70 /* AP-System Core */
  71 #define APARMBAREA 0xe6f10020
  72
  73 #ifdef CONFIG_PM
  74
  75 #define PM_DOMAIN_ON_OFF_LATENCY_NS     250000
  76
  77 static int sh7372_a4r_pd_suspend(void)
  78 {
  79         sh7372_intcs_suspend();
  80         __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
  81         return 0;
  82 }
  83
  84 static bool a4s_suspend_ready;
  85
  86 static int sh7372_a4s_pd_suspend(void)
  87 {
  88         /*
  89          * The A4S domain contains the CPU core and therefore it should
  90          * only be turned off if the CPU is not in use.  This may happen
  91          * during system suspend, when SYSC is going to be used for generating
  92          * resume signals and a4s_suspend_ready is set to let
  93          * sh7372_enter_suspend() know that it can turn A4S off.
  94          */
  95         a4s_suspend_ready = true;
  96         return -EBUSY;
  97 }
  98
  99 static void sh7372_a4s_pd_resume(void)
 100 {
 101         a4s_suspend_ready = false;
 102 }
 103
 104 static int sh7372_a3sp_pd_suspend(void)
 105 {
 106         /*
 107          * Serial consoles make use of SCIF hardware located in A3SP,
 108          * keep such power domain on if "no_console_suspend" is set.
 109          */
 110         return console_suspend_enabled ? 0 : -EBUSY;
 111 }
 112
 113 static struct rmobile_pm_domain sh7372_pm_domains[] = {
 114         {
 115                 .genpd.name = "A4LC",
 116                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 117                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 118                 .bit_shift = 1,
 119         },
 120         {
 121                 .genpd.name = "A4MP",
 122                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 123                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 124                 .bit_shift = 2,
 125         },
 126         {
 127                 .genpd.name = "D4",
 128                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 129                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 130                 .bit_shift = 3,
 131         },
 132         {
 133                 .genpd.name = "A4R",
 134                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 135                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 136                 .bit_shift = 5,
 137                 .suspend = sh7372_a4r_pd_suspend,
 138                 .resume = sh7372_intcs_resume,
 139         },
 140         {
 141                 .genpd.name = "A3RV",
 142                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 143                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 144                 .bit_shift = 6,
 145         },
 146         {
 147                 .genpd.name = "A3RI",
 148                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 149                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 150                 .bit_shift = 8,
 151         },
 152         {
 153                 .genpd.name = "A4S",
 154                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 155                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 156                 .bit_shift = 10,
 157                 .gov = &pm_domain_always_on_gov,
 158                 .no_debug = true,
 159                 .suspend = sh7372_a4s_pd_suspend,
 160                 .resume = sh7372_a4s_pd_resume,
 161         },
 162         {
 163                 .genpd.name = "A3SP",
 164                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 165                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 166                 .bit_shift = 11,
 167                 .gov = &pm_domain_always_on_gov,
 168                 .no_debug = true,
 169                 .suspend = sh7372_a3sp_pd_suspend,
 170         },
 171         {
 172                 .genpd.name = "A3SG",
 173                 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 174                 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
 175                 .bit_shift = 13,
 176         },
 177 };
 178
 179 void __init sh7372_init_pm_domains(void)
 180 {
 181         rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
 182         pm_genpd_add_subdomain_names("A4LC", "A3RV");
 183         pm_genpd_add_subdomain_names("A4R", "A4LC");
 184         pm_genpd_add_subdomain_names("A4S", "A3SG");
 185         pm_genpd_add_subdomain_names("A4S", "A3SP");
 186 }
 187
 188 #endif /* CONFIG_PM */
 189
 190 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
 191 static void sh7372_set_reset_vector(unsigned long address)
 192 {
 193         /* set reset vector, translate 4k */
 194         __raw_writel(address, SBAR);
 195         __raw_writel(0, APARMBAREA);
 196 }
 197
 198 static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
 199 {
 200         if (pllc0_on)
 201                 __raw_writel(0, PLLC01STPCR);
 202         else
 203                 __raw_writel(1 << 28, PLLC01STPCR);
 204
 205         __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
 206         cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
 207         __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
 208
 209          /* disable reset vector translation */
 210         __raw_writel(0, SBAR);
 211 }
 212
 213 static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
 214 {
 215         unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
 216         unsigned long msk, msk2;
 217
 218         /* check active clocks to determine potential wakeup sources */
 219
 220         mstpsr0 = __raw_readl(MSTPSR0);
 221         if ((mstpsr0 & 0x00000003) != 0x00000003) {
 222                 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
 223                 return 0;
 224         }
 225
 226         mstpsr1 = __raw_readl(MSTPSR1);
 227         if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
 228                 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
 229                 return 0;
 230         }
 231
 232         mstpsr2 = __raw_readl(MSTPSR2);
 233         if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
 234                 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
 235                 return 0;
 236         }
 237
 238         mstpsr3 = __raw_readl(MSTPSR3);
 239         if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
 240                 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
 241                 return 0;
 242         }
 243
 244         mstpsr4 = __raw_readl(MSTPSR4);
 245         if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
 246                 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
 247                 return 0;
 248         }
 249
 250         msk = 0;
 251         msk2 = 0;
 252
 253         /* make bitmaps of limited number of wakeup sources */
 254
 255         if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
 256                 msk |= 1 << 31;
 257
 258         if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
 259                 msk |= 1 << 21;
 260
 261         if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
 262                 msk |= 1 << 2;
 263
 264         if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
 265                 msk |= 1 << 1;
 266
 267         if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
 268                 msk |= 1 << 1;
 269
 270         if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
 271                 msk |= 1 << 1;
 272
 273         if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
 274                 msk2 |= 1 << 17;
 275
 276         *mskp = msk;
 277         *msk2p = msk2;
 278
 279         return 1;
 280 }
 281
 282 static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
 283 {
 284         u16 tmp, irqcr1, irqcr2;
 285         int k;
 286
 287         irqcr1 = 0;
 288         irqcr2 = 0;
 289
 290         /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
 291         for (k = 0; k <= 7; k++) {
 292                 tmp = (icr >> ((7 - k) * 4)) & 0xf;
 293                 irqcr1 |= (tmp & 0x03) << (k * 2);
 294                 irqcr2 |= (tmp >> 2) << (k * 2);
 295         }
 296
 297         *irqcr1p = irqcr1;
 298         *irqcr2p = irqcr2;
 299 }
 300
 301 static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
 302 {
 303         u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
 304         unsigned long tmp;
 305
 306         /* read IRQ0A -> IRQ15A mask */
 307         tmp = bitrev8(__raw_readb(INTMSK00A));
 308         tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
 309
 310         /* setup WUPSMSK from clocks and external IRQ mask */
 311         msk = (~msk & 0xc030000f) | (tmp << 4);
 312         __raw_writel(msk, WUPSMSK);
 313
 314         /* propage level/edge trigger for external IRQ 0->15 */
 315         sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
 316         sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
 317         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
 318         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
 319
 320         /* read IRQ16A -> IRQ31A mask */
 321         tmp = bitrev8(__raw_readb(INTMSK20A));
 322         tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
 323
 324         /* setup WUPSMSK2 from clocks and external IRQ mask */
 325         msk2 = (~msk2 & 0x00030000) | tmp;
 326         __raw_writel(msk2, WUPSMSK2);
 327
 328         /* propage level/edge trigger for external IRQ 16->31 */
 329         sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
 330         sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
 331         __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
 332         __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
 333 }
 334
 335 static void sh7372_enter_a3sm_common(int pllc0_on)
 336 {
 337         /* use INTCA together with SYSC for wakeup */
 338         sh7372_setup_sysc(1 << 0, 0);
 339         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 340         sh7372_enter_sysc(pllc0_on, 1 << 12);
 341 }
 342
 343 static void sh7372_enter_a4s_common(int pllc0_on)
 344 {
 345         sh7372_intca_suspend();
 346         sh7372_set_reset_vector(SMFRAM);
 347         sh7372_enter_sysc(pllc0_on, 1 << 10);
 348         sh7372_intca_resume();
 349 }
 350
 351 static void sh7372_pm_setup_smfram(void)
 352 {
 353         memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
 354 }
 355 #else
 356 static inline void sh7372_pm_setup_smfram(void) {}
 357 #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
 358
 359 #ifdef CONFIG_CPU_IDLE
 360 static int sh7372_do_idle_core_standby(unsigned long unused)
 361 {
 362         cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
 363         return 0;
 364 }
 365
 366 static int sh7372_enter_core_standby(struct cpuidle_device *dev,
 367                                      struct cpuidle_driver *drv, int index)
 368 {
 369         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 370
 371         /* enter sleep mode with SYSTBCR to 0x10 */
 372         __raw_writel(0x10, SYSTBCR);
 373         cpu_suspend(0, sh7372_do_idle_core_standby);
 374         __raw_writel(0, SYSTBCR);
 375
 376          /* disable reset vector translation */
 377         __raw_writel(0, SBAR);
 378
 379         return 1;
 380 }
 381
 382 static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
 383                                     struct cpuidle_driver *drv, int index)
 384 {
 385         sh7372_enter_a3sm_common(1);
 386         return 2;
 387 }
 388
 389 static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
 390                                      struct cpuidle_driver *drv, int index)
 391 {
 392         sh7372_enter_a3sm_common(0);
 393         return 3;
 394 }
 395
 396 static int sh7372_enter_a4s(struct cpuidle_device *dev,
 397                             struct cpuidle_driver *drv, int index)
 398 {
 399         unsigned long msk, msk2;
 400
 401         if (!sh7372_sysc_valid(&msk, &msk2))
 402                 return sh7372_enter_a3sm_pll_off(dev, drv, index);
 403
 404         sh7372_setup_sysc(msk, msk2);
 405         sh7372_enter_a4s_common(0);
 406         return 4;
 407 }
 408
 409 static struct cpuidle_driver sh7372_cpuidle_driver = {
 410         .name                   = "sh7372_cpuidle",
 411         .owner                  = THIS_MODULE,
 412         .en_core_tk_irqen       = 1,
 413         .state_count            = 5,
 414         .safe_state_index       = 0, /* C1 */
 415         .states[0] = ARM_CPUIDLE_WFI_STATE,
 416         .states[0].enter = shmobile_enter_wfi,
 417         .states[1] = {
 418                 .name = "C2",
 419                 .desc = "Core Standby Mode",
 420                 .exit_latency = 10,
 421                 .target_residency = 20 + 10,
 422                 .flags = CPUIDLE_FLAG_TIME_VALID,
 423                 .enter = sh7372_enter_core_standby,
 424         },
 425         .states[2] = {
 426                 .name = "C3",
 427                 .desc = "A3SM PLL ON",
 428                 .exit_latency = 20,
 429                 .target_residency = 30 + 20,
 430                 .flags = CPUIDLE_FLAG_TIME_VALID,
 431                 .enter = sh7372_enter_a3sm_pll_on,
 432         },
 433         .states[3] = {
 434                 .name = "C4",
 435                 .desc = "A3SM PLL OFF",
 436                 .exit_latency = 120,
 437                 .target_residency = 30 + 120,
 438                 .flags = CPUIDLE_FLAG_TIME_VALID,
 439                 .enter = sh7372_enter_a3sm_pll_off,
 440         },
 441         .states[4] = {
 442                 .name = "C5",
 443                 .desc = "A4S PLL OFF",
 444                 .exit_latency = 240,
 445                 .target_residency = 30 + 240,
 446                 .flags = CPUIDLE_FLAG_TIME_VALID,
 447                 .enter = sh7372_enter_a4s,
 448                 .disabled = true,
 449         },
 450 };
 451
 452 static void sh7372_cpuidle_init(void)
 453 {
 454         shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
 455 }
 456 #else
 457 static void sh7372_cpuidle_init(void) {}
 458 #endif
 459
 460 #ifdef CONFIG_SUSPEND
 461 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 462 {
 463         unsigned long msk, msk2;
 464
 465         /* check active clocks to determine potential wakeup sources */
 466         if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
 467                 /* convert INTC mask/sense to SYSC mask/sense */
 468                 sh7372_setup_sysc(msk, msk2);
 469
 470                 /* enter A4S sleep with PLLC0 off */
 471                 pr_debug("entering A4S\n");
 472                 sh7372_enter_a4s_common(0);
 473                 return 0;
 474         }
 475
 476         /* default to enter A3SM sleep with PLLC0 off */
 477         pr_debug("entering A3SM\n");
 478         sh7372_enter_a3sm_common(0);
 479         return 0;
 480 }
 481
 482 /**
 483  * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
 484  * @notifier: Unused.
 485  * @pm_event: Event being handled.
 486  * @unused: Unused.
 487  */
 488 static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
 489                                  unsigned long pm_event, void *unused)
 490 {
 491         switch (pm_event) {
 492         case PM_SUSPEND_PREPARE:
 493                 /*
 494                  * This is necessary, because the A4R domain has to be "on"
 495                  * when suspend_device_irqs() and resume_device_irqs() are
 496                  * executed during system suspend and resume, respectively, so
 497                  * that those functions don't crash while accessing the INTCS.
 498                  */
 499                 pm_genpd_name_poweron("A4R");
 500                 break;
 501         case PM_POST_SUSPEND:
 502                 pm_genpd_poweroff_unused();
 503                 break;
 504         }
 505
 506         return NOTIFY_DONE;
 507 }
 508
 509 static void sh7372_suspend_init(void)
 510 {
 511         shmobile_suspend_ops.enter = sh7372_enter_suspend;
 512         pm_notifier(sh7372_pm_notifier_fn, 0);
 513 }
 514 #else
 515 static void sh7372_suspend_init(void) {}
 516 #endif
 517
 518 void __init sh7372_pm_init(void)
 519 {
 520         /* enable DBG hardware block to kick SYSC */
 521         __raw_writel(0x0000a500, DBGREG9);
 522         __raw_writel(0x0000a501, DBGREG9);
 523         __raw_writel(0x00000000, DBGREG1);
 524
 525         /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
 526         __raw_writel(0, PDNSEL);
 527
 528         sh7372_pm_setup_smfram();
 529
 530         sh7372_suspend_init();
 531         sh7372_cpuidle_init();
 532 }
 533
 534 void __init sh7372_pm_init_late(void)
 535 {
 536         shmobile_init_late();
 537         pm_genpd_name_attach_cpuidle("A4S", 4);
 538 }