2 * r8a73a4 processor support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_data/irq-renesas-irqc.h>
24 #include <linux/serial_sci.h>
25 #include <linux/sh_dma.h>
26 #include <linux/sh_timer.h>
28 #include <asm/mach/arch.h>
31 #include "dma-register.h"
35 static const struct resource pfc_resources[] = {
36 DEFINE_RES_MEM(0xe6050000, 0x9000),
39 void __init r8a73a4_pinmux_init(void)
41 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
42 ARRAY_SIZE(pfc_resources));
45 #define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
46 static struct plat_sci_port scif##index##_platform_data = { \
48 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
52 static struct resource scif##index##_resources[] = { \
53 DEFINE_RES_MEM(baseaddr, 0x100), \
54 DEFINE_RES_IRQ(irq), \
57 #define R8A73A4_SCIFA(index, baseaddr, irq) \
58 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
61 #define R8A73A4_SCIFB(index, baseaddr, irq) \
62 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
65 R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
66 R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
67 R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
68 R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
69 R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
70 R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
72 #define r8a73a4_register_scif(index) \
73 platform_device_register_resndata(NULL, "sh-sci", index, \
74 scif##index##_resources, \
75 ARRAY_SIZE(scif##index##_resources), \
76 &scif##index##_platform_data, \
77 sizeof(scif##index##_platform_data))
79 static const struct renesas_irqc_config irqc0_data = {
80 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
83 static const struct resource irqc0_resources[] = {
84 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
85 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
86 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
87 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
88 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
89 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
90 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
91 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
92 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
93 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
94 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
95 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
96 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
97 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
98 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
99 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
100 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
101 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
102 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
103 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
104 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
105 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
106 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
107 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
108 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
109 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
110 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
111 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
112 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
113 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
114 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
115 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
116 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
119 static const struct renesas_irqc_config irqc1_data = {
120 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
123 static const struct resource irqc1_resources[] = {
124 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
125 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
126 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
127 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
128 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
129 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
130 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
131 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
132 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
133 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
134 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
135 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
136 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
137 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
138 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
139 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
140 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
141 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
142 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
143 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
144 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
145 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
146 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
147 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
148 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
149 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
150 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
153 #define r8a73a4_register_irqc(idx) \
154 platform_device_register_resndata(NULL, "renesas_irqc", \
155 idx, irqc##idx##_resources, \
156 ARRAY_SIZE(irqc##idx##_resources), \
158 sizeof(struct renesas_irqc_config))
160 /* Thermal0 -> Thermal2 */
161 static const struct resource thermal0_resources[] = {
162 DEFINE_RES_MEM(0xe61f0000, 0x14),
163 DEFINE_RES_MEM(0xe61f0100, 0x38),
164 DEFINE_RES_MEM(0xe61f0200, 0x38),
165 DEFINE_RES_MEM(0xe61f0300, 0x38),
166 DEFINE_RES_IRQ(gic_spi(69)),
169 #define r8a73a4_register_thermal() \
170 platform_device_register_simple("rcar_thermal", -1, \
171 thermal0_resources, \
172 ARRAY_SIZE(thermal0_resources))
174 static struct sh_timer_config cmt1_platform_data = {
175 .channels_mask = 0xff,
178 static struct resource cmt1_resources[] = {
179 DEFINE_RES_MEM(0xe6130000, 0x1004),
180 DEFINE_RES_IRQ(gic_spi(120)),
183 #define r8a7790_register_cmt(idx) \
184 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
185 idx, cmt##idx##_resources, \
186 ARRAY_SIZE(cmt##idx##_resources), \
187 &cmt##idx##_platform_data, \
188 sizeof(struct sh_timer_config))
190 void __init r8a73a4_add_dt_devices(void)
192 r8a73a4_register_scif(0);
193 r8a73a4_register_scif(1);
194 r8a73a4_register_scif(2);
195 r8a73a4_register_scif(3);
196 r8a73a4_register_scif(4);
197 r8a73a4_register_scif(5);
198 r8a7790_register_cmt(1);
202 static const struct sh_dmae_slave_config dma_slaves[] = {
204 .slave_id = SHDMA_SLAVE_MMCIF0_TX,
206 .chcr = CHCR_TX(XMIT_SZ_32BIT),
209 .slave_id = SHDMA_SLAVE_MMCIF0_RX,
211 .chcr = CHCR_RX(XMIT_SZ_32BIT),
214 .slave_id = SHDMA_SLAVE_MMCIF1_TX,
216 .chcr = CHCR_TX(XMIT_SZ_32BIT),
219 .slave_id = SHDMA_SLAVE_MMCIF1_RX,
221 .chcr = CHCR_RX(XMIT_SZ_32BIT),
226 #define DMAE_CHANNEL(a, b) \
228 .offset = (a) - 0x20, \
229 .dmars = (a) - 0x20 + 0x40, \
231 .chclr_offset = 0x80 - 0x20, \
234 static const struct sh_dmae_channel dma_channels[] = {
235 DMAE_CHANNEL(0x8000, 0),
236 DMAE_CHANNEL(0x8080, 1),
237 DMAE_CHANNEL(0x8100, 2),
238 DMAE_CHANNEL(0x8180, 3),
239 DMAE_CHANNEL(0x8200, 4),
240 DMAE_CHANNEL(0x8280, 5),
241 DMAE_CHANNEL(0x8300, 6),
242 DMAE_CHANNEL(0x8380, 7),
243 DMAE_CHANNEL(0x8400, 8),
244 DMAE_CHANNEL(0x8480, 9),
245 DMAE_CHANNEL(0x8500, 10),
246 DMAE_CHANNEL(0x8580, 11),
247 DMAE_CHANNEL(0x8600, 12),
248 DMAE_CHANNEL(0x8680, 13),
249 DMAE_CHANNEL(0x8700, 14),
250 DMAE_CHANNEL(0x8780, 15),
251 DMAE_CHANNEL(0x8800, 16),
252 DMAE_CHANNEL(0x8880, 17),
253 DMAE_CHANNEL(0x8900, 18),
254 DMAE_CHANNEL(0x8980, 19),
257 static const struct sh_dmae_pdata dma_pdata = {
259 .slave_num = ARRAY_SIZE(dma_slaves),
260 .channel = dma_channels,
261 .channel_num = ARRAY_SIZE(dma_channels),
262 .ts_low_shift = TS_LOW_SHIFT,
263 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
264 .ts_high_shift = TS_HI_SHIFT,
265 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
266 .ts_shift = dma_ts_shift,
267 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
268 .dmaor_init = DMAOR_DME,
273 static struct resource dma_resources[] = {
274 DEFINE_RES_MEM(0xe6700020, 0x89e0),
275 DEFINE_RES_IRQ(gic_spi(220)),
277 /* IRQ for channels 0-19 */
278 .start = gic_spi(200),
280 .flags = IORESOURCE_IRQ,
284 #define r8a73a4_register_dmac() \
285 platform_device_register_resndata(NULL, "sh-dma-engine", 0, \
286 dma_resources, ARRAY_SIZE(dma_resources), \
287 &dma_pdata, sizeof(dma_pdata))
289 void __init r8a73a4_add_standard_devices(void)
291 r8a73a4_add_dt_devices();
292 r8a73a4_register_irqc(0);
293 r8a73a4_register_irqc(1);
294 r8a73a4_register_thermal();
295 r8a73a4_register_dmac();
298 void __init r8a73a4_init_early(void)
300 #ifndef CONFIG_ARM_ARCH_TIMER
301 shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
307 static const char *r8a73a4_boards_compat_dt[] __initdata = {
312 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
313 .init_early = r8a73a4_init_early,
314 .dt_compat = r8a73a4_boards_compat_dt,
316 #endif /* CONFIG_USE_OF */