2 * r8a7779 processor support
4 * Copyright (C) 2011, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2013 Cogent Embedded, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqchip.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_data/dma-rcar-hpbdma.h>
29 #include <linux/platform_data/gpio-rcar.h>
30 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
31 #include <linux/platform_device.h>
32 #include <linux/delay.h>
33 #include <linux/input.h>
35 #include <linux/serial_sci.h>
36 #include <linux/sh_timer.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/usb/otg.h>
39 #include <linux/usb/hcd.h>
40 #include <linux/usb/ehci_pdriver.h>
41 #include <linux/usb/ohci_pdriver.h>
42 #include <linux/pm_runtime.h>
43 #include <mach/irqs.h>
44 #include <mach/r8a7779.h>
45 #include <mach/common.h>
46 #include <asm/mach-types.h>
47 #include <asm/mach/arch.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/map.h>
50 #include <asm/hardware/cache-l2x0.h>
52 static struct map_desc r8a7779_io_desc[] __initdata = {
53 /* 2M entity map for 0xf0000000 (MPCORE) */
55 .virtual = 0xf0000000,
56 .pfn = __phys_to_pfn(0xf0000000),
58 .type = MT_DEVICE_NONSHARED
60 /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
62 .virtual = 0xfe000000,
63 .pfn = __phys_to_pfn(0xfe000000),
65 .type = MT_DEVICE_NONSHARED
69 void __init r8a7779_map_io(void)
71 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
75 #define INT2SMSKCR0 IOMEM(0xfe7822a0)
76 #define INT2SMSKCR1 IOMEM(0xfe7822a4)
77 #define INT2SMSKCR2 IOMEM(0xfe7822a8)
78 #define INT2SMSKCR3 IOMEM(0xfe7822ac)
79 #define INT2SMSKCR4 IOMEM(0xfe7822b0)
81 #define INT2NTSR0 IOMEM(0xfe700060)
82 #define INT2NTSR1 IOMEM(0xfe700064)
84 static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
85 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
86 .sense_bitfield_width = 2,
89 static struct resource irqpin0_resources[] __initdata = {
90 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
91 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
92 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
93 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
94 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
95 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
101 void __init r8a7779_init_irq_extpin(int irlm)
103 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
107 pr_warn("r8a7779: unable to setup external irq pin mode\n");
111 tmp = ioread32(icr0);
113 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
115 tmp &= ~(1 << 23); /* IRL mode - not supported */
116 tmp |= (1 << 21); /* LVLMODE = 1 */
117 iowrite32(tmp, icr0);
121 platform_device_register_resndata(
122 &platform_bus, "renesas_intc_irqpin", -1,
123 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
124 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
128 static struct resource r8a7779_pfc_resources[] = {
129 DEFINE_RES_MEM(0xfffc0000, 0x023c),
132 static struct platform_device r8a7779_pfc_device = {
133 .name = "pfc-r8a7779",
135 .resource = r8a7779_pfc_resources,
136 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
139 #define R8A7779_GPIO(idx, npins) \
140 static struct resource r8a7779_gpio##idx##_resources[] = { \
141 DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c), \
142 DEFINE_RES_IRQ(gic_iid(0xad + (idx))), \
145 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
146 .gpio_base = 32 * (idx), \
148 .number_of_pins = npins, \
149 .pctl_name = "pfc-r8a7779", \
152 static struct platform_device r8a7779_gpio##idx##_device = { \
153 .name = "gpio_rcar", \
155 .resource = r8a7779_gpio##idx##_resources, \
156 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
158 .platform_data = &r8a7779_gpio##idx##_platform_data, \
170 static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
172 &r8a7779_gpio0_device,
173 &r8a7779_gpio1_device,
174 &r8a7779_gpio2_device,
175 &r8a7779_gpio3_device,
176 &r8a7779_gpio4_device,
177 &r8a7779_gpio5_device,
178 &r8a7779_gpio6_device,
181 void __init r8a7779_pinmux_init(void)
183 platform_add_devices(r8a7779_pinctrl_devices,
184 ARRAY_SIZE(r8a7779_pinctrl_devices));
187 static struct plat_sci_port scif0_platform_data = {
188 .mapbase = 0xffe40000,
189 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
190 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
191 .scbrr_algo_id = SCBRR_ALGO_2,
193 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
196 static struct platform_device scif0_device = {
200 .platform_data = &scif0_platform_data,
204 static struct plat_sci_port scif1_platform_data = {
205 .mapbase = 0xffe41000,
206 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
207 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
208 .scbrr_algo_id = SCBRR_ALGO_2,
210 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
213 static struct platform_device scif1_device = {
217 .platform_data = &scif1_platform_data,
221 static struct plat_sci_port scif2_platform_data = {
222 .mapbase = 0xffe42000,
223 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
225 .scbrr_algo_id = SCBRR_ALGO_2,
227 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
230 static struct platform_device scif2_device = {
234 .platform_data = &scif2_platform_data,
238 static struct plat_sci_port scif3_platform_data = {
239 .mapbase = 0xffe43000,
240 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
241 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
242 .scbrr_algo_id = SCBRR_ALGO_2,
244 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
247 static struct platform_device scif3_device = {
251 .platform_data = &scif3_platform_data,
255 static struct plat_sci_port scif4_platform_data = {
256 .mapbase = 0xffe44000,
257 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
258 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
259 .scbrr_algo_id = SCBRR_ALGO_2,
261 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
264 static struct platform_device scif4_device = {
268 .platform_data = &scif4_platform_data,
272 static struct plat_sci_port scif5_platform_data = {
273 .mapbase = 0xffe45000,
274 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
275 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
276 .scbrr_algo_id = SCBRR_ALGO_2,
278 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
281 static struct platform_device scif5_device = {
285 .platform_data = &scif5_platform_data,
290 static struct sh_timer_config tmu00_platform_data = {
292 .channel_offset = 0x4,
294 .clockevent_rating = 200,
297 static struct resource tmu00_resources[] = {
302 .flags = IORESOURCE_MEM,
305 .start = gic_iid(0x40),
306 .flags = IORESOURCE_IRQ,
310 static struct platform_device tmu00_device = {
314 .platform_data = &tmu00_platform_data,
316 .resource = tmu00_resources,
317 .num_resources = ARRAY_SIZE(tmu00_resources),
320 static struct sh_timer_config tmu01_platform_data = {
322 .channel_offset = 0x10,
324 .clocksource_rating = 200,
327 static struct resource tmu01_resources[] = {
332 .flags = IORESOURCE_MEM,
335 .start = gic_iid(0x41),
336 .flags = IORESOURCE_IRQ,
340 static struct platform_device tmu01_device = {
344 .platform_data = &tmu01_platform_data,
346 .resource = tmu01_resources,
347 .num_resources = ARRAY_SIZE(tmu01_resources),
351 static struct resource rcar_i2c0_res[] = {
355 .flags = IORESOURCE_MEM,
357 .start = gic_iid(0x6f),
358 .flags = IORESOURCE_IRQ,
362 static struct platform_device i2c0_device = {
365 .resource = rcar_i2c0_res,
366 .num_resources = ARRAY_SIZE(rcar_i2c0_res),
369 static struct resource rcar_i2c1_res[] = {
373 .flags = IORESOURCE_MEM,
375 .start = gic_iid(0x72),
376 .flags = IORESOURCE_IRQ,
380 static struct platform_device i2c1_device = {
383 .resource = rcar_i2c1_res,
384 .num_resources = ARRAY_SIZE(rcar_i2c1_res),
387 static struct resource rcar_i2c2_res[] = {
391 .flags = IORESOURCE_MEM,
393 .start = gic_iid(0x70),
394 .flags = IORESOURCE_IRQ,
398 static struct platform_device i2c2_device = {
401 .resource = rcar_i2c2_res,
402 .num_resources = ARRAY_SIZE(rcar_i2c2_res),
405 static struct resource rcar_i2c3_res[] = {
409 .flags = IORESOURCE_MEM,
411 .start = gic_iid(0x71),
412 .flags = IORESOURCE_IRQ,
416 static struct platform_device i2c3_device = {
419 .resource = rcar_i2c3_res,
420 .num_resources = ARRAY_SIZE(rcar_i2c3_res),
423 static struct resource sata_resources[] = {
428 .flags = IORESOURCE_MEM,
431 .start = gic_iid(0x84),
432 .flags = IORESOURCE_IRQ,
436 static struct platform_device sata_device = {
439 .resource = sata_resources,
440 .num_resources = ARRAY_SIZE(sata_resources),
442 .dma_mask = &sata_device.dev.coherent_dma_mask,
443 .coherent_dma_mask = DMA_BIT_MASK(32),
448 static struct usb_phy *phy;
450 static int usb_power_on(struct platform_device *pdev)
455 pm_runtime_enable(&pdev->dev);
456 pm_runtime_get_sync(&pdev->dev);
463 static void usb_power_off(struct platform_device *pdev)
468 usb_phy_shutdown(phy);
470 pm_runtime_put_sync(&pdev->dev);
471 pm_runtime_disable(&pdev->dev);
474 static int ehci_init_internal_buffer(struct usb_hcd *hcd)
477 * Below are recommended values from the datasheet;
478 * see [USB :: Setting of EHCI Internal Buffer].
480 /* EHCI IP internal buffer setting */
481 iowrite32(0x00ff0040, hcd->regs + 0x0094);
482 /* EHCI IP internal buffer enable */
483 iowrite32(0x00000001, hcd->regs + 0x009C);
488 static struct usb_ehci_pdata ehcix_pdata = {
489 .power_on = usb_power_on,
490 .power_off = usb_power_off,
491 .power_suspend = usb_power_off,
492 .pre_setup = ehci_init_internal_buffer,
495 static struct resource ehci0_resources[] = {
498 .end = 0xffe70400 - 1,
499 .flags = IORESOURCE_MEM,
502 .start = gic_iid(0x4c),
503 .flags = IORESOURCE_IRQ,
507 static struct platform_device ehci0_device = {
508 .name = "ehci-platform",
511 .dma_mask = &ehci0_device.dev.coherent_dma_mask,
512 .coherent_dma_mask = 0xffffffff,
513 .platform_data = &ehcix_pdata,
515 .num_resources = ARRAY_SIZE(ehci0_resources),
516 .resource = ehci0_resources,
519 static struct resource ehci1_resources[] = {
522 .end = 0xfff70400 - 1,
523 .flags = IORESOURCE_MEM,
526 .start = gic_iid(0x4d),
527 .flags = IORESOURCE_IRQ,
531 static struct platform_device ehci1_device = {
532 .name = "ehci-platform",
535 .dma_mask = &ehci1_device.dev.coherent_dma_mask,
536 .coherent_dma_mask = 0xffffffff,
537 .platform_data = &ehcix_pdata,
539 .num_resources = ARRAY_SIZE(ehci1_resources),
540 .resource = ehci1_resources,
543 static struct usb_ohci_pdata ohcix_pdata = {
544 .power_on = usb_power_on,
545 .power_off = usb_power_off,
546 .power_suspend = usb_power_off,
549 static struct resource ohci0_resources[] = {
552 .end = 0xffe70800 - 1,
553 .flags = IORESOURCE_MEM,
556 .start = gic_iid(0x4c),
557 .flags = IORESOURCE_IRQ,
561 static struct platform_device ohci0_device = {
562 .name = "ohci-platform",
565 .dma_mask = &ohci0_device.dev.coherent_dma_mask,
566 .coherent_dma_mask = 0xffffffff,
567 .platform_data = &ohcix_pdata,
569 .num_resources = ARRAY_SIZE(ohci0_resources),
570 .resource = ohci0_resources,
573 static struct resource ohci1_resources[] = {
576 .end = 0xfff70800 - 1,
577 .flags = IORESOURCE_MEM,
580 .start = gic_iid(0x4d),
581 .flags = IORESOURCE_IRQ,
585 static struct platform_device ohci1_device = {
586 .name = "ohci-platform",
589 .dma_mask = &ohci1_device.dev.coherent_dma_mask,
590 .coherent_dma_mask = 0xffffffff,
591 .platform_data = &ohcix_pdata,
593 .num_resources = ARRAY_SIZE(ohci1_resources),
594 .resource = ohci1_resources,
598 static struct resource ether_resources[] __initdata = {
602 .flags = IORESOURCE_MEM,
604 .start = gic_iid(0xb4),
605 .flags = IORESOURCE_IRQ,
609 #define R8A7779_VIN(idx) \
610 static struct resource vin##idx##_resources[] __initdata = { \
611 DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \
612 DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \
615 static struct platform_device_info vin##idx##_info __initdata = { \
616 .parent = &platform_bus, \
617 .name = "r8a7779-vin", \
619 .res = vin##idx##_resources, \
620 .num_res = ARRAY_SIZE(vin##idx##_resources), \
621 .dma_mask = DMA_BIT_MASK(32), \
629 static struct platform_device_info *vin_info_table[] __initdata = {
638 /* Asynchronous mode register bits */
639 #define HPB_DMAE_ASYNCMDR_ASMD43_MASK BIT(23) /* MMC1 */
640 #define HPB_DMAE_ASYNCMDR_ASMD43_SINGLE BIT(23) /* MMC1 */
641 #define HPB_DMAE_ASYNCMDR_ASMD43_MULTI 0 /* MMC1 */
642 #define HPB_DMAE_ASYNCMDR_ASBTMD43_MASK BIT(22) /* MMC1 */
643 #define HPB_DMAE_ASYNCMDR_ASBTMD43_BURST BIT(22) /* MMC1 */
644 #define HPB_DMAE_ASYNCMDR_ASBTMD43_NBURST 0 /* MMC1 */
645 #define HPB_DMAE_ASYNCMDR_ASMD24_MASK BIT(21) /* MMC0 */
646 #define HPB_DMAE_ASYNCMDR_ASMD24_SINGLE BIT(21) /* MMC0 */
647 #define HPB_DMAE_ASYNCMDR_ASMD24_MULTI 0 /* MMC0 */
648 #define HPB_DMAE_ASYNCMDR_ASBTMD24_MASK BIT(20) /* MMC0 */
649 #define HPB_DMAE_ASYNCMDR_ASBTMD24_BURST BIT(20) /* MMC0 */
650 #define HPB_DMAE_ASYNCMDR_ASBTMD24_NBURST 0 /* MMC0 */
651 #define HPB_DMAE_ASYNCMDR_ASMD41_MASK BIT(19) /* SDHI3 */
652 #define HPB_DMAE_ASYNCMDR_ASMD41_SINGLE BIT(19) /* SDHI3 */
653 #define HPB_DMAE_ASYNCMDR_ASMD41_MULTI 0 /* SDHI3 */
654 #define HPB_DMAE_ASYNCMDR_ASBTMD41_MASK BIT(18) /* SDHI3 */
655 #define HPB_DMAE_ASYNCMDR_ASBTMD41_BURST BIT(18) /* SDHI3 */
656 #define HPB_DMAE_ASYNCMDR_ASBTMD41_NBURST 0 /* SDHI3 */
657 #define HPB_DMAE_ASYNCMDR_ASMD40_MASK BIT(17) /* SDHI3 */
658 #define HPB_DMAE_ASYNCMDR_ASMD40_SINGLE BIT(17) /* SDHI3 */
659 #define HPB_DMAE_ASYNCMDR_ASMD40_MULTI 0 /* SDHI3 */
660 #define HPB_DMAE_ASYNCMDR_ASBTMD40_MASK BIT(16) /* SDHI3 */
661 #define HPB_DMAE_ASYNCMDR_ASBTMD40_BURST BIT(16) /* SDHI3 */
662 #define HPB_DMAE_ASYNCMDR_ASBTMD40_NBURST 0 /* SDHI3 */
663 #define HPB_DMAE_ASYNCMDR_ASMD39_MASK BIT(15) /* SDHI3 */
664 #define HPB_DMAE_ASYNCMDR_ASMD39_SINGLE BIT(15) /* SDHI3 */
665 #define HPB_DMAE_ASYNCMDR_ASMD39_MULTI 0 /* SDHI3 */
666 #define HPB_DMAE_ASYNCMDR_ASBTMD39_MASK BIT(14) /* SDHI3 */
667 #define HPB_DMAE_ASYNCMDR_ASBTMD39_BURST BIT(14) /* SDHI3 */
668 #define HPB_DMAE_ASYNCMDR_ASBTMD39_NBURST 0 /* SDHI3 */
669 #define HPB_DMAE_ASYNCMDR_ASMD27_MASK BIT(13) /* SDHI2 */
670 #define HPB_DMAE_ASYNCMDR_ASMD27_SINGLE BIT(13) /* SDHI2 */
671 #define HPB_DMAE_ASYNCMDR_ASMD27_MULTI 0 /* SDHI2 */
672 #define HPB_DMAE_ASYNCMDR_ASBTMD27_MASK BIT(12) /* SDHI2 */
673 #define HPB_DMAE_ASYNCMDR_ASBTMD27_BURST BIT(12) /* SDHI2 */
674 #define HPB_DMAE_ASYNCMDR_ASBTMD27_NBURST 0 /* SDHI2 */
675 #define HPB_DMAE_ASYNCMDR_ASMD26_MASK BIT(11) /* SDHI2 */
676 #define HPB_DMAE_ASYNCMDR_ASMD26_SINGLE BIT(11) /* SDHI2 */
677 #define HPB_DMAE_ASYNCMDR_ASMD26_MULTI 0 /* SDHI2 */
678 #define HPB_DMAE_ASYNCMDR_ASBTMD26_MASK BIT(10) /* SDHI2 */
679 #define HPB_DMAE_ASYNCMDR_ASBTMD26_BURST BIT(10) /* SDHI2 */
680 #define HPB_DMAE_ASYNCMDR_ASBTMD26_NBURST 0 /* SDHI2 */
681 #define HPB_DMAE_ASYNCMDR_ASMD25_MASK BIT(9) /* SDHI2 */
682 #define HPB_DMAE_ASYNCMDR_ASMD25_SINGLE BIT(9) /* SDHI2 */
683 #define HPB_DMAE_ASYNCMDR_ASMD25_MULTI 0 /* SDHI2 */
684 #define HPB_DMAE_ASYNCMDR_ASBTMD25_MASK BIT(8) /* SDHI2 */
685 #define HPB_DMAE_ASYNCMDR_ASBTMD25_BURST BIT(8) /* SDHI2 */
686 #define HPB_DMAE_ASYNCMDR_ASBTMD25_NBURST 0 /* SDHI2 */
687 #define HPB_DMAE_ASYNCMDR_ASMD23_MASK BIT(7) /* SDHI0 */
688 #define HPB_DMAE_ASYNCMDR_ASMD23_SINGLE BIT(7) /* SDHI0 */
689 #define HPB_DMAE_ASYNCMDR_ASMD23_MULTI 0 /* SDHI0 */
690 #define HPB_DMAE_ASYNCMDR_ASBTMD23_MASK BIT(6) /* SDHI0 */
691 #define HPB_DMAE_ASYNCMDR_ASBTMD23_BURST BIT(6) /* SDHI0 */
692 #define HPB_DMAE_ASYNCMDR_ASBTMD23_NBURST 0 /* SDHI0 */
693 #define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(5) /* SDHI0 */
694 #define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(5) /* SDHI0 */
695 #define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
696 #define HPB_DMAE_ASYNCMDR_ASBTMD22_MASK BIT(4) /* SDHI0 */
697 #define HPB_DMAE_ASYNCMDR_ASBTMD22_BURST BIT(4) /* SDHI0 */
698 #define HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST 0 /* SDHI0 */
699 #define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(3) /* SDHI0 */
700 #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(3) /* SDHI0 */
701 #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
702 #define HPB_DMAE_ASYNCMDR_ASBTMD21_MASK BIT(2) /* SDHI0 */
703 #define HPB_DMAE_ASYNCMDR_ASBTMD21_BURST BIT(2) /* SDHI0 */
704 #define HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST 0 /* SDHI0 */
705 #define HPB_DMAE_ASYNCMDR_ASMD20_MASK BIT(1) /* SDHI1 */
706 #define HPB_DMAE_ASYNCMDR_ASMD20_SINGLE BIT(1) /* SDHI1 */
707 #define HPB_DMAE_ASYNCMDR_ASMD20_MULTI 0 /* SDHI1 */
708 #define HPB_DMAE_ASYNCMDR_ASBTMD20_MASK BIT(0) /* SDHI1 */
709 #define HPB_DMAE_ASYNCMDR_ASBTMD20_BURST BIT(0) /* SDHI1 */
710 #define HPB_DMAE_ASYNCMDR_ASBTMD20_NBURST 0 /* SDHI1 */
712 static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
714 .id = HPBDMA_SLAVE_SDHI0_TX,
715 .addr = 0xffe4c000 + 0x30,
716 .dcr = HPB_DMAE_DCR_SPDS_16BIT |
718 HPB_DMAE_DCR_DPDS_16BIT,
719 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
720 HPB_DMAE_ASYNCRSTR_ASRST22 |
721 HPB_DMAE_ASYNCRSTR_ASRST23,
722 .mdr = HPB_DMAE_ASYNCMDR_ASMD21_SINGLE |
723 HPB_DMAE_ASYNCMDR_ASBTMD21_NBURST,
724 .mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK |
725 HPB_DMAE_ASYNCMDR_ASBTMD21_MASK,
727 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
730 .id = HPBDMA_SLAVE_SDHI0_RX,
731 .addr = 0xffe4c000 + 0x30,
732 .dcr = HPB_DMAE_DCR_SMDL |
733 HPB_DMAE_DCR_SPDS_16BIT |
734 HPB_DMAE_DCR_DPDS_16BIT,
735 .rstr = HPB_DMAE_ASYNCRSTR_ASRST21 |
736 HPB_DMAE_ASYNCRSTR_ASRST22 |
737 HPB_DMAE_ASYNCRSTR_ASRST23,
738 .mdr = HPB_DMAE_ASYNCMDR_ASMD22_SINGLE |
739 HPB_DMAE_ASYNCMDR_ASBTMD22_NBURST,
740 .mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK |
741 HPB_DMAE_ASYNCMDR_ASBTMD22_MASK,
743 .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
748 static const struct hpb_dmae_channel hpb_dmae_channels[] = {
749 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
750 HPB_DMAE_CHANNEL(0x93, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
753 static struct hpb_dmae_pdata dma_platform_data __initdata = {
754 .slaves = hpb_dmae_slaves,
755 .num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
756 .channels = hpb_dmae_channels,
757 .num_channels = ARRAY_SIZE(hpb_dmae_channels),
763 .num_hw_channels = 44,
766 static struct resource hpb_dmae_resources[] __initdata = {
767 /* Channel registers */
768 DEFINE_RES_MEM(0xffc08000, 0x1000),
769 /* Common registers */
770 DEFINE_RES_MEM(0xffc09000, 0x170),
771 /* Asynchronous reset registers */
772 DEFINE_RES_MEM(0xffc00300, 4),
773 /* Asynchronous mode registers */
774 DEFINE_RES_MEM(0xffc00400, 4),
775 /* IRQ for DMA channels */
776 DEFINE_RES_NAMED(gic_iid(0x8e), 12, NULL, IORESOURCE_IRQ),
779 static void __init r8a7779_register_hpb_dmae(void)
781 platform_device_register_resndata(&platform_bus, "hpb-dma-engine", -1,
783 ARRAY_SIZE(hpb_dmae_resources),
785 sizeof(dma_platform_data));
788 static struct platform_device *r8a7779_devices_dt[] __initdata = {
799 static struct platform_device *r8a7779_standard_devices[] __initdata = {
807 void __init r8a7779_add_standard_devices(void)
809 #ifdef CONFIG_CACHE_L2X0
810 /* Early BRESP enable, Shared attribute override enable, 64K*16way */
811 l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
815 r8a7779_init_pm_domains();
817 platform_add_devices(r8a7779_devices_dt,
818 ARRAY_SIZE(r8a7779_devices_dt));
819 platform_add_devices(r8a7779_standard_devices,
820 ARRAY_SIZE(r8a7779_standard_devices));
821 r8a7779_register_hpb_dmae();
824 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
826 platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
828 ARRAY_SIZE(ether_resources),
829 pdata, sizeof(*pdata));
832 void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
834 BUG_ON(id < 0 || id > 3);
836 vin_info_table[id]->data = pdata;
837 vin_info_table[id]->size_data = sizeof(*pdata);
839 platform_device_register_full(vin_info_table[id]);
842 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
843 void __init __weak r8a7779_register_twd(void) { }
845 void __init r8a7779_earlytimer_init(void)
847 r8a7779_clock_init();
848 r8a7779_register_twd();
849 shmobile_earlytimer_init();
852 void __init r8a7779_add_early_devices(void)
854 early_platform_add_devices(r8a7779_devices_dt,
855 ARRAY_SIZE(r8a7779_devices_dt));
857 /* Early serial console setup is not included here due to
858 * memory map collisions. The SCIF serial ports in r8a7779
859 * are difficult to entity map 1:1 due to collision with the
860 * virtual memory range used by the coherent DMA code on ARM.
862 * Anyone wanting to debug early can remove UPF_IOREMAP from
863 * the sh-sci serial console platform data, adjust mapbase
864 * to a static M:N virt:phys mapping that needs to be added to
865 * the mappings passed with iotable_init() above.
867 * Then add a call to shmobile_setup_console() from this function.
869 * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
870 * command line in case of the marzen board.
874 static struct platform_device *r8a7779_late_devices[] __initdata = {
881 void __init r8a7779_init_late(void)
884 phy = usb_get_phy(USB_PHY_TYPE_USB2);
886 shmobile_init_late();
887 platform_add_devices(r8a7779_late_devices,
888 ARRAY_SIZE(r8a7779_late_devices));
892 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
894 return 0; /* always allow wakeup */
897 void __init r8a7779_init_irq_dt(void)
899 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
903 /* route all interrupts to ARM */
904 __raw_writel(0xffffffff, INT2NTSR0);
905 __raw_writel(0x3fffffff, INT2NTSR1);
907 /* unmask all known interrupts in INTCS2 */
908 __raw_writel(0xfffffff0, INT2SMSKCR0);
909 __raw_writel(0xfff7ffff, INT2SMSKCR1);
910 __raw_writel(0xfffbffdf, INT2SMSKCR2);
911 __raw_writel(0xbffffffc, INT2SMSKCR3);
912 __raw_writel(0x003fee3f, INT2SMSKCR4);
915 void __init r8a7779_init_delay(void)
917 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
920 void __init r8a7779_add_standard_devices_dt(void)
922 /* clocks are setup late during boot in the case of DT */
923 r8a7779_clock_init();
925 platform_add_devices(r8a7779_devices_dt,
926 ARRAY_SIZE(r8a7779_devices_dt));
927 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
930 static const char *r8a7779_compat_dt[] __initdata = {
935 DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
936 .map_io = r8a7779_map_io,
937 .init_early = r8a7779_init_delay,
938 .nr_irqs = NR_IRQS_LEGACY,
939 .init_irq = r8a7779_init_irq_dt,
940 .init_machine = r8a7779_add_standard_devices_dt,
941 .init_late = r8a7779_init_late,
942 .dt_compat = r8a7779_compat_dt,
944 #endif /* CONFIG_USE_OF */